JP2013135034A - Led reliability evaluation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LED reliability evaluation method in which electromigration-related evaluation is suitably carried out without requiring time and effort.SOLUTION: The evaluation method comprises the steps of: forming a p-type electrode and an n-type electrode as well as a p-side branch electrode and an n-side branch electrode in the main region of an insulating substrate; forming a pad part 41, a pad part 42 and a wiring part 46 made from the same material as the p-side and the n-side branch electrodes in a TEG region; obtaining an LED chip and an evaluation chip 51 from the main region and the TEG region, respectively; and carrying out evaluation of the LED with regard to electromigration by using the evaluation chip 51. The step in which evaluation is carried out includes a step of conducting electricity to the pad part 41, the pad part 42 and the wiring part 46 by an electromigration evaluation device, and also automatically measuring a change in characteristics of the evaluation chip 51 under a high temperature condition periodically.

Description

  The present invention generally relates to a method for evaluating the reliability of an LED (Light Emitting Diode), and more specifically, an electromigration of an LED in which a current supply wiring is provided on a conductive thin film. The present invention relates to a reliability evaluation method for carrying out an evaluation for.

  In order to develop LED (Light Emitting Diode) for various lighting applications, a technology for emitting three primary colors of red, green, and blue light is indispensable. Since the completion of blue LEDs was delayed, the LEDs could not be developed for various uses. However, when nitride-based blue LEDs are developed, products using LEDs are not limited to signals, but are used in various applications such as LCD monitor backlights, LCD TV backlights, and home lighting. Has been deployed.

  Furthermore, in recent years, the price of liquid crystal televisions equipped with LED backlights has fallen, and such liquid crystal televisions have begun to spread rapidly. In addition, illumination using LEDs has merits such as low power consumption, space saving, and low load on the environment due to mercury-free compared to conventional illumination. For this reason, illumination using LEDs has been released at a low price, and is spreading rapidly.

  By the way, white light is used for illumination and backlights of liquid crystal televisions. White light is generally realized by a combination of a blue LED and a YAG (yttrium, aluminum, garnet) yellow phosphor, or a combination of a blue LED, a green phosphor and a red phosphor. That is, when realizing white light, a blue LED is required regardless of the combination. For this reason, there is a need for a method for manufacturing high-intensity blue LEDs at low cost and in large quantities.

  In general, for a light emitting layer of a short wavelength LED such as blue or blue green or a laser diode (LD), gallium nitride (GaN), aluminum nitride (AlN) and indium nitride (InN), or these A III-V compound semiconductor containing nitrogen as a group V element, such as a mixed crystal, is used.

  As an example of an LED having such a structure, Japanese Unexamined Patent Application Publication No. 2007-116158 discloses a nitride-based semiconductor light-emitting device intended to implement a low driving voltage within the same unit area LED chip size. (Patent Document 1). In the nitride-based semiconductor light-emitting device disclosed in Patent Document 1, an n-type electrode is formed on an n-type nitride semiconductor layer, and a p-type electrode is formed on the p-type nitride semiconductor layer via a transparent electrode. ing. For the purpose of improving current spreading characteristics, the n-type electrode has one n-type branch electrode, and the p-type electrode has two p-type branch electrodes.

  Japanese Patent Laid-Open No. 2003-152039 discloses a wiring pattern for the purpose of performing an appropriate EM evaluation by devising a wiring pattern shape for EM (EM: Electro Migration) evaluation (patent). Reference 2). The wiring pattern for EM evaluation disclosed in Patent Document 2 is formed in a specific region, a TEG (Test Element Group) region, which is different from a chip region where a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an actual device is formed. Is done.

JP 2007-116158 A JP 2003-152039 A

  When a current supply wiring such as a branch electrode is provided on a conductive thin film of an LED as disclosed in Patent Document 1 described above, a wiring life test (EM evaluation) by electromigration (EM) It is necessary to carry out. Electromigration means a phenomenon in which metal atoms move due to momentum exchange between electrons flowing through a conductor and metal ions. As the movement of the metal atoms proceeds, voids are generated and the wiring is disconnected.

  On the other hand, as a method for evaluating the reliability of the LED, by applying wire bonding to the electrodes (n-type electrode, p-type electrode) of individual LED chips that are finished products and energizing them through the wire wiring, There are methods for evaluating fluctuations such as Po) and operating voltage (VF). However, when an EM evaluation is performed using such a reliability evaluation method, various measured characteristic variations are caused by a compound semiconductor layer formed by epitaxial growth by MOCVD (Metal Organic Chemical Vapor Deposition). There is a problem that it is not possible to distinguish whether it is due to a branch electrode.

  Furthermore, when using a branch electrode to reduce the operating voltage of the LED, it is necessary to make the width of the branch electrode as small as possible in order to increase the light emitting area. Considering the occurrence of electromigration in the branch electrode, although it depends on the applied current and the electrode structure, the narrowing of the electrode width is naturally limited. However, there is a problem that the minimum electrode width cannot be determined by the above-described reliability evaluation method.

  In recent years, as efforts to improve the light output of LED chips, there is a movement to study and adopt electrode materials and structures with high reflectivity. An electromigration evaluation method is adopted as one of the test items for judging whether there is a problem in reliability in adopting such an electrode material or structure. The electromigration evaluation method is used as a method for determining whether there is no resistance variation or electrode material deterioration such as Kirkendall effect by energizing an electrode at a high temperature.

  As an electromigration reliability test of a branch electrode designed for such an evaluation method, for example, a wiring pattern of a branch electrode in a specific TEG (Test Element Group) region different from a region where a LED chip is taken out on a substrate is used. A method is conceivable in which an evaluation chip is formed, and the evaluation chip is mounted on a TO-18 stem or the like to evaluate the variation in wiring resistance. However, in this case, since it is necessary to take out the TO-18 stem from the test apparatus and measure the wiring resistance with a manual measuring instrument every elapsed time, it takes time and labor with human intervention. In addition, while energization of the wiring pattern is performed at a high temperature, the measurement of the wiring resistance is performed at room temperature after the TO-18 stem is once removed from the test apparatus. There is a problem that it cannot be evaluated.

  Accordingly, an object of the present invention is to solve the above-described problems, and to provide a reliability evaluation method for an LED in which evaluation relating to electromigration is suitably performed without taking time and effort.

  In the LED reliability evaluation method according to the present invention, at least one of the first electrode and the second electrode, and the first electrode and the second electrode is formed in the first region on the insulating substrate on which the compound semiconductor layer is formed. Forming a branch electrode extending linearly from one side, forming a wiring pattern made of the same material as the branch electrode in a second region on the insulating substrate, and cutting the insulating substrate The LED (Light Emitting Diode) chip is obtained from the first area, the evaluation chip is obtained from the second area, and the evaluation of the electromigration of the LED is performed using the evaluation chip obtained from the second area. And a step of performing. The step of evaluating the electromigration of the LED includes a step of mounting the evaluation chip on the electromigration evaluation apparatus, and energizing the wiring pattern at a predetermined high temperature by the electromigration evaluation apparatus, and at a high temperature of the evaluation chip. And automatically measuring a change in characteristics at regular intervals.

  According to the LED reliability evaluation method configured as described above, the second region different from the first region for obtaining the LED chip is provided on the insulating substrate, and the wiring pattern is formed from the second region. Obtain an evaluation chip. When the wiring pattern is energized, a current flows through the wiring pattern having a lower resistance than the compound semiconductor layer, so that electromigration evaluation can be performed on the branch electrode of the same material as the wiring pattern.

  At this time, since the change in characteristics of the evaluation chip at a high temperature is automatically measured periodically by the electromigration evaluation apparatus, the electromigration can be evaluated without human intervention. In addition, since the electromigration evaluation apparatus conducts the energization to the wiring pattern and the measurement of the characteristic change of the evaluation chip in a common temperature environment, the electromigration can be evaluated with high accuracy. Therefore, according to this invention, evaluation regarding the electromigration of LED can be implemented suitably, without taking an effort.

  Preferably, the electromigration evaluation apparatus has a stage formed of ceramic. In the step of mounting the evaluation chip on the electromigration evaluation apparatus, the evaluation chip is mounted on the stage.

  According to the reliability evaluation method of the LED configured as described above, the heat dissipation of the stage is enhanced, so that the electromigration evaluation is performed under a higher temperature condition or for a longer time. it can.

  As described above, according to the present invention, it is possible to provide an LED reliability evaluation method in which evaluation relating to electromigration is suitably performed without taking time and effort.

It is a perspective view which shows the LED wafer used for the reliability evaluation method of LED in embodiment of this invention. It is a top view which shows the LED chip obtained from the LED wafer in FIG. It is a top view which shows the chip | tip for evaluation obtained from the LED wafer in FIG. It is sectional drawing which shows the LED chip along the IV-IV line | wire in FIG. FIG. 5 is a cross-sectional view showing the evaluation chip along the line VV in FIG. 3. It is a figure which shows the flow of a step of the reliability evaluation method of LED in embodiment of this invention. It is a top view which shows the electromigration evaluation apparatus used for the reliability evaluation method of LED in embodiment of this invention. It is a perspective view which shows the mode of the electricity test for a comparison. It is sectional drawing which shows the chip | tip for evaluation used in the present Example. It is a graph which shows the relationship between wiring resistance and self-heating temperature. It is a table | surface which shows wiring resistance and self-heating temperature. It is a graph which shows progress which calculates activation energy from the result of an energization test. It is a table | surface which shows the lifetime of the various evaluation chip | tip calculated in the present Example.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings referred to below, the same or corresponding members are denoted by the same reference numerals. The dimensional relationships such as length, width, thickness, and depth shown in the drawings are changed as appropriate for clarity and simplification of the shape, and do not represent actual dimensional relationships.

  FIG. 1 is a perspective view showing an LED wafer used in an LED reliability evaluation method according to an embodiment of the present invention. FIG. 2 is a plan view showing an LED chip obtained from the LED wafer in FIG. FIG. 3 is a plan view showing an evaluation chip obtained from the LED wafer in FIG.

  With reference to FIGS. 1 to 3, in the LED reliability evaluation method in the present embodiment, a plurality of LED chips 21 are obtained from the LED wafer 10 and the evaluation of the LED chips 21 related to electromigration is performed. An evaluation chip 51 is obtained. First, the structure of each of the LED chip 21 and the evaluation chip 51 will be described.

  FIG. 4 is a cross-sectional view showing the LED chip along the line IV-IV in FIG. 2 and 4, LED chip 21 is a double heterojunction blue LED chip.

  The LED chip 21 includes an insulating substrate 22, a lower clad layer 23, a light emitting (active) layer 24, an upper clad layer 25, and a contact layer 26. On the main surface 22a of the insulating substrate 22, a lower clad layer 23, a light emitting layer 24, an upper clad layer 25, and a contact layer 26 are laminated in the order given. The insulating substrate 22 is made of sapphire. The lower cladding layer 23 is formed of an n-type GaN layer to which Si is added. The light emitting layer 24 is formed of an InGaN layer. The upper cladding layer 25 is made of p-type AlGaN to which Mg is added. The lower cladding layer 23, the light emitting layer 24, and the upper cladding layer 25 constitute a compound semiconductor layer 28.

  The LED chip 21 further includes a conductive thin film 27, a p-type electrode 31, and an n-type electrode 36. The conductive thin film 27 is formed on the contact layer 26. A p-type electrode 31 is formed on the conductive thin film 27. In the LED chip 21, a step is provided between the conductive thin film 27 and the lower cladding layer 23 so that the surface of the lower cladding layer 23 is partially exposed. An n-type electrode 36 is formed on the exposed surface of the lower cladding layer 23.

  When the LED chip 21 is viewed in plan, the p-type electrode 31 and the n-type electrode 36 are arranged at a distance from each other. The p-type electrode 31 and the n-type electrode 36 are planes parallel to the main surface 22a of the insulating substrate 22 and are arranged on different planes.

  When a current is supplied from the p-type electrode 31, the current diffuses in the surface direction of the conductive thin film 27. When the current supplied from the p-type electrode 31 flows through the upper cladding layer 25 and the light emitting layer 24 over a wide area, the light emitting layer 24 emits light.

  Light emitted from the light emitting layer 24 passes through the upper cladding layer 25, the contact layer 26 and the conductive thin film 27 and is extracted outside. As the conductive thin film 27, for example, a highly translucent material such as ITO (Indium Tin Oxide) is used. Thereby, the light loss when the light emitted from the light emitting layer 24 passes through the conductive thin film 27 can be reduced. In addition, since the conductive thin film 27 made of ITO has a lower resistance than the contact layer 26, diffusion of an operating current for obtaining light emission to a wide range is promoted. Thereby, since the expansion of the light emission area is brought about, the light emission efficiency can be improved.

  The LED chip 21 in the present embodiment has a p-side branch electrode 32p and a p-side branch electrode 32q (hereinafter referred to as a p-side branch electrode 32 unless otherwise specified) for the purpose of efficiently supplying current to the entire conductive thin film 27. And an n-side branch electrode 37.

  The p-side branch electrode 32 is formed continuously from the p-type electrode 31. The p-side branch electrode 32 is formed extending linearly from the p-type electrode 31 toward the n-type electrode 36. The n-side branch electrode 37 is formed continuously from the n-type electrode 36. The n-side branch electrode 37 is formed to extend linearly from the n-type electrode 36 toward the p-type electrode 31. The p-side branch electrode 32p and the p-side branch electrode 32q extend on both sides of the n-side branch electrode 37, respectively. The p-side branch electrode 32 and the n-side branch electrode 37 extend in parallel to each other. The p-side branch electrode 32p and the p-side branch electrode 32q extend in parallel to each other. The p-side branch electrode 32 and the n-side branch electrode 37 are formed with a certain width B. An n-side branch electrode 37 extending from the n-type electrode 36 is disposed between the p-side branch electrode 32 extending from the p-type electrode 31 and the distance between the p-side branch electrode 32 and the n-side branch electrode 37 is maintained constant. Improves diffusion efficiency.

  The p-type electrode 31, the p-side branch electrode 32, the n-type electrode 36, and the n-side branch electrode 37 are made of a conductive material such as Ti, Al, or Au, for example. These electrodes are not limited to a single layer structure, and may have a multilayer structure. In the LED chip 21, a p-type electrode 31 and a p-side branch electrode 32, an n-type electrode 36 and an n-side branch electrode 37 are provided separately on the compound semiconductor layer 28.

  The structure of the LED chip 21 described above is an example, and the bonding structure of the compound semiconductor layers, the material forming each layer, and the like are not limited to the above.

  FIG. 5 is a cross-sectional view showing the evaluation chip along the line VV in FIG. With reference to FIG. 3 and FIG. 5, the evaluation chip 51 is a chip for performing the evaluation of the LED chip 21 related to electromigration.

  Similar to the LED chip 21, the evaluation chip 51 includes an insulating substrate 22, a lower cladding layer 23, a light emitting layer 24, an upper cladding layer 25, a contact layer 26, and a conductive thin film 27. On the main surface 22a of the insulating substrate 22, a lower clad layer 23, a light emitting layer 24, an upper clad layer 25, a contact layer 26 and a conductive thin film 27 are laminated in the order given. The material forming each layer is the same as that of the LED chip 21. The evaluation chip 51 has the same size as the LED chip 21. However, the evaluation chip 51 is different from the LED chip 21 in that no step is provided between the conductive thin film 27 and the lower cladding layer 23.

  The evaluation chip 51 further includes a pad portion 41 and a pad portion 42 as a wiring pattern, and a wiring portion 46. The pad part 41, the pad part 42 and the wiring part 46 are formed on the conductive thin film 27. Pad portion 41, pad portion 42 and wiring portion 46 are arranged on the same plane parallel to main surface 22 a of insulating substrate 22. When the evaluation chip 51 is viewed in plan, the pad portion 41 and the pad portion 42 are provided apart from each other.

  The wiring part 46 extends between the pad part 41 and the pad part 42. The wiring part 46 is formed extending linearly. The wiring portion 46 extends meandering while changing the traveling direction by 90 °. The wiring part 46 is formed between the pad part 41 and the pad part 42 so as to have the same width B as the p-side branch electrode 32 and the n-side branch electrode 37 of the LED chip 21. The wiring part 46 is formed between the pad part 41 and the pad part 42 so as to have the same cross-sectional shape as the p-side branch electrode 32 and the n-side branch electrode 37.

  In addition, the wiring part 46 is not restricted to the shape shown in the figure, For example, it may be formed extending linearly between the pad part 41 and the pad part 42.

  The pad part 41, the pad part 42, and the wiring part 46 are made of the same material as the p-side branch electrode 32 and the n-side branch electrode 37 of the LED chip 21. The pad part 41, the pad part 42 and the wiring part 46, and the p-side branch electrode 32 and the n-side branch electrode 37 have the same structure. For example, when the electrode of the LED chip 21 has a multilayer structure, the pad part 41, the pad The part 42 and the wiring part 46 also have a multilayer structure. In the evaluation chip 51, the pad portion 41 and the pad portion 42 are provided so as to be connected to each other by the wiring portion 46 on the compound semiconductor layer 28.

  FIG. 6 is a diagram showing a flow of steps of the LED reliability evaluation method according to the embodiment of the present invention. FIG. 7 is a plan view showing an electromigration evaluation apparatus used in the LED reliability evaluation method according to the embodiment of the present invention. Next, the LED reliability evaluation method in the present embodiment will be described.

  Referring to FIGS. 1 and 6, first, compound semiconductor layer 28 is formed on disc-shaped insulating substrate 22 (S101). Specifically, the compound semiconductor layer 28 is epitaxially grown on the insulating substrate 22 using the MOCVD method. Further, the contact layer 26 and the conductive thin film 27 are formed on the compound semiconductor layer 28.

  Next, the p-type electrode 31, the n-type electrode 36, the p-side branch electrode 32, and the n-side branch electrode 37 in FIG. 2 are formed in the main region 14 on the insulating substrate 22 (S102). 1 is formed in the TEG (Test Element Group) region 12 to obtain the LED wafer 10 in FIG. At this time, these electrodes and wiring patterns are formed by using known photolithography, electron beam evaporation and lift-off methods. The p-type electrode 31 and the p-side branch electrode 32 in the main region 14, and the pad portion 41, the pad portion 42, and the wiring portion 46 in the TEG region 12 are simultaneously formed using a common mask.

  Next, by cutting the insulating substrate 22, a plurality of LED chips 21 are obtained from the main region 14, and an evaluation chip 51 is obtained from the TEG region 12 (S104).

  Subsequently, the evaluation chip 51 is used to evaluate the LED chip 21 related to electromigration.

  Referring to FIGS. 6 and 7, specifically, first, evaluation chip 51 is mounted on electromigration evaluation apparatus 71 (S105).

  The electromigration evaluation apparatus 71 includes a stage 72 for mounting a test piece, and a plurality of pad portions provided around the stage 72 for electrically connecting the test piece mounted on the stage 72 and the evaluation apparatus. 73. The electromigration evaluation apparatus 71 has a function of applying a stress current of an arbitrary magnitude to the test piece mounted on the stage 72 through the pad portion 73 and a function of automatically measuring the wiring resistance in the test piece. The electromigration evaluation apparatus 71 includes an oven (not shown), and can freely set the ambient temperature of the test piece mounted on the stage 72.

  In step S105, the evaluation chip 51 as a test piece is placed on the stage 72, and between the pad portion 41 and the pad portion 42 of the evaluation chip 51 and the pad portion 73 of the electromigration evaluation apparatus 71. Connect by wire bonding.

  Next, the electromigration evaluation apparatus 71 energizes the wiring portion 46 of the evaluation chip 51 at a predetermined high temperature, and automatically changes the characteristics of the evaluation chip 51 at high temperatures periodically (S106). In the present embodiment, the electromigration evaluation apparatus 71 automatically measures the wiring resistance in the periodic wiring section 46 after 100 h, 500 h, 1000 h, etc. in a high temperature environment.

  When comparing the LED chip 21 and the evaluation chip 51, the p-type electrode 31 and the n-type electrode 36 are separated on the compound semiconductor layer 28 in the LED chip 21, whereas in the evaluation chip 51, The pad portion 41 and the pad portion 42 are connected by the wiring portion 46. With such a configuration, when a current is supplied to the pad portions 41 and 42 of the evaluation chip 51, the current flows preferentially to the low resistance wiring portion 46, so that it is separated from the compound semiconductor layer 28 that is an epitaxial growth layer. Reliability evaluation of only the wiring part 46 can be performed.

  The wiring portion 46 is formed of the same material as the p-side branch electrode 32 and the n-side branch electrode 37, and in the present embodiment, is formed to have the same width as the p-side branch electrode 32 and the n-side branch electrode 37. . For this reason, the electromigration evaluation for the p-side branch electrode 32 and the n-side branch electrode 37 of the LED chip 21 can be performed through an energization test to the wiring portion 46.

  FIG. 8 is a perspective view showing a state of an energization test for comparison. With reference to FIG. 8, a method of mounting the evaluation chip 51 on the TO18 stem 76 is an example of a method for conducting an energization test on the evaluation chip 51. However, in such a method, the evaluation chip 51 that has been subjected to a current test in a high temperature environment is periodically taken out, the IV characteristics are measured with a manual measuring instrument, and the wiring resistance is calculated to determine the aging time. It is necessary to evaluate the rate of change for each. In addition, when the LED is energized, heat (Joule heat) generated by the energization is almost loaded as a heat amount in the chip, and the temperature rapidly decreases when the energization is stopped. When the TO18 stem 76 is used, a delay time must be generated between the energization test and the wiring resistance measurement, and thus the characteristics of the evaluation chip 51 cannot be measured accurately.

  On the other hand, in the present embodiment, since the electromigration evaluation apparatus 71 automatically automatically measures the change in the wiring resistance in the wiring section 46, the labor required for the test can be greatly reduced. In addition, since the wiring resistance is measured while maintaining the test environment under high temperature, the activation energy and self-heating value, which will be described later, are calculated more accurately, and the life of the chip is also calculated accurately. can do.

  Furthermore, in the present embodiment, the stage 72 on which the evaluation chip 51 is mounted is formed from ceramic. According to such a configuration, since the heat dissipation of the stage 72 is improved, the electromigration evaluation can be performed under a higher temperature environment or for a longer time.

  In the above-described reliability evaluation method, one evaluation chip 51 is mounted on the stage 72, but a plurality of evaluation chips 51 can also be mounted. In this case, a plurality of evaluation chips having different layouts can be simultaneously evaluated under the same test conditions. The electromigration evaluation apparatus 71 can also evaluate a plurality of evaluation chips under different test conditions.

  In the reliability evaluation method described above, the electromigration was evaluated by energizing the wiring portion 46 having the same width as that of the p-side branch electrode 32 and the n-side branch electrode 37. However, a plurality of wiring portions 46 having different widths are used. The electromigration may be evaluated for each wiring portion 46 by energizing each of the wiring portions 46. In this case, it is possible to specify the minimum branch electrode width in which electromigration is not a problem. Hereinafter, examples of such a reliability evaluation method will be described.

  FIG. 9 is a cross-sectional view showing the evaluation chip used in this example. In the drawing, a cross section of the evaluation chip 51 along the line IX-IX in FIG. 3 is shown. In this example, four types of evaluation chips 51 in which the line width of the wiring portion 46 is 5 μm or 8 μm and the electrode thickness of the pad portions 41 and 42 is 750 nm or 1050 nm were prepared as samples. Then, as shown in FIG. 7, the evaluation chip 51 is placed on the stage 72, and between the pad portions 41 and 42 of each evaluation chip 51 and the pad portion 73 of the electromigration evaluation apparatus 71. Connected by wire bonding.

  FIG. 10 is a graph showing the relationship between the wiring resistance and the self-heating temperature. FIG. 11 is a table showing wiring resistance and self-heating temperature.

  Next, in a state where the ambient temperature was set to 60 ° C., 120 ° C., 180 ° C., and 250 ° C., the wiring portion 46 was slightly energized through the pad portions 41 and 42, and the wiring resistance was measured. 10 and 11 show the wiring resistance and self-heating temperature for each wiring width when the ambient temperature is set to 250 ° C.

  Next, at each ambient temperature, the current value (I) and the voltage value (V) were measured for each energization time. In this example, the current value (I) and the voltage value (V) were measured by setting the applied current to the wiring portion 46 to 120 mA, 150 mA and 180 mA, and the elapsed time to 100 h, 500 h and 1000 h.

  FIG. 12 is a graph showing a process of calculating the activation energy from the result of the energization test. FIG. 13 is a table showing the lifetimes of various evaluation chips calculated in this example.

Referring to FIG. 12, the activation energy was calculated from the result of the energization test when the applied current was 120 mA. In the graph in which the vertical axis is ln [MTTF (mean time to failure)] and the horizontal axis is 1 / T (temperature) (K ⁻¹ ), 60 ° C., 100 ° C. and 150 ° C. The results of life conversion after 1000 hours at each temperature are plotted. The activation energy Ea is obtained by the product of the slope (slope) of the straight line in the graph and the Boltzmann constant (k). In this embodiment, slope = 13200 and Ea = 1.14.

  On the basis of the self-heating temperature shown in FIG. 10 and the activation energy shown in FIG. The results are shown in the table in FIG. From the results shown in FIG. 13, it can be confirmed that if the p-side branch electrode 32 and the n-side branch electrode 37 in FIG. 2 have a width of 5 μm or more, no problem in electromigration occurs. Further, it was confirmed that even if the electrode film thickness was reduced to 700 nm, no problem was caused.

  As described above, the LED reliability evaluation method according to the embodiment of the present invention includes the p region as the first electrode in the main region 14 as the first region on the insulating substrate 22 on which the compound semiconductor layer 28 is formed. Forming a p-type branch electrode 32 and an n-type side branch electrode 37 as a branch electrode extending linearly from at least one of the p-type electrode 31 and the n-type electrode 36 A pad portion 41, a pad portion 42, and a wiring portion as a wiring pattern formed of the same material as the p-side branch electrode 32 and the n-side branch electrode 37 in the TEG region 12 as the second region on the insulating substrate 22. 46, and cutting the insulating substrate 22 to obtain the LED chip 21 from the main region 14 and the evaluation chip from the TEG region 12. Comprising obtaining a flop 51, using the evaluation chip 51 obtained from the TEG region 12, and a step of performing an evaluation to electromigration the LED. The step of performing the evaluation on the electromigration of the LED includes the step of mounting the evaluation chip 51 on the electromigration evaluation device 71 and the pad portion 41, the pad portion 42 and the wiring portion at a predetermined high temperature by the electromigration evaluation device 71. 46, and automatically and periodically measuring changes in characteristics of the evaluation chip 51 at high temperatures.

  According to the LED reliability evaluation method in the embodiment of the present invention configured as described above, when the evaluation chip 51 is energized, the current is supplied to the wiring portion 46 having a lower resistance than the compound semiconductor layer 28. Therefore, electromigration evaluation can be performed on the p-side branch electrode 32 and the n-side branch electrode 37 formed of the same material as that of the wiring portion 46. Furthermore, in the present embodiment, since the LED chip 21 and the evaluation chip 51 are simultaneously formed in the same process, the manufacturing process of the evaluation chip 51 can be simplified.

  In the present embodiment, the electromigration evaluation apparatus 71 periodically and automatically measures changes in characteristics of the evaluation chip 51 at high temperatures, so that the electromigration evaluation work can be simplified without human intervention. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is mainly suitably used for reliability evaluation of LEDs used for illumination, backlights of liquid crystal televisions, and the like.

  10 LED wafer, 12 TEG region, 14 main region, 21 LED chip, 22 insulating substrate, 22a main surface, 23 lower cladding layer, 24 light emitting layer, 25 upper cladding layer, 26 contact layer, 27 conductive thin film, 28 compound Semiconductor layer, 31 p-type electrode, 32, 32p, 32q p side branch electrode, 36 n type electrode, 37 n side branch electrode, 41, 42 pad part, 46 wiring part, 51, 52 evaluation chip, 61, 66 electrode part, 62 62p, 62q, 67 Branch electrode part, 63, 63p, 63q, 68 Pad part, 71 Electromigration evaluation device, 72 stage, 73 pad part, 76 TO18 stem.

Claims (2)

A first electrode and a second electrode and a branch electrode extending linearly from at least one of the first electrode and the second electrode are formed in a first region on the insulating substrate on which the compound semiconductor layer is formed. And steps to
Forming a wiring pattern made of the same material as the branch electrode in the second region on the insulating substrate;
Cutting the insulating substrate to obtain an LED (Light Emitting Diode) chip from the first region, and obtaining an evaluation chip from the second region;
Using the evaluation chip obtained from the second region, and performing an evaluation on the electromigration of the LED,
The step of performing an evaluation on the electromigration of the LED comprises:
Mounting the evaluation chip on an electromigration evaluation apparatus;
A method for evaluating the reliability of an LED, comprising: energizing the wiring pattern at a predetermined high temperature by the electromigration evaluation apparatus and periodically automatically measuring a change in characteristics of the evaluation chip at a high temperature. The electromigration evaluation apparatus has a stage formed of ceramic,
The LED reliability evaluation method according to claim 1, wherein in the step of mounting the evaluation chip on an electromigration evaluation apparatus, the evaluation chip is mounted on the stage.

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