JP2013131651A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can manufacture a semiconductor device having a nitride semiconductor and high uniformity, with high yield.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming a nitride semiconductor layer on a substrate; forming a conductive film on the nitride semiconductor layer; forming a resist pattern on the conductive film; and removing the conductive film by dry etching in a region where the resist pattern is formed to form an electrode. An etching gas used for the dry etching is a gas in which a fluorine-containing gas or oxygen is added to a chlorine-containing gas.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A nitride semiconductor such as GaN, AlN, InN, or a mixed crystal material thereof has a wide band gap, and is used as a high-power electronic device, a short wavelength light-emitting device, or the like. Among these, as a high-power device, a technique related to a field-effect transistor (FET), in particular, a high electron mobility transistor (HEMT) has been developed (for example, Patent Document 1). ). HEMTs using such nitride semiconductors are used in high power / high efficiency amplifiers, high power switching devices, and the like.

  In the HEMT using a nitride semiconductor, for example, an aluminum gallium nitride / gallium nitride (AlGaN / GaN) heterostructure is formed on a substrate, and the GaN layer is an electron transit layer. As the substrate, a substrate formed of sapphire, silicon carbide (SiC), gallium nitride (GaN), silicon (Si), or the like is used.

  The band gap of GaN is 3.4 eV, which is larger than that of Si (1.1 eV) and GaAs (1.4 eV), and has a high breakdown voltage strength. Further, since the saturation electron velocity is high, high voltage operation and high output can be obtained, it can be used for a high-efficiency switching element, a high breakdown voltage power device for electric vehicles, and the like. Further, a device having an insulated gate structure in which an insulating film is formed under the gate electrode in order to suppress a leakage current in the transistor is disclosed (for example, Patent Document 2).

  As described above, in a HEMT using a nitride semiconductor, a gate electrode having a structure in which a metal nitride film having conductivity and a metal film are stacked is formed via an insulating film which is a nitride semiconductor or a gate insulating film. The thing of the structure which has been disclosed is disclosed (for example, patent document 3).

JP 2002-359256 A JP 2010-199481 A JP 2009-33041 A

  Here, a case where a metal nitride film for forming a gate electrode is formed on a nitride semiconductor will be described with reference to FIGS. First, as shown in FIG. 1, a buffer layer (not shown) is formed on a substrate 910 such as a Si wafer, and further, a nitride semiconductor layer 920 such as GaN and AlGaN is formed by epitaxial growth. Thereafter, a conductive film 930 such as TiN is formed on the nitride semiconductor layer 920 by sputtering or the like, a photoresist is applied to the surface of the conductive film 930, and a gate electrode is formed by exposure and development with an exposure apparatus. A resist pattern 940 is formed in the region to be formed. In the case of HEMT or the like, the nitride semiconductor layer 920 is formed of a laminated film of GaN and AlGaN or the like.

  Next, as shown in FIG. 2, the conductive film 930 in the region where the resist pattern 940 is not formed is removed by performing dry etching such as RIE (Reactive Ion Etching). At this time, the conductive film 930 in the region where the resist pattern 940 is not formed is completely removed, and the conductive film 930 is formed on the nitride semiconductor layer 920 in the region where the resist pattern 940 is formed.

  By the way, when a conductive film 930 such as a TiN film is formed on a substrate 910 such as a Si wafer by sputtering, the film thickness of the formed conductive film 930 is different between the central portion and the peripheral portion of the substrate 910. . That is, as shown in FIG. 1A, a thick film is formed at the central portion of the substrate 910, and a thin film is formed at the peripheral portion as shown in FIG. Specifically, when the TiN film, which is the conductive film 930, is formed in the central portion of the substrate 910 by sputtering to have a thickness of about 200 nm, the conductive film is formed in the peripheral portion of the semiconductor substrate 920. The film thickness of the TiN film 930 is about 175 nm. Thus, when the TiN film as the conductive film 930 is formed by sputtering, an in-plane distribution of the film thickness in the TiN film is generated. Therefore, in the formed TiN film, the central portion and the peripheral portion of the substrate 910 Thus, a film thickness difference of about 25 nm occurs.

  Therefore, as shown in FIG. 2, when dry etching such as RIE is performed using chlorine gas or the like, the substrate 910 shown in FIG. 2B is more than the central portion of the substrate 910 shown in FIG. In the peripheral portion, a large amount of the nitride semiconductor layer 920 is removed by etching. For this reason, variations in semiconductor devices to be manufactured may occur, and yield and the like may decrease. Even in the case where a semiconductor device having a structure in which the nitride semiconductor layer 920 is over-etched is manufactured, the nitride according to the thickness difference of the TiN film as the conductive film 930 between the central portion and the peripheral portion of the substrate 920 The amount of etching of the semiconductor layer 920 is different. Therefore, the thickness of the nitride semiconductor layer 920 after etching varies in the central portion and the peripheral portion of the substrate 910.

Incidentally, when the TiN film as the conductive film 930 is removed by dry etching, chlorine gas or the like is generally used as an etching gas. In this case, the etching rate ratio between the conductive film 930 and the nitride semiconductor layer 920 is about 1. Specific etching conditions include, for example, supplying ₁₀ to 150 sccm of Cl ₂ into the chamber of the ECR etching apparatus, setting the pressure in the chamber to ₂ to 10 mTorr, top power of 600 to 1200 W, and bias (bottom) power of 30. ˜80W. Note that in this embodiment, the ratio of the etching rate of the conductive film 930 to the nitride semiconductor layer 920 may be referred to as the selection ratio of the conductive film 930 to the nitride semiconductor layer 920 in some cases.

  On the other hand, as described in Patent Document 3, there is also a method of forming a conductive film by nitriding a metal oxide film formed on a nitride semiconductor. However, this method uses a nitrogen radical or the like and requires a special apparatus or the like, so that it is difficult to easily form a metal nitride film. In addition, when nitriding an oxide, the nitride semiconductor may be damaged, which is not preferable because yield in a manufactured semiconductor device is reduced.

  Therefore, when forming the gate electrode or the like, the difference in the etching amount of the nitride semiconductor can be reduced between the central portion and the peripheral portion of the substrate, and the semiconductor device has high uniformity and high yield. There is a need for a manufacturing method.

  According to one aspect of the present embodiment, a step of forming a nitride semiconductor layer over a substrate, a step of forming a conductive film over the nitride semiconductor layer, and over the conductive film, Forming a resist pattern; and removing the conductive film in the region where the resist pattern is formed by dry etching to form an electrode; and the etching gas used for the dry etching is a chlorine component A gas containing fluorine is added to a gas containing a fluorine component or oxygen.

  According to the disclosed method for manufacturing a semiconductor device, when forming a gate electrode or the like, the difference in the etching amount of the nitride semiconductor can be reduced between the central portion and the peripheral portion of the substrate. And a high yield semiconductor device can be manufactured.

Explanatory drawing of variation in etching amount in dry etching (1) Explanatory drawing of variation in etching amount in dry etching (2) Relationship diagram between gas added to etching gas and selectivity Explanatory drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Explanatory drawing (2) of the manufacturing method of the semiconductor device in 1st Embodiment Explanatory drawing (3) of the manufacturing method of the semiconductor device in 1st Embodiment Explanatory drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Explanatory drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Explanatory drawing (3) of the manufacturing method of the semiconductor device in 2nd Embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
First, the results of studying the etching rate between the nitride semiconductor layer and the metal nitride film that becomes the conductive film will be described. As described above, when dry etching is performed, variation in the etching amount of the nitride semiconductor layer occurs in the central portion and the peripheral portion of the substrate. This variation is caused by the difference in film thickness of the metal nitride film formed between the central portion and the peripheral portion of the substrate. Accordingly, if the film can be formed by a film forming method such as sputtering so that the metal nitride film has a uniform thickness, the etching amount of the nitride semiconductor layer is substantially the same in the central portion and the peripheral portion of the substrate. Can be. However, it is difficult for a film forming method such as sputtering to form a metal nitride film such as a TiN film so that the film thickness is uniform over the entire surface of the substrate.

  By the way, when the etching rate of the metal nitride film is faster than the etching rate of the nitride semiconductor layer, even if the film thickness of the metal nitride film such as TiN is not uniform in the central portion and the peripheral portion of the substrate. The difference in the etching amount of the nitride semiconductor layer can be reduced. That is, when the ratio of the etching rate of the metal nitride film to the etching rate of the nitride semiconductor layer (selection ratio) is about 1, when the selection ratio is about 10, the overetching amount in the peripheral portion is It becomes about 1/10. Specifically, when the selection ratio is about 1, the overetching amount in the peripheral portion is about 25 nm. By setting the selection ratio to about 10, the overetching amount in the peripheral portion is about 2. 5 nm. By increasing the selection ratio in this manner, the difference in the etching amount of the nitride semiconductor layer between the central portion and the peripheral portion of the substrate can be reduced, and the variation in the etching amount of the nitride semiconductor layer can be reduced. be able to. Thereby, the uniformity of the characteristic of the semiconductor device manufactured can be improved, and also the yield can be improved.

  Based on such a viewpoint, the inventor examined the relationship between the etching gas used in dry etching such as RIE and the ratio of the etching rate, that is, the selection ratio. The results of this study are shown in FIG. In FIG. 3, GaN is used as the nitride semiconductor, and TiN is used as the nitride metal film. In the present embodiment, RIE includes ECR (Electron Cyclotron Resonance) etching and ICP (Inductively coupled plasma) etching in addition to the parallel plate type. The results shown in FIG. 3 were obtained by ECR etching.

Condition 1 is a case where Cl ₂ (chlorine) is used as an etching gas used for dry etching. In this case, the selectivity of TiN to GaN (ratio of etching rate) is about 1.3, and the selectivity of TiN to photoresist is about 1.4. The bias power in dry etching is about 60 W, which is a relatively high power.

Condition 2 is a case in which 3% of SF ₆ is mixed with Cl ₂ as an etching gas used for dry etching. In this case, the selectivity ratio of TiN to GaN is about 5.4, and the selectivity ratio of TiN to the photoresist is about 1.1. The bias power in dry etching is about 60 W, which is a relatively high power.

Condition 3 is a case where 8% of SF ₆ is mixed into Cl ₂ as an etching gas used for dry etching. In this case, the selectivity of TiN to GaN is about 6.2, and the selectivity of TiN to photoresist is about 0.4. The bias power in dry etching is about 60 W, which is a relatively high power.

Condition 4 is a case where 3% of SF ₆ is mixed with Cl ₂ as an etching gas used for dry etching. In this case, the selectivity ratio of TiN to GaN is about 9.4, and the selectivity ratio of TiN to the photoresist is about 0.8. The bias power in dry etching is about 30 W, which is a relatively low power.

Condition 5 is a case where 6% of SF ₆ is mixed with Cl ₂ as an etching gas used for dry etching. In this case, the selectivity of TiN to GaN is about 12, and the selectivity of TiN to photoresist is about 0.6. The bias power in dry etching is about 30 W, which is a relatively low power.

Condition 6 is a case where an etching gas used for dry etching is a mixture of Cl ₂ mixed with 10% O ₂ . In this case, the selection ratio of TiN to GaN is about 6.3, and the selection ratio of TiN to photoresist is about 0.7. The bias power in dry etching is about 60 W, which is a relatively high power.

Condition 7 is a case where an etching gas used for dry etching is a mixture of Cl ₂ mixed with 20% O ₂ . In this case, the selectivity of TiN to GaN is about 6.7, and the selectivity of TiN to photoresist is about 0.5. The bias power in dry etching is about 60 W, which is a relatively high power.

As described above, based on the results shown in FIG. 3, in dry etching, the selectivity of TiN to GaN can be increased by using an etching gas in which SF ₆ or O ₂ is mixed into Cl _2. . Moreover, the more SF ₆ or O ₂ mixed in the etching gas, the higher the selectivity of TiN to GaN. However, if SF ₆ or O ₂ mixed in the etching gas is large, the etching rate is lowered. In addition, the bias power in dry etching can increase the TiN to GaN selection ratio at about 30 W, which is a relatively low power, compared to about 60 W, which is a relatively high power. In order to increase the selection ratio to 6 or more, when SF ₆ is mixed into Cl ₂ , SF ₆ is 8% or more when the bias power is about 60 W, and SF ₆ is 3% or more when the bias power is about 30 W. It is preferable to mix. Further, when O ₂ is mixed into Cl ₂ , it is preferable to mix O ₂ by 10% or more.

  As described above, the present invention has been made based on the results of studies by the inventors.

(Method for manufacturing semiconductor device)
Next, the semiconductor device in the first embodiment will be described. The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a HEMT using a nitride semiconductor, and will be described with reference to FIGS.

  First, as shown in FIG. 4A, a nitride semiconductor layer is formed on the substrate 10. Specifically, a buffer layer (not shown) that becomes a nitride semiconductor layer, an electron transit layer 21, an electron supply layer 22, and a cap layer 23 are sequentially formed on a substrate such as Si by a MOVPE (Metal Organic Vapor Phase Epitaxy) method. It is formed by epitaxial growth. As a result, 2DEG (two dimensional electron gas) 21 a is formed in the electron transit layer 21 in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22.

  As the substrate 10, a substrate such as Si, sapphire, SiC, GaN, or AlN can be used.

  The electron transit layer 21 is a layer that becomes a first semiconductor layer, and is formed of an intentionally undoped GaN having a thickness of about 3 μm.

The electron supply layer 22 is a layer that becomes a second semiconductor layer, and is formed of an intentionally undoped Al _0.25 Ga _0.75 N having a thickness of about 20 nm. The electron supply layer 22 may be an n-type layer doped with an impurity element such as Si.

  The cap layer 23 is a layer that becomes a third semiconductor layer, and is formed of GaN or AlGaN having a thickness of about 5 nm. In the present embodiment, the cap layer 23 is formed of n-GaN doped with an impurity element such as Si.

In the present embodiment, in MOVPE, TMG (trimethylgallium) is used as the Ga source gas, TMA (trimethylaluminum) is used as the Al source gas, and NH ₃ (ammonia) is used as the N source gas. For this source gas, SiH ₄ (monosilane) or the like is used. These source gases are supplied to the reactor of the MOVPE apparatus using hydrogen (H ₂ ) as a carrier gas.

  Next, as shown in FIG. 4B, a TiN film as the conductive film 30a is formed on the cap layer 23 by sputtering to a thickness of about 200 nm. The conductive film 30a is for forming a gate electrode 30 to be described later, and is formed of a film having a metal nitride film, that is, a metal nitride film or a laminated film of a metal nitride film and a metal film. . The metal nitride film may be any material that is a metal nitride and has conductivity, and specifically includes TaN, TiN, ZrN, WN, VN, TiSiN, TaCN, and the like. Further, when the conductive film 30a is formed of a laminated film of a metal nitride film and a metal film, a laminated film of Ti / TiN, Al / TaN, or the like can be given.

  Next, as shown in FIG. 4C, a resist pattern 40 is formed on the conductive film 30a. The resist pattern 40 is formed on a region where the gate electrode 30 is formed in the conductive film 30a. Specifically, a photoresist is applied on the TiN film which is the conductive film 30a, and exposure and development are performed by an exposure apparatus, whereby a resist pattern is formed on the conductive film 30a on the region where the gate electrode 30 is formed. 40 is formed. The film thickness of the resist pattern 40 formed at this time is about 1.2 μm.

Next, as shown in FIG. 5A, the conductive film 30a in the region where the resist pattern 40 is not formed is removed by dry etching such as RIE, and the gate electrode 30 is formed. This condition is as follows: Cl ₂ is supplied at 10 to 50 sccm, N ₂ is supplied at 10 to 100 sccm, SF ₆ is supplied at ₂ to 10 sccm, the pressure in the chamber is set at ₂ to 10 mTorr, and the top power is 600 to 1200 W. The bias power is 3 to 30 W. Since the selection ratio of TiN to GaN under this condition is about 10, even if the TiN film thickness distribution (film thickness difference) is 25 nm, GaN is only removed by etching at a maximum of 2.5 nm. In this way, the gate electrode 30 is formed from the remaining metal nitride film by removing the TiN film that is the conductive film 30a in the region where the resist pattern 40 is not formed. In this embodiment, the case where SF ₆ is added to Cl ₂ as an etching gas has been described. However, a gas containing a fluorine component may be added to a gas containing a chlorine component. As the gas containing chlorine components, other Cl _2, BCl _3, CCl _4, and the like. Further, as the gas containing a fluorine component, other _{SF 6, F 2, CF 4} , NF 3 or the like. The selectivity of TiN to GaN in this step is effective because the difference in film thickness can be reduced to about half if it is 2 or more, but in order to reduce the difference in film thickness, 5 or more, 6 or more. The resist pattern 40 is removed with an organic solvent or the like.

Next, as shown in FIG. 5B, a first interlayer insulating film 50 is formed. Specifically, the first interlayer insulating film 50 is formed by forming a SiO ₂ film on the surface on which the gate electrode 30 is formed by a film forming method such as CVD or sputtering.

  Next, as shown in FIG. 5C, in the first interlayer insulating film 50, openings 51 and 52 are formed in a region where a source electrode 61 and a drain electrode 62 described later are formed. Specifically, a photoresist is applied on the first interlayer insulating film 50, and exposure and development are performed by an exposure apparatus, whereby openings 51 and 52 are formed in the first interlayer insulating film 50. A resist pattern (not shown) having an opening in the region is formed. Thereafter, the first interlayer insulating film 50 in the region where the resist pattern is not formed is removed by dry etching such as RIE or wet etching until the surface of the nitride semiconductor layer such as the cap layer 23 is exposed, and the opening 51 and 52 are formed. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as shown in FIG. 6A, a source electrode 61 and a drain electrode 62 are formed of a metal material such as Al in the openings 51 and 52 formed in the first interlayer insulating film 50. Specifically, a source electrode 61 and a drain electrode 62 are formed by applying a photoresist on the first interlayer insulating film 50 in which the openings 51 and 52 are formed, and performing exposure and development. A resist pattern (not shown) having an opening in a region to be formed is formed. Thereafter, a metal film of Al or the like is formed by vacuum deposition and immersed in an organic solvent or the like, thereby removing the metal film formed on the resist pattern together with the resist pattern by lift-off. As a result, the source electrode 61 is formed in the opening 51 in the first interlayer insulating film 50, and the drain electrode 62 is formed in the opening 52.

  Note that the source electrode 61 and the drain electrode 62 may be formed by methods other than those described above. Specifically, a metal film such as Al is formed by sputtering or the like on the first interlayer insulating film 50 in which the openings 51 and 52 are formed, and the source electrode 61 is further formed on the metal film. A resist pattern is formed on the region where the drain electrode 62 is to be formed. Thereafter, the metal film in a region where the resist pattern is not formed is removed by RIE or the like, and the resist pattern is removed by an organic solvent or the like, whereby the source electrode 61 and the drain electrode 62 can be formed from the remaining metal film. it can.

Next, as shown in FIG. 6B, a second interlayer insulating film 70 is formed on the first interlayer insulating film 50, the source electrode 61 and the drain electrode 62, and further, a second interlayer insulating film is formed. Openings 71, 72, and 73 are formed in the film 70 and the first interlayer insulating film 50. The openings 71, 72, and 73 are formed by removing the second interlayer insulating film 70 and the first interlayer insulating film 50 by etching until the surfaces of the source electrode 61, the drain electrode 62, and the gate electrode 30 are exposed. Form. More specifically, the second interlayer insulating film 70 is formed by forming a SiO ₂ film by a film forming method such as CVD or sputtering. Thereafter, a photoresist is applied onto the second interlayer insulating film 70, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the openings 71, 72 and 73 are formed (not shown). A resist pattern is formed. Thereafter, by performing dry etching such as RIE, the second interlayer insulating film 70 and the first interlayer insulating film 50 in the region where the resist pattern is not formed are removed, and the source electrode 61, the drain electrode 62, and the gate are removed. The surface of the electrode 30 is exposed. Thereby, openings 71, 72, and 73 can be formed in the second interlayer insulating film 70 and the first interlayer insulating film 50. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as illustrated in FIG. 6C, wiring layers 81, 82, and 83 connected to the source electrode 61, the drain electrode 62, and the gate electrode 30 are formed in the openings 71, 72, and 73. Specifically, a photoresist is applied on the second interlayer insulating film 70 in which the openings 71, 72, and 73 are formed, and exposure and development are performed, whereby the wiring layers 81, 82, and 83 are formed. A resist pattern (not shown) having an opening in the region to be formed is formed. Thereafter, a metal film of Al or the like is formed by vacuum deposition and immersed in an organic solvent or the like, thereby removing the metal film formed on the resist pattern together with the resist pattern by lift-off. Thus, a wiring layer 81 connected to the source electrode 61 in the opening 71, a wiring layer 82 connected to the drain electrode 62 in the opening 72, and a wiring layer 83 connected to the gate electrode 30 in the opening 73 are formed. .

  The method for forming the wiring layers 81, 82 and 83 may be other than the above. Specifically, a metal film such as Al is formed on the second interlayer insulating film 70 in which the openings 71, 72, and 73 are formed by sputtering or the like, and further, a wiring is formed on the metal film. A resist pattern is formed in a region where the layers 81, 82 and 83 are formed. Thereafter, the metal film in the region where the resist pattern is not formed is removed by dry etching such as RIE, and the resist pattern is removed by an organic solvent or the like, thereby forming the wiring layers 81, 82 and 83 from the remaining metal film. can do.

  As described above, the semiconductor device in this embodiment can be manufactured. The semiconductor device in the present embodiment may have a structure in which an insulating film serving as a gate insulating film is formed between the gate electrode 30 and the cap layer 23. In this case, after forming the cap layer 23, an insulating film to be a gate insulating film is formed, and a conductive film 30a is formed on the insulating film.

  Further, a structure in which a recess is formed by removing a part of the nitride semiconductor in a region where the gate electrode 31 is formed may be used. In this case, after forming the cap layer 23, a recess is formed by removing a part of the nitride semiconductor in the region where the gate electrode 31 is formed, and then a conductive film 30a is formed on the insulating film. Furthermore, the semiconductor device in the present embodiment may use InGaN as the electron supply layer 22.

  Further, although not shown, this embodiment can be applied to a semiconductor device using a nitride semiconductor in addition to a HEMT using a nitride semiconductor. Specifically, the present invention can also be applied to a method for manufacturing a semiconductor device having a step of forming a metal nitride electrode such as TiN on the surface of AlGaN, GaN, InAlN or the like by dry etching.

[Second Embodiment]
Next, a semiconductor device according to the second embodiment will be described. The semiconductor device manufacturing method according to the present embodiment is a HEMT manufacturing method using a nitride semiconductor having a structure different from that of the first embodiment, and will be described with reference to FIGS.

  First, as shown in FIG. 7A, a nitride semiconductor layer is formed on the substrate 10. Specifically, a buffer layer (not shown) serving as a nitride semiconductor layer, an electron transit layer 121, and an electron supply layer 122 are sequentially epitaxially grown on a substrate of Si or the like by MOVPE. As a result, 2DEG 121 a is formed in the electron transit layer 121 in the vicinity of the interface between the electron transit layer 121 and the electron supply layer 122.

  As the substrate 10, a substrate such as Si, sapphire, SiC, GaN, or AlN can be used.

  The electron transit layer 121 is a layer that serves as a first semiconductor layer, and is formed of intentionally undoped GaN having a thickness of about 3 μm.

The electron supply layer 122 is a layer that becomes a second semiconductor layer, and is formed of an intentionally undoped Al _0.25 Ga _0.75 N having a thickness of about 20 nm. Note that the electron supply layer 122 may be an n-type layer doped with an impurity element such as Si.

In the present embodiment, in MOVPE, TMG (trimethylgallium) is used as the Ga source gas, TMA (trimethylaluminum) is used as the Al source gas, and NH ₃ (ammonia) is used as the N source gas. For this source gas, SiH ₄ (monosilane) or the like is used. These source gases are supplied to the reactor of the MOVPE apparatus using hydrogen (H ₂ ) as a carrier gas.

  Next, as shown in FIG. 7B, a TiN film as the conductive film 30a is formed on the electron supply layer 122 by sputtering to a thickness of about 200 nm. The conductive film 30a is for forming a gate electrode 30 to be described later, and is formed of a film having a metal nitride film, that is, a metal nitride film or a laminated film of a metal nitride film and a metal film. . The metal nitride film may be any material that is a metal nitride and has conductivity, and specifically includes TaN, TiN, ZrN, WN, VN, TiSiN, TaCN, and the like. Further, when the conductive film 30a is formed of a laminated film of a metal nitride film and a metal film, a laminated film of Ti / TiN, Al / TaN, or the like can be given.

  Next, as shown in FIG. 7C, a resist pattern 40 is formed on the conductive film 30a. The resist pattern 40 is formed on a region where the gate electrode 30 is formed in the conductive film 30a. Specifically, a photoresist is applied on the TiN film which is the conductive film 30a, and exposure and development are performed by an exposure apparatus, whereby a resist pattern is formed on the conductive film 30a on the region where the gate electrode 30 is formed. 40 is formed. The film thickness of the resist pattern 40 formed at this time is about 1.2 μm.

Next, as shown in FIG. 8A, the conductive film 30a in the region where the resist pattern 40 is not formed is removed by dry etching such as RIE, and the gate electrode 30 is formed. This condition is as follows: Cl ₂ is supplied at 10 to 50 sccm, N ₂ is supplied at 10 to 100 sccm, SF ₆ is supplied at ₂ to 10 sccm, the pressure in the chamber is set at ₂ to 10 mTorr, and the top power is 600 to 1200 W. The bias power is 3 to 30 W. Since the selection ratio of TiN to GaN under this condition is about 10, even if the TiN film thickness distribution (film thickness difference) is 25 nm, GaN is only removed by etching at a maximum of 2.5 nm. In this manner, the TiN film as the conductive film 30a in the region where the resist pattern 40 is not formed is removed, and the gate electrode 30 is formed from the remaining metal nitride film. At this time, a part of the electron supply layer 122 in the region where the resist pattern 40 is not formed may be removed. In this embodiment, the case where SF ₆ is added to Cl ₂ as an etching gas has been described. However, a gas containing a fluorine component may be added to a gas containing a chlorine component. As the gas containing chlorine components, other Cl _2, BCl _3, CCl _4, and the like. Further, as the gas containing a fluorine component, other _{SF 6, F 2, CF 4} , NF 3 and the like. The resist pattern 40 is removed with an organic solvent or the like.

Next, as shown in FIG. 8B, a first interlayer insulating film 50 is formed. Specifically, the first interlayer insulating film 50 is formed by forming a SiO ₂ film on the surface on which the gate electrode 30 is formed by a film forming method such as CVD or sputtering.

  Next, as shown in FIG. 8C, in the first interlayer insulating film 50, openings 51 and 52 are formed in regions where a source electrode 61 and a drain electrode 62 described later are formed. Specifically, a photoresist is applied on the first interlayer insulating film 50, and exposure and development are performed by an exposure apparatus, whereby openings 51 and 52 are formed in the first interlayer insulating film 50. A resist pattern (not shown) having an opening in the region is formed. Thereafter, the first interlayer insulating film 50 in the region where the resist pattern is not formed is removed by dry etching such as RIE or wet etching until the surface of the nitride semiconductor layer such as the electron supply layer 122 is exposed, and the openings are opened. Portions 51 and 52 are formed. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as shown in FIG. 9A, a source electrode 61 and a drain electrode 62 are formed of a metal material such as Al in the openings 51 and 52 formed in the first interlayer insulating film 50. Specifically, a source electrode 61 and a drain electrode 62 are formed by applying a photoresist on the first interlayer insulating film 50 in which the openings 51 and 52 are formed, and performing exposure and development. A resist pattern (not shown) having an opening in a region to be formed is formed. Thereafter, a metal film of Al or the like is formed by vacuum deposition and immersed in an organic solvent or the like, thereby removing the metal film formed on the resist pattern together with the resist pattern by lift-off. As a result, the source electrode 61 is formed in the opening 51 in the first interlayer insulating film 50, and the drain electrode 62 is formed in the opening 52.

  Note that the source electrode 61 and the drain electrode 62 may be formed by methods other than those described above. Specifically, a metal film such as Al is formed by sputtering or the like on the first interlayer insulating film 50 in which the openings 51 and 52 are formed, and the source electrode 61 is further formed on the metal film. A resist pattern is formed on the region where the drain electrode 62 is to be formed. Thereafter, the metal film in a region where the resist pattern is not formed is removed by RIE or the like, and the resist pattern is removed by an organic solvent or the like, whereby the source electrode 61 and the drain electrode 62 can be formed from the remaining metal film. it can.

Next, as shown in FIG. 9B, a second interlayer insulating film 70 is formed on the first interlayer insulating film 50, the source electrode 61, and the drain electrode 62, and further, the second interlayer insulating film is formed. Openings 71, 72, and 73 are formed in the film 70 and the first interlayer insulating film 50. The openings 71, 72, and 73 are formed by removing the second interlayer insulating film 70 and the first interlayer insulating film 50 by etching until the surfaces of the source electrode 61, the drain electrode 62, and the gate electrode 30 are exposed. Form. More specifically, the second interlayer insulating film 70 is formed by forming a SiO ₂ film by a film forming method such as CVD or sputtering. Thereafter, a photoresist is applied onto the second interlayer insulating film 70, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the openings 71, 72 and 73 are formed (not shown). A resist pattern is formed. Thereafter, by performing dry etching such as RIE, the second interlayer insulating film 70 and the first interlayer insulating film 50 in the region where the resist pattern is not formed are removed, and the source electrode 61, the drain electrode 62, and the gate are removed. The surface of the electrode 30 is exposed. Thereby, openings 71, 72, and 73 can be formed in the second interlayer insulating film 70 and the first interlayer insulating film 50. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as illustrated in FIG. 9C, wiring layers 81, 82, and 83 connected to the source electrode 61, the drain electrode 62, and the gate electrode 30 are formed in the openings 71, 72, and 73. Specifically, a photoresist is applied on the second interlayer insulating film 70 in which the openings 71, 72, and 73 are formed, and exposure and development are performed, whereby the wiring layers 81, 82, and 83 are formed. A resist pattern (not shown) having an opening in the region to be formed is formed. Thereafter, a metal film of Al or the like is formed by vacuum deposition and immersed in an organic solvent or the like, thereby removing the metal film formed on the resist pattern together with the resist pattern by lift-off. Thus, a wiring layer 81 connected to the source electrode 61 in the opening 71, a wiring layer 82 connected to the drain electrode 62 in the opening 72, and a wiring layer 83 connected to the gate electrode 30 in the opening 73 are formed. .

  The method for forming the wiring layers 81, 82 and 83 may be other than the above. Specifically, a metal film such as Al is formed on the second interlayer insulating film 70 in which the openings 71, 72, and 73 are formed by sputtering or the like, and further, a wiring is formed on the metal film. A resist pattern is formed in a region where the layers 81, 82 and 83 are formed. Thereafter, the metal film in the region where the resist pattern is not formed is removed by dry etching such as RIE, and the resist pattern is removed by an organic solvent or the like, thereby forming the wiring layers 81, 82 and 83 from the remaining metal film. can do.

  As described above, the semiconductor device in this embodiment can be manufactured. In this embodiment, since the etching rate of AlGaN is substantially the same as the etching rate of GaN, variation in the etching amount in the electron supply layer 122 can be reduced as in the first embodiment. Further, even when the electron supply layer 122 is formed of InAlN, the etching rate of InAlN and GaN is substantially equal, so that the variation in the etching amount in the electron supply layer 122 can be similarly reduced.

  The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. In the present embodiment, dry etching conditions such as RIE when forming the gate electrode are different from those in the first embodiment and the second embodiment. Specifically, the gate electrode 30 is formed by removing a predetermined region in the conductive film 30a by dry etching. The conditions in this step are the first embodiment and the second embodiment. Is different. In the method of manufacturing the semiconductor device in the present embodiment, as shown in FIG. 4C in the first embodiment or FIG. 7C in the second embodiment, the resist pattern 40 is formed. After the formation, dry etching in this embodiment is performed. The dry etching in this embodiment performs two etching processes, that is, a first etching process and a second etching process.

First, a first etching process is performed. The conditions of the first etching process are as follows: Cl ₂ is supplied at 10 to 150 sccm, SF ₆ is supplied at 1 to 15 sccm, the pressure in the chamber is set at ₂ to 10 mTorr, the top power is 600 to 1200 W, and the bias is set. The power is 30-80W. Since the selection ratio of TiN to GaN under this condition is about 6, even if the TiN film thickness distribution (film thickness difference) is 25 nm, GaN is only removed by etching at a maximum of about 4 nm.

Next, a second etching process is performed. The conditions of the second etching process are as follows: Cl ₂ is supplied at 10 to 50 sccm, N ₂ is supplied at 10 to 100 sccm, SF ₆ is supplied at ₂ to 10 sccm, the pressure in the chamber is set at ₂ to 10 mTorr, and the top power is 600. ˜1200 W, bias power is 3 to 30 W. Since the selection ratio of TiN to GaN under this condition is about 10, even if the TiN film thickness distribution (film thickness difference) is 25 nm, GaN is only removed by etching at a maximum of 2.5 nm.

  The first etching process has a relatively low selectivity but a high etching rate, and the second etching process has a relatively high selectivity but a low etching rate. Therefore, the first etching process is performed until just before the surface of the nitride semiconductor layer is exposed, and then the second etching process is performed, so that the etching with less variation in the etching amount in the nitride semiconductor layer can be performed in a short time. Can be done. Thereby, the manufacturing time of a semiconductor device can be shortened and a semiconductor device can be manufactured at low cost.

In this embodiment, the selectivity in the second etching process is made higher than that in the first etching process by lowering the bias power of the dry etching in the second etching process than in the first etching process. Can do. Further, the selectivity in the second etching step is made higher than that in the first etching step by increasing the concentration of SF ₆ added to the etching gas in the second etching step in comparison with the first etching step. Can do. Further, the selection ratio can be further increased by combining both contents.

In this embodiment, the case where SF ₆ is added to Cl ₂ as an etching gas has been described. However, a gas containing a fluorine component or oxygen may be added to a gas containing a chlorine component. As the gas containing chlorine components, other Cl _2, BCl _3, CCl _4, and the like. Further, as the gas containing a fluorine component, other _{SF 6, F 2, CF 4} , NF 3 and the like.

  Thereafter, as shown in FIG. 5B in the first embodiment or FIG. 8B in the second embodiment, a first interlayer insulating film 50 is formed. The subsequent steps are the same as those in the first embodiment or the second embodiment. The contents other than those described above are the same as those in the first or second embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. In the present embodiment, dry etching conditions such as RIE when forming the gate electrode are different from those in the first embodiment and the second embodiment. Specifically, the gate electrode 30 is formed by removing a predetermined region in the conductive film 30a by dry etching. The conditions in this step are the first embodiment and the second embodiment. Is different. In the method of manufacturing a semiconductor device in the present embodiment, a resist pattern 40 is formed as shown in FIG. 4C in the first embodiment and FIG. 7C in the second embodiment. Thereafter, dry etching in this embodiment is performed.

The dry etching conditions are as follows: Cl ₂ is supplied in a chamber at 10 to 150 sccm, N ₂ is supplied at 0 to 100 sccm, O ₂ is supplied at ₅ to 30 sccm, the pressure in the chamber is set at ₂ to 10 mTorr, and the top power is 600 to 1200 W. The bias power is 30-80 W. Since the selection ratio of TiN to GaN under this condition is about 6, even if the TiN film thickness distribution (film thickness difference) is 25 nm, GaN is only removed by etching at a maximum of about 4 nm. As the gas containing chlorine components, other Cl _2, BCl _3, CCl ₄ and the like.

  Thereafter, as shown in FIG. 5B in the first embodiment or FIG. 8B in the second embodiment, a first interlayer insulating film 50 is formed. The subsequent steps are the same as those in the first embodiment or the second embodiment. The contents other than those described above are the same as those in the first or second embodiment.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
Forming a nitride semiconductor layer on the substrate;
Forming a conductive film on the nitride semiconductor layer;
Forming a resist pattern on the conductive film;
Forming the electrode by removing the conductive film in the region where the resist pattern is formed by dry etching;
Have
An etching gas used for the dry etching is obtained by adding a gas containing a fluorine component or oxygen to a gas containing a chlorine component.
(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the conductive film includes a conductive metal nitride film.
(Appendix 3)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the conductive film is a laminated film of a metal nitride film and a metal film.
(Appendix 4)
The metal nitride film is formed of a material containing one or more of TaN, TiN, ZrN, WN, VN, TiSiN, and TaCN. A method for manufacturing a semiconductor device.
(Appendix 5)
4. The method of manufacturing a semiconductor device according to appendix 2 or 3, wherein the metal nitride film is formed of a material containing TiN.
(Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein the conductive film is formed by sputtering.
(Appendix 7)
7. The method of manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the gas containing a chlorine component is a gas containing one or more of Cl ₂ , BCl ₃ , and CCl ₄ .
(Appendix 8)
The manufacturing method of a semiconductor device according to any one of appendices 1 to 7, wherein the gas containing the fluorine component is a gas containing one or more of SF ₆ , F ₂ , CF ₄ , and NF _3. Method.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to any one of appendices 1 to 8, wherein the dry etching is RIE.
(Appendix 10)
The step of removing the conductive film by dry etching and forming an electrode includes a first etching step and a second etching step,
10. The method of manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the bias power in the dry etching is lower in the second etching step than in the first etching step.
(Appendix 11)
The step of removing the conductive film by dry etching and forming an electrode includes a first etching step and a second etching step,
Any one of Supplementary notes 1 to 10, wherein the second etching step has a higher concentration of a gas or oxygen containing a fluorine component contained in an etching gas in dry etching than the first etching step. The manufacturing method of the semiconductor device of description.
(Appendix 12)
12. The semiconductor according to any one of appendices 1 to 11, wherein the step of forming the electrode by removing the conductive film by dry etching has a selection ratio of the conductive film to the nitride semiconductor layer of 2 or more. Device manufacturing method.
(Appendix 13)
13. The method of manufacturing a semiconductor device according to any one of appendices 1 to 12, wherein the nitride semiconductor layer in contact with the electrode is any one of GaN, AlGaN, and InAlN.
(Appendix 14)
From the supplementary note 1, the nitride semiconductor layer includes a first semiconductor layer formed on a substrate and a second semiconductor layer formed on the first semiconductor layer. 14. A method for manufacturing a semiconductor device according to any one of 13 above.
(Appendix 15)
15. The method of manufacturing a semiconductor device according to appendix 14, wherein the nitride semiconductor layer is a layer in which a third semiconductor layer is formed on the second semiconductor layer.
(Appendix 16)
16. The method for manufacturing a semiconductor device according to appendix 15, wherein the third semiconductor layer is made of a material containing GaN.
(Appendix 17)
The first semiconductor layer is made of a material containing GaN,
17. The method for manufacturing a semiconductor device according to any one of appendices 14 to 16, wherein the second semiconductor layer is formed of a material containing AlGaN or InAlN.
(Appendix 18)
18. The method of manufacturing a semiconductor device according to any one of appendices 1 to 17, wherein the nitride semiconductor layer is formed by MOVPE.
(Appendix 19)
The electrode is a gate electrode;
19. The method for manufacturing a semiconductor device according to any one of appendices 1 to 18, further comprising forming a source electrode and a drain electrode on the nitride semiconductor layer.
(Appendix 20)
20. The method of manufacturing a semiconductor device according to any one of appendices 1 to 19, wherein the semiconductor device is a HEMT.

10 Substrate 21 Electron travel layer (first semiconductor layer)
21a 2DEG
22 Electron supply layer (second semiconductor layer)
23 Cap layer (third semiconductor layer)
30 gate electrode 30a conductive film 40 resist pattern 50 first interlayer insulating film 51 opening 52 opening 61 source electrode 62 drain electrode 70 first interlayer insulating film 71 opening 72 opening 73 opening 81 wiring layer (source)
82 Wiring layer (drain)
83 Wiring layer (gate)

Claims (6)

Forming a nitride semiconductor layer on the substrate;
Forming a conductive film on the nitride semiconductor layer;
Forming a resist pattern on the conductive film;
Forming the electrode by removing the conductive film in the region where the resist pattern is formed by dry etching;
Have
An etching gas used for the dry etching is obtained by adding a gas containing a fluorine component or oxygen to a gas containing a chlorine component.   The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film includes a conductive metal nitride film. _3. The method of manufacturing a semiconductor device according to claim 1, wherein the gas containing a fluorine component is a gas containing one or more of SF ₆ , F ₂ , CF ₄ , and NF ₃ . The step of removing the conductive film by dry etching and forming an electrode includes a first etching step and a second etching step,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the bias power in the dry etching is lower in the second etching step than in the first etching step. 5.   5. The step of removing the conductive film by dry etching to form an electrode has a selectivity of the conductive film with respect to the nitride semiconductor layer of 2 or more. A method for manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the nitride semiconductor layer in contact with the electrode is any one of GaN, AlGaN, and InAlN.

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