JP2013125570A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of improving a layout area by omitting a pseudo random number generator and the like.SOLUTION: The nonvolatile semiconductor storage device includes: a nonvolatile memory cell array 10 which has a word line 51 allocated for user data and a word line 52 allocated for randomized seed data, stores data obtained by randomizing input data using the word line 51, and stores the randomized seed data using the word line 52; a latch 31 for storing the randomized seed data which has been read using the word line 52; and a randomization circuit 33 for determining an exclusive OR of input data stored in a latch 32 and randomized seed data stored in the latch 31 as data to be written in the nonvolatile memory cell array 10 using the word line 51.

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In the NAND flash memory cell array, when the number of memory cells into which electrons are injected increases, a problem called program disturb occurs in which data held in non-selected cells is destroyed. Also, when the same data continues in the memory cell array, a problem of program disturb occurs due to GIDL (Gate Induced Drain Leakage). For example, when a CSL (Common Source Line) method is employed, CSL noise becomes unstable due to the bias of data in the same string. Also, when the memory cell is an MLC (Multi Level Cell), if the data bias is large, there is a high possibility that an error will occur in the data due to charge loss or gain in the floating gate.

  The above problems can be suppressed by randomizing the write data and reducing the bias between ‘0’ and ‘1’. An example of such a technique is described in Patent Document 1. In Patent Document 1, a technique for averaging write data based on a cumulative value of each bit of write data, or a pseudorandom number is generated using an address as a randomization seed, and randomization is performed in the word line direction using this pseudorandom number. A technique for averaging write data is shown (see FIG. 24 of Patent Document 1, paragraphs 0116 to 0122 for the latter technique).

JP 2009-163774 A

  In the nonvolatile semiconductor memory device described in Patent Document 1, in order to reduce the deviation between “0” and “1” of the write data, the cumulative value of the write data is held and determined in a configuration using the cumulative value, In a circuit for selecting data based on the determination result, or a configuration that does not use an accumulated value, a pseudo random number generator that generates pseudo random numbers from address data is provided. For this reason, reduction of the layout area allocated to such a circuit has been a problem.

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can solve the above-described problems.

  In order to solve the above problems, a nonvolatile semiconductor memory device of the present invention has a user data word line allocated for user data and a randomized seed data word line allocated for randomized seed data. Non-volatile memory cell array for storing the randomized input data using the user data word line and storing the randomized seed data using the randomized seed data word line, and a bit for storing the input data A latch for line data, a random seed data latch for storing random seed data read using the random seed data word line, data stored in the bit line data latch, and the random seed data. The exclusive OR of the randomization seed data stored in the data latch, characterized in that it comprises a randomizing circuit for obtaining a data to be written to the nonvolatile memory cell array by using the user data word lines.

  In the nonvolatile semiconductor memory device of the present invention, randomized seed data is stored in the nonvolatile memory cell array for storing input data. Then, by obtaining an exclusive OR of the input data and the randomized seed data, randomized data is written into the nonvolatile memory cell array. Therefore, it is not necessary to provide a circuit for holding and determining the accumulated value of write data, selecting data based on the determination result, and a pseudo random number generator for generating pseudo random numbers, and improving the layout area. be able to.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device 100 as an embodiment of the present invention (however, a data flow at the time of programming) is shown. FIG. 2 is a block diagram showing a data flow at the time of reading in the nonvolatile semiconductor memory device 100 of FIG. 1. 3 is a flowchart showing a flow of processing during programming in the nonvolatile semiconductor memory device 100 of FIG. 1. 2 is a flowchart showing a flow of processing at the time of reading in the nonvolatile semiconductor memory device 100 of FIG. 1. FIG. 2 is a diagram showing an example of data stored in the nonvolatile semiconductor memory device 100 of FIG. 1.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device 100 as an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of the same nonvolatile semiconductor memory device 100 as FIG. 1, whereas FIG. 1 shows a data flow at the time of data programming (during writing). FIG. 2 shows a data flow at the time of data reading (at the time of reading).

  The nonvolatile semiconductor memory device 100 includes a nonvolatile memory cell array 10, a word line decoder 20, a page buffer 30a, a page buffer 30b, a peripheral circuit 40, and the like. 1 and 2 show only the configuration of the portion related to the features of the present invention as the configuration of the nonvolatile semiconductor memory device 100. FIG. That is, the non-volatile semiconductor memory device 100 has a plurality of I / O terminals (input / output terminals) connected to an external device, a write enable terminal, a read enable terminal, a ready / busy terminal, a power supply, and the like. Terminals, ground terminals, etc. are provided. The nonvolatile semiconductor memory device 100 includes a control circuit, a power supply circuit, various registers, a timing generation circuit, and the like, which are not shown.

  The nonvolatile memory cell array 10 includes a plurality of nonvolatile memory cells such as NAND flash memory cells. The non-volatile memory cell array 10 also includes a plurality of user data word lines 51 and one or a plurality of randomized seed data used when selecting each non-volatile memory cell. The word line 52 has a plurality of bit lines 61 and one or a plurality of bit lines 62 laid in the vertical direction. The plurality of user data word lines 51 are word lines assigned for storing externally input data. One or a plurality of randomized seed data word lines 52 are allocated for storing randomized seed data used when randomizing input data (pseudo-randomization) or restoring original input data from randomized data. Word line. The word line decoder 20 selects the user data word line 51 and the randomized seed data word line 52. The nonvolatile memory cell array 10 also belongs to the memory cell array 10a belonging to the main data area 1a for storing the data obtained by randomizing the input data, and to the randomization seed condition storage area 1b for storing the selection conditions for the randomized seed data. The memory cell array 10b is divided. The user data word line 51 and the randomized seed data word line 52 are laid in common with respect to the main data area 1a and the randomized seed condition storage area 1b. In the present embodiment, the random seed selection conditions (that is, information for specifying the random seed) used when the data stored in the main data area 1a using the user data word line 51 are randomized are the same. Are stored in the randomized seed condition storage area 1b. The bit line 61 is laid for the memory cell array 10a belonging to the main data area 1a, and the bit line 62 is laid for the memory cell array 10b belonging to the randomized seed condition storage area 1b.

  In FIG. 1 and FIG. 2, only one user data word line 51, randomized seed data word line 52, bit line 61 and bit line 62 are shown.

  The page buffer 30a is a circuit that temporarily stores data when the data is programmed into the memory cell array 10a in the main data area 1a or when data is read from the memory cell. In particular, the page buffer 30a of the present embodiment includes a randomized seed data latch 31, a bit line data latch 32, and a randomizing circuit 33. The randomized seed data latch 31 is a latch circuit used when storing the randomized seed data read using the randomized seed data word line 52. The bit line data latch 32 is used when storing externally input data during programming, and is used when storing data read using the user data word line 51 during reading. These randomized seed data latches 31 and bit line data latches 32 are provided by the number of bit lines 61.

  The randomizing circuit 33 is a circuit that obtains an exclusive OR of the data stored in the bit line data latch 32 and the randomized seed data stored in the randomized seed data latch 31 for each bit. The exclusive OR obtained by the randomizing circuit 33 is written into the memory cell array 10a of the nonvolatile memory cell array 10 using the user data word line 51 at the time of programming. Further, the exclusive OR obtained by the randomizing circuit 33 becomes read data output from the nonvolatile semiconductor memory device 100 at the time of reading.

  The page buffer 30b programs data representing the selection conditions for random seed data to the memory cell array 10b in the random seed condition storage area 1b, and reads data representing the selection conditions for random seed data from the memory cells. In such a case, the data is temporarily stored. The page buffer 30b has a bit line data latch 34 for selection conditions.

  In this embodiment, randomized seed data used for pseudo-randomization is stored in advance in the nonvolatile memory cell array 10, but the randomized seed data can be prepared as follows, for example. First, the number of randomized seed data to be prepared is arbitrary. There may be one or more. In addition, in the case of a plurality, the selection process of randomized seed data is required, but the selection method can be arbitrarily set. For example, it is possible to select according to the result of decoding all or part of the address specified by the user, or to select according to the value of an arbitrary 1 bit of the address when two randomized seed data are prepared. can do. It can also be made selectable whether or not pseudo-randomization is performed. Therefore, in the present embodiment, the data indicating the selection condition of the randomized seed data includes, for example, 1-bit data indicating whether or not pseudorandomization is performed and the number of bits corresponding to the number of randomized seed data that can be selected. Data. Therefore, the selection condition bit line data latches 34 are provided for a predetermined number of bits.

  Next, the peripheral circuit section 40 includes a randomized seed data word line selection circuit 41 and a user address word line selection circuit 42. At the time of programming, the randomize seed data word line selection circuit 41 performs a process of selecting any one of a plurality of prepared random seeds based on the value of an address designated from the outside, for example, and represents the selected result. Data is output to the page buffer 30b and the word line decoder 20. However, when the number of randomized seed data prepared in advance is one, the selection process based on the input address can be omitted. Further, at the time of reading, a plurality of randomized seed data word line selection circuits 41 are prepared based on data representing the selection conditions of random seed data latched in the selection condition bit line data latch 34 of the page buffer 30b. Data specifying any one of the seeds is output to the word line decoder 20. In the page buffer 30b, the data input from the randomized seed data word line selection circuit 41 is latched in the selection condition bit line data latch 34 during programming. The word line decoder 20 selects a predetermined random seed data word line 52 at a predetermined timing based on data input from the random seed data word line selection circuit 41 during programming and reading.

  The user address word line selection circuit 42 generates data for selecting the user data word line 51 based on an externally designated address and outputs the data to the word line decoder 20. In the word line decoder 20, based on the data input from the user address word line selection circuit 42, a predetermined user data word line 51 is selected at a predetermined timing during programming and reading.

  Next, with reference to FIG. 1, FIG. 3, and FIG. 5, an operation at the time of programming in the nonvolatile semiconductor memory device 100 will be described. In addition, control of each part shall be performed by the control circuit which is not shown in figure, when the main body of control is not shown especially. First, assuming that a command for specifying a predetermined address and data from the outside by the user and programming the data is input to the nonvolatile semiconductor memory device 100, the nonvolatile semiconductor memory device 100 (predetermined control of the nonvolatile semiconductor memory device 100). The circuit) stores the input data in the bit line data latch 32 of the page buffer 30a (step S11).

  Next, the randomized seed data word line selection circuit 41 performs a process of selecting one of a plurality of randomized seeds prepared based on the value of an address designated from the outside, and data representing the selected result Is output to the word line decoder 20 (for example, data indicated by an arrow A2 in the figure is output). The word line decoder 20 selects the random seed data word line 52 specified by the random seed data word line selection circuit 41 (for example, selects the random seed data word line 52 at the address A2), and selects the random seed data. Sense is performed, and the sense result (for example, data D2) is stored in the randomized seed data latch 31 of the page buffer 30a in the main data area 1a (step S12).

  Next, the randomizing circuit 33 obtains an exclusive OR using each data stored in the bit line data latch 32 and the randomized seed data latch 31 in the page buffer 30a in the main data area 1a, and then randomizes. Is performed (step S13).

  Next, the randomization seed data word line selection circuit 41 stores information indicating the selection conditions of the selected random seed data word line 52 into the selection condition bit line data latch 34 of the page buffer 30b in the randomization seed condition storage area 1b. (Step S14).

  Next, the user data word line 51 selected by the word line decoder 20 in accordance with the data (A1) output from the user address word line selection circuit 42 based on the address designated by the user (for example, user data at the address A1) The output data D1 of the randomizing circuit 33 is also stored in the nonvolatile memory cell in the main data area 1a selected by the word line 51), and the user data word line 51 (for example, the user data word line of the address A1) The data D3 latched in the selection condition bit line data latch 34 is simultaneously programmed in the nonvolatile memory cell in the randomization seed condition storage area 1b selected in 51) (step S15).

  Through the above processing, data as shown in FIG. 5 is programmed in the nonvolatile memory cell array 10. That is, in the memory cell selected by the user data word line 51 at the address A1, the data D1 obtained by randomizing the input data in the main data area 1a with the random seed D2 at the address A2, and the random seed condition storage area 1b The data D3 representing the randomized seed condition is stored. Here, the data D3 representing the randomized seed condition includes, for example, data 71 representing presence or absence of randomization and data 72 representing the address A2 of the randomized seed data D2. The random seed data D2 is stored in advance in the memory cell selected by the random seed data word line 52 at the address A2. Further, the memory cell 73 in the randomization seed condition storage area 1b selected by the randomization seed data word line 52 at the address A2 is not used.

  Next, an operation at the time of reading in the nonvolatile semiconductor memory device 100 will be described with reference to FIGS. In addition, control of each part shall be performed by the control circuit which is not shown in figure, when the main body of control is not shown especially. It is assumed that data as shown in FIG. 5 is programmed in the nonvolatile memory cell array 10.

  First, it is assumed that a command is input to the nonvolatile semiconductor memory device 100 by the user to designate a predetermined address (assuming that it corresponds to the address A1 in FIG. 2) from the outside and read the address. Then, the selection data (A1) corresponding to the address designated by the user is output from the user address word line selection circuit 42, and the user data word line 51 (in this case, the user data word at the address A1) is output by the word line decoder. Line 51) is selected. Then, the data (in this case, data D1) of the user data word line 51 at the address A1 is stored in the bit line data latch 32 (step S21).

  At the same time, the data (in this case, data D3) in the randomized seed condition storage area 1b stored on the same user data word line 51 (in this case, the user data word line 51 at the address A1) is used for the selection condition. The data is latched by the bit line data latch 34 and further transferred to the randomized seed data word line selection circuit 41 (step S22).

  Next, the random seed data word line selection circuit 41 selects the random seed data word line 52 based on the data transferred from the selection condition bit line data latch 34 (in this case, data D3) (in this case). , A2), and the word line decoder 20 selects the random seed data word line 52 designated by the random seed data word line selection circuit 41 (in this case, the random seed data word line 52 at the address A2 is selected). Then, the randomized seed data is sensed, and the sense result (data D2) is stored in the randomized seed data latch 31 of the page buffer 30a in the main data area 1a (step S23).

  Next, the randomizing circuit 33 randomizes the data (data D1) stored in the bit line data latch 32 in step S21 and the data (data D2) stored in the randomized seed data latch 31 in step S23. (In other words, an exclusive OR is obtained), and data is restored (step S24). Then, the restored data is output (step S25).

  As described above, in the nonvolatile semiconductor memory device 100 of this embodiment, randomized seed data is stored in the nonvolatile memory cell array 10 for storing input data. Then, by obtaining an exclusive OR of the input data and the randomized seed data, randomized data is written into the nonvolatile memory cell array 10. Therefore, it is not necessary to provide a circuit for holding and determining the accumulated value of write data, selecting data based on the determination result, and a pseudo random number generator for generating pseudo random numbers, and improving the layout area. be able to.

  Further, since randomized seed data can be easily stored by placing the randomized seed data on the nonvolatile memory cell array 10, it becomes easy to make the data uniform.

  The embodiment of the present invention is not limited to the above. For example, a part of the randomized seed data word line selection circuit 41 and the user address word line selection circuit 42 may be configured integrally or prepared in advance. Changes such as omitting the configuration related to the randomization seed condition storage area 1b (that is, the memory cell array 10b, the page buffer 30b, etc.) with one randomization seed data as appropriate can be performed.

DESCRIPTION OF SYMBOLS 100 Nonvolatile semiconductor memory device 10 Nonvolatile memory cell array 1a Main data area 1b Randomization seed condition storage area 10a, 10b Memory cell array 20 Word line decoder 30a, 30b Page buffer 31 Randomization seed data latch 32 Bit line data latch 33 Randomization circuit 34 Selection condition bit line data latch 40 Peripheral circuit 41 Randomized seed data word line selection circuit 42 User address word line selection circuit 51 User data word line 52 Randomized seed data word line 61, 62 Bit line

Claims (3)

A user data word line allocated for user data and a random seed data word line allocated for randomized seed data, and the input data randomized data is stored using the user data word line And a nonvolatile memory cell array for storing the randomized seed data using the randomized seed data word line;
A bit line data latch for storing the input data;
A randomized seed data latch for storing randomized seed data read using the randomized seed data word line;
An exclusive OR of the data stored in the bit line data latch and the random seed data stored in the random seed data latch is obtained using the user data word line. A non-volatile semiconductor memory device comprising: a randomizing circuit that is obtained as data to be written to the memory. The nonvolatile memory cell array is divided into a main data area that stores data obtained by randomizing the input data, and a random seed condition storage area that stores selection conditions for the random seed data.
The user data word line is laid in common for the main data area and the randomized seed condition storage area,
A random seed selection condition of data stored in the main data area using the user data word line is stored in the random seed condition storage area using the same user data word line. The nonvolatile semiconductor memory device according to claim 1. When reading data,
The bit line data latch stores data read using the user data word line;
The randomization circuit obtains, as read data, an exclusive OR of the data stored in the bit line data latch and the random seed data stored in the random seed data latch. The nonvolatile semiconductor memory device according to claim 1.

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