JP2013122740A - Data processing device, conversion device, data processing system, conversion method, and conversion program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase efficiency in debugging.SOLUTION: From a CPU 101, an accelerator 102 accepts a native instruction 112 of the accelerator 102, and information 113 specifying an intermediate instruction 111 associated with the native instruction 112. As a first instruction, the accelerator 102 accepts "NOT R3,1" as a native instruction 112-1, and "ldrp" as information 113-1. Then, as a second instruction, the accelerator 102 accepts "AND R3,R2,R3" as a native instruction 112-2, and "and" as information 113-2. Next, the accelerator 102 executes the native instructions 112 "NOT R3,1" and "AND R3,R2,R3", and records the information 113 "ldrp" and "and" specifying the intermediate instructions.

Description

  The present invention relates to a data processing device, a conversion device, a data processing system, a conversion method, and a conversion program related to hardware acceleration.

  Conventionally, in order to perform specific processing at a higher speed than when executing software on a CPU (Central Processing Unit), additional hardware is prepared for the CPU so that the specific processing can be performed at high speed. To be executed. Such a technique is called hardware acceleration, and the additional hardware is called an accelerator. Examples of accelerators include a GPU (Graphics Processing Unit) that performs image processing, a DSP (Digital Signal Processor) that performs digital signal processing, and the like.

  The accelerator has a native instruction that can be executed by the accelerator. Alternatively, there are intermediate instructions abstracted for compatibility, and the developer may develop application software using the intermediate instructions. In the following description, application software is referred to as an application. When an application including an intermediate instruction is executed, the CPU converts the intermediate instruction into a native instruction by a JIT (Just In Time) compiler, and causes the accelerator to execute the converted native instruction.

  For example, as a technique using an accelerator, regarding an intermediate instruction of Java (registered trademark), an intermediate instruction that can be executed by the Java accelerator is converted into a native instruction and executed by the Java accelerator, and the other intermediate instructions are executed by the CPU. There is something. Further, regarding a Java accelerator, there is disclosed a technique for improving the execution speed of a Java program by not supplying a redundant load instruction when reproducing a Java stack machine with a register machine (for example, Patent Document 1 below) 2).

Japanese Patent Laid-Open No. 2004-280766 JP 2009-176411 A

  However, in the above-mentioned conventional technology, when the developer wants to acquire the execution history and the number of executions for debugging and tuning of the accelerator operation, the accelerator side mechanism is used, so acquisition is performed in units of accelerator native instructions. Will do. Since developers are developing using intermediate instructions, there is a problem that debugging and tuning are difficult even if the execution history and the number of executions are acquired in units of native instructions.

  An object of the present invention is to provide a data processing device, a conversion device, a data processing system, a conversion method, and a conversion program capable of improving the efficiency of debugging in order to solve the above-described problems caused by the conventional technology.

  In order to solve the above-described problems and achieve the object, according to one aspect of the present invention, an instruction code and information for identifying a code before conversion of the instruction code associated with the instruction code are received, and the instruction code By executing the above, a data processing apparatus for recording information for specifying the code before conversion is proposed.

  According to another aspect, an annotation code or a series of instruction codes including information indicating annotations for a series of instruction codes and information for identifying codes before conversion of the series of instruction codes is accepted, and the annotation codes are accepted. In this case, before the execution of the series of instruction codes, information for identifying the codes before conversion of the series of instruction codes is recorded, and when the series of instruction codes is received, the data processing device that executes the series of instruction codes Proposed.

  According to another aspect, the combination of the instruction code and the code before conversion of the instruction code is stored, and when the code before conversion is detected, the code before conversion is referred to by referring to the stored combination. , Converts the instruction code and information to identify the code before conversion associated with the instruction code, and transmits the instruction code and information to identify the code before conversion associated with the instruction code from the own device to another device. A conversion device, a conversion method, and a conversion program are proposed.

  According to another aspect, there is provided a data processing system including a first device and a second device that executes a specific process, wherein an instruction code executable by the second device and an instruction code The combination with the code before conversion is stored, and when the code before conversion is detected, the code before conversion is converted into an instruction code and information identifying the code before conversion associated with the instruction code, An instruction code and information for identifying a code before conversion associated with the instruction code are transmitted from the first apparatus to the second apparatus, and the instruction code and the pre-conversion associated with the instruction code are transmitted by the second apparatus. A data processing system is proposed in which information for identifying the code before the conversion is recorded by the second device by executing the instruction code.

  According to one aspect of the present invention, there is an effect that debugging efficiency can be improved.

FIG. 1 is an explanatory diagram illustrating an operation example of the accelerator according to the first embodiment. FIG. 2 is a block diagram of an example of hardware of the data processing system according to the first embodiment. FIG. 3 is a block diagram of an example of functions of the data processing system according to the first embodiment. FIG. 4 is an explanatory diagram illustrating an example of software and input / output data. FIG. 5 is a sequence diagram illustrating an operation example of the data processing system. FIG. 6 is an explanatory diagram showing an example of the stored contents of the template information. FIG. 7 is an explanatory diagram showing an example of intermediate instruction conversion by the JIT compiler in the first embodiment. FIG. 8 is an explanatory diagram showing a specific example of the execution history and the number of executions in the intermediate instruction. FIG. 9 is a flowchart showing an example of conversion processing by the JIT compiler. FIG. 10 is a flowchart illustrating an operation example of the accelerator according to the first embodiment. FIG. 11 is a block diagram of a function example of the data processing system according to the second embodiment. FIG. 12 is an explanatory diagram showing an example of intermediate instruction conversion by the JIT compiler in the second embodiment. FIG. 13 is a flowchart illustrating an operation example of the accelerator according to the second embodiment. FIG. 14 is a flowchart of a function example of the data processing system according to the third embodiment. FIG. 15 is an explanatory diagram illustrating an example of intermediate instruction conversion by the JIT compiler according to the third embodiment. FIG. 16 is a flowchart illustrating an operation example of the accelerator according to the third embodiment. FIG. 17 is an explanatory diagram of an application example of a system using a computer according to the first to third embodiments.

  Exemplary embodiments of a disclosed data processing device, conversion device, data processing system, conversion method, and conversion program will be described in detail below with reference to the accompanying drawings. In the following description, the data processing device is described as an accelerator, and the conversion device is described as a CPU.

(Description of Embodiment 1)
FIG. 1 is an explanatory diagram illustrating an operation example of the accelerator according to the first embodiment. The data processing system 100 includes a CPU 101 and an accelerator 102 such as a GPU or a DSP. The CPU 101 and the accelerator 102 are connected by a bus 103.

  The CPU 101 converts the intermediate instruction 111 into the native instruction 112 of the accelerator 102 and information 113 specifying the intermediate instruction 111 in advance. Further, in the first embodiment, the accelerator 102 is intended to provide the performance information 121 shown in units of intermediate instructions 111 in addition to executing specific processing at high speed. The performance information 121 is information in which an instruction execution history and the number of executions are recorded.

  The accelerator 102 receives from the CPU 101 the native instruction 112 of the accelerator 102 and information 113 specifying the intermediate instruction 111 associated with the native instruction 112.

  In the example of FIG. 1, the accelerator 102 receives “NOT R3, 1” as the first instruction and “ldrp” as the information 113-1, as the first instruction. Further, as the second instruction, the accelerator 102 receives “and” as the information 113-2 and the native instruction 112-2 is “AND R3, R2, R3”.

  Next, the accelerator 102 executes the native instructions 112 “NOT R3, 1” and “AND R3, R2, R3”, and records information 113 “ldrp” and “and” specifying the intermediate instruction. As a result, the CPU 101 can provide the developer with the execution history and the number of executions of instructions in units of intermediate instructions, so that debugging by the developer can be made more efficient. Details of the data processing system 100 that performs the operation shown in FIG. 1 will be described below with reference to FIGS.

(Hardware of data processing system 100)
FIG. 2 is a block diagram of an example of hardware of the data processing system according to the first embodiment. In FIG. 2, the data processing system 100 includes a CPU 101, an accelerator 102, a ROM (Read-Only Memory) 201, and a RAM (Random Access Memory) 202. The data processing system 100 also includes a magnetic disk drive 203, a magnetic disk 204, an optical disk drive 205, and an optical disk 206. Further, the data processing system 100 as an input / output device for a user or other devices includes a display 207, an I / F (Interface) 208, a keyboard 209, and a mouse 210. Each unit is connected by a bus 103.

  Here, the CPU 101 controls the entire data processing system 100. The accelerator 102 executes specific processing according to an instruction from the CPU 101. Further, when the accelerator 102 is a GPU, there is a case where a technique called GPGPU (General-Purpose computing on GPU) used for a more general calculation process other than image processing is used.

  The ROM 201 stores a program such as a boot program. The RAM 202 is used as a work area for the CPU 101. The magnetic disk drive 203 controls data read / write with respect to the magnetic disk 204 according to the control of the CPU 101. The magnetic disk 204 stores data written under the control of the magnetic disk drive 203.

  The optical disk drive 205 controls reading / writing of data with respect to the optical disk 206 according to the control of the CPU 101. The optical disk 206 stores data written under the control of the optical disk drive 205, or causes the computer to read data stored on the optical disk 206. Note that the conversion program according to the first to third embodiments may be stored in any one of the ROM 201, the magnetic disk 204, and the optical disk 206.

  A display 207 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. For example, the display 207 may be a CRT, a TFT liquid crystal display, a plasma display, or the like.

  The I / F 208 is connected to a network 211 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to another device via the network 211. The I / F 208 controls an internal interface with the network 211 and controls input / output of data from an external device. For example, a modem or a LAN adapter can be adopted as the I / F 208.

  The keyboard 209 has keys for inputting characters, numbers, various instructions, and the like, and inputs data. The keyboard 209 may be a touch panel type input pad or a numeric keypad. The mouse 210 performs cursor movement, range selection, window movement, size change, and the like. The data processing system 100 may be a trackball or a joystick as long as it has the same function as a pointing device instead of the mouse 210.

(Function of data processing system 100)
Next, functions of the data processing system 100 will be described. FIG. 3 is a block diagram of an example of functions of the data processing system according to the first embodiment. In the data processing system 100, the CPU 101 executes a JIT compiler 301 and a device driver 302. In addition, the data processing system 100 according to the first exemplary embodiment includes a reception unit 311, a determination unit 312, an execution unit 313, a recording unit 314, an output unit 315, a storage unit 321, a detection unit 322, and a conversion A unit 323, a transmission unit 324, and an acquisition unit 325 are included. The detection unit 322 to the acquisition unit 325 realize their functions when the CPU 101 executes a program stored in the storage device. Here, specifically, the storage device is, for example, the ROM 201, the RAM 202, the magnetic disk 204, the optical disk 206, etc. shown in FIG.

  Further, the accelerator 102 can access the performance information 121. The performance information 121 is information in which an instruction execution history and the number of executions are recorded in units of intermediate plane examples. Whether the performance information 121 is recorded as an execution history or the number of executions may be set by the CPU 101 at the initial stage of the accelerator 102 or set by an initial setting of an application using the accelerator 102. Also good.

  Further, the CPU 101 can access the template information 331. The template information 331 is a table showing a conversion method between intermediate instructions and native instructions. Details of the template information 331 will be described later with reference to FIG. The template information 331 exists in a storage area such as the RAM 202, the magnetic disk 204, and the optical disk 206.

  The JIT compiler 301 has a function of converting an intermediate instruction into a native instruction including information on the intermediate instruction. A specific conversion method will be described later with reference to FIGS. The device driver 302 is software that controls the accelerator 102. A specific operation will be described with reference to FIG. The receiving unit 311 to the output unit 315 are functions of the accelerator 102, the conversion unit 323 is a function of the JIT compiler 301, and the transmission unit 324 and the acquisition unit 325 are functions of the device driver 302. .

  The receiving unit 311 has a function of receiving an instruction code and information for specifying a code before conversion of the instruction code associated with the instruction code. Here, the instruction code is a native instruction of the accelerator 102, and the code before conversion is an intermediate instruction. As an association method, for example, the instruction code and the code before conversion may be combined before and after one instruction, or the order may be changed. Further, the information specifying the code before conversion is identification information that makes the code before conversion unique, and is, for example, an opcode portion of an intermediate instruction. Further, the information specifying the code before conversion may be the code itself before conversion.

  For example, the reception unit 311 receives “NOT R3, 1” that is an instruction code and “ldrp” that is a code before conversion. The received information is stored in a storage area such as a register of the accelerator 102.

  The determination unit 312 has a function of determining whether or not the information specifying the code before conversion received by the reception unit 311 is information indicating that the code before conversion does not exist. The information indicating that there is no code before conversion may be, for example, a bit code that does not correspond to all intermediate instructions, or a bit code that indicates “nop” if there is no bit string that does not correspond to all intermediate instructions. Good. Note that the determination result is stored in a storage area such as a register of the accelerator 102.

  The execution unit 313 has a function of executing an instruction code. For example, the execution unit 313 executes instruction codes such as a native instruction “NOT” and a native instruction “AND”. The execution result is stored in a storage area such as a register of the accelerator 102.

  The recording unit 314 has a function of recording information for specifying the code before conversion by executing the instruction code by the execution unit 313. For example, the recording unit 314 records information “ldrp” that identifies the code before conversion by executing the native instruction “NOT”. The recording timing may be simultaneous with the execution of the instruction code by the execution unit 313, or may be before or after. Note that the recording unit 314 records information specifying the code before conversion as performance information 121 in a storage area such as a register of the accelerator 102.

  When the determination unit 312 determines that the information for specifying the code before conversion is information indicating that the code before conversion does not exist, the recording unit 314 executes the instruction code to execute the code before conversion. Do not record the information that you identify.

  Further, the recording unit 314 may record information for specifying the code before conversion in the order of execution of the instruction code by executing the instruction code. For example, when executed in the order of “NOT” and “AND”, the recording unit 314 records in the order of “ldrp” and “and”.

  Further, the recording unit 314 may record the number of executions of the instruction code in association with information specifying the code before conversion by executing the instruction code. For example, when “NOT” and “AND” are executed once, the recording unit 314 records “ldrp” once and “and” once.

  The output unit 315 has a function of outputting the performance information 121. For example, the output unit 315 outputs the execution history and the number of executions, which are the intermediate instruction unit as the performance information 121, to a storage area in the accelerator 102 accessible by the CPU 101.

  The storage unit 321 has a function of storing a combination of an instruction code and a code before conversion of the instruction code. Each set is recorded as one record of the template information 331. The storage unit 321 exists in a storage area such as the RAM 202, the magnetic disk 204, and the optical disk 206.

  The detection unit 322 has a function of detecting a code before conversion. For example, the detection unit 322 detects an intermediate command for executing image processing. The detection results exist in storage areas such as the register of the CPU 101, the RAM 202, the magnetic disk 204, and the optical disk 206.

  The conversion unit 323 has a function of referring to the storage unit 321 and converting the code before conversion into an instruction code and information specifying the code before conversion associated with the instruction code. A specific conversion method will be described with reference to FIGS. Note that the converted information exists in storage areas such as the register of the CPU 101, the RAM 202, the magnetic disk 204, and the optical disk 206.

  The transmission unit 324 has a function of transmitting an instruction code and information for specifying a code before conversion associated with the instruction code to another device. For example, the transmission unit 324 transmits the instruction code “NOT R3, 1” and information “ldrp” that identifies the code before conversion to the accelerator 102.

  The acquisition unit 325 acquires the performance information 121 from the accelerator 102. For example, the acquisition unit 325 acquires the performance information 121 from the accelerator 102 at a predetermined cycle. The acquired performance information 121 exists in storage areas such as the RAM 202, the magnetic disk 204, and the optical disk 206. Next, software and input / output data used in the data processing system 100 will be described with reference to FIG.

  FIG. 4 is an explanatory diagram illustrating an example of software and input / output data. Software executed in the data processing system 100 or data input to or output from the accelerator 102 includes performance information 121, source code 401, native instructions 402, input data 403, and output data 404. As software executed in the data processing system 100, there are a JIT compiler 301, a compiler 411, an application 412, and a device driver 302.

  The source code 401 is a computer program written according to a programming language. The source code 401 includes a part executed by the CPU 101 and a part executed by the accelerator 102.

  The native instruction 402 is an execution code written as an instruction that can be directly executed by the accelerator 102. Input data 403 is data input to the accelerator 102. Output data 404 is data output from the accelerator 102.

  The compiler 411 has a function of generating software executable by the CPU 101 from the source code 401. In the example of FIG. 4, the compiler 411 generates an application 412 from the source code 401.

  The application 412 is software that can be executed by the data processing system 100. The application 412 includes an execution code executed by the CPU 101 and an intermediate instruction executed by the accelerator 102.

  The device driver 302 is software that controls the accelerator 102. Specifically, the device driver 302 has an API (Application Programming Interface), and inputs / outputs data between the application 412 and the accelerator 102. For example, the device driver 302 receives the input data 403 and writes the input data 403 into a buffer accessible by the accelerator 102.

  Further, the device driver 302 refers to the register of the accelerator 102, and when the output data 404 can be read, reads the output data 404 and saves it in a storage area accessible by the CPU 101. Similarly, the device driver 302 acquires the performance information 121 and saves it in a storage area accessible by the CPU 101. FIG. 5 is a sequence diagram showing the operation of the software and accelerator 102 described in FIG.

  FIG. 5 is a sequence diagram illustrating an operation example of the data processing system. The application 412 transmits an intermediate instruction execution request to the JIT compiler 301 (step S501). The JIT compiler 301 that has received the intermediate instruction converts the intermediate instruction into a native instruction 402 (step S502). Next, the JIT compiler 301 transmits a native instruction to the device driver 302 (step S503). The device driver 302 that has received the native command transmits the native command to the accelerator 102 (step S504).

  The accelerator 102 that has received the native instruction executes the native instruction 402 (step S505), and further records information for specifying the intermediate instruction that becomes the performance information 121 (step S506). Next, the accelerator 102 transmits the output data 404 to the device driver 302 (step S507). The device driver 302 that has received the output data 404 transmits the output data 404 to the application 412 (step S508). Further, the accelerator 102 outputs the performance information 121 to the device driver 302 at a predetermined cycle (step S509).

  FIG. 6 is an explanatory diagram showing an example of the stored contents of the template information. The template information 331 registers records 331-1 to 331-7. The template information 331 includes three fields: a pattern, a pattern matching condition, and a template code. The pattern field stores the intermediate instruction of the conversion source. The pattern matching condition field stores the matching condition of the intermediate instruction stored in the pattern field. The template code field stores information that is the source of the converted native instruction. Further, <addr> shown in FIG. 6 indicates an address, <reg> indicates a register name, and <imm> indicates an immediate value.

  For example, the record 331-1 indicates that the intermediate instruction branch (branch instruction) is converted into the native instruction BRA (branch instruction) regardless of the condition. Also, a bit code indicating branch, which is the last argument of the template code field, is stored as information on the intermediate instruction in the converted native instruction. Specific storage locations will be described with reference to FIG.

  The record 331-2 indicates that the intermediate instruction ldrp (immediate load instruction) is converted into a native instruction MOV (register transfer instruction) if the immediate value is from 0 to 0xffff. Further, the ldrp bit code is stored in the converted native instruction.

  The record 331-3 indicates that the intermediate instruction ldrp (immediate load instruction) is converted into a native instruction NOT (bit inversion instruction) if the immediate value is from 0xffff0000 to 0xffffffff. In addition, a bit code indicating ldrp is stored in the converted native instruction.

  Further, the record 331-4 is the native instruction SHL (left shift instruction) if the immediate value is from 0x10000 to 0xffffeffff and all the lower 4 bits of the immediate value are all 0 regarding the intermediate instruction ldrp (immediate load instruction). Indicates that it will be converted. In addition, a bit code indicating ldrp is stored in the converted native instruction.

  Also, the record 331-5 indicates that the intermediate instruction ldrp (immediate load instruction) has an immediate value from 0x10000 to 0xffffffff, and if there are non-zero bits in the lower 4 bits of the immediate value, the native instruction SHL and the native instruction ADDI It is converted to (immediate value addition instruction). In addition, a bit code indicating ldrp is stored in the first instruction of the converted native instruction, and a bit code indicating “” indicating that there is no corresponding intermediate instruction is stored in the second instruction. Similarly, records 331-6 and 331-7 indicate the contents to be converted from the intermediate instruction to the native instruction.

  FIG. 7 is an explanatory diagram showing an example of intermediate instruction conversion by the JIT compiler in the first embodiment. (A) in FIG. 7 shows the format of the native instruction after conversion, and (b) in FIG. 7 shows a specific conversion example of the intermediate instruction.

  The converted native instruction 701 has two fields, an intermediate instruction and a native instruction. The intermediate instruction field stores information for specifying an intermediate instruction corresponding to the native instruction. For example, the intermediate instruction field may store all bits of the intermediate instruction, or may store bits of the opcode portion of the intermediate instruction. Further, when the performance information 121 provides the execution count for each instruction, the intermediate instruction field may store a minimum number of bits that can identify the intermediate instruction. The native instruction is an execution code that can be executed by the accelerator 102. Whether or not to provide either the execution history or the number of executions is set by the CPU at the initial stage of the accelerator 102, for example.

  For example, the case where “setzero r3” is converted as the intermediate instruction 702_M is shown. At this time, the JIT compiler 301 converts the intermediate instruction 702_M into the native instruction 702_N from the record 331-6 of the template information 331. Hereinafter, the suffix “_M” indicates an intermediate instruction, and the suffix “_N” indicates a native instruction. A bit indicating “setzero” is stored in the intermediate instruction field of the native instruction 702_N, and a bit indicating “MOV R3, R0” is stored in the native instruction field.

  Further, the case where “ldrp r3, 0x10001” is converted as the intermediate instruction 703_M is shown. At this time, the JIT compiler 301 converts the intermediate instruction 703_M into the native instruction 703_N from the record 331-5 of the template information 331. A bit indicating “ldrp” is stored in the intermediate instruction field of the first instruction of the native instruction 703_N, and bits indicating “SHL R3, 1, 16” are stored in the native instruction field of the first column. ing. A bit indicating “nop” for performing no processing is stored in the intermediate instruction field of the second instruction, and “ADDI R3, R3, 1” is indicated in the second column of the native instruction field. A bit is stored.

  Thus, when the number of native instructions is 2 or more with respect to the intermediate instruction 1, the bit code indicating “” indicating that the corresponding intermediate instruction does not exist after the second instruction of the corresponding record of the template information 331 is Stored. Based on this, the JIT compiler 301 stores a bit indicating “nop” in the intermediate instruction field after the second instruction. Alternatively, the JIT compiler 301 may store bits that do not correspond to all intermediate instructions. This is because, when the “nop” instruction is used in the compiler 411, it is counted that the nop instruction has been executed. Therefore, if there is a bit that does not correspond to all intermediate instructions, the JIT compiler 301 may store the corresponding bit, and if not, may store a bit indicating “nop”.

  Although not illustrated in FIG. 7, when the native instruction is 1 for the intermediate instruction 2 or more, the JIT compiler 301 stores a bit indicating “nop” in the native instruction field after the second instruction. Alternatively, if there is an instruction for skipping the code, the accelerator 102 may store a bit indicating the corresponding instruction.

  As described above, when the integers m and n are integers of 1 or more, are native instructions n with respect to the intermediate instruction m, and m and n are different, the JIT compiler 301 displays “nop” in a field corresponding to many instructions. "Is stored. Or, when n is larger than m, the JIT compiler 301 stores bits not corresponding to all intermediate instructions in the intermediate instruction field, and when m is larger than n, the JIT compiler 301 stores an instruction to skip code in the native instruction field. Also good.

  FIG. 8 is an explanatory diagram showing a specific example of the execution history and the number of executions in the intermediate instruction. FIG. 8 shows an execution history and the number of executions when the native instruction 801_N is executed. Table 802 shows the execution history of native instructions, table 803 shows the execution history of intermediate instructions, and table 804 shows the number of executions of intermediate instructions.

  For example, when the register R1 is 1, the accelerator 102 executes “BEQ L2” of the fourth instruction and makes a transition to the label L2. Next, the accelerator 102 executes “BRA L4” of the third instruction from the label L2, and transitions to the label L4. Therefore, the execution history with native instructions is shown in Table 802.

  When outputting the execution history of the intermediate instruction, the accelerator 102 acquires “switch2d” stored in the intermediate instruction field by executing “CMP R1, 0” which is the first instruction of the native instruction 801_N, and performs performance information 121. Record as. Further, the accelerator 102 obtains “ldrp” stored in the intermediate instruction field when the first instruction “SHL R3, 1, 16” from the label L2 of the native instruction 801_N is executed, and stores it as performance information 121. To do. Further, the accelerator 102 acquires the branch stored in the intermediate instruction field when the third instruction “BRA L4” from the label L2 of the native instruction 801_N is executed, and stores it as performance information 121. Finally, the performance information 121 has values as shown in Table 803.

  When outputting the execution count of the intermediate instruction, the accelerator 102 acquires “switch2d” and increments the execution count of “switch2d” by one. Similarly, the accelerator 102 acquires “ldrp”, increments the execution count of “ldrp” by 1, acquires “branch”, and increments the execution count of “branch” by 1.

  FIG. 9 is a flowchart showing an example of conversion processing by the JIT compiler. First, the JIT compiler 301 accepts an intermediate instruction (step S901). Next, the JIT compiler 301 determines from the template information 331 whether there is a pattern that matches the intermediate instruction (step S902). When the pattern exists (step S902: Yes), the JIT compiler 301 converts the matched intermediate instruction using the template code (step S903), and proceeds to the process of step S902. If the pattern does not exist (step S902: No), it indicates that all the conversion has been completed, so the JIT compiler 301 transmits a native instruction including information for specifying the intermediate instruction to the accelerator 102 (step S904). ), And finishes the conversion process.

  FIG. 10 is a flowchart illustrating an operation example of the accelerator according to the first embodiment. The accelerator 102 receives a native command (step S1001). Next, the accelerator 102 determines whether or not information indicating that no intermediate instruction exists is stored in the intermediate instruction field (step S1002). When the information is information specifying an intermediate instruction (step S1002: No), the accelerator 102 executes the instruction in the native instruction field (step S1003). Subsequently, the accelerator 102 records information for specifying the intermediate instruction stored in the intermediate instruction field (step S1004). Note that step S1003 and step S1004 are desirably executed within the same clock cycle, but may be executed in different clock cycles. In that case, step S1003 and step S1004 may be executed first.

  If the information indicates that no intermediate instruction exists (step S1002: Yes), the accelerator 102 executes the instruction in the native instruction field (step S1005). After execution of both step S1003 and step S1004 or step S1005, accelerator 102 determines whether or not execution of accelerator 102 has been completed (step S1006). If the execution has not ended (step S1006: No), the accelerator 102 proceeds to the process of step S1002. When the execution is finished (step S1006: Yes), the accelerator 102 outputs the performance information 121 (step S1007), and the operation is finished.

  As described above, according to the data processing apparatus, the native instruction and the information specifying the intermediate instruction are received, and the execution of the intermediate instruction is recorded by executing the native instruction. As a result, the data processing apparatus can provide an instruction execution history and the number of executions in units of intermediate instructions, so that debugging by the developer can be made more efficient. If the information specifying the native instruction and the intermediate instruction is one instruction, the number of instructions is the same as when the information specifying the intermediate instruction is not included, so the execution timing is the same as that of the data processing apparatus according to the conventional example. Can be.

  Further, when the information specifying the intermediate instruction is information indicating that the intermediate instruction does not exist, the data processing apparatus does not need to record that the intermediate instruction has been executed. Thereby, the data processing apparatus can record one intermediate instruction before conversion even when the intermediate instruction is converted into two or more native instructions.

  In addition, the data processing apparatus may record information for specifying the intermediate instruction in the execution order of the native instruction by executing the native instruction. Thus, the data processing system can provide an instruction execution history in units of intermediate instructions. In the data processing system in the conventional example, when the execution history for each intermediate instruction is provided to the developer, it is estimated which CPU corresponds to the intermediate instruction from the execution history of the native instruction. In the case of this method, there is a problem that complicated pattern matching is performed after execution of the accelerator. In addition, when there are a plurality of intermediate instructions that are converted into exactly the same native instructions including arguments, it is difficult for the data processing system in the conventional example to provide correct information.

  Further, the data processing device may record the number of executions of the native instruction code in association with the information specifying the intermediate instruction. As a result, the data processing system can provide the number of execution times of instructions in units of intermediate instructions. In the data processing system in the conventional example, when it is intended to provide the developer with the number of executions in units of intermediate instructions, the CPU performs a conversion process of the number of executions. This conversion process has a problem that a larger amount of calculation is performed as the number of types of instructions is larger. Also, when there are a plurality of intermediate instructions that are converted into the same native instruction, this conversion processing method cannot be converted into the original intermediate instruction. There is also a method of obtaining the execution history of the intermediate instruction from the execution history of the native instruction and obtaining the execution count of the intermediate instruction. However, in order to obtain the execution count, a memory for storing the execution history is required. The overhead becomes large.

(Description of Embodiment 2)
In the first embodiment, information specifying intermediate instructions is assigned to all native instructions. In the second embodiment, a method for reducing the amount of memory used in the first embodiment is proposed. Note that the hardware of the data processing system 100 according to the second embodiment is the same as the hardware of the data processing system 100 according to the first embodiment, and a description thereof will be omitted.

  FIG. 11 is a block diagram of a function example of the data processing system according to the second embodiment. The data processing system 100 according to the second exemplary embodiment includes a reception unit 1101, a determination unit 1102, an execution unit 1103, a recording unit 1104, an output unit 315, a storage unit 321, a detection unit 322, and a conversion unit 1111. And a transmission unit 1112 and an acquisition unit 325. The detection unit 322, the acquisition unit 325, the conversion unit 1111, and the transmission unit 1112 realize their functions when the CPU 101 executes a program stored in the storage device. Here, specifically, the storage device is, for example, the ROM 201, the RAM 202, the magnetic disk 204, the optical disk 206, etc. shown in FIG. In addition, about the function part of the code | symbol same as Embodiment 1, since it has the same function as Embodiment 1, description is abbreviate | omitted.

  The accepting unit 1101 has a function of accepting an annotation code or a series of instruction codes including information indicating an annotation for the series of instruction codes and information for specifying a code before conversion of the series of instruction codes. As the information indicating the annotation, for example, an unused bit code among the operation codes of the accelerator native instruction is adopted. The annotation code is one of native instructions.

  For example, the reception unit 1101 may include an annotation code including information indicating an annotation and information “switch2d” specifying an intermediate instruction, or a series of instruction codes “CMP R1, 0”, “BEQ L1”, “CMP R1, 1”, “BEQ L2” and “BRA L3” are accepted. The received annotation code or series of instruction codes is stored in a storage area such as a register of the accelerator 102.

  The determination unit 1102 has a function of determining whether a series of instruction codes or an annotation code is received by the reception unit 1101. The determination result is stored in a storage area such as a register of the accelerator 102.

  The execution unit 1103 has a function of executing a series of instruction codes when a series of instruction codes is received by the reception unit 1101. For example, the execution unit 1103 sequentially executes a series of instruction codes “CMP R1, 0”, “BEQ L1”, “CMP R1, 1”, “BEQ L2”, and “BRA L3”.

  The recording unit 1104 has a function of recording information for identifying a code before conversion of a series of instruction codes before execution of the series of instruction codes when an annotation code is received by the reception unit 1101. For example, when the annotation code is accepted, the recording unit 1104 records “switch2d”. Further, the recording unit 1104 may record information for specifying the code before conversion in the order of execution of the instruction codes, or may record the number of executions of the instruction code in association with the information for specifying the code before conversion. Good.

  The conversion unit 1111 refers to the storage unit 321, the code before conversion, an annotation code including information indicating an annotation for the series of instruction codes, and information specifying the code before conversion of the series of instruction codes, and a series of And a function of converting into an instruction code. A specific conversion method will be described later with reference to FIG. The transmission unit 1112 has a function of transmitting the annotation code and a series of native instructions to another device.

  FIG. 12 is an explanatory diagram showing an example of intermediate instruction conversion by the JIT compiler in the second embodiment. (A) in FIG. 12 shows the format of the annotation code 1201 used in the second embodiment, and (b) in FIG. 12 shows a specific conversion example of the intermediate instruction.

  The annotation code 1201 has two fields of an operation code and an intermediate instruction. The opcode field stores information indicating an annotation. The information indicating the annotation is, for example, “111” as shown in FIG. Hereinafter, when “111” is stored in the operation code field, it is expressed as an annotation code (ANON). In the intermediate instruction field, information for specifying an intermediate instruction corresponding to the native instruction subsequent to the annotation code 1201 is stored. For example, the intermediate instruction field may store all bits of the intermediate instruction, or may store bits of the opcode portion of the intermediate instruction.

  The JIT compiler 301 converts the intermediate instruction 1202_M into the native instruction 1202_N. As a more detailed example, a case where the intermediate instruction 1202-1_M “switch2d r1, 0, L1, 1, L2, L3” included in the intermediate instruction 1202_M is converted will be described. At this time, the JIT compiler 301 converts the intermediate instruction 1202-1_M into the native instruction 1202-M that includes the information indicating the annotation, the native instruction including the information “switch2d” specifying the intermediate instruction, the conversion by the record 331-7, and the native instruction. Convert to 1_N.

  As described above, the number of bits consumed per instruction of the native instruction is reduced as compared with the conversion example according to the first embodiment. Specifically, in the conversion example according to the second embodiment, information specifying the correspondence between the intermediate instruction and the native instruction can be embedded. On the other hand, in the conversion example according to the first embodiment, when either one of the corresponding intermediate instructions and native instructions is large, information indicating that it is invalid is embedded in the field. Equal to or greater than 2. Therefore, the conversion example according to the second embodiment can execute the number of instructions equal to or greater than that of the first embodiment with the same instruction memory size.

  FIG. 13 is a flowchart illustrating an operation example of the accelerator according to the second embodiment. Note that step S1301, step S1305, and step S1306 shown in FIG. 13 are the same processing as step S1001, step S1006, and step S1007, and thus description thereof is omitted.

  After the process of step S1301, the accelerator 102 determines whether or not information indicating an annotation is stored in the opcode field (step S1302). When the information indicating the annotation is stored (step S1302: Yes), the accelerator 102 records the information specifying the intermediate instruction stored in the intermediate instruction field (step S1303), and proceeds to the process of step S1305. When the information indicating the annotation is not stored (step S1302: No), the accelerator 102 executes the native instruction (step S1304), and proceeds to the process of step S1305.

  As described above, according to the data processing device, when an annotation code is received, information specifying an intermediate instruction in the annotation code is recorded. Thereby, the data processing system can reduce the amount of memory used per native instruction as compared to the first embodiment.

(Description of Embodiment 3)
The data processing system 100 according to the second embodiment reduces the amount of memory used per native instruction from that of the first embodiment. The data processing system 100 according to the third embodiment provides a method that can further reduce the amount of used memory than the data processing system 100 according to the second embodiment. Note that the hardware of the data processing system 100 according to the third embodiment is the same as the hardware of the data processing system 100 according to the first embodiment, and a description thereof will be omitted.

  FIG. 14 is a block diagram of an example of functions of the data processing system according to the third embodiment. The data processing system 100 according to the third exemplary embodiment includes a storage unit 1401, a reception unit 1101, a determination unit 1402, an execution unit 1403, a recording unit 1404, an output unit 315, a storage unit 321, and a detection unit 322. A conversion unit 1411, a transmission unit 1112, and an acquisition unit 325. The detection unit 322, the acquisition unit 325, the conversion unit 1411, and the transmission unit 1112 realize their functions when the CPU 101 executes a program stored in the storage device. Here, specifically, the storage device is, for example, the ROM 201, the RAM 202, the magnetic disk 204, the optical disk 206, etc. shown in FIG. Note that the functional units having the same reference numerals as those in the first or second embodiment have the same functions as those in the first or second embodiment, and thus the description thereof is omitted.

  The storage unit 1401 has a function of storing a combination of an instruction code that has a one-to-one correspondence with a code before conversion and information that identifies the code before conversion. Here, the instruction code corresponding one-to-one with the code before conversion is an instruction code corresponding to the code before conversion not included in the instruction code corresponding to the other code before conversion. For example, the storage unit 1401 stores “and” as a code before conversion and a native instruction “AND” corresponding to “and” one-to-one.

  The determination unit 1402 has a one-to-one correspondence with the code before conversion that is different from the code before conversion of the series of instruction codes, whether the subsequent code of the annotation code is any one of the series of instruction codes. It has a function of determining whether or not the corresponding instruction code. For example, the determination unit 1402 determines whether or not the subsequent code is “AND” which is an instruction code corresponding to one to one. Note that the determination result is stored in a storage area such as a register of the accelerator 102.

  The execution unit 1403 has a function of executing an instruction code having a one-to-one correspondence with another code before conversion when the determination unit 1402 determines that the instruction code has a one-to-one correspondence with another code before conversion. Have. For example, the execution unit 1403 executes the native instruction “AND”.

  The recording unit 1404 records instruction codes that have a one-to-one correspondence with other codes before conversion. For example, the recording unit 1404 records “AND”. In addition, the recording unit 1404 may store information that identifies another code before conversion with reference to the storage unit 1401.

  The conversion unit 1411 refers to the storage unit 321 and converts the code before conversion into an instruction code when the code before conversion has a one-to-one correspondence with the instruction code. It has a function to convert to code. As for the method for determining whether or not the code before conversion has a one-to-one correspondence with the instruction code, for example, a new field for storing an identifier indicating whether or not the template information 331 has a one-to-one correspondence is set. The determination may be made with reference to a new field. Further, the set content is the same information as the recording unit 1404.

  FIG. 15 is an explanatory diagram illustrating an example of intermediate instruction conversion by the JIT compiler according to the third embodiment. FIG. 15 shows a specific conversion example of the intermediate instruction. The JIT compiler 301 converts the intermediate instruction 1501_M into a native instruction 1501_N. As a more detailed example, a case will be described in which the intermediate instruction 1501-1_M “and r3, r2, r3” included in the intermediate instruction 1501_M is converted.

  The JIT compiler 301 determines from the opcode portion of the intermediate instruction 1501-1_M that the intermediate instruction has a one-to-one correspondence with the native instruction, and converts it to the native instruction 1501-1_N without adding an annotation code. Since other intermediate instructions are not one-to-one correspondence, the JIT compiler 301 assigns an annotation code.

  As described above, the annotation code is not assigned to the native instruction that corresponds to the intermediate instruction on a one-to-one basis, so that the data processing system 100 according to the third embodiment uses a memory amount that is larger than that of the data processing system 100 according to the second embodiment. Can be reduced.

  FIG. 16 is a flowchart illustrating an operation example of the accelerator according to the third embodiment. Note that step S1601 to step S1603, step S1608, and step S1609 shown in FIG. 16 are the same processing as step S1301 to step S1303, step S1305, and step S1306, and thus description thereof is omitted.

  When the information indicating the annotation is not stored (step S1602: No), the accelerator 102 determines whether the instruction is a native instruction that has a one-to-one correspondence with the intermediate instruction (step S1604). If the native instruction has a one-to-one correspondence (step S1604: YES), the accelerator 102 executes the native instruction (step S1605). Subsequently, the accelerator 102 records information for specifying an intermediate instruction corresponding to the native instruction (step S1606), and proceeds to the process of step S1608. Note that step S1605 and step S1606 may be executed within the same clock cycle, or may be executed in the order of step S1606 and step S1605. If it is not a one-to-one corresponding native instruction (step S1604: No), the accelerator 102 executes the native instruction (step S1607), and proceeds to the process of step S1608.

  FIG. 17 is an explanatory diagram of an application example of a system using a computer according to the first to third embodiments. In FIG. 17, a network NW is a network in which a server 1701 and clients 1711 to 1714 can communicate, and includes, for example, a LAN, a WAN, the Internet, a mobile phone network, and the like.

  The client 1711 is a notebook PC (Personal Computer). A client 1712 is a desktop PC, and a client 1713 is a mobile phone. As a mobile phone, the client 1713 may be a smartphone or a PHS (Personal Handyphone System). The client 1714 is a tablet terminal. The server 1701 and the clients 1711 to 1714 in FIG. 17 each have a CPU and an accelerator, and execute the operation according to any one of the first to third embodiments.

  As described above, according to the data processing apparatus, when a native instruction corresponding to the intermediate instruction is received, the native instruction is recorded. Thereby, the data processing system can reduce the amount of memory used per native instruction as compared to the second embodiment. Therefore, the data processing system can execute the number of instructions equal to or greater than that of the second embodiment with the same instruction memory size.

  In addition, the data processing apparatus stores a combination of an instruction code that corresponds to the code before conversion and the information that specifies the code before conversion, and responds when a native instruction that corresponds to the code is received. Information identifying the code before conversion may be recorded. Thereby, the data processing system can make all the performance information provided to the developer in units of intermediate instructions. Further, the data processing apparatus may not store a combination of an instruction code corresponding to one-to-one and information specifying the code before conversion. In this case, the native information is included in the performance information, but since it has a one-to-one correspondence, it is easy for the CPU to convert from the native instruction to the intermediate instruction.

  The conversion method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The conversion program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The conversion program may be distributed through a network such as the Internet.

  Further, the accelerator 102 described in the present embodiment is an application-specific IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device) such as an FPGA. ) Can also be realized. Specifically, the functions of the accelerator 102 described above (reception unit 311 to output unit 315, reception unit 1101 to recording unit 1104, storage unit 1401 to recording unit 1404) are defined by HDL description, and the HDL description is logically synthesized. Then, the accelerator 102 can be manufactured by giving it to the ASIC or PLD.

  The following additional notes are disclosed with respect to the above-described first to third embodiments.

(Additional remark 1) The reception part which receives instruction code and the information which specifies the code before the conversion of the said instruction code linked | related with the said instruction code,
A recording unit that records information for specifying the code before the conversion by executing the instruction code;
A data processing apparatus comprising:

(Additional remark 2) It further has the judgment part which judges whether the information which specifies the code before the conversion received by the reception part is the information which shows that the code before the conversion does not exist,
The recording unit is
When the determination unit determines that the information for specifying the code before conversion is information indicating that the code before conversion does not exist, information for specifying the code before conversion by executing the instruction code Do not record,
The data processing apparatus according to appendix 1, characterized by the above.

(Additional remark 3) The reception part which receives the comment code | symbol containing the information which shows the comment with respect to a series of instruction codes, and the information which identifies the code before conversion of the said series of instruction codes, or the said series of instruction codes,
When the annotation code is received by the receiving unit, before executing the series of instruction codes, a recording unit for recording information that identifies the code before conversion of the series of instruction codes;
When the series of instruction codes is received by the reception unit, an execution unit that executes the series of instruction codes;
A data processing apparatus comprising:

(Appendix 4) The recording unit
By executing the instruction code, record information for identifying the code before the conversion in the execution order of the instruction code;
The data processing apparatus according to appendix 1 or 3, characterized by the above.

(Appendix 5) The recording unit
By executing the instruction code, the number of executions of the instruction code is recorded in association with information for specifying the code before the conversion.
The data processing apparatus according to appendix 1 or 3, characterized by the above.

(Supplementary Note 6) The subsequent code of the annotation code is one of the instruction codes in the series of instruction codes, or another code before conversion that is different from the code before conversion of the series of instruction codes and 1 A determination unit for determining whether the instruction code corresponds to one-to-one,
The execution unit is
If it is determined that the instruction code has a one-to-one correspondence with the other code before conversion, the instruction code has a one-to-one correspondence with the other code before conversion;
The recording unit is
Record an instruction code that has a one-to-one correspondence with the other code before conversion;
The data processing device according to attachment 3, wherein

(Supplementary Note 7) A storage unit that stores a combination of an instruction code that has a one-to-one correspondence with the other code before conversion and information that specifies the other code before conversion,
The recording unit is
Referring to the storage unit, and recording information identifying the other code before conversion,
The data processing apparatus according to appendix 6, wherein:

(Appendix 8) The recording unit
Information for specifying the pre-conversion code, information for specifying the other pre-conversion code, in order of execution of the instruction code and the one-to-one correspondence with the other pre-conversion code; Record,
The data processing apparatus according to appendix 7, characterized by the above.

(Appendix 9) The recording unit
Recording the number of executions of the instruction code corresponding one-to-one with the other code before conversion in association with the information specifying the other code before conversion;
The data processing apparatus according to appendix 7, characterized by the above.

(Supplementary Note 10) A storage unit that stores a combination of an instruction code and a code before conversion of the instruction code;
When the pre-conversion code is detected, the pre-conversion code is converted into information specifying the instruction code and the pre-conversion code associated with the instruction code with reference to the storage unit. A conversion unit;
A transmission unit that transmits the instruction code and information identifying the pre-conversion code associated with the instruction code from the own device to another device;
A conversion device comprising:

(Supplementary note 11) A data processing system including a first device and a second device that executes a specific process,
A storage unit for storing a combination of an instruction code executable by the second device and a code before conversion of the instruction code;
When the pre-conversion code is detected, a conversion unit that converts the pre-conversion code into the instruction code and information identifying the pre-conversion code associated with the instruction code;
A transmission unit that transmits the instruction code and information identifying the pre-conversion code associated with the instruction code from the first device to the second device;
A receiving unit that receives, by the second device, the instruction code and information that identifies the code before conversion associated with the instruction code;
A recording unit configured to record information for identifying the code before conversion by the execution of the instruction code by the second device;
A data processing system comprising:

(Additional remark 12) The computer which can access the memory | storage part which memorize | stores the combination of the instruction code and the code before conversion of the said instruction code,
When the pre-conversion code is detected, the pre-conversion code is converted into information specifying the instruction code and the pre-conversion code associated with the instruction code by referring to the storage unit. ,
Transmitting the instruction code and information identifying the pre-conversion code associated with the instruction code to another device;
The conversion method characterized by performing a process.

(Supplementary note 13) To a computer accessible to a storage unit storing a combination of an instruction code and a code before conversion of the instruction code,
When the pre-conversion code is detected, referring to the combination, the pre-conversion code is converted into the instruction code and information identifying the pre-conversion code associated with the instruction code.
A conversion program characterized by causing processing to be executed.

100 Data processing system 101 CPU
DESCRIPTION OF SYMBOLS 102 Accelerator 301 JIT compiler 302 Device driver 311, 1101 Reception part 312, 1102, 1402 Judgment part 313, 1103, 1403 Execution part 314, 1104, 1404 Recording part 315 Output part 321 Storage part 322 Detection part 323, 1111, 1411 Conversion part 324, 1112, 1412 Transmission unit 325 Acquisition unit 331 Template information 1401 Storage unit

Claims (9)

An accepting unit that accepts an instruction code and information that identifies a code before conversion of the instruction code associated with the instruction code;
A recording unit that records information for specifying the code before the conversion by executing the instruction code;
A data processing apparatus comprising: A determination unit that determines whether or not the information specifying the code before conversion received by the reception unit is information indicating that the code before conversion does not exist;
The recording unit is
When the determination unit determines that the information for specifying the code before conversion is information indicating that the code before conversion does not exist, information for specifying the code before conversion by executing the instruction code Do not record,
The data processing apparatus according to claim 1. A reception unit for receiving an annotation code including information indicating an annotation for a series of instruction codes and information specifying a code before conversion of the series of instruction codes, or the series of instruction codes;
When the annotation code is received by the receiving unit, before executing the series of instruction codes, a recording unit for recording information that identifies the code before conversion of the series of instruction codes;
When the series of instruction codes is received by the reception unit, an execution unit that executes the series of instruction codes;
A data processing apparatus comprising: The subsequent code of the annotation code is one of the instruction codes in the series of instruction codes, or has a one-to-one correspondence with another code before conversion different from the code before conversion of the series of instruction codes. A determination unit for determining whether or not the instruction code;
The execution unit is
If it is determined that the instruction code has a one-to-one correspondence with the other code before conversion, the instruction code has a one-to-one correspondence with the other code before conversion;
The recording unit is
Record an instruction code that has a one-to-one correspondence with the other code before conversion;
The data processing apparatus according to claim 3. A storage unit that stores a combination of an instruction code that has a one-to-one correspondence with the other code before conversion and information that identifies the other code before conversion;
The recording unit is
Referring to the storage unit, and recording information identifying the other code before conversion,
The data processing apparatus according to claim 4, wherein: A storage unit for storing a combination of an instruction code and a code before conversion of the instruction code;
When the pre-conversion code is detected, the pre-conversion code is converted into information specifying the instruction code and the pre-conversion code associated with the instruction code with reference to the storage unit. A conversion unit;
A transmission unit that transmits the instruction code and information identifying the pre-conversion code associated with the instruction code from the own device to another device;
A conversion device comprising: A data processing system including a first device and a second device that executes a specific process,
A storage unit for storing a combination of an instruction code executable by the second device and a code before conversion of the instruction code;
When the pre-conversion code is detected, a conversion unit that converts the pre-conversion code into the instruction code and information identifying the pre-conversion code associated with the instruction code;
A transmission unit that transmits the instruction code and information identifying the pre-conversion code associated with the instruction code from the first device to the second device;
A receiving unit that receives, by the second device, the instruction code and information that identifies the code before conversion associated with the instruction code;
A recording unit configured to record information for identifying the code before conversion by the execution of the instruction code by the second device;
A data processing system comprising: A computer capable of accessing a storage unit that stores a combination of an instruction code and a code before conversion of the instruction code,
When the pre-conversion code is detected, the pre-conversion code is converted into information specifying the instruction code and the pre-conversion code associated with the instruction code by referring to the storage unit. ,
Transmitting the instruction code and information identifying the pre-conversion code associated with the instruction code to another device;
The conversion method characterized by performing a process. To a computer accessible to a storage unit storing a combination of an instruction code and a code before conversion of the instruction code,
When the pre-conversion code is detected, referring to the combination, the pre-conversion code is converted into the instruction code and information identifying the pre-conversion code associated with the instruction code.
A conversion program characterized by causing processing to be executed.

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