JP2013118266A - Manufacturing method of magnetoresistive element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a magnetoresistive element capable of preventing formation of a short path.SOLUTION: According to one embodiment, a manufacturing method of a magnetoresistive element comprises the steps of: sequentially laminating, on a first electrode, a recording layer having a variable magnetization direction, a non-magnetic layer, a fixed layer having a fixed magnetization direction and a second electrode; processing the fixed layer by using the second electrode processed into a predetermined shape as a mask; forming side wall portions having first side wall films and second side wall films interposed among the first side wall films, the fixed layer and the second electrode on both side portions of the fixed layer and the second electrode; and processing the non-magnetic layer and the recording layer by physical etching by using the side wall portions as the mask. The first side wall films have an etching rate in the physical etching less than that of the second side wall films.

Description

  Embodiments described herein relate generally to a method of manufacturing a magnetoresistive element.

  A magnetic random access memory (MRAM) using a ferromagnetic material includes an MTJ (Magnetic Tunnel Junction) element using a tunneling magnetoresistive (TMR) effect as a memory element. An MTJ element is composed of three thin films, a recording layer and a reference layer made of a magnetic material, and an insulating layer (barrier layer) sandwiched between them, and stores information according to the magnetization state of the recording layer and the reference layer. To do. In a spin injection MRAM using a spin momentum transfer (SMT) writing method, information is written to the MTJ element by energizing the film surface of the MTJ element in the vertical direction.

  When forming an MTJ element, the stacked recording layer, insulating layer, and reference layer are processed using physical etching such as ion beam etching. When the recording layer under the insulating layer is processed, the magnetic material scattered by the processing adheres to the side surfaces of the insulating layer, and a short path is formed to short-circuit the magnetic layers. As countermeasures against deposits, it is known to oxidize the side surface of the MTJ element and to provide a sidewall mask.

  However, when the side surface of the MTJ element is oxidized, there is a problem that a bird's beak occurs in the MTJ element and the spin injection efficiency is deteriorated. When the side wall mask is provided, a short circuit near the insulating layer can be avoided, but another short path is formed by the material attached to the side wall mask.

JP 2008-218829 A

  An object of this invention is to provide the manufacturing method of the magnetoresistive element which can prevent formation of a short path.

  According to this embodiment, the method of manufacturing a magnetoresistive element includes a step of sequentially stacking a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a second electrode on a first electrode, and processing into a predetermined shape. The step of processing the second magnetic layer using the second electrode as a mask, the first side wall film, the first side wall film, and the second magnetic film on both sides of the second magnetic layer and the second electrode Forming a sidewall portion having a second sidewall film sandwiched between a layer and the second electrode, and processing the nonmagnetic layer and the first magnetic layer by physical etching using the sidewall portion as a mask. A process. The first sidewall film has a lower etching rate in the physical etching than the second sidewall film.

It is a schematic block diagram of the magnetoresistive element which concerns on embodiment of this invention. It is a schematic block diagram of MRAM provided with the magnetoresistive element based on the embodiment. It is process sectional drawing explaining the manufacturing method of the magnetoresistive element based on the embodiment. FIG. 4 is a process cross-sectional view subsequent to FIG. 3. FIG. 5 is a process cross-sectional view subsequent to FIG. 4. FIG. 6 is a process cross-sectional view subsequent to FIG. 5. FIG. 7 is a process cross-sectional view subsequent to FIG. 6. FIG. 8 is a process cross-sectional view subsequent to FIG. 7. It is a figure which shows the side wall film | membrane etched. It is a schematic block diagram of the magnetoresistive element by a 1st comparative example. It is a schematic block diagram of the magnetoresistive element by the 2nd comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of a magnetoresistive element (MTJ element) 1 according to an embodiment of the present invention. The MTJ element 1 has a laminated structure in which a lower electrode 10, an underlayer 11, a recording layer (free layer) 12, a tunnel barrier layer (nonmagnetic layer) 13, a reference layer (fixed layer) 14, and an upper electrode 15 are laminated in this order. Have. The upper electrode 15 also functions as a hard mask layer. The recording layer 12 and the reference layer 14 may be stacked in reverse order. Further, the planar shape of the MTJ element 1 is not particularly limited.

  The recording layer 12 has a variable (reversed) magnetization (or spin) direction. The reference layer 14 has the same magnetization direction (fixed). That the magnetization direction of the reference layer 14 is unchanged means that the magnetization direction of the reference layer 14 does not change when a magnetization reversal current used to reverse the magnetization direction of the recording layer 12 is passed through the reference layer 14. Means.

  Therefore, by using a magnetic layer having a large reversal current as the reference layer 14 and using a magnetic layer having a reversal current smaller than that of the reference layer 14 as the recording layer 12, the recording layer 12 having a variable magnetization direction and the magnetization direction unchanged. The MTJ element 1 including the reference layer 14 can be realized.

  When the magnetization reversal is caused by spin-polarized electrons, the reversal current is proportional to the attenuation constant, the anisotropic magnetic field, and the volume. Therefore, these are appropriately adjusted so that the reversal current between the recording layer 12 and the reference layer 14 You can make a difference.

  The easy magnetization directions of the recording layer 12 and the reference layer 14 may be perpendicular (perpendicular magnetization) to the film surface (or laminated surface) or parallel (in-plane magnetization) to the film surface. Good. The perpendicular magnetization magnetic layer has magnetic anisotropy in the direction perpendicular to the film surface, and the in-plane magnetization magnetic layer has in-plane magnetic anisotropy. The underlayer 11 is provided to control the crystal orientation of the perpendicular magnetization magnetic layer.

  As shown in FIG. 1, sidewall films 16 and 17 are provided on both sides of the reference layer 14 and the upper electrode 15. The sidewall film 16 is provided on both sides of the reference layer 14 and the upper electrode 15 and on the deactivated region of the recording layer 12. The sidewall film 17 is adjacent to the sidewall film 16. In other words, the sidewall film 16 is provided between the side portions of the reference layer 14 and the upper electrode 15 and the sidewall film 17. Further, a sidewall film 16 is provided between the tunnel barrier layer 13 and the sidewall film 17 above the deactivation region of the recording layer 12. Therefore, the upper portion (top portion) of the sidewall film 17 is located at a position separated from the side surface of the upper electrode 15 by more than the film thickness of the sidewall film 16.

As shown in FIG. 1, the upper portion of the sidewall film 17 is located higher than the upper portion (upper surface) of the sidewall film 16. Further, the upper portion of the sidewall film 17 is at a position lower than the upper surface of the upper electrode 15.

  Deposits 18 are attached to the side surface of the side wall film 17, the side surface of the side wall film 16 below the side wall film 17, the side surface of the tunnel barrier layer 13, and the side surface of the deactivation region of the recording layer 12. The deposit 18 is a material that is etched and scattered when the tunnel barrier layer 13, the recording layer 12, and the base layer 11 are processed by physical etching using the sidewall films 16 and 17 as a mask.

  FIG. 2 shows an example of a schematic configuration of the MRAM including the MTJ element 1. Here, an MRAM including a 1Tr + 1MTJ type memory cell configured by connecting one MTJ element 1 and one select transistor 22 in series will be described.

  The semiconductor substrate 20 has an element isolation insulating layer 21 in a surface region, and a surface region where the element isolation insulating layer 21 is not formed becomes an element region (active region). The element isolation insulating layer 21 is configured by, for example, STI (Shallow Trench Isolation), and silicon oxide is used.

  A selection transistor 22 made of an NMOS transistor is formed on the semiconductor substrate 20. The selection transistor 22 is formed on the semiconductor substrate 20 between the source region 23A and the drain region 23B via the gate insulating film 24 and the source region 23A and the drain region 23B that are formed in the semiconductor substrate 20 so as to be separated from each other. A gate electrode 25 is provided. Source region 23A is connected to a source line (not shown) via a contact.

  An interlayer insulating film 26 is provided so as to cover the selection transistor 22. The MTJ element 1 is provided on the interlayer insulating film 26. The lower electrode 10 of the MTJ element 1 and the drain region 23B are electrically connected by a contact 27.

  An interlayer insulating film 28 is provided on the interlayer insulating film 26 so as to cover the MTJ element 1. The upper surface of the interlayer insulating film 28 is planarized by a CMP (Chemical Mechanical Polishing) method so that the upper surface of the upper electrode 15 is exposed. A wiring layer (bit line) 29 is provided on the interlayer insulating film 28 and the upper electrode 15.

  As shown in FIG. 1, the upper portion of the side wall film 17 is located at a position separated from the side surface of the upper electrode 15 by more than the film thickness of the side wall film 16. Therefore, it is possible to prevent the upper electrode 15 and the lower electrode 10 from being short-circuited by the deposit 18.

  Further, the upper portion of the sidewall film 17 is at a position lower than the upper surface of the upper electrode 15. Therefore, it is possible to prevent the lower electrode 10 and the wiring layer 29 (see FIG. 2) from being short-circuited due to the deposits.

  Next, a method for manufacturing such an MTJ element 1 will be described with reference to FIGS.

  As shown in FIG. 3, a lower electrode 10, an underlayer 11, a recording layer 12, a tunnel barrier layer 13, a reference layer 14, and an upper electrode 15 are sequentially formed. For example, the recording layer 12 has a thickness of 1 to 1.5 nm, the tunnel barrier layer 13 has a thickness of 1 nm, the reference layer 14 has a thickness of 20 nm, and the upper electrode 15 has a thickness of 80 nm. Note that an interlayer insulating film 26 and a contact 27 as shown in FIG. 2 are provided under the lower electrode 10, but illustration thereof is omitted.

  For the lower electrode 10 and the upper electrode 15, for example, tantalum (Ta) or titanium nitride (TiN) is used.

  The recording layer 12 and the reference layer 14 include, for example, at least one element of iron (Fe), cobalt (Co), and nickel (Ni), chromium (Cr), platinum (Pt), and palladium (Pd). An alloy containing at least one of these elements is used.

  The underlayer 11 is for controlling crystal orientation, and a suitable material varies depending on the material of the recording layer 12. For example, when the recording layer 12 is FePt, the underlayer 11 is preferably a Pt / Cr / NiTa laminated film.

  The tunnel barrier layer 13 is made of an insulating material such as magnesium oxide (MgO).

  As shown in FIG. 4, the upper electrode 15 is processed into the same shape as the planar shape of the MTJ element 1 using lithography and RIE (Reactive Ion Etching). Then, the reference layer 14 is processed by an IBE (Ion Beam Etching) method using the upper electrode 15 as a hard mask.

  As shown in FIG. 5, ion implantation is performed using the upper electrode 15 as a mask, and the deactivation process of the recording layer 12 protruding from the reference layer 14 (the recording layer 12 in a region other than the region below the reference layer 14) is performed. Do. As a result, the region other than the region below the reference layer 14 in the recording layer 12 becomes an inactive region.

  As shown in FIG. 6, the insulating film 16 is formed so as to cover the surfaces of the upper electrode 15, the reference layer 14, and the tunnel barrier layer 13 by using a CVD (Chemical Vapor Deposition) method. Subsequently, an insulating film 17 is formed on the insulating film 16 using a CVD method.

  The insulating film 16 has the same or higher etching resistance than the reference layer 14 (or the recording layer 12) with respect to the subsequent etching process of the recording layer 12 (see FIG. 8) (the etching rate is the same). Degree or low).

  Compared to the upper electrode 15, the insulating film 17 has the same or lower etching resistance (the etching rate is the same or higher) with respect to the etching process of the recording layer 12 performed later. In addition, the insulating film 17 has higher etching resistance against the etching process of the recording layer 12 performed later (the etching rate is lower) than the insulating film 16.

  That is, the etching resistance to the etching process of the recording layer 12 to be performed later has a relationship of upper electrode 15 ≧ insulating film 17> insulating film 16 ≧ reference layer 14.

  For the insulating film 16, for example, a silicon oxide film or a silicon nitride film can be used. As the insulating film 17, an aluminum nitride film, a nitride-rich tantalum nitride film, a tantalum silicon nitride film, or the like can be used.

  As shown in FIG. 7, the insulating films 16 and 17 are etched back until the upper surface of the upper electrode 15 is exposed. Thereby, the sidewall films 16 and 17 can be formed on both sides of the upper electrode 15 and the reference layer 14.

  As shown in FIG. 8, the tunnel barrier layer 13, the recording layer 12, and the base layer 11 are processed by physical etching such as the IBE method using the sidewall films 16 and 17 as a mask.

  Since the sidewall film 16 has lower etching resistance than the sidewall film 17, the etching rate is higher than that of the sidewall film 17, and the position of the upper surface is lower than the upper portion of the sidewall film 17. For example, the upper surface of the sidewall film 16 is lower than the upper surface of the upper electrode 15 by 50 nm or more. In this embodiment, since the side wall film 17 exists outside the side wall film 16, the side wall film 16 to be removed is smaller than in the case where the side wall mask is composed of only the side wall film 16.

  As shown in FIG. 9, the side wall film 17 is exposed not only on the outer side but also on the inner side as the position of the upper surface of the inner side wall film 16 is lowered. Therefore, in this embodiment, more sidewall films 17 are removed than when the sidewall mask is composed of only the sidewall films 17, and the height between the upper portion of the sidewall films 17 and the upper surface height of the upper electrode 15 is sufficient. Can make a big difference.

  By etching the recording layer 12 and the like, the metal material scatters and adheres to the side surfaces of the side wall film 17 and becomes the deposit 18. However, in the present embodiment, since there is a sufficient difference d1 between the height of the upper portion of the sidewall film 17 and the height of the upper surface of the upper electrode 15, the deposit 18 is a wiring layer 29 provided on the upper electrode 15. (See FIG. 2) and a short path between the lower electrode 10 can be prevented.

  Further, since the sidewall film 16 is provided between the sidewall film 17 and the upper electrode 15, there is a gap d <b> 2 greater than the film thickness of the sidewall film 16 between the deposit 18 and the upper electrode 15. Therefore, it is possible to prevent the deposit 18 from becoming a short path between the upper electrode 15 and the lower electrode 10.

  (First Comparative Example) In the above embodiment, the sidewall mask having the sidewall films 16 and 17 is formed on both sides of the upper electrode 15 and the reference layer 14. In other words, the case where only the insulating film 16 is formed in the step shown in FIG. 6 will be described.

  As shown in FIG. 10, when the tunnel barrier layer 13, the recording layer 12, and the base layer 11 are processed by the IBE method, the sidewall mask formed only of the sidewall film 16 is removed because it has low etching resistance (high etching rate). A large amount is applied, and the side surface of the upper electrode 15 is exposed.

  Then, the deposit 18 generated when the metal material scattered by the etching of the recording layer 12 or the like adheres to the side surface of the sidewall film 16 or the like becomes a short path that short-circuits the upper electrode 15 and the lower electrode 10.

  (Second Comparative Example) In the above embodiment, the side wall masks having the side wall films 16 and 17 are formed on both sides of the upper electrode 15 and the reference layer 14. In other words, the case where only the insulating film 17 is formed in the step shown in FIG. 6 will be described.

  As shown in FIG. 11, when the tunnel barrier layer 13, the recording layer 12, and the base layer 11 are processed by the IBE method, the sidewall mask formed only of the sidewall film 17 has high etching resistance (low etching rate) and is removed. Therefore, the difference between the height of the upper portion of the sidewall film 17 and the height of the upper surface of the upper electrode 15 is reduced. A metal material (attachment 18) scattered by etching of the recording layer 12 or the like is attached to the side surface of the sidewall film 17.

  In the subsequent process, the wiring layer 29 (see FIG. 2) is formed on the upper electrode 15, but the sidewall film 17 may be exposed during the planarization process of the interlayer insulating film 28 (see FIG. 2). The wiring layer 29 formed after such planarization is in contact with the deposit 18 on the side surface of the sidewall film 17. Therefore, the deposit 18 becomes a short path that short-circuits the wiring layer 29 and the lower electrode 10.

  On the other hand, in this embodiment, the sidewall mask provided on both sides of the upper electrode 15 and the reference layer 14 is between the sidewall film 17 having high etching resistance and between the sidewall film 17 and the upper electrode 15 and the reference layer 14. And a sidewall film 16 having a low etching resistance.

  Since there is a space larger than the film thickness of the sidewall film 16 between the deposit 18 on the side surface of the sidewall film 17 and the upper electrode 15, the deposit 18 becomes a short path between the upper electrode 15 and the lower electrode 10. Can be prevented.

  Further, since the etching rate of the sidewall film 16 is high, the inside of the sidewall film 17 is exposed, and the sidewall film 17 is etched not only from the outside but also from the inside. Therefore, there is a sufficient difference between the height of the upper portion of the sidewall film 17 and the height of the upper surface of the upper electrode 15, and the deposit 18 is formed on the wiring layer 29 (see FIG. 2) provided on the upper electrode 15 and the lower portion. A short path with the electrode 10 can be prevented.

  Thus, according to the present embodiment, it is possible to prevent the formation of a short path when manufacturing a magnetoresistive element.

  In the above embodiment, the manufacturing method in which the reference layer 14 is located above the recording layer 12 has been described. However, this manufacturing method can also be applied to a configuration in which the recording layer 12 is located above the reference layer 14. . When the recording layer 12 is located above the reference layer 14, the deactivation process corresponding to FIG. 5 is not necessary.

  In the above embodiment, a single junction type MTJ element in which one reference layer and one recording layer sandwich a tunnel barrier layer is illustrated. However, the present invention is not limited to this configuration, and may be applied to a double junction type MTJ element in which two reference layers are arranged above and below the recording layer via a nonmagnetic layer.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

DESCRIPTION OF SYMBOLS 1 MTJ element 10 Lower electrode 11 Underlayer 12 Recording layer 13 Tunnel barrier layer 14 Reference layer (fixed layer)
15 Upper electrode 16, 17 Side wall film 18 Deposit 29 Wiring layer

Claims (7)

Laminating a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a second electrode in order on the first electrode;
Processing the second magnetic layer using the second electrode processed into a predetermined shape as a mask;
A first sidewall film and a second sidewall film sandwiched between the first sidewall film and the second magnetic layer and the second electrode are provided on both sides of the second magnetic layer and the second electrode. Forming a sidewall portion;
Processing the nonmagnetic layer and the first magnetic layer by ion beam etching using the side wall as a mask;
With
The first sidewall film has a lower etching rate in the ion beam etching than the second sidewall film and the second magnetic layer, and includes an aluminum nitride film, a tantalum nitride film, or a tantalum silicon nitride film,
The second sidewall film has a higher etching rate in the ion beam etching than the second electrode, and includes a silicon oxide film or a silicon nitride film,
The material of the first magnetic layer scattered by the ion beam etching adheres to the side surface of the first sidewall film,
One of the first magnetic layer and the second magnetic layer is a recording layer having a variable magnetization direction, and the other is a fixed layer having a fixed magnetization direction. Laminating a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a second electrode in order on the first electrode;
Processing the second magnetic layer using the second electrode processed into a predetermined shape as a mask;
A first sidewall film and a second sidewall film sandwiched between the first sidewall film and the second magnetic layer and the second electrode are provided on both sides of the second magnetic layer and the second electrode. Forming a sidewall portion;
Processing the nonmagnetic layer and the first magnetic layer by physical etching using the side wall as a mask;
With
The method of manufacturing a magnetoresistive element, wherein the first side wall film has a lower etching rate in the physical etching than the second side wall film.   3. The first sidewall film has a lower etching rate in the physical etching than the second magnetic layer, and the second sidewall film has a higher etching rate in the physical etching than the second electrode. The manufacturing method of the magnetoresistive element of description.   4. The method of manufacturing a magnetoresistive element according to claim 2, wherein a material of the first magnetic layer scattered by the physical etching adheres to a side surface of the first sidewall film. 5.   The first sidewall film is an aluminum nitride film, a tantalum nitride film, or a tantalum silicon nitride film, and the second sidewall film is a silicon oxide film or a silicon nitride film. 5. A method for producing a magnetoresistive element according to any one of 4 above.   6. The method of manufacturing a magnetoresistive element according to claim 2, wherein the physical etching is ion beam etching.   7. One of the first magnetic layer and the second magnetic layer is a recording layer whose magnetization direction is variable, and the other is a fixed layer whose magnetization direction is fixed. The manufacturing method of the magnetoresistive element of description.

Images