JP2013114714A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having an advantage in terms of miniaturization.SOLUTION: According to an embodiment, the semiconductor memory device comprises: a memory cell array 11 in which a plurality of memory cells are arranged; a plurality of address areas (IO<0> area to IO<7> area) that latch data of the plurality of memory cells, and are divided and arranged for each input or output (I/O) of data of the memory cell array; internal bus wires 20 that are arranged so as to correspond to the plurality of address areas and electrically connected in series to the plurality of address areas, respectively; and a control circuit 15 that controls data transfer of the internal bus wires.

Description

  The present invention relates to a semiconductor memory device.

  As an example of the semiconductor memory device, there is a NAND flash memory, for example.

  Here, the decoder of the NAND flash memory is strongly driven by a relatively large buffer when data is input.

  On the other hand, at the time of data output, a shared bus (Shared-1bit-bus) or the like must be driven by a small-sized transistor. Therefore, it is necessary to first buffer the data in a buffer in the decoder and then transfer the data to an internal I / O bus. This can cause the decoder area to increase. That is, the size of the buffer arranged in the decoder is large.

  Furthermore, the current consumption increases because the size of the buffer in the decoder is large. In recent years, there is a case where an internal I / O bus (Internal I / O bus) is divided for input and output for speeding up, and each of them is operated in parallel. In this case, the number of internal I / O buses (Internal I / O buses) increases by the number of divisions, and the occupied area increases. In addition, in this case, a shield wiring such as a power supply wiring needs to be laid out between the internal I / O buses so that the data is not affected. This also causes an increase in wiring area.

JP-A-9-274527

  A semiconductor memory device advantageous for miniaturization is provided.

  According to the embodiment, a semiconductor memory device according to an aspect latches a memory cell array in which a plurality of memory cells are arranged, data of the plurality of memory cells, and inputs or outputs (I / A plurality of address areas that are divided for each O), internal bus lines that are arranged corresponding to the plurality of address areas and are electrically connected to the plurality of address areas in series, and And a control circuit for controlling data transfer of the internal bus wiring.

1 is a block diagram showing an example of the overall configuration of a semiconductor memory device according to a first embodiment. FIG. 2 is an equivalent circuit diagram illustrating a configuration example of a block in FIG. 1. The figure which shows the example of address allocation of the data latch area | region in FIG. FIG. 4 is a diagram showing an example of address allocation of the data latch area in FIG. 3 in more detail. The figure which shows the structural example of address area | region IO <0>. FIG. 6 is a diagram showing a configuration example of an address area IO <0> in Add 0 in FIG. 5. The block diagram which shows the bad column replacement system which concerns on 2nd Embodiment. The equivalent circuit diagram which shows the pointer system which concerns on 3rd Embodiment. The figure which shows the pointer signal which concerns on 3rd Embodiment. The timing chart figure which shows the operation | movement waveform of the pointer system which concerns on 3rd Embodiment. 1 is a block diagram showing an example of the overall configuration of a semiconductor memory device according to a reference example. FIG. 12 is an equivalent circuit diagram showing the decoder circuit in FIG. 11. The top view which shows the layout of the internal I / O bus concerning a reference example. The figure which shows the example of address allocation of the data latch area | region which concerns on a reference example. The figure which shows the example of address allocation of the data latch area | region which concerns on a reference example in more detail. The equivalent circuit diagram which shows the pointer system which concerns on a reference example. The figure which shows the pointer signal which concerns on a reference example.

  Embodiments and reference examples will be specifically described below with reference to the drawings. In this description, a NAND flash memory is taken as an example of the semiconductor memory device, but the present invention is not limited to this. For example, the same applies to other semiconductor memory devices such as BiCS in which NAND flash memories are stacked in three dimensions, ReRAM (Resistance Random Access Memory), PRAM (Phase change Random Access Memory), and MRAM (Magnetic Random Access Memory). It is possible to apply to. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor memory device according to the first embodiment will be described.
<1. Configuration example>
1-1. Overall configuration example
First, an example of the overall configuration of the semiconductor memory device according to the first embodiment will be described with reference to FIG. As illustrated, the semiconductor memory device according to the first embodiment includes a memory cell array 11, a data latch region 12, a bus control circuit 15, and an interface 16.

  The memory cell array 11 is composed of a plurality of blocks (BLOCK0 to BLOCKn). Each of the blocks (BLOCK0 to BLOCKn) includes a plurality of memory cells arranged in a matrix at intersections between the bit lines and the word lines, as will be described in detail later.

  The data latch area 12 is divided into a plurality of address areas IO areas <0> to <0 provided in the column (Cullum) direction for each input or output (I / O) of data. 7> is arranged. In this example, eight IO areas <0>, ~, IO areas <n>, ~, IO areas <7> are arranged. Each of the IO regions <0> to <7> includes an internal I / O bus 20, a decoder 21, a shared bus 22, and a data latch circuit 23. For example, the IO area <0> includes an internal I / O bus (internal I / O bus <0>) 20, a decoder 21, a shared bus (Shared-1bit-bus) 22, and a data latch circuit <0>-<7>. 23.

  An internal I / O bus 20 is arranged for each of the IO regions <0> to <7>, and is electrically connected in series with the IO regions <0> to <7>. The IO regions <0> to <7> are driven according to control signals, addresses, etc. generated by the BUS control circuit 15.

  The decoder 21 is electrically connected to the internal I / O bus 20 and decodes addresses, control signals, and the like.

  A shared bus (Shared-1 bit-bus) 22 electrically connects a data latch 23 and a sense amplifier 25 in units of 8 bits. Details will be described later.

  The data latch circuit (data latch <0>-<7>) 23 is electrically connected to the shared bus 22 in parallel. In this example, eight data latch circuits 23 are arranged for each shared bus 22.

  The sense amplifier (Sense Amp * 8) 25 senses read data and write data from the memory cell array 11 via bit lines (BIT line <7: 0>). Here, the sense amplifier 25 and the bit lines are collectively displayed every 8 bits.

  The BUS control circuit 15 generates, for example, the control signal and controls data transfer to the internal bus wiring 20, and controls the overall operation of the semiconductor memory device.

  The interface 16 is connected to an external I / O bus (External I / O bus <n: 0>), and is electrically connected to a host device outside the semiconductor memory device. As a result, input / output data, an address, a command, and the like are given from the host device or the like.

1-2. Block (BLOCK) configuration example
Next, a configuration example of a block (BLOCK) according to the first embodiment will be described with reference to FIG. Here, one block (BLOCK 1) will be described as an example. Here, since the memory cells in the block BLOCK 1 are erased collectively, the block is a data erasing unit.

  As shown in the drawing, the block BLOCK1 is composed of a plurality of memory cell units MU arranged in the word line direction (WL direction). The memory cell unit MU is arranged in a bit line direction (BL direction) intersecting the WL direction, and a NAND string (memory cell string) including eight memory cells MC0 to MC7 whose current paths are connected in series, and a NAND string The source-side selection transistor S1 connected to one end of the current path of the current and the drain-side selection transistor S2 connected to the other end of the current path of the NAND string.

  In this example, the memory cell unit MU is composed of eight memory cells MC0 to MC7, but may be composed of two or more memory cells, for example, 56, 32, etc. It is not limited to individuals.

  The other end of the current path of the source side select transistor S1 is connected to the source line SL. The other end of the current path of the drain-side selection transistor S2 is provided above the memory cell unit MU corresponding to each memory cell unit MU, and is connected to the bit line BLm-1 extending in the BL direction.

  Word lines WL0 to WL7 extend in the WL direction and are commonly connected to control gate electrodes CG of a plurality of memory cells in the WL direction. The selection gate line SGS extends in the WL direction and is commonly connected to a plurality of selection transistors S1 in the WL direction. The selection gate line SGD also extends in the WL direction and is commonly connected to a plurality of selection transistors S2 in the WL direction. Each of the memory cells MC0 to MC7 has a stacked structure including a tunnel insulating film, a floating gate FG, an inter-gate insulating film (IPD), and a control gate CG which are sequentially provided on a semiconductor substrate (not shown).

  A page (PAGE) exists for each of the word lines WL0 to WL7. For example, as indicated by being surrounded by a broken line in the figure, the page 7 (PAGE 7) exists in the word line WL7. Since a data read operation and a data write operation which will be described later are performed for each page (PAGE), the page (PAGE) is a data read unit and a data write unit.

1-3. Data latch area address assignment example
Next, an example of address assignment of the Data latch area 12 according to the first embodiment will be described.

  First, it compares with the reference example mentioned later. In the reference example, for example, as shown in FIGS. 14 and 15, the areas A to H corresponding to the IO <0> area to IO <7> which are address areas are all internal I / O bus <0>. ~ Internal I / O bus <7> is connected in parallel, and 2048bit I0 <7: 0> column addresses (colum add) 0-255, 256-511, 512-767, ... are assigned respectively. This is different from the first embodiment. As described above, in the reference example, eight Internal I / O bus <7: 0> are wired in parallel to the Data latch are. The Internal I / O bus <7: 0> is connected to the Shared-1bit-bus in each area. For this reason, the internal I / O bus <7: 0> is wired in parallel, which increases the buffer area and the wiring area, which is disadvantageous in that the current consumption increases.

  On the other hand, in the first embodiment, as shown in FIGS. 3 and 4, the internal I / O bus <0> to Internal for each of the IO <0> area to IO <7> area which are address areas. The I / O bus <7> is connected in series, and the 2048-bit column address (colum add) 0-2047 of the data latch circuit 23 is assigned.

  For example, in the IO <0> area, Internal I / O bus <0> is connected in series, and a 2048-bit column address (colum add) 0-2047 is allocated. Similarly, in the IO <1> area, Internal I / O bus <1> is connected in series, and a 2048-bit column address (colum add) 0-2047 is allocated.

  As described above, in the first embodiment, the area of Internal I / O bus <0> to <7> can be reduced. Therefore, the wiring area can be reduced to about 1/16 in consideration of the shield wiring described later, and the buffer of Decorder 21 can be reduced. The area can be reduced to about 1/8. Furthermore, the power consumed by the wiring of the data latch area 12 can be reduced to about 1/8.

  Here, in the first embodiment, Internal I / O buses <0> to <7> are 8 bits common to input and output, and are wired to the data latch area 12 over the entire surface.

  On the other hand, in the reference example, it is necessary to wire all the internal I / O buses <0> to <7> in parallel from end to end of the data latch area, so that an unnecessary wiring area occurs.

  On the other hand, in the first embodiment, the internal I / O bus <0> to <7> may be wired only in a necessary area. Therefore, it is possible to further reduce the buffer area and current consumption by optimizing the buffer driving force according to the wiring length.

1-4. Address area for address assignment
Address area
Next, a configuration example of the address area in the above address allocation example will be described. Here, the address area IO <0> shown in FIGS. 3 and 4 will be described as an example.

  The address area IO <0> according to the first embodiment is shown as shown in FIG. Each unit of Add0-255 is 8 bits, and 256 are arranged per I / O area. The 8-bit Add0-255 corresponds to UNIT <0>-<255> in a third embodiment to be described later. Details will be described later.

  As shown in the figure, a 2048-bit column address (colum add) 0-2047 is allocated to the address area IO <0> area. In the address area I / O <0> area, sense amplifiers S / A0 to S / A255, data latches 0 to 255, and a decoder 21 are arranged, and these are serially connected to the Internal I / O bus <0>. Connected to. Although not shown here, a shared bus 22 that electrically connects the data latch 23 and the sense amplifier 25 is disposed.

  The sense amplifiers S / A0 to S / A255 sense read data, write data, and the like of the bit line BL (0-2047) to which the 2048-bit column address (colum add) 0-2047 is assigned. The sense amplifiers S / A0 to S / A255 are assigned 8-bit Add0-Add255, respectively, and sense the potential of the corresponding bit line. For example, 8-bit Add0 is assigned to the sense amplifier S / A0 and senses the potential of the corresponding bit line (0-7). Similarly, 8-bit Add1 is assigned to the sense amplifier S / A1, and the potential of the corresponding bit line (8-15) is sensed.

  Data latches 0 to 255 are arranged corresponding to the sense amplifiers S / A0 to S / A255, and latch read data, write data, and the like.

  The decoder 21 selects data latches 0-255 corresponding to 2048-bit column addresses (colum add) 0-2047 for input / output data from the Internal I / O bus <0>.

About address area IO <0>
Next, a configuration example of the address area IO <0> in FIG. 5 will be described in more detail with reference to FIG.

  As shown in the figure, an 8-bit column address 0-7 is assigned to the address Add 0, and a sense amplifier S / A0, a shared bus 22, a data latch 0, and a decoder 21 are arranged, and these are internal I / O bus < 0> in series.

  The sense amplifier S / A0 includes a plurality of sense amplifiers (SA * 8) 25 each including eight sense amplifier circuits SA. In this example, eight sense amplifiers (SA * 8) 25 are arranged to sense the potential of the bit line (0-7) corresponding to the 8-bit column address.

  A shared bus (Shared-1 bit-bus) 22 electrically connects the data latch 23 and the sense amplifier 25 in units of 8 bits. For example, a shared bus 22 that electrically connects eight sense amplifier circuits SA that sense the potential of the bit line (0-7) and data latch <0>-<7> in an 8-bit column address unit. Is done.

  The data latch 0 is composed of a plurality of data latches <0>-<7> corresponding to the sense amplifier S / A0. In this example, as with the sense amplifier 25, eight data latches 23 are arranged to correspond to an 8-bit column address.

  Similarly to the above, the decoder 21 selects the data latch 23 corresponding to the 8-bit column address (colum Add) 0-7 for the input / output data from the Internal I / O bus <0>.

  The same applies to the configuration example of the address area IO <0> in the other addresses Add 8-2047.

<2. Data flow>
Next, the data flow in the above configuration will be described.

Write data flow
First, the flow of write data input from the outside will be described as an example.

  In the above configuration, write data input from outside the chip of the semiconductor memory device passes through an interface 16 (not shown) and is buffered by the BUS control circuit 15.

  Subsequently, the BUS control circuit 15 transfers the write data bit by bit to each of the address areas I / O <0> to <7> of the Data latch area 12 according to the internal I / O addresses <0> to <7>. For example, in the case of the internal I / O address <0>, the BUS control circuit 15 transfers the write data to the address <0> in all the address areas of the Data latch area 12.

  Subsequently, in the address areas I / O <0> to <7>, first, write data is transferred to the internal I / O bus (internal I / O bus) <0> to <7>.

  Subsequently, for the write data of the internal I / O buses <0> to <7>, the decoder 21 selects one of the column address areas divided into 256, and the data is latched corresponding to the latch selection signal (FIG. 8). 23 is selected. For example, the decoder 21 electrically connects the Shared-1 bit-bus 22 and the Internal I / O bus <0> to the column address (see FIG. 4) 0, 256, 512, 768, 1024, 1280, 1536, 1792, and latch selection signal 0 selects data latch 0 in data latch 23 corresponding to column address 0.

  Subsequently, when a write execution command is input from the outside, the data latch circuit <0>-<7> is transferred bit by bit through the Shared-1bit-bus 22 to the Sense Amp 25 corresponding to the corresponding column address, Data is written to the memory cell MC.

Flow of read data In principle, the flow of read data is opposite to the flow of write data.

  First, when a read command is input from the outside of the chip of the semiconductor memory device, data read by the Sense Amp 25 is held in the Data latch 23 through the Shared-1 bit-bus 22.

  Subsequently, after the reading of all data is completed, when the clock for reading data is toggled from the outside of the chip, it is transferred from the selected data latch 23 to the Decorder 21 through the Shared-1bit-bus 22 each time.

  Subsequently, the transferred read data is buffered by the Decorder 21, transferred to the internal I / O bus <0> to <7>, collected into 8 bits by the BUS control circuit 15, and output outside the chip of the semiconductor memory device. Is done.

<3. Effect>
According to the semiconductor memory device of the first embodiment, at least the following effects (1) to (2) can be obtained.

(1) The wiring area and buffer area of the data bus wiring 20 can be reduced, which is advantageous for miniaturization.
As described above, in the semiconductor memory device according to the first embodiment, the address areas IO <0> to <7> of the data latch area 12 that latches the write data / read data of the memory cell array 11 are used as the data I / O. Divided into units. Further, the address areas IO <0> to <7> are connected in series to internal bus lines Internal I / O bus <0> to <7> that control data input / output inside the chip of the semiconductor memory device.

  Further, for example, in the address area IO <0> area, sense amplifiers S / A0 to S / A255, data latches 0 to 255, and a decoder 21 are arranged, and these are internal I / O bus <0. > In series. Also, a shared bus 22 that electrically connects the data latch 23 and the sense amplifier 25 is disposed.

  Therefore, the 2048-bit column address (colum add) 0-2047 of the data latch circuit 23 is assigned to each of the IO <0> area to IO <7> area as the address area. For example, in the IO <0> area, Internal I / O bus <0> is connected in series, and a 2048-bit column address (colum add) 0-2047 is allocated.

  On the other hand, in the reference example, as shown in FIG. 14, for example, the areas A to H corresponding to the IO <0> area to IO <7> which are address areas are all internal I / O bus < 0> ~ Internal I / O bus <7> are connected in parallel, and 2048-bit I0 <7: 0> column addresses (colum add) 0-255, 256-511, 512-767,. .

  Thus, in the first embodiment, Internal I / O bus <0> to <7> can be integrated into one. For example, in the reference example, eight Internal I / O buses <0> to <7> arranged in parallel are changed to one Internal I / O bus <0> to <7> according to the first embodiment. Can be integrated. Therefore, since the area of the internal I / O bus <0> to <7> can be reduced, the wiring area can be reduced to about 1/16 when the shield wiring as shown in FIG. It can be reduced to about 1/8.

  Furthermore, in the reference example, since it is necessary to wire all the internal I / O buses <0> to <7> in parallel from end to end of the data latch area, an unnecessary wiring area is generated.

  On the other hand, in the first embodiment, the internal I / O bus <0> to <7> may be divided corresponding to the address areas <0> to <7> and wired only to the necessary areas. In that respect, the area can be further reduced.

  Thus, according to the first embodiment, it is advantageous for miniaturization.

  (2) It is advantageous for reducing power consumption.

  As described above, in the semiconductor memory device according to the first embodiment, the area of Internal I / O bus <0> to <7> can be reduced, and the shield wiring as shown in FIG. The power consumed by the wiring of the latch area 12 can be reduced to about 1/8.

  Furthermore, in the first embodiment, the internal I / O bus <0> to <7> need only be wired in a necessary area, so that the power consumption is reduced by optimizing the buffer driving force according to the wiring length. It becomes possible to do.

  Thus, according to the first embodiment, it is advantageous for reducing power consumption.

[Second Embodiment (an example of defective column replacement system)]
Next, a semiconductor memory device according to the second embodiment will be described. This embodiment relates to an example of a defective column replacement system. A defective column replacement system refers to a system that relieves a column defect of about several bytes in a NAND flash memory. This example relates to a corresponding address area when this system is supported. In this description, a detailed description of the same parts as those in the first embodiment is omitted.

<About defective column replacement system>
As shown in FIG. 7, the second embodiment is different from the first embodiment in that the address area further includes a dedicated replacement area 12-2 different from the main data area 12-1.

<Configuration example>
The main data area 12-1 is composed of the address areas IO areas <0> to <7>. As described above, the address area IO areas <0> to <7> are main data latch areas that hold correct data that is not defective.

  The replacement area 12-2 includes a defective column replacement area 33. The defective column replacement area 33 is a dedicated data latch area for holding defective data. The defective column replacement area 33 is connected in series to the replacement area bus 35. The replacement area bus 35 is controlled by the BUS control circuit 15. The configuration of the replacement area 12-2 is the same as that of the address area IO areas <0> to <7>. The replacement area bus 35 is the same as the internal I / O bus <0> to <7>.

<Data transfer operation>
In the above configuration, the defective data input to the defective column replacement area 33 is transferred to the Data latch circuit in the replacement area 33 through the replacement area BUS35.

  In this example, since the configuration of the replacement area 12-2 is the same as that of the address areas IO <0> to <7>, defective data can be replaced with a minimum unit of 1-bit unit. Therefore, there is no extra data latch circuit 23 and the area of the replacement region 33 can be reduced.

  For example, in the reference example shown in FIG. 14, defective data can be replaced only in units of 8 bits. Therefore, the occupied area of the defective column replacement region 33 according to this example can be reduced to about 1/8 compared to the reference example.

  The data transfer operation includes a case where data is directly input to the replacement area 33 and a case where data is once stored in the data latch circuit 23 of the main data area 12-1 and then transferred to the replacement area 33. In this embodiment, either case may be used.

  Other configurations, operations, and the like are substantially the same as those in the first embodiment.

<Effect>
According to the semiconductor memory device of the second embodiment, at least the same effects as the above (1) and (2) can be obtained.

  Further, the second embodiment further includes a dedicated replacement area 12-2 different from the main data area 12-1 in the address area.

  Here, since the configuration of the replacement area 12-2 is the same as that of the address areas IO <0> to <7>, the defective data can be replaced with a minimum unit of 1-bit unit. This is advantageous in that there is no extra data latch circuit 23 and the area of the replacement region 33 can be reduced.

  For example, in the reference example shown in FIG. 14, defective data can be replaced only in units of 8 bits. Therefore, the occupied area of the defective column replacement region 33 according to this example can be reduced to about 1/8 compared to the reference example.

[Third embodiment (an example of a pointer system)]
Next, a semiconductor memory device according to the third embodiment will be described with reference to FIGS. This embodiment relates to an example of a pointer system. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example>
A configuration example of the pointer system according to this example is shown in FIG. Here, two pointer circuits (UNIT <0>, UNIT <1>) in the address area IO <0> will be described as an example. Here, as described above, a case where 1 page = 2048 columns is taken as an example. Further, in this example, since it is configured with 1 UNIT = 8 bits, it differs from the reference example described later in that 1pate = 256 UNIT × 8. In the reference example, 1page = 256UNIT is the same, but 1UNIT = 8 bytes.

  As shown in the figure, each of the two pointer circuits (UNIT <0>, <1>) includes an internal IO bus 20 <0>, a flip-flop FF, a decoder_0 <0> 21, an AND circuit AND <0> ˜ <7> and data latch_0 <0> to _0 <7> 23. The internal IO bus 20 <0>, decoder_0 <0> 21, and data latch_0 <0> to _0 <7> 23 are the same as described above.

  The flip-flop FF is connected to the clock signal input from the bus control circuit 15 and the output of the preceding flip-flop FF, and outputs a pointer signal (pointer 0, pointer 1). The pointer signal is connected to the input of the decoder 21 and the AND circuit ADD.

  Here, the pointer signal is a UNIT selection signal. Therefore, only one pointer signal is in a high state in the address area, and a total of eight pointer signals operate in parallel in units of address areas in one page.

  The AND circuits AND <0> to <7> output the input pointer signals and the AND signals of the latch decode signals <0> to <7> to the inputs of the data latch_0 <0> to _7 <0>, respectively. .

<Pointer signal>
Next, the pointer signal according to this example will be described more specifically with reference to FIG.

  As described above, the pointer signal is a UNIT selection signal. Therefore, only one pointer signal is in a high state in the address area, and a total of eight pointer signals operate in parallel in one address area in one page.

  Therefore, as shown in the figure, in this example, only one high state (“1” is selected in order to select any one of the UNITs <0> to <255> in the IO areas <0> to <7>. The pointer signal pointer in the “state” operates simultaneously in units of address areas IO <0> to <7>.

  For example, in order to select UNIT <0> in the IO areas <0> to <7>, the pointer signal (pointer 0) is in the high state, and the eight pointers in the IO areas <0> to <7> Each of the signals (pointer 0) operates simultaneously and in parallel. Subsequently, the pointer signal selects the next incremented UNIT <1> each time the clock signal toggles. Finally, the pointer signal pointer 3 selects the first UNIT <0> and repeats the same operation.

  On the other hand, when compared with the pointer signal according to the reference example shown in FIG. 17, only one pointer signal according to the reference example is in a high state in the address area IO <7: 0> in order to select UNIT. For example, only one pointer signal (pointer 0) according to the reference example is in a high state in the address area IO <7: 0> in order to select UNIT <0>.

<Operation waveform>
Next, operation waveforms of the pointer system according to this example will be described with reference to FIG. Here, two UNIT <0> and UNIT <1> described in FIG. 8 are taken as an example.

  First, at time t1, the bus control circuit 15 sets the latch decode signal <0> to the high state.

  Subsequently, at time t2, when the clock signal is in the high state, the latch decode signal <0> is also in the high state, and the pointer signal pointer 0 is in the high state. Therefore, UNIT <0> in address areas IO <0> to <7> is selected.

  Subsequently, at time t3, when the clock signal is in the high state, the pointer signal pointer 0 and the latch decode signal <0> are in the low state, and the next latch decode signal <8> and the pointer signal pointer 1 are in the high state. . Therefore, UNIT <1> in address areas IO <0> to <7> is selected.

  Thereafter, similarly, the pointer system is operated to select UNIT <0> to <255> in the address areas IO <0> to <7>.

<Effect>
According to the semiconductor memory device of the third embodiment, at least the same effects as the above (1) and (2) can be obtained.

  Furthermore, in this example, one address area IO <0> is constituted by UNIT <0> to <255> as a pointer system.

  For example, each of UNIT <0> and <1> includes an internal IO bus 20 <0>, a flip-flop FF, a decoder_0 <0> 21, an AND circuit AND <0> to <7>, and a data latch_0 < 0> to _0 <7> 23. The internal IO bus 20 <0>, decoder_0 <0> 21, and data latch_0 <0> to _0 <7> 23 are the same as described above.

  Therefore, for example, compared with the pointer system according to the reference example shown in FIG. 16, in the configuration of this example, the one page configuration can be divided into eight and each can be allocated to the IO area.

[Reference example]
Next, for comparison with the first to third embodiments, a semiconductor memory device according to a reference example will be described. In this description, detailed description of portions overlapping with the first to third embodiments is omitted.

<Example of overall configuration>
An example of the entire configuration of the semiconductor memory device according to the reference example is shown in FIG. Here, similarly to the above, the data flow will be described by taking the case where the BUS is 8 bits as an example.
As shown in the drawing, in the reference example, data input from the outside of the chip of the semiconductor memory device passes through the interface 160 in the External I / O BUS <7: 0>, and eight internal I / O bus <7: Latched to 0>.

  Thus, in the comparative example, eight Internal I / O bus <7: 0> are wired in parallel to the Data latch area 120. The internal I / O bus <7: 0> is wired from end to end of the chip. When the switch inside Decorder 210 is opened, it is input to the designated data latch through the Shared-1bit-bus bit by bit. Similarly, 8 Data latches are connected to the Shared-1bit-bus.

  When all data input is completed and an execution command is input, write data is transferred from the Data latch to the Sense Amp through the Shared-1bit-bus, and the write operation starts. When a read command is input, the data written in the Memory Cell Array 110 is read by the Sense Amp and once held in the Data latch through the Shared-1bit-bus.

  Each time the external clock toggles, the read data passes from the Data latch through the Shared-1bit-bus, and is buffered by the Decorder 210 to become the Internal I / O bus <7: 0>. Output to the outside of the chip as BUS.

<About Decoder 210>
A configuration example of a decoder 210 according to the reference example is shown in FIG.

  As shown in the figure, in the Decorder 210, the input switch SW10, the output buffer BF210, and the output switch SW20 are arranged by the number of internal I / O buses (eight in this example). Then, parallel-serial conversion is performed on the input / output data.

  At the time of data input, the input data is strongly driven by a large buffer in the BUS control circuit 150.

  On the other hand, at the time of data output, the output data must be driven by the eight transistors BF210 in the Decorder 210 since the Shared-1bit-bus must be driven by a small transistor in the Data latch, and then the Internal I / O bus <7 : 0> transfer data. This can cause the area of the Decorder 210 to increase. This is because the buffer size of the buffer BF210 in the decoder 210 is large. Furthermore, since the buffer size of the buffer BF210 is large, the current consumption also increases. In recent years, the internal I / O bus is often divided into an input and an output for speeding up, and each of them is operated in parallel. The number of Internal I / O buses increases by the amount of division, and the area of the BUS control circuit increases.

<Example of internal I / O bus <7: 0>layout>
Further, as shown in the layout example of the internal I / O bus <7: 0> shown in FIG. 13, in order to prevent the data from being affected by the adjacent internal I / O bus wiring, the adjacent internal I / O bus It is also necessary to arrange shield wiring such as power wiring between bus wiring. This is because the internal I / O bus is shielded by shield wiring.

  For this reason, a wiring area by the shield wiring is added, which may cause an increase in the area of the decoder 210.

  As described above, the semiconductor memory device according to the comparative example tends to be disadvantageous for miniaturization.

<Address area>
The address area according to the reference example is shown as shown in FIGS. 14 and 15, for example.
As shown in the figure, the areas A to H corresponding to the I / O <0> area to I / O <7>, which are the above address areas, are all internal I / O bus <0> to Internal I / O bus. 1st implementation in that the column addresses (colum add) 0-255, 256-511, 512-767, etc. of 2048bit I / 0 <7: 0> are assigned in parallel to <7>. It differs from the form.

  As described above, in the reference example, eight Internal I / O bus <7: 0> are wired in parallel to the Data latch are. The Internal I / O bus <7: 0> is connected to the Shared-1bit-bus in each area. For this reason, the internal I / O bus <7: 0> is wired in parallel, which increases the buffer area and the wiring area, which is disadvantageous in that the current consumption increases.

<Pointer system>
A pointer system according to the reference example is shown in FIG. The reference example is different from the third embodiment in that it is composed of 1UNIT = 8 bytes and 1page = 256UNIT.

  That is, in the configuration of one page in the illustrated reference example, one column address is configured by 8-byte data. One unit is constituted by an 8-byte address. One page is composed of 256 UNITs. Accordingly, similarly, one page is composed of 256 column addresses.

  Of the 256 pointer signals in the reference example, only one of the pointer signals is in the high state (“1” state) in one page, and the unit is selected.

  For example, as shown in FIG. 17, only one pointer signal (pointer 0 to pointer 255) according to the reference example is selected in the address area IO <7: 0> in order to select UNIT <0> to <255>. It becomes high state. For example, only one pointer signal (pointer 0) according to the reference example is in a high state in the address area IO <7: 0> in order to select UNIT <0>. The pointer signal pointer 255 moves to the right UNIT by the clock signal and returns to UNIT <0> after UNIT <255>.

  As for address selection, internal addresses 0 to 7 are assigned in the UNIT and are controlled by a latch decode signal. Only one column is selected by the latch decode signal and the pointer signal.

  As described above, when the pointer system is used, only one pointer circuit is arranged for each UNIT, so that the area can be reduced.

  The embodiments and reference examples of the present invention have been described above. However, these embodiments and reference examples are presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Data latch area | region, IO <0> area-IO <7> area | region ... Address area | region, 20 ... Internal bus wiring, 15 ... Bus control circuit, 16 ... Interface.

Claims (5)

A memory cell array in which a plurality of memory cells are arranged;
Latching data of the plurality of memory cells, and a plurality of address areas arranged separately for each data input or output (I / O) of the memory cell array;
An internal bus wiring arranged corresponding to the plurality of address areas, each electrically connected in series with the plurality of address areas;
A semiconductor memory device comprising: a control circuit that controls data transfer of the internal bus wiring. Latching defective column data of the plurality of memory cells, and a defective column replacement region having the same configuration as the address region;
A replacement region bus wiring disposed corresponding to the defective column replacement region and electrically connected in series with the defective column replacement region;
The semiconductor memory device according to claim 1, wherein data transfer between a data latch of defective column data of the plurality of memory cells and the defective column replacement region is performed in 1-bit units. Each of the plurality of address areas is
A decoder electrically connected to the internal bus wiring and decoding a column address;
A sense amplifier for sensing read data and write data from the memory cell array;
A shared bus wiring for electrically connecting the decoder and the sense amplifier;
The semiconductor memory device according to claim 1, further comprising a plurality of data latches electrically connected in parallel to the shared bus wiring. A plurality of pointer circuits provided corresponding to the address areas;
The semiconductor memory device according to claim 1, wherein the plurality of pointer circuits are selected in parallel by the plurality of pointer signals. Each of the plurality of pointer circuits is
A flip-flop circuit that outputs the pointer signal in response to a clock signal input from the control circuit;
The semiconductor memory device according to claim 4, further comprising: an AND circuit that outputs a logical product signal of the pointer signal and a latch decode signal input from the control circuit.

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