JP2013114712A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve throughput of the operation test of a semiconductor device.SOLUTION: A determination circuit 112 inspects 16-bit test data in total that are read from two memory banks, BANK(A) and BANK(E). In all 16-bit memory cells MC to be inspected, "H" has been written. If none of the memory cells MC are defective, "H" is read as is. The determination circuit 112 comprises: a first detection circuit 124 that compares test data of the memory bank BANK(A) with each other; a second detection circuit 126 that compares test data of the memory bank BANK(E) with each other; and in addition, a third detection circuit 128 that compares the test data of the memory bank BANK(A) with the test data of the memory bank BANK(E).

Description

  The present invention relates to a semiconductor device, and more particularly to an operation test of a semiconductor device.

  Many semiconductor devices such as a DRAM (Dynamic Random Access Memory) are manufactured simultaneously using a single silicon wafer. A test for confirming the operation (hereinafter referred to as “operation test”) is performed on the DRAM group on the wafer, and the product is sorted into a non-defective product and a defective product. In the operation test, usually, the same clock is supplied to a plurality of DRAMs formed on the same silicon wafer, the DRAMs are operated simultaneously, and the data transmitted from each DRAM is detected.

  As an example, a DRAM that inputs / outputs 8-bit data in parallel is assumed, and input / output terminals are DQ0 to DQ7. First, a tester probe (hereinafter simply referred to as a “test pin”) is connected to DQ0 to DQ7, a memory bank and a memory cell are designated, and 8-bit data is written. As an example, “H: high level” is written from all DQ0 to DQ7. Next, the data of the memory cell to be written is read, and it is confirmed whether or not “H” as written from DQ0 to DQ7 is output. Since “H” is not output from the defective memory cell, the presence or absence of the defective memory cell can be confirmed by confirming the output from DQ0 to DQ7.

  Since a general DRAM has a plurality of memory banks (see Patent Document 1), an operation test is executed for each bank.

JP 2006-253270 A

  In the future, since DRAM capacity will be further increased, it is desired to test a DRAM having a plurality of memory banks at high speed using a small number of test pins. Such a request applies not only to DRAMs but also to all semiconductor devices having a plurality of memory banks.

  The semiconductor device according to the present invention includes a plurality of data terminals, a first memory bank having a plurality of first memory cells corresponding to the plurality of data terminals, and a plurality of second terminals corresponding to the plurality of data terminals, respectively. When both the second memory bank having the memory cells and the first and second memory banks are selected, the plurality of first memory cells output from the plurality of first memory cells in the first memory bank are selected. It is determined whether the data and the plurality of second data output from the plurality of second memory cells of the second memory bank match each other, and the plurality of first data are determined according to the determination result And a determination circuit that controls whether or not to output from a plurality of corresponding data terminals.

  According to the present invention, the throughput in the operation test of the semiconductor device can be improved.

It is a functional block diagram of a semiconductor device. It is a peripheral circuit diagram of a memory bank and a switch circuit. It is a peripheral circuit diagram of a multiplexer and a determination circuit. It is a circuit diagram of a determination circuit. It is a circuit diagram of an input / output circuit. It is a table | surface which shows the relationship of the various signals in an input / output circuit. It is a time chart when the failure detection by a determination circuit is not made at the time of an operation test. It is a time chart when the defect detection by a determination circuit is made at the time of an operation test. It is a time chart at the time of normal operation. It is a circuit diagram for demonstrating the write-in process at the time of an operation test. It is a circuit diagram of the judgment circuit in a modification.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present embodiment, a DRAM is described as the semiconductor device, but the present invention is not limited to the DRAM.

  FIG. 1 is a functional block diagram of the semiconductor device 100. The semiconductor device 100 includes an address / command decoder 102. The address / command decoder 102 receives address information BA, ADD and a command CMD supplied from the outside, and outputs internal address information and an internal command ICMD. The internal address information includes an internal bank address IBA designating a memory bank and an internal memory address IADD designating a memory cell in the designated memory bank. These bank address IBA and internal memory address IADD are supplied to the storage area 106. The internal command ICMD is supplied to the storage area 106 and the test circuit 104. The internal command ICMD includes a test command in addition to a read command and a write command.

  The test circuit 104 activates the operation test signal TEST when a test command is input. The operation test signal TEST is high active. The operation test signal TEST is supplied to the storage area 106, the multiplexer 110, the determination circuit 112, and the input / output circuit 114.

  The storage area 106 in this embodiment includes eight memory banks BANK (A) to BANK (H). The memory bank is a command execution unit, and these memory banks BANK (A) to BANK (H) operate non-exclusively. Since each of the memory banks BANK (A) to BANK (H) operates at different timings, there is no data collision between the memory banks. However, in the operation test, reading from two memory banks is executed simultaneously. This will be described later. These memory banks are divided into two groups, BANK (A) to BANK (D) and BANK (E) to BANK (H). A switch circuit 108a is connected to the memory banks BANK (A) to BANK (D), and a switch circuit 108b is connected to the memory banks BANK (E) to BANK (H).

  Each of the memory banks BANK (A) to (H) inputs / outputs 64-bit data in parallel. Although details will be described later, since the memory banks BANK (A) to (H) have 8 sets of MIO lines, and each set includes 8 MIO lines, a total of 64 bits of data are input / output in parallel. . The memory banks BANK (A) to BANK (D) and the switch circuit 108 are connected by the first bus 116a. As will be described later, the first bus 116a is connected to the MIO line via a read / write amplifier. The switch circuit 108a connects one of the first buses 116a corresponding to each of the four memory banks BANK (A) to BANK (D) to the second bus 118a based on the internal bank address IBA. Similarly, the switch circuit 108b connects either the first bus 116b or the second bus 118b corresponding to each of the four memory banks BANK (E) to BANK (H) based on the internal bank address IBA. The second buses 118a and 118b are buses that transfer 64-bit data in parallel. Data transferred through the second buses 118 a and 118 b is supplied to the multiplexer 110 and the determination circuit 112.

  The multiplexer 110 connects one of the second buses 118 a and 118 b to the third bus 120. The third bus 120 is a bus that transfers 64 bits in parallel. That is, the multiplexer 110 outputs 64-bit data in parallel to the input / output circuit 114 via the third bus 120 among the maximum 128-bit data output in parallel from the switch circuits 108 a and 108 b.

  Input / output circuit 114 is connected to eight input / output terminals DQ0 to DQ7. The input / output circuit 114 serializes the 64-bit data supplied from the multiplexer 110, thereby outputting 8-bit data in parallel eight times. Thus, the 64-bit data read in parallel from any of the memory banks is serially output from the input / output terminals DQ0 to DQ7 in units of 8 bits.

  When a write command is input, 8-bit data input in parallel from the input / output terminals DQ0 to DQ7 is written to the specified address of the memory bank specified by the address information.

  The read signal RD is activated when a read command is input, and the write signal WR is activated when a write command is input. The read signal RD and the write signal WR are supplied to the multiplexer 110 and the input / output circuit 114. The multiplexer 110 and the input / output circuit 114 execute a read operation or a write operation based on the read signal RD and the write signal WR.

  The determination circuit 112 operates when the operation test is executed, that is, when the operation test signal TEST is activated to a high level. The determination circuit 112 compares the data transferred through the second buses 118a and 118b in bit units to check whether there is a defective memory cell. Details of the determination circuit 112 will be described in detail with reference to FIGS.

  FIG. 2 is a peripheral circuit diagram of the memory bank BANK (A) and the switch circuit 108a. A set of MIO lines (MIO0 to MIO7) is associated with each of the eight input / output terminals DQ0 to DQ7. One set of MIO lines consists of eight MIO lines. Corresponding to the eight input / output terminals DQ0 to DQ7, the plurality of memory cell arrays 122 included in the memory bank BANK (A) are also classified into eight groups.

  In the memory bank BANK (A), an X decoder XDEC and Y decoders YDEC0 to YDEC7 are arranged. The X decoder XDEC controls the main word driver MWD and the sub word driver SWD according to the internal memory address IADD inputted in synchronization with the active command. The Y decoder YDEC selects the sense amplifier circuit SA according to the internal memory address IADD input in synchronization with the read command or the write command. Thereby, the memory cell MC to be accessed is specified.

  Memory cell arrays 122 included in memory bank BANK (A) are arranged in a matrix. The main word driver MWD controls the sub word driver SWD arranged in each memory cell array 122 through the main word line MWL.

  In the memory cell array 122, a plurality of word lines WL and bit lines BL intersect, and memory cells MC are arranged at the intersections. Around the memory cell array 122, a sense amplifier circuit SA and a sub word driver SWD are arranged. When any one of the word lines WL is activated, the corresponding memory cell MC is connected to the bit line BL, and the potential of the bit line BL changes according to the charge held in the memory cell MC. The potential change of the bit line BL is amplified by the sense amplifier circuit SA and output as read data. The read data is transmitted via the LIO line and the MIO line, further amplified by the read / write amplifier RWA, and then supplied to the switch circuit 108a. The semiconductor device 100 according to the present embodiment is a DRAM that performs 8-bit prefetching, and therefore, the data of the memory cells MC for 8 bits per one input / output terminal DQ are collectively read. Since the semiconductor device 100 according to the present embodiment has eight input / output terminals DQ0 to DQ7, a total of 64 bits of data are transmitted in parallel via the first bus 116a.

  FIG. 3 is a peripheral circuit diagram of the multiplexer 110 and the determination circuit 112. In the semiconductor device 100 according to the present embodiment, at the time of an operation test, reading is simultaneously performed from two memory banks. One memory bank to be accessed is selected from each of the memory banks BANK (A) to BANK (D) and BANK (E) to BANK (H). In the following description, it is assumed that reading is performed from the memory bank BANK (A) and the memory bank BANK (E). In addition, bit data to be subjected to an operation test in each of the memory banks BANK (A) and BANK (E) are A0 to A7 and E0 to E7. These 16-bit data are input to the multiplexer 110 and the determination circuit 112 via the switch circuits 108a and 108b.

  First, “H (high level bit data)” is written as test data to A0 to A7 and E0 to E7. Test data is input via the input / output terminals DQ0 to DQ3. Nothing is input to the input / output terminals DQ4 to DQ7. Therefore, in the operation test, the test pins are connected only to the input / output terminals DQ0 to DQ3. In the operation test, the input / output circuit 114 and the multiplexer 110 share the 4-bit test data input via the input / output terminals DQ0 to DQ3 as A0 to A3, A4 to A7, E0 to E3, and E4 to E7. Used for. Accordingly, if “H” test data is input to the input / output terminals DQ0 to DQ3, A0 to A7 and E0 to E7 are all “H”.

  At the time of reading, the read signal RD is activated, and the multiplexer 110 outputs 8 bits A0 to A7 of 16 bits A0 to A7 and E0 to E7 to the input / output circuit 114 via the third bus 120. .

  The input / output circuit 114 outputs A0 to A3 of A0 to A7 from the input / output terminals DQ0 to DQ3. Nothing is output from the input / output terminals DQ4 to DQ7. As described above, during the operation test, the test pins are connected only to the input / output terminals DQ0 to DQ3. Although details will be described later, in the semiconductor device 100 according to the present embodiment, two memory banks can be inspected with four test pins. In other words, the quality of the 16-bit memory cell MC can be inspected with four test pins. However, only 4 bits A0 to A3 are to be output.

  The determination circuit 112 determines whether or not the test data “H” is normally written in A0 to A7 and E0 to E7. When a defect is detected, the determination signal NG is activated to a high level. That is, the signal is at a high level when a defect is detected and at a low level when it is not detected. When the determination signal NG is activated, the input / output circuit 114 suppresses output of A0 to A3. A0 to A3 correspond to “first bit group”, A4 to A7 correspond to “second bit group”, B0 to B3 correspond to “third bit group”, and B4 to B7 correspond to “fourth bit group”. .

  FIG. 4 is a circuit diagram of the determination circuit 112. The determination circuit 112 includes a first detection circuit 124, a second detection circuit 126, and a third detection circuit 128. The first detection circuit 124 compares the 8-bit data A0 to A7 of the memory bank BANK (A) with each other. Specifically, A0 and A4, A1 and A5... Are compared by an EOR circuit (exclusive OR circuit). The output of the EOR circuit is aggregated by the OR circuit and becomes the inspection signal NG1. If there is no defect in the memory cell, the logic levels of A0 to A7 should all be “H”. Therefore, if there is no abnormality in the memory cells MC into which A0 to A7 are written, the inspection signal NG1 becomes low level (inactive). The second detection circuit 126 compares the 8-bit data E0 to E7 of the memory bank BANK (E) with each other. The configuration of the second detection circuit 126 is the same as that of the first detection circuit 124. The inspection signal NG2, which is the output of the second detection circuit 126, is at a low level (inactive) if there is no abnormality in the memory cells MC into which E0 to E7 are written.

  The third detection circuit 128 compares A0 and E0, A1 and E1,. The outputs of the EOR circuit are aggregated by the OR circuit and become the inspection signal NG3. If there is no abnormality in the memory cells MC written with A0, E0, A1,... To be compared, the inspection signal NG3 becomes low level (inactive).

  The inspection signals NG1 to NG3 are collected by the OR circuit and become the determination signal NG. When the determination signal NG is at a high level (active level), the input / output circuit 114 suppresses output of A0 to A3 from the input / output terminals DQ0 to DQ4.

  As an example, when there is an abnormality only in the memory cell MC corresponding to A0 (hereinafter referred to as “memory cell MC (A0)”) among the 16 memory cells MC corresponding to A0 to A7 and E0 to E7, Since the first detection circuit 124 activates the inspection signal NG1, the determination signal NG is also activated. As another example, when the memory cell MC (E0) is abnormal, the second detection circuit 126 activates the inspection signal NG2. When the memory cell MC (A0) and the memory cell MC (A4) are abnormal, the first detection circuit 124 cannot detect a defect, but the third detection circuit 128 activates the inspection signal NG1, so that the determination signal NG is activated. It becomes.

  When the memory cells MC (A0), MC (A4), and MC (E0) are abnormal, the second detection circuit 126 detects the abnormality. When the memory cells MC (A0), MC (A4), MC (E0), and MC (E4) are abnormal, the determination signal NG is not activated. At this time, A0 to A3 are output from the input / output terminals DQ0 to DQ4. Since A0 is not H, this allows the tester to detect the occurrence of a failure. That is, one or more defects in 16 memory cells MC (A0 to A7, E0 to E7) in two memory banks can be inspected with four test pins.

  FIG. 5 is a circuit diagram of the input / output circuit 114. The input / output circuit 114 includes an input control circuit 130 and an output control circuit 132. The input / output terminals DQ0 to DQ3 are connected to the third bus 120 via the input buffer 134a and the output buffer 136a, and the input terminals DQ4 to DQ7 are connected to the third bus 120 via the input buffer 134b and the output buffer 136b. .

  When the write signal WR is activated, the input control circuit 130 takes the data of DQ0 to DQ3 into the input buffer 134b and the data of DQ4 to DQ7 into the input buffer 134a and inputs the input data to the memory cell array 122 via the third bus 120. Send. Even when the operation test signal TEST is activated during the operation test, the test data is written before the reading. The writing of test data will be described later with reference to FIG.

  When the read signal RD is activated, the output control circuit 132 controls the output of data flowing through the third bus 120 to the output buffers 136a and 136b. The data written in the output buffers 136a and 136b is externally output from DQ0 to DQ7.

  When the operation test is executed, the operation test signal TEST becomes high active. Here, if the determination circuit 112 detects a defective memory cell MC, the determination signal NG is activated to a high level. At this time, the control signals CTRL [3: 0] for controlling the output buffer 136b are inactivated to a low level, and no data is output from the output buffer 136b. On the other hand, when the operation test signal TEST is at a high level, the control signal CTRL [7: 4] is also inactivated, and outputs from the input / output terminals DQ4 to DQ7 are also suppressed. That is, when the failure signal NG is activated, data is not output to any of the input / output terminals DQ0 to DQ7.

  When the determination circuit 112 does not detect a defective memory cell MC during execution of the operation test, the determination signal NG becomes inactive (low level). The control signal CTRL [3: 0] is activated to a high level, and the output buffer 136b outputs A0 to A3 from DQ0 to DQ3. On the other hand, the control signal CTRL [7: 4] becomes inactive. That is, when the failure signal NG is inactive, A0 to A3 are output only from the input / output terminals DQ0 to DQ3. In this case, the presence or absence of a defect is confirmed by inspecting A0 to A3 with an external tester.

  During normal operation, the operation test signal TEST is inactivated to a low level. The determination signal NG is also deactivated to a low level. As a result, the control signal CTRL [7: 0] is activated to a high level, and 8-bit data A0 to A7 are output in parallel from DQ0 to DQ7. FIG. 6 shows the above relationship.

  FIG. 7 is a time chart when a failure is not detected by the determination circuit 112 during the operation test. A test command, an ACT command, and a read command are sequentially input to the address / command decoder 102. Also, both the memory banks BANK (A) and BANK (E) and their respective memory addresses (16 bits) are designated. The operation test signal TEST is activated to a high level, and the main word line MWL in the memory banks BANK (A) and BANK (E) is also activated. When the determination signal NG is inactive, A0 to A3 are output from DQ0 to DQ3. Even if the determination circuit 112 misses the defect of the memory cell MC, the presence / absence of the defective memory cell MC can be finally confirmed from the output A0 to A3. For example, even when the determination signal NG is inactive and A0 to A3 are output from DQ0 to DQ3, the output test data of A0 is not “H (high level)” but “L (low level)”. , The test data of A4, E0, and E4 compared with A0 in the determination circuit 112 coincided with “L (low level)”, so that the memory cells A0, A4, E0 And E4 can be confirmed to be defective.

  FIG. 8 is a time chart when a failure is detected by the determination circuit 112 during the operation test. In FIG. 8, the determination circuit 112 detects a defect in the memory cell MC, and the determination signal NG is activated to a high level. As a result, data output by the input / output circuit 114 is suppressed. More specifically, since DQ0 to DQ3 are in a high impedance state, the presence of the defective memory cell MC can be confirmed by an external tester.

  FIG. 9 is a time chart during normal operation. During normal operation, no test command is input and the operation test signal TEST is not activated. One memory bank is selected as an access target. From DQ0 to DQ7, 8-bit A0 to A7 are output in parallel.

  FIG. 10 is a circuit diagram for explaining a writing process during an operation test. In the operation test, first, 16-bit test data “H” is written as memory cells MC (A0) to MC (A7) and MC (E0) to MC (E7). The four test pins of the tester are connected to DQ0 to DQ3. The multiplexer 110 writes the test data input from DQ0 into the memory cells MC (A0), MC (A4), MC (E0), and MC (E4). The same applies to DQ1 and later. In this way, 16-bit test data is written via the four test pins. After this writing, the above-described reading operation is executed.

  FIG. 11 is a circuit diagram of the determination circuit 112 in the modification. A feature of this modification is that only two test pins are required for testing 16-bit memory cells MC in two memory banks. The input / output terminals for outputting data during the operation test are DQ0 and DQ2. The determination circuit 112 in the modification also includes a first detection circuit 124, a second detection circuit 126, and a third detection circuit 128. The first detection circuit 124 compares A0, A1, A4, and A5 of the memory bank BANK (A) with one EOR circuit (four inputs). A2, A3, A6, and A7 are also compared by a 4-input EOR circuit. The output of the EOR circuit is aggregated by the OR circuit and becomes the inspection signal NG1. The second detection circuit 126 compares the 8-bit data E0 to E7 of the memory bank BANK (E) with each other. The configuration of the second detection circuit 126 is the same as that of the first detection circuit 124. The inspection signal NG2, which is the output of the second detection circuit 126, is at a low level (inactive) if there is no abnormality in the memory cells MC into which E0 to E7 are written.

  The third detection circuit 128 compares A1 and E1, A2 and E2,. The outputs of the EOR circuit are aggregated by the OR circuit and become the inspection signal NG3. In the modification, A0, A4, A1, and A5 are “first bit group”, A2, A3, A6, and A7 are “second bit group”, and E0, E4, E1, and E5 are “third bit group”. “Group”, E2, E3, E6, and E7 correspond to “fourth bit group”.

  The inspection signals NG1 to NG3 are collected by the OR circuit and become the determination signal NG. When the determination signal NG becomes high level (active level), the input / output circuit 114 suppresses the output of A0 to A3 from the input / output terminals DQ0 to DQ3.

  Of the 16 memory cells MC corresponding to A0 to A7 and E0 to E7, when only the memory cell MC (A0) is abnormal, the first detection circuit 124 activates the inspection signal NG1, and therefore the determination signal NG Is activated. When the memory cell MC (E0) is abnormal, the second detection circuit 126 activates the inspection signal NG2. When the memory cell MC (A0) and the memory cell MC (A4) are abnormal, the first detection circuit 124 activates the inspection signal NG1. When the memory cells MC (A0), MC (A4), MC (A1), and MC (A5) are abnormal, the third detection circuit 128 activates the inspection signal NG3.

  When the memory cells MC (A0), MC (A4), MC (A1), MC (A5), and MC (E1) are abnormal, the second detection circuit 126 activates the inspection signal NG2. When the memory cells MC (A0), MC (A4), MC (A1), MC (A5), MC (E0), MC (E4), MC (E1), MC (E5) are abnormal, the determination signal NG Is not activated. At this time, A0 and A2 are output from the input / output terminals DQ0 and DQ2. Since A0 does not become H, an abnormality can be detected by a tester. That is, one or more defects in 16 memory cells MC (A0 to A7, E0 to E7) in two memory banks can be inspected with two test pins.

  The semiconductor device 100 has been described based on the embodiments. According to the semiconductor device 100 in the present embodiment, it is possible to simultaneously test the operation of memory cells included in a plurality of memory banks. Further, since a total of 16-bit test data output in parallel can be inspected at a time with the number of test pins equal to or less than a quarter of the test data, the throughput of the operation test can be improved.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  100 semiconductor device, 102 address / command decoder, 104 test circuit, 106 storage area, 108 switch circuit, 110 multiplexer, 112 determination circuit, 114 input / output circuit, 116 first bus, 118 second bus, 120 third bus, 122 Memory cell array, 124 first detection circuit, 126 second detection circuit, 128 third detection circuit, 130 input control circuit, 132 output control circuit, 134 input buffer, 136 output buffer, IBA internal bank address, IADD internal memory address, ICMD Internal command, TEST operation test signal, RD read signal, WR write signal, XDEC X decoder, YDEC Y decoder, MWD main word driver, SWD sub word driver, WL word line, BL bit Trine, MC memory cell, SA a sense amplifier circuit, RWA read-write amplifier, NG determination signal.

Claims (5)

Multiple data terminals,
A first memory bank having a plurality of first memory cells corresponding to each of the plurality of data terminals;
A second memory bank having a plurality of second memory cells corresponding to each of the plurality of data terminals;
When both the first and second memory banks are selected, the plurality of first data output from the plurality of first memory cells of the first memory bank and the second memory bank It is determined whether or not the plurality of second data output from the plurality of second memory cells match each other, and the plurality of first data corresponding to the plurality of first data is determined according to the determination result And a determination circuit that controls whether to output from the data terminal.   The plurality of second data is not output from the plurality of data terminals regardless of whether or not the plurality of first data and the plurality of second data match each other. The semiconductor device according to claim 1.   The first and second memory banks are selected based on a bank address signal, and the plurality of first memory cells and the plurality of second memory cells are selected based on a memory address signal. The semiconductor device according to claim 1. A plurality of first data terminals and a plurality of second data terminals;
A plurality of first memory cells for outputting a plurality of first data to be supplied to each of the plurality of first data terminals; and a plurality of first memory cells to be supplied to each of the plurality of second data terminals. A first memory bank having a second memory cell that outputs two data;
A plurality of third memory cells for outputting a plurality of third data to be supplied to each of the plurality of first data terminals; and a plurality of second memory terminals to be supplied to each of the plurality of second data terminals. A second memory bank having a fourth memory cell that outputs four data;
The plurality of first data and the plurality of second data are the same, the plurality of third data and the plurality of fourth data are the same, and the plurality of first data And when the plurality of third data are the same as each other, the plurality of first data are output from the plurality of first data terminals, and the plurality of second, third, and fourth data are output. And a determination circuit that controls so as not to output.   The determination circuit compares the plurality of first data and the plurality of second data with each other and outputs the first inspection signal as a first inspection signal, and the plurality of third data and the plurality of data A second inspection circuit that compares the fourth data with each other and outputs the second inspection signal as a second inspection signal; and a third inspection signal that compares the plurality of first data and the plurality of third data with each other. And when the data mismatch is indicated by any one of the first, second and third detection signals, the plurality of first, second, third and second 5. The semiconductor device according to claim 4, wherein none of the four data is output from the plurality of first data terminals and the plurality of second data terminals.

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