JP2013110678A - Interleaving device, address translation method and address translation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interleaving device that supports a plurality of interleaving schemes and implements a high speed interleaving process in a small circuit scale.SOLUTION: An address translation circuit 11 of an interleaving device 10 includes: a first address translation section 100 for processing an input initial address on the basis of a first setting fed from a setting controller to output a resultant intermediate address; and a second address translation section 200 for processing the intermediate address on the basis of a second setting fed from the setting controller to output a resultant output address to a memory controller. The configuration executes a single continuous interleaving process.

Description

  The present invention relates to an interleaving device, an address translation method, and an address translation program, and more particularly to an interleaving device capable of performing a plurality of types of interleaving processing while suppressing a circuit scale.

  In storage devices and digital communication / signal processing, error correction of transmitted data is necessary in order to ensure their reliability. In particular, recently, high-speed data transmission is frequently performed in wireless communication, so that techniques for error correction processing are also required to be advanced.

  Currently used error detection and correction coding schemes have a relatively high correction capability for random errors that occur sporadically with respect to a single bit. However, it is often difficult to detect and correct a burst error in which a large number of errors occur continuously and intensively in a short interval even if the overall error rate is within an allowable range. Specifically, for example, impulse noise generated from automobile engines and specific electrical appliances (microwave ovens, cathode ray tubes, etc.), signal strength fluctuations (especially unavoidable in wireless communications), and multipath are burst errors. It is easy to cause.

  In order to cope with such burst errors, it is often performed to arrange a plurality of code words and rearrange their symbols. Such processing is called interleaving. By this interleaving, continuous data can be dispersed and burst errors can be converted into random errors, and as a result, the ability to correct burst errors can be enhanced.

  When performing interleaving, data rearrangement is generally realized by writing or reading target data using a specific address string in a memory having the same scale as the data to be interleaved. Depending on the rearrangement method, it can be classified into several methods such as block interleaving and convolutional interleaving. Here we focus on block interleaving.

  Block interleaving can be classified mainly into normal interleaving and random interleaving. Normal interleaving refers to a memory area used for interleaving as a two-dimensional array, in which data is written sequentially in the vertical direction and read sequentially in the horizontal direction to perform vertical insertion and horizontal extraction processing. Further, in addition to vertical insertion and horizontal extraction processing, there is a type in which processing such as column / row replacement or column twist is added.

  Random interleaving is a random rearrangement of symbols within a block. The random rearrangement can be performed by using a random value stored in a look-up table, or by using an M-sequence pseudo-sequence. There are methods using random values. These block interleaves are used for wireless data communication such as terrestrial digital television broadcasting and wireless LAN in Japan and overseas.

  Interleaving uses different types of interleaving methods for each wireless communication standard because the channel characteristics differ depending on the use environment. There may be a case where a plurality of interleaves are included in one wireless communication standard. In some interleaving schemes, it may be defined that a plurality of types of interleaving are continuously performed.

  For example, the frequency interleaving of ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), which is the standard of terrestrial digital television broadcasting described in Non-Patent Document 1, includes inter-segment interleaving, intra-segment carrier rotation, intra-segment carrier randomization. Three different processes are combined to form one continuous interleave.

  In addition, the symbol interleaving of IEEE (The Institute of Electrical and Electronics Engineers) 802.11a, which is a wireless LAN standard described in Non-Patent Document 2, is the first permutation and Two different processes called second permutation are combined into one continuous interleave.

  Even when a plurality of types of interleaving are continuously performed as described above, it is naturally necessary not to impair the real-time property of communication. Furthermore, in recent years, there has been a demand for improvement in data transmission speed. For this reason, it is increasingly necessary to increase the speed of interleave processing.

  As a technique for this, in the technique described in Patent Document 3, for example, data is read out from a memory in which data before interleaving is stored in a state where all of a plurality of types of continuous interleaving are performed. Create a table that stores the read address, and read from the address specified by the created table to generate an interleave address in one behavior, reducing the number of memory accesses and the interleave processing time. ing.

  Further, in recent wireless communication systems, a multi-mode is required to support a plurality of communication standards in one device, and interleaving is also required to support a plurality of interleaving methods with a single interleave device. ing. On the other hand, in the technique described in Non-Patent Document 3, the interleave address generation equation is transformed into a difference equation, and the resulting operation is realized by a combination of a plurality of adders / accumulators and accumulators. By using this method, the circuit scale is reduced while supporting a plurality of interleaving methods.

  In addition, there are the following as technical documents related to this. Among them, Patent Document 1 describes a receiving apparatus that uses a replica signal generated by remodulating a data sequence to reduce the processing delay of a parallel interference canceller. In Patent Document 2, OFDM (Orthogonal Wave Frequency Division Multiplexing) symbols, which are LDPC (Low Density Parity Check) -encoded standards, are used as subcarrier signals in accordance with digital television broadcasting standards such as DVB-T (Digital Video Broadcasting-Terrestrial). An example of a mapping technique is described.

  Patent Document 4 describes an example of deinterleaving (reversal processing of interleaving) used when receiving and demodulating a signal modulated by OFDM in digital television broadcasting or the like. Non-Patent Document 3 describes a technique for realizing an operation required for generating an interleave address mainly by an adder / subtractor and an adder, as will be described later.

JP 2008-205801 A JP 2009-153109 A Japanese Patent No. 3911401 Japanese Patent No. 4152854

Standard number “ARIB-STD-B31”, Standard name “Transmission method of digital terrestrial television broadcasting” version 1.9, Radio Industry Association (ARIB), July 15, 2010 Standard number `` IEEE Std 802.11a-1999 (R2003) '', Standard name `` Supplement to IEEE Standard for Information Technology Telecommunications and information exchange between systems Local and metropolitan area networks Specific requirements, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications High-speed Physical Layer in the 5 GHz Band '' Rizwan Asghar and Dake Liu, “Multimode Flex-Interleaver Core for Baseband Processor Platform”, Hindawi Publishing Corporation, Journal of Computer Systems, Networks, and Communications, 2010

  As described above, in data communication, it is naturally necessary not to impair the real-time property. In recent years, in particular, there has been a strong demand for improvement in data transmission speed and support for a plurality of communication methods. In addition, since downsizing, low cost, and low power consumption of the device are always required, the interleaving device also supports multiple interleaving methods while keeping the circuit scale small, and further speeds up interleaving. Of course it is necessary to do.

  However, as in the above-mentioned Patent Document 3, in the case of creating a table for storing read addresses in advance in order to reduce the number of accesses to the memory, when the interleave processing size increases, The problem is that the data size is increased, the circuit scale is increased, and it is difficult to increase the speed.

  In addition, as in Non-Patent Document 3, when a calculation required for generating an interleave address is realized by hardware using an adder / subtractor and an adder, a plurality of different interleaves are combined to generate one interleave. In this case, since the address generation formula cannot be expressed by a difference equation, each combined interleaving needs to be performed individually.

  Accordingly, it is necessary to write the data after each processing once in the memory a plurality of times, which increases the number of accesses to the memory and increases the processing time. Furthermore, with this method, separate hardware is required for each method in order to support a plurality of interleaving methods, and it is difficult to suppress the circuit scale.

  The technology that can solve the above problems is not described in the remaining Non-Patent Documents 1 and 2 and Patent Documents 1, 2, and 4. Non-Patent Documents 1 and 2 only describe the standard regarding interleaving as described above. In addition, the techniques described in Patent Documents 1, 2, and 4 are not intended to suppress the circuit scale in interleaving and to cope with a plurality of interleaving methods.

  An object of the present invention is to provide an interleaving device, an address translation method, and an address translation program that can cope with a plurality of interleaving methods and can perform interleaving processing at high speed while suppressing the circuit scale to be small. is there.

  To achieve the above object, an interleaving device according to the present invention includes a memory that temporarily stores input data, an address conversion circuit that performs an interleaving process on an address at which the data is stored on the memory, and An interleaving device comprising: a setting controller that gives a setting given from a host device to an address conversion circuit; and a memory controller that outputs data stored in an address subjected to interleaving processing on a memory. A first address conversion unit that outputs an intermediate address obtained by performing a process according to a first setting given by the setting controller on the input initial address; The output address obtained by performing processing according to the second setting given by the setting controller And a second address translation unit to be output to the memory controller, thereby characterized by being configured to execute one continuous interleaved.

  In order to achieve the above object, an address conversion method according to the present invention includes a memory that temporarily stores input data, an address conversion circuit that performs an interleaving process on an address at which the data is stored on the memory, and An interleaving device comprising a setting controller for giving a setting given from a host device to an address conversion circuit and a memory controller for inputting / outputting data to / from the memory, wherein the setting controller is the first of the address conversion circuit. The first and second settings are given to the second and second address conversion units, respectively, and the memory controller stores the input data in the memory, and uses the address on the memory where the data is stored as an initial address to the address conversion circuit. The first address conversion unit performs processing according to the first setting for the initial address. The obtained intermediate address is output, and the second address conversion unit outputs the output address obtained by performing processing corresponding to the second setting on the intermediate address to the memory controller, and the memory controller The data stored in the output address is output.

  In order to achieve the above object, an address conversion program according to the present invention includes a memory that temporarily stores input data, an address conversion circuit that performs interleaving processing on the address at which the data is stored on the memory, and An interleaving device comprising a setting controller for giving a setting given from a host device to an address conversion circuit, and a memory controller for inputting / outputting data to / from the memory, wherein the address conversion circuit is connected to a computer provided in the interleaving device. The procedure for giving the first and second settings to the first and second address conversion units, respectively, storing the input data in the memory and using the address on the memory where the data is stored as the initial address in the address conversion circuit Obtained by performing processing according to the first setting for the input procedure and initial address It characterized the steps of outputting an intermediate address, and a second output address obtained by performing a process according to the setting for the intermediate address to be executed the steps of outputting to the memory controller.

  In the present invention, as described above, the first address and the second address conversion unit operating according to the first and second settings respectively convert the initial address to the output address via the intermediate address. It is possible to perform processing continuously in a line, and it is possible to support multiple types of interleaving methods according to the initial setting value, and it is necessary to prepare hardware and lookup table etc. corresponding to each method separately There is no.

  As a result, an interleaving device, an address conversion method, and an address conversion program having excellent characteristics that it is possible to perform a plurality of interleaving methods and perform interleaving processing at high speed while suppressing the circuit scale to be small. Can be provided.

FIG. 3 is an explanatory diagram showing a more detailed configuration of the address conversion circuit shown in FIG. 2. It is explanatory drawing shown about the structure of the interleaving apparatus which concerns on the 1st Embodiment of this invention. It is explanatory drawing shown about the more detailed structure of the 1st calculating means shown in FIG. 1, and a 3rd calculating means. It is explanatory drawing shown about the more detailed structure of the 2nd calculating means shown in FIG. 1, and a 4th calculating means. It is a flowchart shown about the operation | movement of the interleaving by the interleaving apparatus shown in FIG. It is explanatory drawing shown about the structure of the interleaving apparatus which concerns on the 2nd Embodiment of this invention. FIG. 7 is an explanatory diagram showing a more detailed configuration of the address conversion circuit shown in FIG. 6. It is a flowchart shown about the operation | movement of the interleaving by the interleaving apparatus shown in FIG. It is explanatory drawing shown about the structure of the interleaving apparatus which concerns on the 3rd Embodiment of this invention. FIG. 10 is an explanatory diagram showing a more detailed configuration of the address conversion circuit shown in FIG. 9. 10 is a flowchart showing an interleaving operation by the interleaving apparatus shown in FIG. 9.

(First embodiment)
Hereinafter, the configuration of the embodiment of the present invention will be described with reference to FIGS.
First, the basic content of the present embodiment will be described, and then more specific content will be described.
The interleaving device 10 according to the present embodiment includes a memory 14 that temporarily stores input data, an address conversion circuit 11 that performs interleaving processing on addresses at which data is stored in the memory, and an address conversion circuit Is an interleaving device including a setting controller 12 for giving a setting given from a host device and a memory controller 13 for outputting data stored at an address subjected to interleaving on the memory. The address conversion circuit 11 includes a first address conversion unit 100 that outputs an intermediate address obtained by performing processing according to a first setting given by the setting controller on an input initial address, and an intermediate address And a second address conversion unit 200 that outputs to the memory controller an output address obtained by performing processing corresponding to the second setting given to the address by the setting controller. The interleaving process is executed.

  Here, the first address conversion unit 100 stores the first initial setting value holding unit 110 that stores a plurality of initial setting values given by the first setting, the first address and the initial setting value as the first. The first calculation means 120 for calculating according to the calculation rule given by the setting of the first calculation means, the second calculation means 130 for calculating the initial address and the initial set value according to the calculation rule given in advance, the first and second A first adder 140 that adds the outputs from the arithmetic means and outputs the result as an intermediate address. At the same time, the second address converting unit 200 stores the second initial setting value holding unit 210 that stores a plurality of initial setting values given by the second setting, and stores the intermediate address and the initial setting value in the second. The third computing means 220 for computing according to the computation rule given by the setting of the above, the fourth computing means 230 for computing the intermediate address and the initial set value according to the computation rule given in advance, and the third and fourth And a second adder 240 that adds the outputs from the arithmetic means and outputs them as output addresses.

  Further, the first calculation unit 120 of the first address conversion unit 100 sets the initial address and the first to fifth initial setting values stored in the first initial setting value holding unit 110 according to the first setting. Arithmetic according to the given calculation rule, the second calculation means 130 is given with the initial address and the sixth and seventh initial setting values stored in the first initial setting value holding means 110 in advance. And the third calculation means 220 of the second address conversion unit 200 calculates the second address of the initial address and the eighth to twelfth initial setting values stored in the second initial setting value holding means 210. The fourth arithmetic unit 230 calculates the initial address and the thirteenth and fourteenth initial set values stored in the second initial set value holding unit 210. Calculating according beforehand given calculation rules.

の式で示される演算によって中間アドレスに変換し、第８ないし第１４の初期設定値を各々ｉ８〜ｉ１４とし、出力アドレスをｇｘとすると、第２のアドレス変換部２００は中間アドレスを

の式で示される演算によって出力アドレスに変換する。 Further, if the first to seventh initial setting values are i1 to i7 and the initial address and intermediate address are x and fx, respectively, the first address conversion unit 100 sets the initial address to

The intermediate address is converted into an intermediate address by the operation expressed by the following equation, the eighth to fourteenth initial set values are i8 to i14, and the output address is gx.

It is converted into an output address by the operation shown in the equation.

With the above configuration, the interleaving apparatus 10 according to the present embodiment can cope with a plurality of interleaving schemes and can perform interleaving processing at high speed while suppressing the circuit scale to be small.
Hereinafter, this will be described in more detail.

  FIG. 2 is an explanatory diagram showing the configuration of the interleave device 10 according to the first embodiment of the present invention. The interleaving device 10 includes a memory controller 13 for inputting / outputting data to / from an external device, a setting controller 12 for changing device settings in response to a parameter setting operation from the host CPU 20, and data to be interleaved. Is temporarily stored, an address conversion circuit 11 that outputs an address of data stored in the memory 14 by performing an interleaving process described later, and an address conversion circuit 11 that generates an initial value of the address. And an initial address generation circuit 15 that outputs the data. The initial value of the address generated by the initial address generation circuit 15 can be generated by a known method such as a pure increase value or a random value.

  FIG. 1 is an explanatory diagram showing a more detailed configuration of the address conversion circuit 11 shown in FIG. The address conversion circuit 11 includes a first address conversion unit 100 and a second address conversion unit 200.

  The first address conversion unit 100 receives as input the input data shown in FIG. 2 stored in the memory 14 (this is referred to as an initial address), and receives the first initial set value holding means 110, the first calculation. Means 120, second arithmetic means 130, and adder 140 are provided, and an output value from adder 140 is output to second address conversion unit 200 as an intermediate address.

  The first initial set value holding means 110 stores in advance the first to seventh initial values set by the first setting from the setting controller 12. The first calculation means 120 receives the initial address and the first to fifth initial setting values as inputs and outputs the first calculation result as an output. The second calculation means 130 receives the initial address and the sixth to seventh initial set values as inputs, and outputs the second calculation result as an output. The adder 140 outputs an address obtained by adding the first calculation result and the second calculation result. This output address becomes an intermediate address.

  The second address conversion unit 200 has an intermediate address as an input, and includes a second initial setting value holding unit 210, a third calculation unit 220, a fourth calculation unit 230, and an adder 240. The output value is output to the memory controller 13 as an output address.

  The second initial set value holding unit 210 holds the eighth to fourteenth initial values set by the second setting from the setting controller 12. The third calculation means 220 receives the intermediate address and the eighth to twelfth initial set values as inputs, and outputs the third calculation result as an output. The fourth calculation means 230 receives the intermediate address and the thirteenth to fourteenth initial set values as inputs, and outputs a fourth calculation result. The adder 240 outputs an address obtained by adding the third calculation result and the fourth calculation result. This output address becomes the output address.

  FIG. 3 is an explanatory diagram showing a more detailed configuration of the first calculation means 120 and the third calculation means 220 shown in FIG. The first calculation unit 120 and the third calculation unit 220 have different input / output values, but have the same circuit configuration, and therefore are shown in the same figure.

  As described above, the first calculation means 120 receives the initial address and the first to fifth initial setting values as input, and the multiplier 121, the divider 122, the floor calculator 123, and the addition / subtraction with respect to this input value. The calculator 124, the remainder calculator 125, and the multiplier 126 perform an operation, and the output value from the multiplier 126 is output as a first operation result.

  The multiplier 121 receives the initial address and the second initial set value and outputs the multiplication result. The divider 122 receives the output of the multiplier 121 and the third initial setting value, and outputs the result of the division. The floor calculator 123 receives the output of the divider 122 and outputs the calculation result.

  The adder / subtractor 124 receives the initial address, the first initial set value, and the output from the floor calculator 123 as an input, and outputs the calculation result. At that time, the adder / subtractor 124 determines whether (addition, addition, subtraction) or (addition, addition, addition) is performed on these three inputs according to the first setting given from the setting controller 12. Perform one of the operations.

  The remainder calculator 125 receives the output of the adder / subtractor 124 and the fourth initial set value, and outputs the calculation result. The multiplier 126 receives the output of the remainder calculator 125 and the fifth initial setting value, and uses the multiplication result as the first calculation result.

  The third computing means 220 has the same circuit configuration as the first computing means 120 and has different input / output values. That is, the third calculation means 220 receives the intermediate address and the eighth to twelfth initial set values as input, and the multiplier 221, the divider 222, the floor calculator 223, the adder / subtractor 224, An operation is performed by the remainder calculator 225 and the multiplier 226, and an output value from the multiplier 226 is output as a third operation result.

  The multiplier 221 receives the intermediate address and the ninth initial setting value, and outputs the multiplication result. The divider 222 receives the output of the multiplier 221 and the tenth initial setting value and outputs the division result. The floor calculator 223 receives the output of the divider 222 and outputs the calculation result.

  The adder / subtractor 224 receives the intermediate address, the eighth initial set value, and the output from the floor calculator 223 as inputs, and outputs the calculation result. At that time, the adder / subtracter 224 determines whether (addition, addition, subtraction) or (addition, addition, addition) is performed on these three inputs according to the second setting given from the setting controller 12. Perform one of the operations.

  The remainder calculator 225 receives the output of the adder / subtractor 224 and the eleventh initial set value and outputs the calculation result. The multiplier 226 receives the output of the remainder calculator 225 and the twelfth initial set value and uses the multiplication result as the third calculation result.

  FIG. 4 is an explanatory diagram showing a more detailed configuration of the second calculation means 130 and the fourth calculation means 230 shown in FIG. The second calculation means 130 and the fourth calculation means 230 have different input / output values, but have the same circuit configuration, and therefore are shown in the same figure.

  The second computing means 130 receives the initial address and the sixth to seventh initial set values as input, and performs computation on the input value by the divider 131, the floor computing unit 132, and the multiplier 133, and the multiplier The output value from 133 is output as the second calculation result.

  The divider 131 receives the initial address and the sixth initial set value and outputs the division result. The floor calculator 132 receives the output of the divider 131 and outputs the calculation result. The multiplier 133 receives the output of the floor calculator 132 and the seventh initial set value as input, and sets the multiplication result as the second calculation result.

  The fourth arithmetic means 230 receives the intermediate address and the thirteenth to fourteenth initial set values as input, performs arithmetic operations on the input values by the divider 231, the floor arithmetic unit 232, and the multiplier 233. The output value from 233 is output as the fourth calculation result.

  The divider 231 receives the intermediate address and the thirteenth initial set value and outputs the division result. The floor calculator 232 receives the output of the divider 231 and outputs the calculation result. The multiplier 233 receives the output of the floor calculator 232 and the fourteenth initial set value and uses the multiplication result as the fourth calculation result.

(Calculation operation of the first embodiment)
A calculation operation by the address conversion circuit 11 described above will be described. FIG. 5 is a flowchart showing the interleaving operation by interleaving apparatus 10 shown in FIG. First, in response to a parameter setting operation from the host CPU 20, the setting controller 12 sets the first setting in the first address conversion unit 100 of the address conversion circuit 11 and the second setting in the second address conversion unit 200. Is given (step S251).

  When the first and second settings for the address conversion circuit 11 are completed, the memory controller 13 waits for input of data to be interleaved from the outside (step S252), and stores the data in the memory 14 if data is input. (Step S253).

  The stored address of the target data in the memory 14 is input to the address conversion circuit 11 as an initial address, and the first address conversion unit 100 outputs an intermediate address with respect to the initial address (step In step S254, the second address conversion unit 200 outputs an output address for the intermediate address (step S255). Then, the memory controller 13 reads out the output address data from the memory 14 and outputs it (step S256).

  This will be described based on the premise of the above operation. The block interleaving process is expressed as the following equation 1 by combining a plurality of types. Here, x indicates the sequence number of the interleaved block, and fx indicates the x-th output address of the sequence. Further, i1 to i7 indicate initial setting values set according to each communication standard. “%” Is a remainder operator, and “A% B” represents a remainder obtained by dividing the numerical value A by the numerical value B. Moreover, the symbol of the shape without the upper part of [] is a floor operator (floor operator).

即ち、初期アドレスをｘとすると、ｆｘは中間アドレスとなり、ｉ１〜ｉ７は第１のアドレス変換部１００に対して第１の設定で与えられる第１〜第７の初期値となり、上記の数１は第１のアドレス変換部１００で行われる処理を表す。 [Equation 1]

That is, assuming that the initial address is x, fx is an intermediate address, i1 to i7 are first to seventh initial values given to the first address conversion unit 100 by the first setting, and the above equation 1 Represents processing performed in the first address conversion unit 100.

  When gx is an output address and i8 to i14 are the eighth to fourteenth initial values given to the second address conversion unit 200 by the second setting, the second address conversion unit 200 performs the process. The processing is expressed by the following formula 2 in which only the variable of the above formula 1 is replaced.

[Equation 2]

  As shown in FIG. 5, the address conversion circuit 11 operates in two phases: first, setting parameters (step S251), and then operating based on the parameters (step S252 and subsequent steps). Hereinafter, in order to simplify the description, the adder / subtractor 124 and the adder / subtractor 224 are set by the setting controller 12 according to the first and second settings so as to perform the operation of (addition, addition, subtraction). And

  First, the first and second settings are given from the upper CPU 20 to the first address conversion unit 100 and the second address conversion unit 200 via the setting controller 12. As a result, the first initial value to the seventh initial value of the first initial set value holding unit 110 are set, and the eighth initial value to the fourteenth initial value of the second initial set value holding unit 210 are set. Value is set to value. The adder / subtractor 124 is set to perform (addition, addition, subtraction) on three inputs. Similarly, the adder / subtractor 224 is also set to perform (addition, addition, subtraction) on the three inputs.

  Here, the first to seventh initial values in the first initial set value holding unit 110 correspond to i1 to i7 of the above formula 1, respectively, and the eighth to 14th in the second initial set value holding unit 210. Also correspond to i8 to i14 in the above equation 2, respectively.

  An initial address is input to the first address conversion unit 100 that has completed the above settings. As the initial address to be input, addresses corresponding to the number of blocks in the block interleave are sequentially input without excess or deficiency. The initial address input to the first address conversion unit 100 is input to the first calculation unit 120 and the second calculation unit 130. The first initial set value holding unit 110 outputs the first to fifth initial set values (i1 to i5) to the first calculation unit 120, and the sixth to seventh initial set values (i6 to i7). Is output to the second calculation means 130.

  In the first computing means 120, the multiplier 121 multiplies the input initial address and the second initial set value (i2) and outputs the multiplication result. The divider 122 divides the output from the multiplier 121 by the third initial setting value (i3) and outputs the division result. The floor calculator 123 performs a floor calculation on the output from the divider 122 and outputs the calculation result.

  The adder / subtractor 124 performs addition / subtraction (addition, addition, subtraction) on the initial address, the first initial setting value (i1), and the output from the floor calculator 123, and outputs the calculation result. The remainder calculator 125 performs a remainder operation on the output from the adder / subtractor 124 with the fourth initial set value (i4), and outputs the result of the operation. The multiplier 126 multiplies the output from the remainder calculator 125 and the fifth initial setting value (i5), and outputs the multiplication result as the first calculation result.

  On the other hand, in the second calculation means 130, the divider 131 divides the input initial address by the sixth initial set value (i6) and outputs the division result. The floor calculator 132 performs a floor calculation on the output from the divider 131 and outputs the calculation result. The multiplier 133 multiplies the output from the floor calculator 132 and the seventh initial setting value (i7), and outputs the multiplication result as the second calculation result.

  The adder 140 adds the first calculation result and the second calculation result, and outputs the result as an intermediate address. The output intermediate address is input to the second address conversion unit 200.

  The intermediate address input to the second address conversion unit 200 is input to the third calculation unit 220 and the fourth calculation unit 230. The second initial setting value holding unit 210 outputs the eighth to twelfth initial setting values (i8 to i12) to the third arithmetic unit 220, and the thirteenth to fourteenth initial setting values (i13 to i4). Is output to the fourth computing means 230.

  In the third computing means 220, the multiplier 221 multiplies the inputted intermediate address by the ninth initial setting value (i9) and outputs the multiplication result. The divider 222 divides the output from the multiplier 221 by the tenth initial setting value (i10) and outputs the division result. The floor calculator 223 performs a floor calculation on the output from the divider 222 and outputs the calculation result.

  The adder / subtractor 224 performs addition / subtraction (addition, addition, subtraction) to the intermediate address, the eighth initial setting value (i8), and the output from the floor calculator 223, and outputs the calculation result. The remainder calculator 225 performs a remainder operation on the output from the adder / subtractor 224 with the eleventh initial setting value (i11), and outputs the result of the operation. The multiplier 226 multiplies the output from the remainder calculator 225 and the twelfth initial setting value (i12), and outputs the multiplication result as a third calculation result.

  On the other hand, in the fourth computing means 230, the divider 231 divides the intermediate address by the thirteenth initial setting value (i13) and outputs the division result. The floor calculator 232 performs a floor calculation on the output from the divider 231 and outputs the calculation result. The multiplier 233 multiplies the output from the floor calculator 232 and the fourteenth initial setting value (i14), and outputs the multiplication result as the fourth calculation result.

  The adder 240 adds the third calculation result and the fourth calculation result, and outputs the result as an output address.

  The output address output from the second address conversion unit 200 as described above is an address output to the memory controller 13 in order to access the memory 14 in which the data to be interleaved is stored. Since the first address conversion unit 100 and the second address conversion unit 200 are connected in series, processing can be continuously performed in a pipeline manner. Therefore, as long as the initial address is continuously input to the first address conversion unit 100, the interleaving apparatus 10 of the present embodiment continuously performs the interleaving process as shown in the flowchart of FIG. It is possible.

  That is, the interleaving device 10 does not interleave the data itself, but performs the above-described processing on the address used to access the memory 14 and reads the data of the output address converted thereby from the memory 14. Thus, interleaving processing is realized.

  As a result, since the interleaved address is supplied to the memory 14, even when interleaving is performed by combining a plurality of processes, only one access to the memory is required. That is, the number of accesses to the memory 14 can be reduced, and processing can be continued continuously in a pipeline manner with respect to initial addresses that are continuously input, so the load and time required for processing can be reduced. .

(Application example of the first embodiment for actual communication)
Hereinafter, two examples of application of the interleave device 10 to actual communication will be described. First, the case where the interleaving apparatus 10 is applied to the IEEE 802.11a symbol interleaving process will be described. In the IEEE802.11a symbol interleaving, as described above, two types of different processes, the first permutation and the second permutation, are combined into one interleave.

  In this case, in the address conversion circuit 11, the first address conversion unit 100 corresponds to the first permutation process, and the second address conversion unit 200 corresponds to the second permutation process. It is. The parameters here are the interleave block size N = 192, and 16QAM is used as the modulation scheme.

  At this time, each address generation formula of the first permutation and the second permutation is expressed by the following equations 3 to 3. fx is an intermediate address output by the first address conversion unit 100 with respect to the input initial address x. Gx is an output address output by the second address conversion unit 200 with respect to the input intermediate address fx.

[Equation 3]

[Equation 4]

  Here, at the time of the first setting to the first address conversion unit 100, the first to seventh initial setting values set in the first initial setting value holding means 110 from the host CPU 20 via the setting controller 12 i1 to i7 are respectively (i1, i2, i3, i4, i5, i6, i7) = (0, 0, 1, 16, 12, 16, 1).

  Then, at the time of the second setting in the second address conversion unit 200, the eighth to fourteenth initial setting values i8 set in the second initial setting value holding means 210 from the host CPU 20 via the setting controller 12 ˜i14 is (i8, i9, i10, i11, i12, i13, i14) = (128, 1, 8, 2, 1, 2, 2).

  Further, the adder / subtractor 124 of the first calculation means 120 is set so as to perform a calculation (addition, addition, subtraction) from the upper CPU 20 via the setting controller 12. On the other hand, the adder / subtracter 224 of the third calculation means 220 is set to perform a calculation (addition, addition, subtraction). The initial address x is input in order from 0 to 191 without excess or deficiency.

  At this time, the first address conversion unit 100 performs address conversion based on the input initial address x and the first to seventh initial setting values i1 to i7 set based on the first setting, The address fx is output. Further, the second address conversion unit 200 performs address conversion based on the intermediate address fx and the eighth to fourteenth initial setting values i8 to i14 set based on the second setting, and outputs the output address gx To do. As described above, address generation for IEEE802.11a symbol interleaving can be performed.

  Next, the case where the interleaving apparatus 10 is applied to the DVB-T2 cell interleaving process will be described. DVB-T2 cell interleaving is an interleaving in which a random value generated by a circuit based on a linear feedback shift register is used as an initial address, and a shift based on a symbol number is combined therewith.

  The parameters here are the interleave block size N = 8100 (= 64800/8), and the cell interleave shift amount is 4096. At this time, an address generation formula of a permutation function of DVB-T2 cell interleaving is expressed by the following equation (5).

[Equation 5]

  Here, at the time of the first setting to the first address conversion unit 100, the first to seventh initial setting values i1 set in the first initial setting value holding means 110 from the host CPU 20 via the setting controller 12 ˜i7 is (i1, i2, i3, i4, i5, i6, i7) = (0, 0, 1, 4096, 1, 1, 0), respectively.

  The second address conversion unit 200 does not perform address conversion and outputs the output address as it is without changing the intermediate address. Therefore, at the time of the second setting for the second address conversion unit 200, the initial setting value holding unit 210 is not set. That is, the 8th to 14th initial setting values i8 to i14 are (i8, i9, i10, i11, i12, i13, i14) = (0, 0, 1, 8100, 0, 0, 0), respectively. Is equivalent to the case.

  The initial address is generated by a circuit based on a linear feedback shift register according to the standard, and the value does not overlap while the initial address of one block size is output. In the above parameters, the initial address is a value not less than 0 and less than 8100.

  At this time, the first address conversion unit 100 performs address conversion based on the input initial address and the first to seventh initial setting values i1 to i7 set based on the first setting, and the intermediate address Output fx. The second address conversion unit 200 does not convert the intermediate address fx and outputs the output address gx as fx = gx as it is. As described above, address generation for DVB-T2 cell interleaving can be performed.

(Overall operation of the first embodiment)
Next, the overall operation of the above embodiment will be described.
The address conversion method according to the present embodiment includes a memory 14 that temporarily stores input data, an address conversion circuit 11 that performs an interleaving process on addresses at which data is stored in the memory, and an address conversion circuit. The interleaving device 10 includes a setting controller 12 for giving a setting given from a host device and a memory controller 13 for inputting / outputting data to / from the memory. First and second settings are respectively given to the second address conversion unit (FIG. 5, step S251), and the memory controller stores the input data in the memory and initializes the address on the memory where the data is stored. The address is input to the address conversion circuit (FIG. 5, steps S252 to 253), and the first address is input. The conversion unit outputs an intermediate address obtained by performing processing corresponding to the first setting on the initial address (FIG. 5, step S254), and the second address conversion unit outputs the intermediate address to the intermediate address. 2 is output to the memory controller (step S255 in FIG. 5), and the memory controller outputs the data stored in the output address on the memory (FIG. 5). Step S256).

Here, each of the above-described operation steps may be programmed to be executable by a computer, and may be executed by the interleave device 10 that directly executes each of the steps. Further, the interleave device 10 itself can be virtually realized by a computer. The program may be recorded on a non-temporary recording medium, such as a DVD, a CD, or a flash memory. In this case, the program is read from the recording medium by a computer and executed.
By this operation, this embodiment has the following effects.

  As described above, the interleaving apparatus 10 can support a plurality of interleaving / deinterleaving schemes only by changing the initial setting values i1 to i14. For example, not only IEEE 802.11a described as the first application example but also other similar interleaving / deinterleaving processing such as WiMAX (IEEE802.16 series) can be applied. Further, not only DVB-T2 cell interleaving described as the second application example but also other similar interleaving / deinterleaving can be applied.

  In addition, the interleaving device 10 performs a plurality of processes by performing address conversion using a plurality of stages of address conversion devices (first address conversion unit 100 and second address conversion unit 200) that calculate a block interleaving general formula. Even when the interleaves are combined into one interleave, it is possible to generate an interleave address in one behavior without dividing it into a plurality of times. Therefore, the circuit scale can be reduced as compared with the case where data is directly interleaved using a memory.

  Here, the operation example in which the address conversion circuit 11 is applied to the interleave device 10 has been described. However, the address conversion circuit 11 is applied to the deinterleave device by changing the supply destination of the generated output address to either the read / write address port. You can also. For example, if the address conversion circuit 11 that supplies the write address to the memory 14 at the time of interleaving is changed to supply a read address, the same address conversion circuit 11 is used for deinterleaving. be able to.

  Further, since the address conversion circuit 11 rearranges the addresses based on a predetermined rule, it can be applied to any device other than the interleave device as long as it rearranges the data.

(Second Embodiment)
In the interleaving device 310 according to the second embodiment of the present invention, in addition to the configuration of the first embodiment, the address conversion circuit 11 performs interleaving processing according to the third setting given by the setting controller 12. The configuration includes an initial address generation unit 400 that generates a random number or a count value corresponding to the block size and outputs this as an initial address.

  The initial address generation unit 400 includes a random number generation unit 420 that generates a random number that does not overlap for each process within the block size range, and a count that is changed by 1 for each process within the block size range. A counter (N-ary counter 410) that generates a value, and a multiplexer 430 that selects and outputs one of the generated random number or count value according to the third setting.

With this configuration, the effect obtained by the first embodiment can be obtained even in an interleaving method in which an initial address needs to be generated by an N-ary counter or a random number.
This will be described in more detail below.

  FIG. 6 is an explanatory diagram showing the configuration of the interleaving apparatus 310 according to the second embodiment of the present invention. Compared with the interleave device 10 according to the first embodiment described above, the interleave device 310 is obtained by replacing the address conversion circuit 11 with another address conversion circuit 311 and further omitting the initial address generation circuit 15. Since other configurations are the same, the same elements are denoted by the same designations and reference numerals.

  FIG. 7 is an explanatory diagram showing a more detailed configuration of the address conversion circuit 311 shown in FIG. The address conversion circuit 311 is a new initial address generation unit in addition to the first address conversion unit 100 and the second address conversion unit 200 provided in the address conversion circuit 11 according to the first embodiment. 400 has been added. That is, the input address input to the address conversion circuit 11 according to the first embodiment is only provided with conditions, but in this embodiment, the initial address input to the first address conversion unit 100 is used. It is generated by the initial address generator 400. Since the address conversion circuit 311 includes the initial address generation unit 400, the initial address generation circuit 15 according to the first embodiment is not required.

  The initial address generation unit 400 includes an N-ary counter 410, a random number generation unit 420, and a multiplexer 430, and an output value from the multiplexer 430 becomes an initial address input to the first address conversion unit 100. Here, N is an integer representing the block size of block interleaving, and is set by the third setting given from the host CPU 20 via the setting controller 12.

  The N-ary counter 410 outputs a count value in the range of 0 to N-1. The random number generation means 420 generates a random number in the range of 0 to N-1. In addition, the random number generation unit 420 does not generate duplicate values within the block size N. The multiplexer 430 receives the count value output from the N-ary counter 410 and the random number output from the random number generation means 420, and either one of them is given from the host CPU 20 via the setting controller 12. And output based on the third setting.

  The configurations of the first address conversion unit 100 and the second address conversion unit 200 are the same as those of the first embodiment described with reference to FIG. Therefore, only the outline of the configuration will be described here. The first address conversion unit 100 has an initial address output from the multiplexer 430 as an input, and includes a first initial setting value holding unit 110, a first calculation unit 120, a second calculation unit 130, and an adder 140. The output value from the adder 140 is output to the second address conversion unit 200 as an intermediate address.

  The first initial set value holding means 110 stores in advance the first to seventh initial values set by the first setting from the setting controller 12. The first calculation means 120 receives the initial address and the first to fifth initial setting values as inputs and outputs the first calculation result as an output. The second calculation means 130 receives the initial address and the sixth to seventh initial set values as inputs, and outputs the second calculation result as an output.

  The adder 140 outputs an address obtained by adding the first calculation result and the second calculation result. This output address becomes an intermediate address. The more detailed configuration of the first to second calculation means 120 and 130 is the same as that of the first embodiment shown in FIGS.

  The second address conversion unit 200 has an intermediate address as an input, and includes a second initial setting value holding unit 210, a third calculation unit 220, a fourth calculation unit 230, and an adder 240. The output value is output to the memory controller 13 as an output address.

  The second initial set value holding unit 210 holds the eighth to fourteenth initial values set by the second setting from the setting controller 12. The third calculation means 220 receives the intermediate address and the eighth to twelfth initial set values as inputs, and outputs the third calculation result as an output. The fourth calculation means 230 receives the intermediate address and the thirteenth to fourteenth initial set values as inputs, and outputs a fourth calculation result.

  The adder 240 outputs an address obtained by adding the third calculation result and the fourth calculation result. This output address becomes the output address. The more detailed configuration of the third to fourth calculation means 220 and 230 is the same as that of the first embodiment shown in FIGS.

(Calculation operation of the second embodiment)
The operation of the calculation by the address conversion circuit 311 described above will be described. FIG. 8 is a flowchart showing an interleaving operation by interleaving apparatus 310 shown in FIG. First, in response to a parameter setting operation from the host CPU 20, the setting controller 12 sets a first setting in the first address conversion unit 100 and a second setting in the second address conversion unit 200 of the address conversion circuit 311. Then, the third setting is given to the initial address generator 400 (step S451).

  When the first to third settings for the address conversion circuit 311 are completed, the memory controller 13 waits for input of data to be interleaved from the outside (step S452), and stores the data in the memory 14 if data is input. (Step S453).

  Then, the initial address generation unit 400 generates an initial address based on the given third setting and inputs it to the first address conversion unit 100 (step S454), and the first address conversion unit 100 An intermediate address is output with respect to the initial address (step S455), and the second address conversion unit 200 outputs an output address with respect to the intermediate address (step S456). Then, the memory controller 13 reads out the output address data from the memory 14 and outputs it (step S457).

  Hereinafter, in order to simplify the description, it is assumed that the setting controller 12 sets the adder / subtractor 124 and the adder / subtractor 224 so as to perform an operation of (addition, addition, subtraction).

  First, the first to third settings are given from the upper CPU 20 to the first address conversion unit 100, the second address conversion unit 200, and the initial address generation unit 400 via the setting controller 12.

  As a result, the first initial value to the seventh initial value of the first initial set value holding unit 110 are set, and the eighth initial value to the fourteenth initial value of the second initial set value holding unit 210 are set. Value is set to value. The adder / subtractor 124 is set to perform (addition, addition, subtraction) on three inputs. Similarly, the adder / subtractor 224 is also set to perform (addition, addition, subtraction) on the three inputs. Further, in the multiplexer 430, it is set whether to select and output one of the two inputs. Here, it is assumed that the count value output from the N-ary counter 410 is set to be output.

  Address conversion processing is started in the address conversion circuit 311 that has completed the above settings. At this time, in the initial address generation unit 400, count values from 0 to N-1 are sequentially output from the N-ary counter 410 to the multiplexer 430, and this is input from the multiplexer 430 to the first address conversion unit 100 by setting. This is the initial address to be used.

  Subsequent operations of the first address conversion unit 100 and the second address conversion unit are the same as those in the first embodiment. The output address output from the second address conversion unit 200 as described above is an address output to the memory controller 13 in order to access the memory 14 in which data to be interleaved is stored.

  Since the initial address generation unit 300, the first address conversion unit 100, and the second address conversion unit 200 are connected in series, processing can be continuously performed in a pipeline manner. Therefore, as long as the initial address is continuously output from the initial address generation means 300, the interleave device 310 of this embodiment can output the output address continuously, and the same effect as that of the first embodiment. Can be obtained.

(Application example of the second embodiment for actual communication)
Hereinafter, two types of application examples of the interleave device 310 for actual communication will be described. First, the case where the interleaving apparatus 310 is applied to the IEEE 802.11a symbol interleaving process will be described. In the IEEE802.11a symbol interleaving, two different types of processing, the first permutation and the second permutation, are combined into one interleave.

  In this case, in the address conversion circuit 311, the first address conversion unit 100 corresponds to the first permutation process, and the second address conversion unit 200 corresponds to the second permutation process. It is. The parameters here are the interleave block size N = 192, and 16QAM is used as the modulation scheme. Further, the initial address increases sequentially from 0 to 191.

  At this time, each address generation formula of the first permutation and the second permutation is expressed by the same formula as the above-described equations 3 to 3. Accordingly, the first to seventh initial setting values i1 set in the first initial setting value holding means 110 from the host CPU 20 via the setting controller 12 at the time of the first setting to the first address conversion unit 100. To i7 are (i1, i2, i3, i4, i5, i6, i7) = (0, 0, 1, 16, 12, 16, 1), respectively, as in the first embodiment.

  Further, at the time of the second setting in the second address conversion unit 200, the eighth to fourteenth initial setting values i8 set in the second initial setting value holding means 210 from the host CPU 20 via the setting controller 12 ˜i14 are respectively (i8, i9, i10, i11, i12, i13, i14) = (128, 1, 8, 2, 1, 2, 2), as in the first embodiment.

  Further, the adder / subtractor 124 of the first calculation means 120 is set so as to perform a calculation (addition, addition, subtraction) from the upper CPU 20 via the setting controller 12. On the other hand, the adder / subtracter 224 of the third calculation means 220 is set to perform a calculation (addition, addition, subtraction). The multiplexer 430 of the initial address generator 400 is set to select and output the input on the N-ary counter 410 side.

  At this time, the first address conversion unit 100 performs address conversion based on the input initial address and the first to seventh initial setting values set based on the first setting, and outputs an intermediate address. . The second address translation unit performs address translation based on the intermediate address and the eighth to fourteenth initial setting values set based on the second setting, and outputs an output address. This specific operation is the same as that of the first embodiment. As described above, address generation for IEEE802.11a symbol interleaving can be performed.

  Next, the case where the interleaving apparatus 310 is applied to the DVB-T2 cell interleaving process will be described. DVB-T2 cell interleaving is an interleaving in which a random value generated by a circuit based on a linear feedback shift register is used as an initial address, and a shift based on a symbol number is combined therewith. Here, the initial address generation unit 400 corresponds to the generation of a basic permutation function in the interleaving device 310.

  The parameters here are the interleave block size N = 8100 (= 64800/8), and the cell interleave shift amount is 4096. At this time, the DVB-T2 cell interleave permutation function address generation formula is expressed by the same formula as Equation 5 described above.

  Here, at the time of the first setting to the first address conversion unit 100, the first to seventh initial setting values i1 set in the first initial setting value holding means 110 from the host CPU 20 via the setting controller 12 ˜i7 is (i1, i2, i3, i4, i5, i6, i7) = (0, 0, 1, 4096, 1, 1, 0), respectively.

  The second address conversion unit 200 does not perform address conversion and outputs the output address as it is without changing the intermediate address. Therefore, at the time of the second setting for the second address conversion unit 200, the initial setting value holding unit 210 is not set. That is, the 8th to 14th initial setting values i8 to i14 are (i8, i9, i10, i11, i12, i13, i14) = (0, 0, 1, 8100, 0, 0, 0), respectively. Is equivalent to the case.

  Further, in the third setting to the initial address generation unit 400, the setting is made so that the multiplexer 430 selects the input on the random number generation unit 420 side from the host CPU 20 via the setting controller 12. In the random number generation means 420, a random number is generated by a circuit based on a linear feedback shift register according to the standard. This random number is an integer value in the range of 0-8099.

  At this time, the first address conversion unit 100 performs address conversion based on the input initial address and the first to seventh initial setting values set based on the first setting, and outputs an intermediate address. . The second address conversion unit does not convert the intermediate address and outputs it as an output address. As described above, address generation for DVB-T2 cell interleaving can be performed.

  As described above, the interleaving device 310 can cope with a plurality of interleaving / deinterleaving schemes only by changing the initial setting values i1 to i14 and the setting for the multiplexer 430. For example, not only IEEE 802.11a described as the first application example but also other similar interleaving / deinterleaving processing such as WiMAX (IEEE802.16 series) can be applied. Further, not only DVB-T2 cell interleaving described as the second application example but also other similar interleaving / deinterleaving can be applied.

  The interleaving device 310 performs a plurality of processes by performing address conversion using a plurality of stages of address conversion devices (first address conversion unit 100 and second address conversion unit 200) that calculate a general formula of block interleaving. Even when the interleaves are combined into one interleave, it is possible to generate an interleave address in one behavior without dividing it into a plurality of times. Therefore, it is possible to obtain the same effect as that of the first embodiment that the circuit scale can be reduced as compared with the case where the data is directly interleaved using the memory.

  In the present embodiment, the same effect as that of the first embodiment described above can be obtained even in an interleaving method in which an initial address needs to be generated by an N-ary counter or a random number.

(Third embodiment)
In the interleaving apparatus 510 according to the third embodiment of the present invention, in addition to the configuration of the second embodiment, the address conversion circuit 511 sets the output address according to the fourth setting given by the setting controller 12. A look-up table unit 600 that converts the final output address and outputs it to the memory controller is provided.

  Further, the lookup table unit 600 subtracts the offset value output from the offset output means from the output address, and the offset output means 610 that outputs an offset value that increases with each processing count given in the fourth setting. A subtractor 620 for outputting a value; a memory means 630 for storing a value given by a setting controller; and a value stored at an address corresponding to the value outputted from the subtractor; and an output from the memory means And an adder 640 for adding the output value and the value output from the offset output means and outputting the result as a final output address.

With this configuration, the effects obtained by the first and second embodiments can be obtained even in an interleaving method that requires the use of a table-type interleaving.
This will be described in more detail below.

  FIG. 9 is an explanatory diagram illustrating a configuration of an interleave apparatus 510 according to the third embodiment of the present invention. Compared with the interleaving device 10 according to the first embodiment described above, the interleaving device 510 is obtained by replacing the address conversion circuit 11 with another address conversion circuit 511 and further omitting the initial address generation circuit 15. Since other configurations are the same, the same elements are denoted by the same designations and reference numerals.

  FIG. 10 is an explanatory diagram showing a more detailed configuration of the address conversion circuit 511 shown in FIG. The address conversion circuit 511 includes the first address conversion unit 100, the second address conversion unit 200, and the initial address generation unit 400 provided in the address conversion circuit 311 according to the second embodiment described above. A lookup table unit 600 is newly added after the second address conversion unit 200. Therefore, here, the output from the first address translation unit 100 is referred to as a first intermediate address, and the output from the second address translation unit 200 is referred to as a second intermediate address. Incidentally, in the claims, the output from the second address conversion unit 200 is used as an output address, and the output from the lookup table unit 600 is used as a final output address. Since the address conversion circuit 511 includes the initial address generation unit 400, the initial address generation circuit 15 according to the first embodiment is not required.

  The lookup table unit 600 has the second intermediate address output from the second address conversion unit 200 as an input, and includes an offset output unit 610, a subtracter 620, a memory unit 630, and an adder 640. Are output to the memory controller 13 as output addresses.

  The offset output means 610 outputs the offset value set by the fourth setting from the setting controller 12. The subtractor 620 receives the second intermediate address and the offset value output from the offset output means 610, and outputs the subtraction result. The memory means 630 stores a value in advance by the fourth setting from the setting controller 12, and uses the output from the subtracter 620 as an input address and outputs the value stored at that address. The adder 640 receives the output from the memory unit 630 and the output from the offset output unit 610, and outputs the addition result as an output address.

  The other configurations of the first address conversion unit 100, the second address conversion unit 200, and the initial address generation unit 400 are the same as those in the first and second embodiments described with reference to FIGS. Therefore, only the outline thereof will be described here.

  The initial address generation unit 400 includes an N-ary counter 410, a random number generation unit 420, and a multiplexer 430, and an output value from the multiplexer 430 becomes an initial address input to the first address conversion unit 100. Here, N is an integer representing the block size of block interleaving, and is set by the third setting given from the host CPU 20 via the setting controller 12.

  The N-ary counter 410 outputs a count value in the range of 0 to N-1. The random number generation means 420 generates a random number in the range of 0 to N-1. In addition, the random number generation unit 420 does not generate duplicate values within the block size N. The multiplexer 430 receives the count value output from the N-ary counter 410 and the random number output from the random number generation means 420, and either one of them is given from the host CPU 20 via the setting controller 12. And output based on the third setting.

  The first address conversion unit 100 has an initial address output from the multiplexer 430 as an input, and includes a first initial setting value holding unit 110, a first calculation unit 120, a second calculation unit 130, and an adder 140. The output value from the adder 140 is output to the second address conversion unit 200 as the first intermediate address.

  The first initial set value holding means 110 stores in advance the first to seventh initial values set by the first setting from the setting controller 12. The first calculation means 120 receives the initial address and the first to fifth initial setting values as inputs and outputs the first calculation result as an output. The second calculation means 130 receives the initial address and the sixth to seventh initial set values as inputs, and outputs the second calculation result as an output.

  The adder 140 outputs an address obtained by adding the first calculation result and the second calculation result. This output address becomes the first intermediate address. The more detailed configuration of the first to second calculation means 120 and 130 is the same as that of the first embodiment shown in FIGS.

  The second address conversion unit 200 has an intermediate address as an input, and includes a second initial setting value holding unit 210, a third calculation unit 220, a fourth calculation unit 230, and an adder 240. The output value is output to the lookup table unit 600 as a second intermediate address.

  The second initial set value holding unit 210 holds the eighth to fourteenth initial values set by the second setting from the setting controller 12. The third calculation means 220 receives the intermediate address and the eighth to twelfth initial set values as inputs, and outputs the third calculation result as an output. The fourth calculation means 230 receives the intermediate address and the thirteenth to fourteenth initial set values as inputs, and outputs a fourth calculation result.

  The adder 240 outputs an address obtained by adding the third calculation result and the fourth calculation result. This output address becomes the second intermediate address. The more detailed configuration of the third to fourth calculation means 220 and 230 is the same as that of the first embodiment shown in FIGS.

(Calculation operation of the third embodiment)
The calculation operation by the address conversion circuit 511 described above will be described. FIG. 11 is a flowchart showing an interleaving operation by interleaving apparatus 510 shown in FIG. First, in response to a parameter setting operation from the host CPU 20, the setting controller 12 sets the first setting in the first address conversion unit 100 and the second setting in the second address conversion unit 200 of the address conversion circuit 511. The third setting is given to the initial address generation unit 400, and the fourth setting is given to the lookup table unit 600 (step S651).

  When the first to fourth settings for the address conversion circuit 511 are completed, the memory controller 13 waits for input of data to be interleaved from the outside (step S652), and stores the data in the memory 14 if data is input. (Step S653).

  Then, the initial address generation unit 400 generates an initial address based on the given third setting and inputs it to the first address conversion unit 100 (step S654), and the first address conversion unit 100 The first intermediate address is output for the initial address (step S655), and the second address converter 200 outputs the second intermediate address for the first intermediate address (step S656).

  Then, the lookup table unit 600 outputs an output address corresponding to the second intermediate address (step S657), and the memory controller 13 reads out the output address data from the memory 14 and outputs it (step S658).

  Hereinafter, in order to simplify the description, it is assumed that the setting controller 12 sets the adder / subtractor 124 and the adder / subtractor 224 so as to perform an operation of (addition, addition, subtraction).

  First, the first to fourth address converters 100, 200, 200, and 600 through the setting controller 12 from the upper CPU 20 are respectively used. Give settings.

  As a result, the first initial value to the seventh initial value of the first initial set value holding unit 110 are set, and the eighth initial value to the fourteenth initial value of the second initial set value holding unit 210 are set. Value is set to value. The adder / subtractor 124 is set to perform (addition, addition, subtraction) on three inputs. Similarly, the adder / subtractor 224 is also set to perform (addition, addition, subtraction) on the three inputs.

  Further, in the multiplexer 430, it is set whether to select and output one of the two inputs. Here, it is assumed that the count value output from the N-ary counter 410 is set to be output. The memory unit 630 stores in advance a pattern corresponding to an interleaving method for converting an input address to an output address.

  Address conversion processing is started in the address conversion circuit 511 that has completed the above settings. At this time, in the initial address generation unit 400, count values from 0 to N-1 are sequentially output from the N-ary counter 410 to the multiplexer 430, and this is input from the multiplexer 430 to the first address conversion unit 100 by setting. This is the initial address to be used.

  Subsequent operations of the first address conversion unit 100 and the second address conversion unit are the same as those in the first embodiment. As described above, the second intermediate address is output from the second address conversion unit 200 to the lookup table unit 600.

  In the look-up table unit 600, the offset output unit 610 outputs an offset value that increases every time the second intermediate address is input the number of times specified by the fourth setting. The subtractor 620 subtracts the offset value from the second intermediate address and outputs it, which becomes the read address to the memory means 630.

  The memory means 630 outputs the converted address value held at the input read address. The adder 640 adds the output from the memory means 630 and the offset value, and outputs the addition result as an output address. The output address output from the look-up table unit 600 as described above is an address output to the memory controller 13 in order to access the memory 14 in which data to be interleaved is stored.

  Since the initial address generation unit 300, the first address conversion unit 100, the second address conversion unit 200, and the lookup table unit 600 are connected in series, processing can be continuously performed in a pipeline manner. It is. Therefore, as long as the initial address is continuously output from the initial address generation means 300, the interleave device 510 of this embodiment can output the output address continuously, and the same effect as in the first embodiment. Can be obtained.

  In the present embodiment, the lookup table unit 600 is additionally provided, so that even when interleaving using a table is combined, the number of accesses to the memory can be reduced to one. Therefore, by using this configuration, the circuit scale can be reduced as compared with the case where all input / output patterns are stored in the memory and only one memory access is completed using the patterns. That is, even when interleaving using a table is used, the same effects as those of the first and second embodiments can be obtained.

(Application example of the third embodiment for actual communication)
Hereinafter, as an application example of the interleave apparatus 510 for actual communication, a case where the interleave apparatus 510 is applied to frequency interleaving processing of ISDB-T will be described. As described above, the frequency interleaving of ISDB-T is a single interleaving by combining three different processes of inter-segment interleaving, intra-segment carrier rotation, and intra-segment carrier randomization.

  At this time, in the interleaving apparatus 510 according to the present embodiment, the first address conversion unit 100 corresponds to inter-segment interleaving processing, and the second address conversion unit 200 corresponds to intra-segment carrier rotation. The look-up table unit 600 corresponds to intra-segment carrier randomization. Further, the initial address increases sequentially by 1 in the range of 0 to N-1.

  The parameter here is the interleave block size N = 384 × 12 = 4608. Further, frequency interleaving is performed on the mode 3 synchronous modulation section. At this time, an inter-segment interleave address generation formula is expressed by the following equation (6). The address generation formula for intra-segment carrier rotation is expressed by the following equation (7). Regarding intra-segment carrier randomization, a table is used, so there is no particular generation formula.

[Equation 6]

[Equation 7]

  Here, the first to fourth settings performed from the host CPU 20 via the setting controller 12 are first the third settings to the initial address generating means 400. The multiplexer 430 selects the input on the N-ary counter 410 side. (N = 4608). The first to seventh initial setting values i1 to i7 set in the first initial setting value holding unit 110 in the first setting to the first address conversion unit 100 are (i1, i2, i3, i4, i5, i6, i7) = (0, 0, 1, 12, 384, 12, 1).

  Further, in the second setting to the second address conversion unit 200, the eighth to fourteenth initial setting values i8 to i14 set in the second initial setting value holding unit 210 are (i8, i9, i10, i11, i12, i13, i14) = (0, 1, 384, 384, 1, 384, 384).

  Further, the adder / subtractor 124 of the first calculation means 120 is set to perform (addition, addition, addition) on the three inputs. Similarly, the adder / subtracter 224 of the third calculation means 220 is set to perform (addition, addition, addition) on the three inputs. Then, an input / output pattern of an address for one segment (= 384 carriers) is input and stored in the memory means 630 by the fourth setting in the lookup table unit 600. The initial address is input in order from 0 to 4607 without excess or deficiency.

  At this time, the first address conversion unit 100 performs address conversion based on the input initial address and the first to seventh initial setting values i1 to i7 set based on the first setting, The intermediate address of is output. The second address conversion unit performs address conversion based on the first intermediate address and the eighth to fourteenth initial setting values i8 to i14 set based on the second setting, The intermediate address of is output.

  The offset value output from the offset output unit 610 of the lookup table unit 600 increases by 384 once every time the second intermediate address is input 384 times into the lookup table unit. As described above, address generation for frequency interleaving of ISDB-T can be performed.

  In the prior art, in order to perform the same frequency interleaving, a memory capable of storing input / output patterns for at least the total number of subcarriers (= 4608) is required. On the other hand, the interleave device 510 of this embodiment only needs to be able to store an input / output pattern for one segment (= 384 carriers). That is, since the capacity of the memory means 630 can be reduced to 1/12, as a result, the circuit scale can be reduced.

  As described above, in the present embodiment, the same effects as those in the first and second embodiments can be obtained even in the case where interleaving using a table is used. Further, by performing address conversion using a combination of small tables, even when a plurality of processes are combined to form one interleave, only one memory access can be performed. Therefore, the circuit scale can be reduced as compared with the case where only one memory access is performed using the memory.

  Here, the operation example in which the address conversion circuit 511 is applied to the interleave device 510 has been described. However, the address conversion circuit 511 is applied to the deinterleave device by changing the supply destination of the generated output address to either the read / write address port. You can also. For example, if the address conversion circuit 511 supplies a write address to the memory 14 when interleaving is changed to supply a read address, the same address conversion circuit 11 is used for deinterleaving. be able to.

  Since the address conversion circuit 511 rearranges the addresses based on a predetermined rule, it can be applied to any device other than the interleave device as long as it rearranges the data.

  The present invention has been described with reference to the specific embodiments shown in the drawings. However, the present invention is not limited to the embodiments shown in the drawings, and any known hitherto provided that the effects of the present invention are achieved. Even if it is a structure, it is employable.

  Regarding the embodiment described above, the main points of the new technical contents are summarized as follows. In addition, although part or all of the said embodiment is summarized as follows as a novel technique, this invention is not necessarily limited to this.

(Supplementary Note 1) Memory that temporarily stores input data, address conversion circuit that performs interleaving on the address at which the data is stored in the memory, and host device for the address conversion circuit An interleaving device comprising: a setting controller for giving a setting given from a memory controller; and a memory controller for outputting the data stored at an address subjected to the interleaving process on the memory,
The address conversion circuit is
A first address conversion unit that outputs an intermediate address obtained by performing a process according to a first setting given by the setting controller on the input initial address;
A second address conversion unit that outputs to the memory controller an output address obtained by performing processing corresponding to the second setting given by the setting controller to the intermediate address, thereby An interleaving apparatus configured to execute one continuous interleaving process.

(Supplementary Note 2) The first address conversion unit includes:
First initial setting value holding means for storing a plurality of initial setting values given by the first setting;
First calculating means for calculating the initial address and the initial setting value according to an operation rule given by the first setting;
A second calculating means for calculating the initial address and the initial set value according to a predetermined calculation rule;
A first adder that adds the outputs from the first and second arithmetic means and outputs the result as the intermediate address;
The second address conversion unit is
Second initial setting value holding means for storing a plurality of initial setting values given by the second setting;
Third computing means for computing the intermediate address and the initial set value according to a computation rule given by the second setting;
A fourth computing means for computing the intermediate address and the initial set value according to a predetermined computation rule;
The interleave apparatus according to appendix 1, further comprising: a second adder that adds outputs from the third and fourth arithmetic means and outputs the result as the output address.

(Supplementary Note 3) The first calculation means of the first address conversion unit calculates the initial address and the first to fifth initial setting values stored in the first initial setting value holding means. Operate according to the operation rules given by the first setting,
The second calculation means calculates the initial address and the sixth and seventh initial setting values stored in the first initial setting value holding means according to a predetermined calculation rule,
The third calculation means of the second address conversion unit sets the second setting to the initial address and the eighth to twelfth initial setting values stored in the second initial setting value holding means. Operate according to the operation rules given by
The fourth calculation means calculates the initial address and the thirteenth and fourteenth initial set values stored in the second initial set value holding means according to a predetermined calculation rule. The interleaving apparatus according to appendix 2.

の式で示される演算によって前記中間アドレスに変換し、
前記第８ないし第１４の初期設定値を各々ｉ８〜ｉ１４とし、前記中間アドレスおよび出力アドレスを各々ｆｘおよびｇｘとすると、前記第２のアドレス変換部は前記中間アドレスを

の式で示される演算によって前記出力アドレスに変換することを特徴とする、付記３に記載のインタリーブ装置。 (Supplementary Note 4) When the first to seventh initial setting values are i1 to i7 and the initial address and the intermediate address are x and fx, respectively, the first address conversion unit sets the initial address to

Is converted into the intermediate address by an operation represented by the formula:
Assuming that the eighth to fourteenth initial setting values are i8 to i14 and the intermediate address and output address are fx and gx, respectively, the second address conversion unit sets the intermediate address to

4. The interleaving apparatus according to appendix 3, wherein the interleaving device converts the output address by an operation represented by the following formula.

(Supplementary Note 5) The address conversion circuit generates a random number or a count value corresponding to a block size related to the interleaving process according to a third setting given by the setting controller, and uses this as the initial address. The interleaving apparatus according to appendix 1, further comprising an initial address generation unit for outputting.

(Supplementary Note 6) The initial address generation unit
Random number generating means for generating the random numbers that do not overlap for each process within the block size range;
A counter that generates a count value obtained by changing the value by 1 for each process within the block size range;
The interleave apparatus according to appendix 5, further comprising a multiplexer that selects and outputs one of the generated random number or count value in accordance with the third setting.

(Additional remark 7) The address conversion circuit converts the output address into a final output address according to the fourth setting given by the setting controller, and outputs it to the memory controller. The interleaving device according to claim 5, further comprising:

(Supplementary Note 8) The lookup table section is
Offset output means for outputting an offset value that increases for each processing count given in the fourth setting;
A subtractor that outputs a value obtained by subtracting the offset value output from the offset output means from the output address;
Memory means for storing a value given by the setting controller and outputting a value stored at an address corresponding to the value output from the subtractor;
The interleaving device according to claim 7, further comprising: an adder that adds the value output from the memory unit and the value output from the offset output unit and outputs the result as the final output address. .

(Supplementary note 9) A memory for temporarily storing input data, an address conversion circuit for performing interleaving on the address at which the data is stored in the memory, and a host device for the address conversion circuit An interleaving device comprising a setting controller for giving a setting given from a memory controller for inputting and outputting the data on the memory;
The setting controller gives first and second settings to the first and second address conversion units of the address conversion circuit, respectively;
The memory controller stores the input data in the memory and inputs an address on the memory where the data is stored as an initial address to the address conversion circuit,
The first address conversion unit outputs an intermediate address obtained by performing processing according to the first setting on the initial address;
The second address conversion unit outputs an output address obtained by performing processing according to the second setting on the intermediate address to the memory controller;
The address conversion method, wherein the memory controller outputs data stored at the output address on the memory.

(Additional remark 10) Memory which memorize | stores the input data temporarily, The address conversion circuit which performs the process of interleaving with respect to the address where the said data was memorize | stored on the said memory, High-order apparatus with respect to the said address conversion circuit An interleaving device comprising a setting controller for giving a setting given from a memory controller for inputting and outputting the data on the memory;
A computer provided in the interleave device,
A procedure for giving first and second settings to the first and second address conversion units of the address conversion circuit, respectively;
A procedure for storing the input data in the memory and inputting an address on the memory in which the data is stored to the address conversion circuit as an initial address;
A procedure for outputting an intermediate address obtained by performing processing according to the first setting for the initial address;
And an address conversion program for causing the memory controller to execute an output address obtained by performing processing corresponding to the second setting on the intermediate address.

  The present invention is generally applicable to an apparatus that rearranges data, but is particularly suitable for an apparatus that performs interleaving / deinterleaving processing. In particular, fields that should be compatible with multiple communication systems while achieving both high-speed communication and downsizing, low cost, and low power consumption of devices, such as mobile phone terminals, smart phone terminals, or terrestrial digital TV broadcast reception Suitable for machines.

10, 310, 510 Interleave device 11, 311, 511 Address conversion circuit 12 Setting controller 13 Memory controller 14 Memory 15 Initial address generation circuit 20 Host CPU
DESCRIPTION OF SYMBOLS 100 1st address conversion part 110 1st initial setting value holding means 120 1st calculating means 121, 126, 133, 221, 226, 233 Multipliers 122, 131, 222, 231 Dividers 123, 132, 223, 232 Floor calculator 124, 224 Adder / Subtractor 125, 225 Remainder calculator 130 Second calculation means 140, 240 Adder 200 Second address conversion unit 210 Second initial set value holding means 220 Third calculation means 230 Second 4 arithmetic means 400 initial address generation section 410 N-ary counter 420 random number generation means 430 multiplexer 600 lookup table section 610 offset output means 620 subtractor 630 memory means 640 adder

Claims (10)

A memory that temporarily stores input data, an address conversion circuit that performs an interleaving process on an address at which the data is stored on the memory, and an address conversion circuit that is supplied from a host device. An interleaving device comprising: a setting controller that gives a setting; and a memory controller that outputs the data stored in the address subjected to the interleaving process on the memory,
The address conversion circuit is
A first address conversion unit that outputs an intermediate address obtained by performing a process according to a first setting given by the setting controller on the input initial address;
A second address conversion unit that outputs to the memory controller an output address obtained by performing processing corresponding to the second setting given by the setting controller to the intermediate address, thereby An interleaving apparatus configured to execute one continuous interleaving process. The first address conversion unit includes:
First initial setting value holding means for storing a plurality of initial setting values given by the first setting;
First calculating means for calculating the initial address and the initial setting value according to an operation rule given by the first setting;
A second calculating means for calculating the initial address and the initial set value according to a predetermined calculation rule;
A first adder that adds the outputs from the first and second arithmetic means and outputs the result as the intermediate address;
The second address conversion unit is
Second initial setting value holding means for storing a plurality of initial setting values given by the second setting;
Third computing means for computing the intermediate address and the initial set value according to a computation rule given by the second setting;
A fourth computing means for computing the intermediate address and the initial set value according to a predetermined computation rule;
The interleaving apparatus according to claim 1, further comprising: a second adder that adds outputs from the third and fourth arithmetic means and outputs the result as the output address. The first calculation means of the first address conversion unit sets the first setting to the initial address and the first to fifth initial setting values stored in the first initial setting value holding means. Operate according to the operation rules given by
The second calculation means calculates the initial address and the sixth and seventh initial setting values stored in the first initial setting value holding means according to a predetermined calculation rule,
The third calculation means of the second address conversion unit sets the second setting to the initial address and the eighth to twelfth initial setting values stored in the second initial setting value holding means. Operate according to the operation rules given by
The fourth calculation means calculates the initial address and the thirteenth and fourteenth initial set values stored in the second initial set value holding means according to a predetermined calculation rule. The interleaving device according to claim 2. Assuming that the first to seventh initial setting values are i1 to i7 and the initial address and intermediate address are x and fx, respectively, the first address conversion unit sets the initial address to

Is converted into the intermediate address by an operation represented by the formula:
Assuming that the eighth to fourteenth initial setting values are i8 to i14 and the intermediate address and output address are fx and gx, respectively, the second address conversion unit sets the intermediate address to

4. The interleaving apparatus according to claim 3, wherein the interleaving apparatus converts the output address by an operation represented by the following formula.   An initial address in which the address conversion circuit generates a random number or a count value according to a block size related to the interleaving process according to a third setting given by the setting controller and outputs this as the initial address The interleaving apparatus according to claim 1, further comprising a generation unit. The initial address generation unit
Random number generating means for generating the random numbers that do not overlap for each process within the block size range;
A counter that generates a count value obtained by changing the value by 1 for each process within the block size range;
6. The interleaving apparatus according to claim 5, further comprising a multiplexer that selects and outputs one of the generated random number or count value in accordance with the third setting.   The address conversion circuit includes a lookup table unit that converts the output address into a final output address according to a fourth setting given by the setting controller and outputs the final output address to the memory controller. 6. Interleaving device according to claim 5, characterized in that The lookup table unit is
Offset output means for outputting an offset value that increases for each processing count given in the fourth setting;
A subtractor that outputs a value obtained by subtracting the offset value output from the offset output means from the output address;
Memory means for storing a value given by the setting controller and outputting a value stored at an address corresponding to the value output from the subtractor;
The interleave according to claim 7, further comprising an adder that adds the value output from the memory means and the value output from the offset output means and outputs the result as the final output address. apparatus. A memory that temporarily stores input data, an address conversion circuit that performs an interleaving process on an address at which the data is stored on the memory, and an address conversion circuit that is supplied from a host device. In an interleaving apparatus comprising a setting controller for giving a setting and a memory controller for inputting and outputting the data on the memory,
The setting controller gives first and second settings to the first and second address conversion units of the address conversion circuit, respectively;
The memory controller stores the input data in the memory and inputs an address on the memory where the data is stored as an initial address to the address conversion circuit,
The first address conversion unit outputs an intermediate address obtained by performing processing according to the first setting on the initial address;
The second address conversion unit outputs an output address obtained by performing processing according to the second setting on the intermediate address to the memory controller;
The address conversion method, wherein the memory controller outputs data stored at the output address on the memory. A memory that temporarily stores input data, an address conversion circuit that performs an interleaving process on an address at which the data is stored on the memory, and an address conversion circuit that is supplied from a host device. In an interleaving apparatus comprising a setting controller for giving a setting and a memory controller for inputting and outputting the data on the memory,
A computer provided in the interleave device,
A procedure for giving first and second settings to the first and second address conversion units of the address conversion circuit, respectively;
A procedure for storing the input data in the memory and inputting an address on the memory in which the data is stored to the address conversion circuit as an initial address;
A procedure for outputting an intermediate address obtained by performing processing according to the first setting for the initial address;
And an address conversion program for causing the memory controller to execute an output address obtained by performing processing corresponding to the second setting on the intermediate address.

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