JP2013110312A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in device characteristics, which reduces writing/reading failures by preventing an increase in contact resistance between a capacitor and a contact pad.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: forming a tungsten film 8b; forming a lower electrode 13 formed of a titanium nitride film on the tungsten film 8b; oxidizing the titanium nitride film by heat-treating the titanium nitride film under an oxidizing atmosphere; forming a capacitance insulating film 14 on the lower electrode 13; and forming an upper electrode 15 on the capacitance insulating film 14.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, DRAM (Dynamic Random Access Memory) has been used as a main memory of a personal computer. DRAM has a basic cell structure of 1Tr. A one-capacitor structure is employed, and the capacitor side has a structure of capacitor-contact pad-capacitance contact plug-diffusion layer-memory cell transistor. In this structure, information is stored depending on the presence or absence of charge in the capacitor.

  In order to ensure the stable operation and reliability of the DRAM, a certain capacity of the capacitor is required. However, as the miniaturization of semiconductor elements progresses, the area corresponding to 1 bit is reduced, and the area for arranging capacitors is also reduced. For this reason, the gate lengths of the memory cell transistors are short, and the contact pads and capacitor contact plugs connecting them are also small.

Therefore, in order to ensure a high capacitor capacity, a method for increasing the surface area of the electrode and a development of a low EOT (equivalent oxide film thickness) film are being promoted. As a method for increasing the surface area of the electrode, as disclosed in Patent Documents 1 and 2 (Japanese Patent Laid-Open Nos. 07-7084 and 2003-142605), research on a capacitor having a high aspect ratio crown structure has progressed. It is out. In addition, as a low EOT film, an oxide film of an IV group or V group element or a film in which these oxide films are stacked is also being developed. In particular, as a low EOT film, first, a crystalline film of zirconium oxide (ZrO ₂ ) is formed, and then a thin film of alumina (Al ₂ O ₃ ) and several layers of zirconium oxide (ZrO ₂ ) are laminated. EOT = 0.8 nm can be achieved and is attracting attention.

Japanese Patent Application Laid-Open No. 07-7084 JP 2003-142605 A

  The lower electrode of the capacitor is connected to the source or drain region of the memory cell transistor via a capacitive contact plug under the contact pad. Titanium nitride is used for the lower electrode, and tungsten is used for the contact pad in order to reduce the contact resistance with titanium nitride.

  Two problems have occurred in the capacitor using the lower electrode made of titanium nitride on the tungsten film as described above.

  The first problem is that, in this semiconductor memory device, when an oxide film is used as a capacitor insulating film, oxygen atoms are converted into a titanium nitride film (as shown in FIG. 22A) when the capacitor insulating film (oxide film) 14 is formed. Diffusion to the tungsten film 21 through the grain boundary of the lower electrode 13a. Thereby, the surface of the tungsten film 21 is oxidized, and a portion where the contact resistance is increased is generated.

  The second problem is that, as shown in FIG. 22B, due to the difference in expansion coefficient between the titanium nitride film 13a and the tungsten film 21, heat applied in the steps after the formation of the capacitive insulating film 14 causes the titanium nitride film 13a. Is peeled off from the tungsten film 21, and the contact resistance between the titanium nitride film 13a and the tungsten film 21 is increased. The occurrence of peeling, which is the second problem, is accelerated by oxidation of the surface of the tungsten film 21, which is the first problem.

  When the contact resistance increases, the time for reading and writing to the capacitor becomes longer, which causes a write / read failure. As a result, the device characteristics are lowered, and the yield is lowered.

One embodiment is:
Forming a tungsten film;
Forming a lower electrode made of a titanium nitride film on the tungsten film;
Oxidizing the titanium nitride film by performing a heat treatment on the titanium nitride film in an oxidizing atmosphere;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode on the capacitive insulating film;
The present invention relates to a method for manufacturing a semiconductor device having

  This prevents an increase in contact resistance between the lower electrode of the capacitor and the tungsten film, and reduces writing / reading defects. As a result, a semiconductor device having excellent device characteristics is provided. In addition, the yield can be improved.

FIG. 6 is a plan view illustrating a method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the first example. It is sectional drawing explaining the problem of the conventional semiconductor device. FIG. 6 is a plan view illustrating a method for manufacturing the semiconductor device of the first embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these examples.

(First embodiment)
The present embodiment relates to a method of manufacturing a semiconductor device having a DRAM (Dynamic Random Access Memory), which will be described with reference to FIGS. 1 and 23 are plan views schematically showing the main structure, and a part of the structure is omitted. 2 to 21, the A diagram corresponds to the AA ′ section of FIGS. 1 and 23, and the B diagram corresponds to the BB ′ section of FIG. 1.

  First, as shown in FIG. 2, an element isolation region 2 having a depth of 250 nm is formed in the peripheral circuit region X and the memory cell region Y of the semiconductor substrate 50 by the STI (Shallow Trench Isolation) method, respectively, and the memory cell region X In addition, active regions 32 and 32 'partitioned by the element isolation region 2 are provided in the peripheral circuit region Y, respectively. Boron (B), which is a p-type impurity, phosphorus (P), and arsenic (As), which are n-type impurities, are required in the active regions 32 and 32 ′ for performance adjustment of transistors provided in the active regions 32 and 32 ′. Inject at the required concentration and depth.

When the impurity implantation region is switched for each of the active regions 32 and 32 ′, the implantation region is switched by a step of providing a pattern of a photoresist (not shown) having an opening on the active region where the target impurity is to be implanted. Then, the step of injecting the target impurity and the step of removing the photoresist pattern are repeated. After the impurity implantation, annealing is performed at 1000 ° C. for 10 seconds in an N ₂ atmosphere to activate the impurity.

  As shown in FIG. 3, after completing the implantation of impurities into the active regions 32 and 32 ', a silicon oxide film is formed on the surface of the semiconductor substrate 50 by thermal oxidation. Thereafter, in order to prevent boron (B) leakage from the gate electrode, the silicon oxide film is doped with nitrogen to form the silicon oxynitride film 24. At this time, the silicon oxynitride film 24 in the peripheral circuit region X becomes a gate oxide film in the peripheral circuit region X in a later step. A polysilicon film 29 is formed on the entire surface of the semiconductor substrate 50 by a CVD (Chemical Vapor Deposition) method. The polysilicon film 29 is formed to a thickness of about 20 nm in a non-doped state without introducing impurities.

As shown in FIG. 4, after the formation of the polysilicon film 29, a photoresist (not shown) covering the peripheral circuit region X is formed, and boron (p-type impurity) is formed in the active region 32 of the memory cell region Y. B) or indium (In) ions are implanted. At this time, the impurity concentration in the active region 32 is set to a low concentration so as not to exceed 1 × 10 ¹⁸ atoms / cm ³ . Further, the source and drain regions 4 are formed on the surface of the active region 32 in the memory cell region Y. The source and drain regions 4 are formed to have an impurity concentration of 1 × 10 ¹⁸ atoms / cm ³ by implanting phosphorus (P) or arsenic (As) as impurities into the active region 32. The source and drain regions 4 will be the source and drain regions of the buried gate type MOS transistor in a later step, and the capacitor contact plug 34 and the bit line 25 are connected thereto, respectively.

After the impurity is implanted into the active region 32, the polysilicon film 29 in the memory cell region Y is removed by using a dry etching technique using the photoresist as a mask. Thereafter, annealing is performed at 1000 ° C. for 10 s in an N ₂ atmosphere to activate the impurities. Further, a hard mask 41 is formed to a thickness of about 60 nm using a CVD method. An example of the hard mask 41 is a silicon nitride film. Next, by using a lithography technique, a photoresist pattern (not shown) having a line / space pattern is formed on the memory cell region Y while covering the entire peripheral circuit region X. The photoresist is composed of a line pattern that crosses the longitudinal direction of the active region 32. In this embodiment, the width of the photoresist space is 50 nm.

  In the memory cell region Y, a photoresist pattern is transferred to a hard mask by a dry etching method to form a hard mask pattern 41. After that, the hard mask pattern 41 is used to form a plurality of element isolation regions 2 and a plurality of active regions 32. A trench 40 is formed to communicate with each other. The trench 40 is formed to have a width of 50 nm and a depth of 150 nm. At this time, the photoresist is also removed. In this embodiment, it is preferable to form the trench 40 so that the width is 25 to 60 nm. If the thickness is smaller than 25 nm, a space for forming tungsten in the trench 40 cannot be secured in a later process. If the thickness is larger than 60 nm, the characteristics of the semiconductor device do not depend on the resistance of tungsten embedded in the trench 40. is there. Moreover, it is preferable to form so that the depth of the trench 40 may be 100-200 nm. If the thickness is smaller than 100 nm, a space for forming the cap insulating film 23 to be formed on tungsten in a later process cannot be secured, and if the thickness is larger than 200 nm, the depth becomes equal to the depth of the element isolation region 2 and the element isolation characteristics deteriorate. is there.

  As shown in FIG. 5, the surface of the semiconductor substrate 50 exposed as the inner surface of the trench 40 is thermally oxidized to form a cell gate oxide film 45 a made of a silicon oxide film having a thickness of about 5 nm on the inner surface of the trench 40. Thereafter, a barrier film 45b made of a titanium nitride film having a thickness of 5 nm is formed on the entire surface of the semiconductor substrate 50 by a CVD method. Subsequently, a tungsten film 45c is formed on the entire surface of the semiconductor substrate 50 by a SFD (Sequential Flow Deposition) method with a film thickness that allows the trench 40 to be completely buried. In the SFD method, crystal nuclei are formed by an ALD method in which, in the first nucleation step, a cycle including a step of alternately supplying a source gas and a reducing gas is performed one or more times. Thereafter, in a film forming process performed continuously, a tungsten film 45c is formed by performing crystal growth using a crystal nucleus as a seed by a CVD method in which a source gas and a reducing gas are simultaneously supplied. Specifically, the following steps (1) to (4) correspond to a nucleation step, and the following step (5) corresponds to a film formation step. The number of cycles of the SFD method and other conditions are determined according to the desired film thickness of the tungsten film 45c.

(1) A step of adsorbing a tungsten raw material on the surface of the barrier film 45b by supplying a tungsten fluoride (WF ₆ ) gas;
(2) purging tungsten fluoride (WF ₆ ) gas;
(3) a step of reducing tungsten raw material adsorbed on the surface of the barrier film 45b by supplying monosilane (SiH ₄ ) gas to form tungsten crystal nuclei;
(4) purging monosilane (SiH ₄ ) gas;
(5) A step of forming a tungsten film 45c by simultaneously supplying tungsten fluoride (WF ₆ ) gas and hydrogen gas.

  In this example, after the tungsten nuclei were formed by performing five cycles of the above steps (1) to (4), the tungsten film 45c was formed in the step (5), and the tungsten film 45c having a total thickness of 60 nm was formed. A film was formed. Since the SFD method is excellent in step coverage, a trench having a high aspect ratio (depth / width) such as the trench 40 can be completely filled with the tungsten film 45c. Preferably, the tungsten film 45c is formed in the trench 40 having an aspect ratio of 10 or less by the SFD method. In this embodiment, the width of the trench 40 is 50 nm and the depth is 150 nm. Since the gate oxide film 45a having a thickness of 5 nm and the barrier film 45b having a thickness of 5 nm are formed before the formation of the tungsten film 45c, the remaining space has a width of about 30 nm and a depth of about 140 nm. Therefore, the aspect ratio is about 4.7.

  Next, the tungsten film 45c and the barrier film 45b are etched back. This etch back is performed by a dry etching method using chlorine-containing plasma. In this etch back, the upper surfaces of the etched back barrier film 45b and tungsten film 45c are formed so as to be 60 nm lower than the upper surface of the semiconductor substrate 50. As a result, the cell gate oxide film 45a remains in the trench 40, and the buried tungsten film 45c and barrier film 45b also remain, thereby forming the buried gate electrode 20. The buried gate electrode 20 forms a word wiring in the DRAM. In this case, the word line 20 includes a barrier film 45b formed along the inner surface of the trench 40 via the cell gate oxide film 45a, and a tungsten film 45c embedded in the barrier film 45b. In addition, the word wiring 20 has a configuration including a cap insulating film 23 (formed in the next step) in contact with the upper surface of the tungsten film 45c and the two upper surfaces of the barrier film 45b.

A silicon nitride film 21a for the purpose of preventing the oxidation of the word wiring 20 is formed on the entire surface of the hard mask 40 by CVD so as to have a thickness of about 10 nm. Thereafter, a BPSG (Boron Phosphorus Silicon Glass) film 21b, which is a silicon oxide film containing a large amount of boron and phosphorus and reflowing at a high temperature, is formed on the entire surface of the semiconductor substrate 50 to a thickness of about 500 nm. Further, heat treatment is performed at 800 ° C. for 10 minutes in an N ₂ atmosphere to fill the upper surface of the word wiring 20. After performing CMP (Chemical Mechanical Polishing) using the silicon nitride film 21a as a stopper to planarize the surface of the BPSG film 21b, the silicon nitride film 21a and the hard mask are combined with a dry etching technique and a wet etching technique. 41 is removed. More specifically, the hard mask 41 and the silicon nitride film 21a are present on the surface of the semiconductor substrate 50 in a total of about 70 nm. Therefore, first, the silicon nitride films 21a and 41 are etched back to about half the film thickness using a dry etching technique. Then, the silicon nitride films 21a and 41 on the surface of the semiconductor substrate 50 are removed while adjusting the time by a wet etching technique using hot phosphoric acid. Thereby, the cap insulating film 23 which is a laminated film of the silicon nitride film 21a and the BPSG film 21b shown in FIG. 5 is formed.

  As described above, in the memory cell region Y, the MOS transistor Tr having the embedded gate electrode 20 in one active region 32 is completed. The MOS transistor Tr is composed of a buried gate electrode 20 composed of a cell gate oxide film 45a, a titanium nitride film 45b and a tungsten film 45c, and a source and drain 4a (second impurity diffusion layer) and 4b (first impurity diffusion layer). The In this embodiment, two MOS transistors Tr are formed in one active region, and the source region 4b is shared between the two transistors Tr. Note that if the bias application state is reversed, the source region and the drain region are interchanged.

  As shown in FIG. 6, a silicon oxide film 31 is formed to a thickness of about 30 nm on the entire surface of the semiconductor substrate 50 by the CVD method.

  As shown in FIG. 7, a photoresist (not shown) that covers the entire memory cell region Y and opens the peripheral circuit region X is formed. Thereafter, the silicon oxide film 31 in the peripheral circuit region X is removed by a dry etching technique using a photoresist as a mask. Thereafter, the photoresist is removed.

  Next, a photoresist (not shown) having a pattern is formed on the memory cell region Y while covering the entire peripheral circuit region X. This pattern is formed in a linear pattern across a plurality of active regions 32 so as to expose the source region (first impurity diffusion layer) 4b. A part of the silicon oxide film 31 is removed by etching using a photoresist as a mask to expose the surface of the semiconductor substrate 50. Thereafter, the photoresist is removed. This hole in which the surface of the semiconductor substrate 50 is exposed is referred to as a bit contact hole 19.

As shown in FIG. 8, a non-doped polysilicon film 43 having a thickness of 50 nm is sequentially formed on the entire surface of the semiconductor substrate 50 by CVD. At this time, since the non-doped polysilicon film 29 is formed in advance in the peripheral circuit region X, the polysilicon films 29 and 43 having a thickness larger than that of the memory cell region Y in total with the polysilicon film 43 are formed. The Next, the polysilicon film 43 is planarized by CMP processing or the like. Using the lithography technique, phosphorus (P), boron (B), etc. are respectively formed in the polysilicon films 29 and 43 that are part of the gate electrodes of the P channel MOS transistor and the N channel MOS transistor in the peripheral circuit region X. Implant impurities. At this time, impurities are also implanted into the polysilicon film 43 that becomes a part of the bit line in the memory cell region Y. After the impurity implantation, activation annealing is performed in an N ₂ atmosphere, and then a tungsten laminated film 33 having a total thickness of 40 nm is formed. The tungsten stacked film 33 is formed by sequentially stacking tungsten silicide (WSi), tungsten nitride film (WN), and tungsten (W).

  Further, a silicon nitride film 27 having a thickness of 160 nm (hereinafter, a film in which films 43, 33, and 27 are stacked may be referred to as a “stacked body”) is formed. As a barrier film between the polysilicon film 43 and the tungsten film, a titanium nitride film may be formed instead of the tungsten nitride film.

  As shown in FIG. 9, the polysilicon film 29 and the stacked body are etched using a lithography technique to form the bit line 25 made of the stacked body in the memory cell region Y. At the same time, in the peripheral circuit region X, a polysilicon film 29 and a gate electrode 26 for a planar type MOS transistor made of a laminate are formed. At this time, a bit contact plug 19 ′ connected to the source region 4b is also formed at the same time. In this embodiment, the width of the bit line 25 in the extending direction of the buried gate electrode is 50 nm.

  A silicon nitride film is formed on the entire surface, and then etched back by a dry etching method. As a result, sidewalls 44 are formed on the sidewalls of the bit line 25 and the gate electrode 26. A semiconductor substrate located on both sides of the gate electrode 26 by ion implantation of n-type impurities such as phosphorus and arsenic into the peripheral circuit region X in a state where the memory cell region Y is covered with a photoresist (not shown). The source and drain regions 28 are formed in the regions. Thus, a planar type MOS transistor is completed. Thereafter, the photoresist formed on the memory cell region Y is removed.

  As shown in FIG. 10, a first interlayer insulating film 5 having a thickness of 400 nm is formed on the entire surface of the semiconductor substrate 50. Thereafter, the surface of the first interlayer insulating film 5 is planarized by a CMP method using the silicon nitride film 27 as a stopper. Using the lithography technique and the dry etching technique, a capacitor contact hole 37a that penetrates the first interlayer insulating film 5 and the silicon oxynitride film 24 in the memory cell region Y and reaches the drain region 4a is formed. After the formation of the capacitor contact hole 37a, the photoresist is removed. The diameter of the capacitor contact hole 37a is 50 nm.

A silicon film 36 containing phosphorus of 1 × 10 ²⁰ atoms / cm ³ is formed on the entire surface of the semiconductor substrate 50 by CVD so that the capacitor contact hole 37a is completely buried. Next, the silicon film 36 is etched back by dry etching to leave about 80 nm from the bottom in the capacitor contact hole 37a. Note that after the non-doped silicon film is formed, impurities may be introduced into the silicon film by an ion implantation method. It can also be formed by selective epitaxial growth.

  Next, a peripheral contact hole 37b that penetrates the first interlayer insulating film 5 and the gate insulating film 24 and reaches the source and drain regions 28 is formed in the peripheral circuit region X by using a lithography technique and a dry etching technique. After the capacitor contact hole 37a and the peripheral contact hole 37b are formed, a titanium film (Ti) and a titanium nitride film (TiN) are sequentially formed as a barrier film on the entire surface, and then a tungsten film (W) is formed by a CVD method. 10 and the subsequent drawings, the boundaries of the titanium film (Ti), the titanium nitride film (TiN), and the tungsten film (W) are not shown, and these films are collectively shown as a tungsten laminated film 38. After the tungsten laminated film 38 is formed, the tungsten laminated film 38 on the surface of the first interlayer insulating film 5 is removed by CMP, and then a part of the first interlayer insulating film 5 and the silicon nitride film 27 is formed. Grind. In this polishing, the silicon nitride film 27 is set to a remaining condition of about 50 nm. Thus, the peripheral contact plug 7 embedded with the tungsten multilayer film and the capacitive contact plug 34 embedded with the silicon film and the tungsten multilayer film are formed.

  As shown in FIG. 11, after a tungsten film is formed on the first interlayer insulating film 5 by sputtering, a photoresist (FIG. 11) is formed on the wiring formation portion in the peripheral circuit region X and the contact pad formation portion in the memory cell region Y. (Not shown). Etching the tungsten film using a photoresist as a mask connects the contact pad 8b and the source and drain regions 28 of the peripheral circuit region X on the contact plug 34 connected to the drain region 4a of the memory cell region Y. A wiring layer 8 a is formed on the contact plug 7. By forming the contact pad 8b in this way, the contact resistance with the lower electrode formed thereon can be reduced as compared with the case where the lower electrode is formed on the silicon film. Next, a silicon nitride film 9 is formed on the entire surface of the first interlayer insulating film 5 and on the wiring layer 8a and the contact pad 8b by using the ALD method. Depending on the configuration of the device, the contact pad 8b is not provided, and the tungsten film on the capacitor contact plug 34 or the contact plug 34 made of a tungsten film is directly formed, and the lower electrode (later process) is directly formed on the tungsten film. May be formed).

  As shown in FIG. 12, a BPSG film 10a and a silicon oxide film 10b are sequentially formed on the silicon nitride film 9 by plasma CVD using TEOS (Tetra Ethyl Ortho Silicate) as a source gas. After forming the BPSG film 10a and the silicon film oxide 10b, the films 10a and 10b are planarized by the CMP method. Next, a silicon nitride film 11 is formed on the silicon oxide film 10b by ALD. The silicon nitride film 11 functions as a support film that prevents the lower electrode of the capacitor to be formed in a later process from collapsing.

  As shown in FIG. 13, a photoresist (not shown) having a capacitor opening in the memory cell region Y and a guard ring opening at the boundary between the peripheral circuit region X and the memory cell region Y is formed. The insulating films 11, 10b, 10a and 9 are dry-etched using a photoresist as a mask. As a result, a capacitor hole 12a is formed in the memory cell region Y, and the contact pad 8b is exposed on the bottom surface thereof. A guard ring trench 12b is formed at the boundary between the peripheral circuit region X and the memory cell region Y. The capacitor hole 12a has a cylindrical shape with a substantially circular cross section, and the guard ring trench 12b is formed so as to surround the memory cell region Y in a square shape. At this time, since the capacitor hole 12a has a high aspect ratio, the capacitor hole 12a has a bow shape with a large cross-sectional diameter at the center in the depth direction and a small cross-sectional diameter at the top and bottom.

As shown in FIG. 14, the BPSG film 10a and the silicon oxide film 10b are wet-etched also for cleaning after dry etching. Thereby, in the capacitor hole 12a, the difference in cross-sectional diameter between the central portion in the depth direction, the top portion, and the bottom portion is reduced, and the bowing shape is brought closer to a straight shape. Thus, by making the capacitor hole 12a close to a straight shape, it is possible to increase the capacitance C _s of the capacitor formed in a later process. That is, since the interlayer insulating film 10a is a BPSG film and the interlayer insulating film 10b is a TEOS film, the interlayer insulating film 10a can be formed on the 10b so as to increase the etching rate in the step of FIG. As a result, the capacitor hole 12a can be made closer to the straight shape from the bowing shape. Diluted hydrofluoric acid (HF) or ammonia water (NH ₄ OH) is used as a chemical solution for wet etching.

As shown in FIG. 15, a titanium film is formed on the entire surface by CVD. Immediately thereafter, plasma nitridation using ammonia (NH ₃ ) gas is performed to convert the titanium film into a titanium nitride film. Further, a titanium nitride film is formed thereon by SFD (Sequential Flow Deposition) method. In this SFD method, TiCl ₄ gas and ammonia (NH ₃ ) gas are alternately supplied to deposit and nitride the raw material layer. As a result, a total of about 15 nm of titanium nitride 13 is formed. Since the above SFD method is superior in step coverage (coverage) than the CVD method, the titanium nitride film 13 can be formed even on the inner wall of a high aspect ratio hole such as the capacitor hole 12a. it can.

From the viewpoint of achieving both miniaturization and reduction of the context resistance, the contact area of the lower electrode 13 (titanium nitride film) and the contact pad 8b (tungsten film) ≦ {(film thickness of the lower electrode 13) × 3} ² . It is preferable. Table 1 below shows the dimensions of the lower electrode 13 (titanium nitride film) used in each process.

  As shown in Table 1, as the miniaturization progresses and the size of each part decreases, the contact area between the contact pad 8b or contact plug of the tungsten film and the lower electrode 13 decreases, and the increase in contact resistance becomes significant. However, in this embodiment, even when the miniaturization progresses as described above, a titanium oxide film 35 described later is formed on the lower electrode 13 by heat treatment in an oxidizing atmosphere, as will be described later. The titanium oxide film 35 functions as an oxygen barrier when the capacitive insulating film 14 is formed. For this reason, it is possible to prevent the contact resistance between the tungsten film 8b and the lower electrode 13 from increasing due to an adverse effect on the tungsten film 8b due to the diffusion of oxygen from the capacitive insulating film 14. As a result, a semiconductor device having excellent device characteristics can be provided. In addition, the yield can be improved. As shown in Table 1, in this example, when the diameter of the lower electrode 13 is 60 nm or less, the height of the lower electrode 13 is 1.6 μm or less, and the film thickness of the lower electrode 13 is 15 nm or less, the contact resistance increases. The effect of preventing this appears particularly remarkably.

  As shown in FIG. 16, a 200 nm silicon nitride film 42 is formed on the entire surface by plasma CVD. Since the silicon nitride film 42 is formed under conditions with poor coverage, it does not enter the capacitor holes 12a and 12b. The silicon nitride film 42 is formed for the purpose of preventing the photoresist from entering the capacitor hole 12a when a photoresist for forming an opening in the support film 11 is formed in a later step.

  As shown in FIG. 17, a photoresist (not shown) is formed on the silicon nitride film 42, and the photoresist is patterned by a lithography technique. Using the photoresist as a mask, the silicon nitride film 42, the support film 11 and the titanium nitride film 13 are dry-etched, and openings 30 for wet etching of the interlayer insulating films 10a and 10b are formed in the support film 11. FIG. 1 is a plan view schematically showing a state after the opening 30 is formed. The openings 30 are provided on the plurality of capacitor holes 12a.

  After removing the photoresist, the silicon nitride film 42 is removed by etch back. Subsequently, the titanium nitride film 13 on the support film 11 is removed by anisotropic etch back, and the lower electrode 13 is formed on the inner wall of the capacitor hole 12a.

  As shown in FIG. 18, the interlayer insulating films 10a and 10b in the memory cell region Y are removed by wet etching using hydrofluoric acid (HF). At this time, since the peripheral circuit region X is divided by the memory cell region Y and the guard ring trench 12b, the HF aqueous solution does not enter the peripheral circuit region X during wet etching, and the interlayer in the peripheral circuit region X The insulating films 10a and 10b are not removed.

As shown in FIG. 19, a 1 nm thin titanium oxide (TiO ₂ ) film 35 is formed on the titanium nitride film by performing a heat treatment on the titanium nitride film at 220 ° C. for about 30 minutes in an atmosphere of ozone (O ₃ ). Form. The thickness of the titanium oxide (TiO ₂ ) film 35 is preferably 0.5 to 1.5 nm.

As shown in FIG. 20, an amorphous zirconium oxide (ZrO ₂ ) film having a film thickness of 5.2 nm is formed on the entire surface by ALD method set at a temperature of 220 ° C. In this ALD method, Zr [N (C ₂ H ₅ ) (CH ₃ )] ₄ (TEMAZ; tetrakis-ethylmethyl-zirconium) gas as a source gas, oxygen (O ₂ ) gas or ozone (O ₃ ) as an oxidizing gas By alternately supplying the gas, the raw material layer is deposited and oxidized. In addition to TEMAZ, the source gases include Zr (O-tBu) ₄ , Zr [N (CH ₃ ) ₂ ] ₄ , Zr [N (C ₂ H ₅ ) ₂ ] ₄ , Zr (TMHD) ₄ , Zr (OiC). Those containing any one selected from the group consisting of ₃ H ₇ ) ₃ (TMTD) and Zr (OtBu) ₄ can be used.

Next, an aluminum oxide (Al ₂ O ₃ ) film having a thickness of 0.5 nm and a single atomic layer is formed on the entire surface by an ALD method set at a temperature of 220 ° C. In this ALD method, the source layer is deposited and oxidized by alternately supplying trimethylaluminum (TMA) gas as the source gas and oxygen (O ₂ ) gas or ozone (O ₃ ) gas as the oxidizing gas.

Subsequently, an amorphous zirconium oxide film and an aluminum oxide laminated film (LAZO film) having a film thickness of 1.5 nm are formed by an ALD method set at a temperature of 220 ° C. This LAZO film is composed of several layers of zirconium oxide (ZrO ₂ ) film using the same raw material gas, oxidizing gas and film forming method as the zirconium oxide (ZrO ₂ ) film and aluminum oxide (Al ₂ O ₃ ) film. The film is formed by repeating the process of forming several layers of aluminum oxide (Al ₂ O ₃ ) films several times. In FIG. 20 and subsequent drawings, the first formed zirconium oxide film and aluminum oxide film and the LAZO film are collectively indicated by reference numeral 14.

Thereafter, a titanium nitride film and an SiGe film doped with boron (B) are formed using a conventional manufacturing method, and a tungsten film is further formed thereon. Hereinafter, these films are collectively referred to as the upper electrode 15. The step of forming the upper electrode will be specifically described. First, a titanium nitride film having a thickness of 10 nm is formed on the entire surface by the SFD method. Thereafter, a SiGe film doped with boron (B) is formed with a thickness of 150 nm and a tungsten film is formed with a thickness of 100 nm by a CVD method. The heat treatment during the formation of this SiGe film causes the first formed film thickness of 5.2 nm to be amorphous zirconium oxide (ZrO ₂ ) film, but the amorphous film in the LAZO film The zirconium oxide film remains amorphous even by this heat treatment. In order to convert the zirconium oxide (ZrO ₂ ) film to crystalline by the heat treatment during the formation of the SiGe film, the thickness of the zirconium oxide (ZrO ₂ ) film is preferably 4 to 5 nm. In order to keep the zirconium oxide (ZrO ₂ ) film amorphous during the above heat treatment, the thickness of the zirconium oxide (ZrO ₂ ) film is preferably 0.3 to 0.5 nm.

After the upper electrode 15 is formed, a photoresist (not shown) is patterned into the shape of a capacitor plate, and then the upper electrode 15, the capacitor insulating film 14, and the support film 11 are dry-etched using the photoresist as a mask. As a result, these films are left only in the memory cell region Y. As a result, a capacitor having the capacitor structure is formed on the inner wall surface and the outer wall side surface of the lower electrode 13, and a capacitor having a crown structure in which the upper electrode 15 is formed on the capacitor insulating film 14 is completed. With capacitor having such a structure, it is possible to increase the contact area of the electrodes 13 and 15 and the capacitor insulating film 14 to increase the capacitance C _s. Finally, the photoresist is removed.

  In this embodiment, a crystalline zirconium oxide film / aluminum oxide film / amorphous zirconium oxide film and a laminated film of aluminum oxide (LAZO film) are used as the capacitor insulating film 14. The relative dielectric constants of the crystalline zirconium oxide film and the LAZO film are about 45 and 25, respectively. Therefore, by using a crystalline zirconium oxide film having a large relative dielectric constant, the EOT of the entire capacitor insulating film 14 can be reduced to 0.8 nm or less, and the capacitor capacity can be increased.

  In the step of FIG. 19, a titanium oxide film 35 is formed on the lower electrode 13 made of a titanium nitride film by heat treatment in an oxidizing atmosphere. Since the titanium oxide film 35 functions as a barrier for oxygen atoms, oxygen in the zirconium oxide film diffuses in the titanium nitride film 13 even when the zirconium oxide film is formed in the step of FIG. It is possible to prevent reaching the contact pad 8b of the tungsten film located below. As a result, it is possible to prevent the contact resistance from being increased due to oxidation of the surface of the tungsten film 8b.

  Further, during the heat treatment after the capacitor insulating film 14 is formed, peeling of the titanium nitride film 13 from the tungsten film 8b is remarkable due to a difference in expansion coefficient between the titanium nitride film as the lower electrode 13 and the tungsten film as the contact pad 8b. Can also be prevented. That is, such peeling becomes remarkable when the surface of the tungsten film 8b is oxidized. However, in this embodiment, since the oxidation of the surface of the tungsten film 8b is prevented as described above, the peeling is promoted. Can be prevented.

  As a result, the contact resistance between the contact pad 8b and the lower electrode 13 can be prevented from increasing. In addition, it is possible to provide a semiconductor device in which writing / reading failure due to an increase in contact resistance is prevented and device characteristics are excellent. In the present embodiment, the incidence of defective products can be reduced to 1/3 of the conventional one, and the yield can be improved.

  As shown in FIGS. 21 and 23, a silicon oxide film 10c is formed on the entire surface of the interlayer insulating film 10b by a CVD method. FIG. 21 shows an A-A ′ section and a B-B ′ section in FIG. 23. FIG. 23 shows only main structures such as the buried gate electrode 20, the active region 32, the bit line 25, and the capacitor contact plug 34 in the memory cell region Y. Further, the structures of the end portions of the buried gate electrode 20 and the bit line 25 in the memory cell region Y of FIG. 23 are schematically shown. After the contact hole 39 is formed so as to penetrate through the silicon oxide films 10a to 10c, a titanium nitride film and a tungsten film serving as a barrier film are formed on the entire surface by CVD. Further, by removing the titanium nitride film and the tungsten film on the surface of the silicon oxide film 10c by CMP, the contact plug 17 that connects the wiring layer 18 to be formed later and the wiring layer 8a is manufactured. Subsequently, an aluminum film to be the wiring layer 18 is formed on the silicon oxide film 10c. The aluminum film is patterned by the lithography technique and the etching technique to form the wiring layer 18. Further, by forming an upper layer contact plug and wiring (not shown), a DRAM having a plurality of memory cells each including a capacitor and a MOS transistor connected to the capacitor can be completed.

In this embodiment, the zirconium oxide film and the aluminum oxide film are formed as the capacitive insulating film 14 in the step of FIG. 20, but other oxide films may be used. Of the capacitive insulating film 14, as a film closest to the lower electrode 13, a strong oxide having a high dielectric constant and a high ionization tendency is formed, and oxygen atoms hardly diffuse into the tungsten film 8 b. It is preferable to use elemental oxide films. Examples of the oxide film of the group IV element include a hafnium oxide (HfO ₂ ) film and a titanium oxide (TiO ₂ ) film in addition to the zirconium oxide (ZrO ₂ ) film. When a titanium oxide film is used as the capacitor insulating film 14, the titanium oxide film 35 formed on the lower electrode 13 by heat treatment in an oxidizing atmosphere in the step of FIG. The titanium oxide film formed as the capacitor insulating film 14 in the process of FIG. 20 is formed for the purpose of holding charge for information recording, whereas it is formed for the purpose of preventing diffusion to the pad 8b. Is different. However, after the capacitor insulating film 14 is formed, the boundary between the two titanium oxide films may not be clearly identified.

  Further, it is preferable that the temperature for performing the heat treatment on the titanium nitride film 13a used as the lower electrode is 250 ° C. or lower, and the temperature for forming at least the capacitive insulating film formed on the titanium oxide film is 250 ° C. or lower. In addition, it is preferable that the processing temperature for performing the heat treatment on the titanium nitride film is equal to or higher than the processing temperature for forming the capacitive insulating film (preferably equal to or higher than the processing temperature for forming the capacitive insulating film).

(Second embodiment)
This embodiment differs from the first embodiment in the conditions for heat treatment in the process of FIG. Except for this point, the same steps as in the first embodiment are performed. In the following, the manufacturing method of this example will be described, but the description of the same steps as those of the first example will be omitted.

After performing the steps of FIGS. 1 to 18 of the first embodiment, as shown in FIG. 19, a thin titanium oxide film 35 is formed on the titanium nitride film 13 by performing a heat treatment in an atmosphere of ozone (O ₃ ). Form. In this example, unlike the first example, after heat treatment at 190 ° C. for 30 minutes, heat treatment at 220 ° C. is performed for 30 minutes.

  In this embodiment, the initial heat treatment temperature is 190 ° C., which is a milder condition than in the first embodiment, so that adverse effects on other elements can be reduced.

  Furthermore, the present invention is not limited to the invention described in the claims, and the present invention includes the following semiconductor devices.

1. A tungsten film;
A lower electrode made of a titanium nitride film on the tungsten film;
A first titanium oxide film on the lower electrode;
A capacitive insulating film on the first titanium oxide film;
An upper electrode on the capacitive insulating film;
A semiconductor device.

  2. 2. The semiconductor device according to 1 above, wherein the tungsten film constitutes part or all of a contact pad or contact plug.

3. Furthermore,
A transistor having a first impurity diffusion layer connected to the contact pad or the contact plug;
A bit line connected to a second impurity diffusion layer of the transistor;
3. The semiconductor device according to 2 above, comprising:

  4). 4. The semiconductor device according to any one of 1 to 3, wherein the capacitive insulating film includes an oxide film of a group IV element as the capacitive insulating film on the side closest to the lower electrode.

  5. 5. The semiconductor device according to 4 above, wherein the Group IV element oxide film is a hafnium oxide film, a zirconium oxide film, or a second titanium oxide film.

  6). The capacitor insulating film has a crystalline zirconium oxide film, an aluminum oxide film, and a laminated film of an amorphous zirconium oxide film and an aluminum oxide film in order from the closest to the lower electrode. The semiconductor device according to any one of the above.

  7). 7. The semiconductor device according to any one of 1 to 6, wherein the first titanium oxide film has a thickness of 0.5 to 1.5 nm.

  8). 8. The semiconductor device according to any one of 1 to 7, wherein a diameter of a portion of the lower electrode that is in contact with the tungsten film is 60 nm or less.

  9. 9. The semiconductor device according to any one of 1 to 8, wherein the lower electrode has a height of 1.6 nm or less.

  10. 10. The semiconductor device according to any one of 1 to 9 above, wherein the thickness of the lower electrode is 15 nm or less.

  11. 11. The semiconductor device according to any one of 1 to 10, wherein the capacitive insulating film is provided on an inner wall surface and an outer wall side surface of the lower electrode through the first titanium oxide film.

12 A plurality of the lower electrodes;
The semiconductor device according to any one of 1 to 11, further comprising a support film provided so as to be in contact with at least a part of an outer wall side surface of the lower electrode.

2 element isolation region 4 source and drain region 4a drain region 4b source region 5 first interlayer insulating film 7 peripheral contact plug 8a wiring layer 8b contact pad 9 silicon nitride film 10a BPSG film 10b silicon oxide film 10c silicon oxide film 11 support film 12a Capacitor hole 12b Guard ring trench 13a Titanium nitride film 14 Capacitance insulating film 15 Upper electrode 17 Contact plug 18 Wiring layer 19 Bit contact hole 19 'Bit contact plug 20 Embedded gate electrode 21a Silicon nitride film 21b SOD film 22 Photoresist 23 Cap insulating film 24 Silicon oxynitride film 25 Bit line 26 Gate electrode 27 Silicon nitride film 28 Source and drain region 29 Polysilicon film 30 Opening 31 Silicon nitride film 32 Active region ( (Memory cell area)
32 'active region (peripheral region)
33 Tungsten laminated film 34 Capacitor contact plug 35 Titanium oxide film 36 DOPOS film 37a Capacitor contact hole 37b Peripheral contact hole 38 Tungsten laminated film 39 Contact hole 40 Trench 41 Hard mask 42 Silicon nitride film 43 N-type impurity-containing polysilicon film 44 Side wall 45a Cell gate oxide film 45b Barrier film 45c Tungsten film 50 Semiconductor substrate Tr Transistor X Peripheral circuit area Y Memory cell area

Claims (16)

Forming a tungsten film;
Forming a lower electrode made of a titanium nitride film on the tungsten film;
Oxidizing the titanium nitride film by performing a heat treatment on the titanium nitride film in an oxidizing atmosphere;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode on the capacitive insulating film;
A method for manufacturing a semiconductor device comprising: In the step of forming the tungsten film,
The method of manufacturing a semiconductor device according to claim 1, wherein a contact pad or a contact plug having the tungsten film is formed. Before the step of forming the tungsten film,
Forming a transistor such that a first impurity diffusion layer is connected to the contact pad or the contact plug;
Forming a bit line to be connected to the second impurity diffusion layer of the transistor;
The manufacturing method of the semiconductor device of Claim 2 which has these. In the step of oxidizing the titanium nitride film,
The method for manufacturing a semiconductor device according to claim 1, wherein the titanium nitride film is heated to 250 ° C. or lower. In the step of oxidizing the titanium nitride film,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the titanium nitride film is oxidized by a plurality of heat treatments at different temperatures. 6. In the step of oxidizing the titanium nitride film,
The method for manufacturing a semiconductor device according to claim 1, wherein the titanium nitride film is oxidized in an atmosphere of ozone (O ₃ ). In the step of forming the capacitive insulating film,
The method for manufacturing a semiconductor device according to claim 1, wherein the capacitor insulating film is formed at a temperature of 250 ° C. or lower.   The method for manufacturing a semiconductor device according to claim 1, wherein a processing temperature in the step of oxidizing the titanium nitride film is equal to or higher than a processing temperature in the step of forming the capacitive insulating film. In the step of forming the capacitive insulating film,
9. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film of a group IV element is formed as at least the capacitive insulating film closest to the lower electrode.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the Group IV element oxide film is a hafnium oxide film, a zirconium oxide film, or a titanium oxide film. In the step of forming the capacitive insulating film,
A crystalline zirconium oxide film, an aluminum oxide film, and a laminated film of an amorphous zirconium oxide film and an aluminum oxide film are formed as the capacitive insulating film in order from the closest to the lower electrode. 11. A method for manufacturing a semiconductor device according to any one of 10 above. In the step of oxidizing the titanium nitride film,
The method for manufacturing a semiconductor device according to claim 1, wherein a titanium oxide film having a thickness of 0.5 to 1.5 nm is formed on a surface of the titanium nitride film. In the step of forming the lower electrode,
13. The method of manufacturing a semiconductor device according to claim 1, wherein the lower electrode is formed so that a diameter of a portion of the lower electrode in contact with the tungsten film is 60 nm or less. In the step of forming the lower electrode,
The method for manufacturing a semiconductor device according to claim 1, wherein the lower electrode is formed so that a height of the lower electrode is 1.6 μm or less. In the step of forming the lower electrode,
The method for manufacturing a semiconductor device according to claim 1, wherein the lower electrode is formed so that a film thickness of the lower electrode is 15 nm or less. Further, between the step of forming the tungsten film and the step of forming the lower electrode,
Forming an interlayer insulating film on the tungsten film;
Forming a support film on the interlayer insulating film;
Forming a capacitor hole so as to expose the tungsten film in the support film and the interlayer insulating film;
Have
In the step of forming the lower electrode,
Forming the lower electrode in the capacitor hole;
Further, between the step of forming the lower electrode and the step of forming the capacitive insulating film,
Providing an opening in the support film;
Exposing the outer wall side surface of the lower electrode by removing the interlayer insulating film using the support film as a mask; and
The manufacturing method of the semiconductor device of any one of Claims 1-15 which has these.