JP2013106475A - System connection inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized system connection inverter that prevents leakage current and high-frequency noise.SOLUTION: A system connection inverter includes: an inverter 1; a first capacitor pair 41 that is composed of capacitors connected in series on an input side of the inverter 1; a second capacitor pair 42 that is composed of capacitors connected in series on an output side of the inverter 1; a neutral-point connection line g that connects between a neutral point c of the first capacitor pair 41 and a neutral point f of the second capacitor pair 42; a coil 3 that is disposed between the first capacitor pair 41 and the second capacitor pair 42 and the input side of the inverter 1 or the output side of the inverter 1, and prevents a common-mode current generated in the inverter 1; and an output filter 2 having a low-pass filter configuration that converts a pulse-width-modulated voltage outputted from the inverter 1 into a sinusoidal AC voltage. The coil 3 includes a first winding 32a and a second winding 32b of each phase, and a core 31 in which the first winding 32a and the second winding 32b are wound adjacently.

Description

  Embodiments described herein relate generally to a grid interconnection inverter.

  In recent years, high-frequency switching has been progressing in grid-connected inverters that convert the output of a DC power source such as a photovoltaic power generation system or a fuel cell to AC and link it to the power system, and accompanying harmonic leakage current and electromagnetic noise. It is desired to suppress (EMI: Electro-Magnetic Interference).

  Leakage current and EMI may affect the control of the inverter and other devices, and may cause the leakage breaker to malfunction. In Japan, the allowable amount of leakage current is regulated by the Electrical Appliance and Material Safety Law, and EMI is regulated by VCCI (Voluntary Control Council for Information Technology Equipment). In particular, regarding EMI, in recent years, movements to tighten regulations have been accelerating.

JP 2010-119188 A

  For example, in a photovoltaic power generation system, stray capacitance exists between a solar cell panel and a frame of the solar cell panel connected to the ground, and this stray capacitance can be a path for high-frequency common mode noise. In general, an insulating layer made of a glass plate is formed on the surface of the solar cell panel, and since this glass plate has a relatively large plane, when it gets wet with rain, the stray capacitance between the solar cell panel and the frame increases. High frequency common mode current also increases.

  Common-mode high-frequency voltage fluctuations occur when the inverter converts direct current to alternating current by switching semiconductor elements. For this reason, in the inverter, leakage current and high frequency noise are problems that cannot be avoided.

  For example, when using a common mode choke coil that suppresses the common mode current flowing from the DC power source to the inverter, it is necessary to increase the core of the common mode choke coil to effectively suppress the common mode current. Greatly affects the volume of the common mode choke coil, which increases the size of the grid-connected inverter, restricting the installation location and increasing the cost.

  This invention is made | formed in view of the said situation, Comprising: It aims at providing the small grid connection inverter which suppresses a leakage current and a high frequency noise.

  According to the embodiment, an inverter that performs pulse width modulation on the output of a DC power supply, a first capacitor pair that is arranged on the input side of the inverter and connected in series so as to form a neutral point, and the inverter The second capacitor pair is disposed on the output side of the capacitor and connected to form a neutral point, and the neutral point of the first capacitor pair and the neutral point of the second capacitor pair are connected to each other. At least one common that suppresses a common mode current generated between the sex point connection line and the first capacitor pair and the second capacitor pair and that is disposed on the input side or output side of the inverter. A mode choke coil and a reactor for converting the pulse width modulated voltage output from the inverter into a sinusoidal single-phase or three-phase AC An output filter having a low-pass filter structure with a capacitor, and the common mode choke coil includes a first winding on the positive electrode side, a second winding on the negative electrode side, the first winding, and the second winding. There is provided a grid-connected inverter comprising a core wound in a state in which the wire is in close proximity.

FIG. 1 is a block diagram for explaining a configuration example of a grid-connected inverter according to the embodiment. FIG. 2 is a diagram for explaining a configuration example of the common mode choke coil of the grid interconnection inverter shown in FIG. 1. FIG. 3 is a block diagram for explaining another configuration example of the grid interconnection inverter of the embodiment. FIG. 4 is a block diagram for explaining another configuration example of the grid interconnection inverter of the embodiment. FIG. 5 is a diagram for explaining a configuration example of the common mode choke coil of the grid interconnection inverter shown in FIG. 4. FIG. 6 is a diagram illustrating an example of a PWM voltage waveform output when the inverter is driven by the three-level PWM control method. FIG. 7 is a diagram illustrating an example of a PWM voltage waveform output when the inverter is driven by the two-level PWM control method.

  Hereinafter, the grid interconnection inverter of embodiment is demonstrated with reference to drawings.

  FIG. 1 is a block diagram for explaining a configuration example of the grid interconnection inverter of the first embodiment. The grid-connected inverter of this embodiment is connected between a DC power source and a system transformer 7, and is composed of an inverter 1, an output filter 2, a common mode choke coil 3, and a first capacitor pair that are configured by semiconductor switching elements. 41, a second capacitor pair 42, a booster circuit 8, and a capacitor 9.

  The solar cell 5 corresponds to a DC power source in this embodiment and generates a DC voltage. The DC voltage generated by the solar cell 5 is supplied to the inverter 1 via the first capacitor pair 41, the common mode choke coil 3, and the DC line capacitor 9. In the present embodiment, the DC power source is not limited to a solar battery, and a fuel cell or other battery that generates a DC voltage can be used.

  The common mode choke coil 3 is provided on the input side of the inverter 1 and suppresses a common mode current flowing through the inverter 1.

  The inverter 1 is constituted by a bridge circuit made of a semiconductor switching element such as a field effect transistor (FET) or an insulated gate bipolar transistor (IGBT). The inverter 1 is driven by a two-level PWM control method or a three-level PWM control method.

  In the case of the three-level PWM control method, the DC voltage E supplied from the solar cell 5 has an amplitude that varies from + E to 0 or from 0 to −E as shown in FIG. It is converted into a PWM voltage having a pulse waveform that changes sequentially and sent to the output filter 2.

  In the case of the two-level PWM control system, the DC voltage supplied from the solar battery 5 has a pulse waveform having an amplitude that changes from + E to -E and a pulse width that changes sequentially as shown in FIG. Convert to signal and send to output filter.

  The output filter 2 has a reactor 21a whose input end is connected to one output terminal of the inverter 1, a reactor 21b whose input end is connected to the other output terminal of the inverter 1, an output end of the reactor 21a, and an output end of the reactor 21b. The capacitor 22 is connected between the two. The output filter 2 converts the PWM voltage sent from the inverter 1 into a sinusoidal AC voltage as shown by the broken lines in FIGS. 6 and 7 and sends it to the system transformer 7.

  The first capacitor pair 41 is configured by connecting a capacitor 41a and a capacitor 41b in series, and is disposed between the input terminals of the common mode choke coil 3 (between the output terminals of the solar cell 5) ab. A DC line positive voltage appears at point a, and a DC line negative voltage appears at point b. A DC line neutral point c is formed at a connection point between the capacitor 41a and the capacitor 41b. The DC line neutral point c is in the AC output of the second capacitor pair 42 described later by the neutral point connection line g. It is connected to the sex point f.

  The second capacitor pair 42 is configured by connecting a capacitor 42a and a capacitor 42b in series, and is disposed between the input terminals of the system transformer 7 (between the output terminals of the output filter 2) de. A sine wave AC (AC output voltage) appears between points d and e. An AC output neutral point f is formed at the connection point between the capacitors 42a and 42b. The AC output neutral point f is connected to the first capacitor pair 41 by the neutral point connection line g as described above. It is connected to the DC line neutral point c.

  The system transformer 7 transforms the sine wave alternating current supplied from the system interconnection inverter and connects it to the power system end h. The neutral point of the system transformer 7 is connected to the ground by a neutral point ground line i.

  In the grid-connected inverter configured as described above, a “leakage current path” is formed in which the common mode current flows through a path such as the neutral point ground line i → the ground → the stray capacitance 6 of the solar battery 5. The Further, a “bypass path” is formed in which a common mode current flows through a line such as the output of the inverter 1 → the second capacitor pair 42 → the neutral point connection line g → the first capacitor pair 41 → the input of the inverter 1. The bypass path of the common mode current has an impedance sufficiently smaller than the leakage current path at the frequency of the common mode current (equal to the switching frequency of the inverter 1), and the common mode choke coil 3 includes the leakage current path and the bypass path. Has a greater impedance.

  Therefore, most of the common mode current flows through the bypass path, and its magnitude is suppressed by the common mode choke coil 3. As a result, the leakage current that flows out of the grid interconnection inverter is suppressed.

  FIG. 2 schematically shows a configuration example of the common mode choke coil 3. The common mode choke coil 3 is a bifilar wound common mode choke coil. The common mode choke coil 3 of the present embodiment includes a winding of each phase and a core 31 wound in a state where the windings of each phase are close to each other. In the case shown in FIG. 2, the common mode choke coil 3 includes a core 31, a positive side winding (first winding) 32a, and a negative side winding (second winding) 32b. The positive winding 32a and the negative winding 32b are wound around the core 31 in a state of being brought close together. It is desirable that the pairs of the adjacent windings 32a and 32b are wound around the core 31 with a space between them in order to reduce the proximity effect and inter-winding capacitance.

  When a common mode current 34 flows through the common mode choke coil 3, a magnetic flux is generated in the core 31 as indicated by an arrow 33 and exhibits a strengthening inductance. However, when a normal mode current 35 flows, the magnetic flux cancels out. Does not occur and does not show inductance.

  When the normal mode current 35 flows through the common mode choke coil 3, the leakage magnetic fluxes 36a and 36b generated in the respective windings 32a and 32b are wound in a state where the two windings 32a and 32b are close to each other. , Cancel each other. Therefore, the leakage magnetic flux is smaller than when the two windings 32a and 32b are wound around different regions of the core 31, respectively. Since the leakage magnetic flux is reduced, the magnetic flux in the core 31 is also reduced, and the core 31 can be further downsized to reduce the size of the grid-connected inverter.

  In this way, in the circuit as shown in FIG. 6 in which leakage current and noise outflow are suppressed by the bypass path, the winding of the common mode choke coil 3 is wound by bringing the lines of each phase close together. The core 31 of the common mode choke coil 3 can be downsized, and the grid-connected inverter can be downsized.

  In particular, most grid-connected inverters of the photovoltaic power generation system include a booster circuit that adjusts the varying voltage to a constant value because the voltage of the solar cell that is the power source fluctuates. When the voltage of the solar cell is low, the booster circuit operates to increase the voltage, but the current flowing into the grid-connected inverter increases accordingly. Then, since the normal mode current flowing through the common mode choke coil 31 also increases, the generated leakage magnetic flux also increases. It is necessary to design the core large so that the core 31 of the common mode choke coil 3 is not magnetically saturated by the leakage magnetic flux. When the present invention is applied here, the magnetic flux leakage due to the normal mode current can be reduced, so that the core can be made smaller.

  FIG. 3 is a block diagram showing another example of the grid interconnection inverter of the above embodiment. In this grid-connected inverter, a common mode choke coil 3 is disposed between the inverter 1 and the output filter 2.

  Even in such a configuration, the leakage magnetic flux generated in the common mode choke coil 3 due to the normal mode current leads to an increase in the size of the core 31, so that the windings of the common mode choke coil 3 are connected to the wires of each phase as shown in FIG. By winding them close together, leakage magnetic flux can be reduced, the core 31 can be downsized, and the circuit can be downsized.

  That is, the common mode choke coil 3 may be disposed between the first capacitor pair 41 and the second capacitor pair 42. A plurality of inverters 1 may be arranged on both the input side and the output side. When there are a plurality of common mode choke coils 3, only a part of the common mode choke coils 3 may be wound as shown in FIG. 2, and all the common mode choke coils 3 are wound as shown in FIG. It may be how to wind the wire.

  Moreover, although the above-mentioned embodiment is an example applied to the single phase grid connection inverter, it is also applicable to a three phase grid connection inverter. When applied to a three-phase grid-connected inverter, the output side of the inverter 1 has a three-phase configuration. Accordingly, when the common mode choke coil 3 is arranged on the input side from the inverter 1, the winding of the common mode choke coil 3 is the same as in FIG. In the case of arranging the three-phase windings, the same effects as in the above-described embodiment can be obtained by winding three windings for three phases close together and winding them around the core 31.

  In this embodiment, the grid interconnection inverter includes the booster circuit 8, but the booster circuit 8 can be omitted. Even when the booster circuit 8 is omitted, the same effect as in the above embodiment can be obtained.

  Next, the grid interconnection inverter of 2nd Embodiment is demonstrated with reference to drawings. In the following description, the same components as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

  FIG. 4 is a block diagram for explaining a configuration example of the grid interconnection inverter of the second embodiment. The grid interconnection inverter of this embodiment is configured using a magnetically coupled reactor 21c instead of the reactors 21a and 21b constituting the output filter 2 of the grid interconnection inverter of the first embodiment. The magnetic coupling of the reactor 21c has a low impedance with respect to the common mode current and a high impedance with respect to the normal mode current.

  Reactor 21c exhibits inductance because the magnetic flux due to the normal mode current is combined, but cancels out the magnetic flux due to the common mode current and does not exhibit inductance. Therefore, compared with the case where a reactor is comprised separately like 21a and 21b, the magnetic flux by a common mode electric current can be reduced and the core of the reactor 21c can be reduced in size.

  Therefore, according to the present embodiment, the core 31 of the common mode choke coil 3 can be downsized, and the core of the reactor 21c can be downsized, so that the grid-connected inverter can be further downsized.

  In the grid-connected inverter of this embodiment, the common mode choke coil 3 may be located on the output side of the inverter 1 as in the first embodiment, or the input side and the output side of the inverter 1. A plurality of them may be arranged on both. Only some of the common mode choke coils 3 may be wound as shown in FIG. 2, or all may be wound as shown in FIG. Further, the grid interconnection inverter of the present embodiment can be transformed into a three-phase grid interconnection inverter, and the booster circuit 8 can be omitted.

  FIG. 5 is a diagram schematically illustrating a configuration example of the reactor 21c of the grid-connected inverter according to the present embodiment. The reactor 21c is a bifilar-wound normal mode coil. In the present embodiment, the reactor 21c includes windings of respective phases that are magnetically coupled to other phases, and a core around which these windings are wound. In the case illustrated in FIG. 5, the reactor 21 c includes a core 211 and coil windings 212 a and 212 b.

  The reactor 21c exhibits inductance because the magnetic flux 213 due to the normal mode current is combined as described above, but the magnetic flux due to the common mode current cancels out and does not exhibit inductance. In this case, ideally, there is no magnetic flux due to the common mode current 214 flowing through the reactor 21c, but actually, leakage magnetic fluxes 216a and 216b are generated, and accordingly, the core 211 of the reactor 21c has to be designed to be larger.

  However, as shown in FIG. 5, the windings 212 a and 212 b of the respective phases of the reactor 21 c are brought close together and wound around the core 211, so that the leakage magnetic fluxes 216 a and 216 b generated by the common mode current 214 cancel each other. The inner magnetic flux is reduced, and the core 211 can be downsized.

  The positive side winding 212a and the negative side winding 212b are wound around the core 211 in a close state, and at one end thereof, the winding 212a is connected to the inverter 1 and the winding 212b is connected to the system transformer 7, At the other end, the winding 212 a is connected to the system transformer 7, and the winding 212 b is connected to the inverter 1.

  Further, it is desirable that the pairs of the adjacent windings 212a and 212b are wound around the core 31 at an interval from each other because the proximity effect and inter-winding capacitance can be reduced.

  Thus, by winding the windings 212a and 212b of each phase together and winding them around the core 211, the leakage magnetic fluxes 216a and 216b generated by the common mode current 214 cancel each other, so the magnetic flux in the core 211 is reduced. The core 211 can be reduced in size.

  Therefore, according to this embodiment, since the core 31 of the common mode choke coil 3 can be reduced in size and the core of the reactor 21c can be reduced in size, the grid interconnection inverter can be further reduced in size.

  In the grid-connected inverter of the present embodiment, the common mode choke coil 3 may be located on the output side of the inverter as in the grid-connected inverter of the first embodiment described above. May be arranged on both the output side and the output side. Further, when a plurality of common mode choke coils 3 are arranged, the same effects as those of the above-described embodiment can be obtained if a part of the common mode choke coils 3 is wound as shown in FIG. Can do. Further, the grid interconnection inverter of the present embodiment can also be applied to a three-phase grid interconnection inverter as in the first embodiment, and the booster circuit 8 can be omitted.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  c: DC line neutral point, g: neutral point connection line, f: AC output neutral point, 1 ... inverter, 2 ... output filter, 21c ... reactor, 22 ... capacitor, 211 ... core, 212a ... winding ( Positive electrode side), 212b ... Winding (negative electrode side), 3 ... Common mode choke coil, 31 ... Core, 32a ... Winding (positive electrode side), 32b ... Winding (negative electrode side), 41 ... Capacitor pair, 41a ... Capacitor , 41b ... capacitor, 42 ... capacitor pair, 42a ... capacitor, 42b ... capacitor, 5 ... solar cell (DC power supply), 6 ... stray capacitance, 7 ... system transformer.

Claims (3)

An inverter that performs pulse width modulation on the output of the DC power supply;
A first capacitor pair arranged on the input side of the inverter and connected in series to form a neutral point; and
A second capacitor pair by a capacitor disposed on the output side of the inverter and connected to form a neutral point;
A neutral point connection line connecting the neutral point of the first capacitor pair and the neutral point of the second capacitor pair;
At least one common mode choke coil arranged between the first capacitor pair and the second capacitor pair and on the input side or output side of the inverter to suppress a common mode current generated in the inverter;
An output filter for converting the pulse width modulated voltage output from the inverter into a sinusoidal alternating current;
The common mode choke coil includes a winding of each phase and a core wound in a state where the windings of each phase are close to each other. The output filter has a low-pass filter including a reactor and a capacitor,
The reactor has a winding of each phase magnetically coupled to another phase, and a core around which the winding is wound,
The grid interconnection inverter according to claim 1, wherein the magnetic coupling of the windings is coupled so as to have a low impedance with respect to a common mode current and a high impedance with respect to a normal mode current.   3. The grid interconnection inverter according to claim 2, wherein the winding of the reactor is wound around the core in a state where the windings of the respective phases are brought close together.

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