JP2013105988A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a contact arrangement between wirings with an inter-wiring distance being shorter.SOLUTION: A semiconductor device of the embodiment includes first and second wirings, a first insulating film, a second insulating film, a first contact, and a second contact. The first and second wirings are formed in such a manner as they are parallel to each other on a substrate. The first insulating film is formed so as to cover the first and second wirings. The second insulating film is formed to extend to be parallel to the first and second wirings at a predetermined position between first and second control gate wires, and is different from the first insulating film in terms of material. The first contact is formed through the first insulating film positioned on the first wiring side relative to the second insulating film, between the first and second wirings. The second contact is formed through the first insulating film positioned on the second wiring side relative to the second insulating film, with the second contact and the first contact being displaced from each other along the extension direction of the first and second wirings, between the first and second wirings.

Description

  Embodiments described herein relate generally to a semiconductor device manufacturing method and a semiconductor device.

  In the development of semiconductor devices, particularly semiconductor memory devices, chip sizes are being reduced in order to achieve an increase in capacity and the like. For example, in a semiconductor memory device mounted with a floating gate structure such as a NAND flash memory device, the pitch size of the memory cell portion has been reduced. Conventionally, in order to reduce the chip size, the reduction of the pitch size of the memory cell portion has been regarded as important. However, in order to realize this demand for further reduction in the future, in the future, between adjacent blocks. Reduction between the select gates (wiring) facing each other is an indispensable item. Therefore, regarding the bit line contact disposed between the select gates, it is desired to reduce the pitch size between adjacent select gates. Regarding the reduction of the pitch between the bit lines, for example, a method of reducing the pitch between the bit lines by alternately arranging the holes for forming the bit line contacts in a staggered manner along the select gate has been studied.

  However, in the bit line contact that is shifted in the width dimension direction between the select gates as in the staggered arrangement, a plurality of holes are substantially arranged in the width size direction between the select gates. This increases the width between the select gates. For example, in a staggered bit line contact, in order to reduce the distance between the select gates, it is necessary to reduce the contact hole diameter or the distance between the contact holes (back to back).

  However, reduction of the contact hole diameter and reduction between the contact holes becomes very difficult for lithography. This is because if the hole diameter is too small, unopened holes are generated, and a problem that contact cannot be made occurs. Further, when the distance between the holes is reduced, the holes are brought too close to each other so that the positions of the openings are overlapped with each other, causing a problem that the contacts are short-circuited. As described above, it is important to reduce the hole diameter or the distance between holes in order to reduce the chip size, but since patterning has already been performed at the limit of resolution limit, as described above, unopened openings and openings Considering problems such as overlap, it is very difficult to reduce the size further by lithography technology.

JP 2002-313970 A

  An object of the present invention is to provide a semiconductor device that can overcome the above-described problems and can be formed with a smaller distance between wires in a contact arrangement between wires, and a method of manufacturing the same.

  The semiconductor device of the embodiment includes first and second wirings, a first insulating film, a second insulating film, a first contact, and a second contact. The first and second wirings are formed on the substrate so as to be parallel to each other. The first insulating film is formed so as to cover the first and second wirings. The second insulating film is formed to extend in parallel with the first and second wirings at a predetermined position between the first and second control gate lines, and is made of a material different from that of the first insulating film. The first contact is formed between the first wiring and the second wiring through the first insulating film located on the first wiring side with respect to the second insulating film. The second contact is formed on the second insulating film while being displaced from the first contact along the direction in which the first and second wirings extend between the first and second wirings. On the other hand, it is formed through the first insulating film located on the second wiring side.

It is a flowchart figure which shows the principal part process of the manufacturing method of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. It is a top view which shows an example of the arrangement configuration of the gate and active area in 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. 6A and 6B are a top view and a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. It is a top view which shows an example of the semiconductor device in which the bit line contact in 1st Embodiment was formed, and its comparative example. It is a flowchart figure which shows the principal part process of the manufacturing method of the semiconductor device in 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 2nd Embodiment. It is a figure which shows the 1 process cross section of the manufacturing method of the semiconductor device in 3rd Embodiment. It is a top view which shows an example of the semiconductor device in which the bit line contact in 3rd Embodiment was formed.

(First embodiment)
In the first embodiment, a method for manufacturing a nonvolatile NAND flash memory device will be described as an example of a semiconductor device. The first embodiment will be described below with reference to the drawings.

  FIG. 1 is a flowchart showing main steps of the semiconductor device manufacturing method according to the first embodiment. As shown in FIG. 1, in the method of manufacturing a semiconductor device according to the first embodiment, a gate formation step (S102) including an element isolation step, an ion implantation step (S104), a conformal insulating film A formation step (S106), Insulating film B forming step (S112), polishing step (S114), amorphous silicon (a-Si) film forming step (S116), resist pattern forming step (S118), hard mask forming step (S120), A series of steps such as a hole forming step (S122), a conductive material embedding step (S124), and a polishing step (S126) are performed.

  FIG. 2 is a process sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 2 shows from the gate formation step (S102) to the ion implantation step (S104) in FIG. Subsequent steps will be described later.

In FIG. 2A, as a gate formation step (S102), an insulating film 210 is first formed on the semiconductor substrate 200 with a film thickness of, for example, 2 to 20 nm. The insulating film 210 functions as a tunnel insulating film. The forming method is preferably formed by, for example, heat treatment (thermal oxidation treatment) in an oxygen atmosphere. As the insulating film 210, for example, a silicon oxide (SiO ₂ ) film is used. As the semiconductor substrate 200, for example, a p-type silicon substrate made of a silicon wafer having a diameter of 300 mm is used.

  Then, a polysilicon film 220 is formed to a thickness of, for example, 50 nm on the insulating film 210 by using, for example, a CVD method. The polysilicon film 220 functions as a charge storage layer (FG: floating gate). Then, a plurality of groove-shaped openings are formed from the polysilicon film 220 to the middle of the semiconductor substrate 200, and element isolation (not shown) is performed by filling the openings with an insulating film.

  Next, the insulating film 230 is formed with a film thickness of, for example, 2 to 20 nm on the polysilicon film 220 by using, for example, a CVD method. The insulating film 230 functions as an interelectrode insulating film.

  Then, a polysilicon film 240 is formed to a thickness of, for example, 50 nm on the insulating film 230 by using, for example, a CVD method. The polysilicon film 240 functions as a part of the control electrode (GC: control gate). Further, the metal film 250 is formed with a film thickness of, for example, 50 nm on the polysilicon film 240 by using, for example, a CVD method. The metal film 250 functions as the remaining part of the control electrode (GC: control gate). That is, the control electrode has a laminated structure in which the polysilicon film 240 and the metal film 250 are laminated. The laminated film of the polysilicon film 240 and the metal film 250 functions as a word line (an example of a wiring) in a memory element in a NAND flash memory device and as a select gate line (an example of a wiring) in a select gate.

  In FIG. 2B, openings 160, 162, and 164 having a groove structure are formed on both sides of the gate portion by a lithography process and a dry etching process (not shown), and a metal film 250, a polysilicon film 240, an insulating film 230, and a polysilicon film 220. Form in. An exposed metal film 250 and a polysilicon film 240 positioned under the exposed metal film 250 with respect to the semiconductor substrate 200 on which the resist film is formed on the metal film 250 through a lithography process such as a resist coating process and an exposure process (not shown) By removing the insulating film 230 and the polysilicon film 220 by anisotropic etching, the openings 160, 162, 164 can be formed substantially perpendicular to the surface of the semiconductor substrate 200. For example, as an example, the openings 160, 162, and 164 may be formed by a reactive ion etching method. In other words, the metal film 250, the polysilicon film 240, the insulating film 230, and the polysilicon film are etched by etching so that the metal film 250, the polysilicon film 240, the insulating film 230, and the polysilicon film 220 remain (exist) in the gate region. Openings 160, 162, and 164 penetrating through the silicon film 220 are formed. Each of the laminated films of the metal film 250, the polysilicon film 240, the insulating film 230, and the polysilicon film 220 arranged through the opening 164 corresponds to each cell of the NAND flash memory. For example, openings 154 having a width of 25 nm are formed with a pitch of 50 nm. As a result, 1: 1 gates 11a, 11b,... In which the width of the gate portion and the opening 164 are both 25 nm can be formed. Further, select gates 21 can be formed at the ends of the gates 11a, 11b,... Constituting one block. Similarly, 1: 1 gates 13a, 13b,... Can be formed in adjacent blocks. Further, select gates 23 can be formed at the ends of the gates 13a, 13b... Constituting the block. Between the blocks, the select gates 21 and 23 are formed in parallel with each other while having an opening 160 interval.

  Next, as an ion implantation step (S104), n-type impurities are ion-implanted into the surface of the p-type semiconductor substrate 200 on both sides of each gate portion to form an n-type semiconductor region. Such an n-type semiconductor region functions as a source / drain region. In addition, the p-type semiconductor region sandwiched between the n-type semiconductor regions functions as a channel region in which a gate region is formed above. Therefore, a region where the insulating film 210 on the bottom surface of the openings 160, 162, and 164 is exposed becomes a source portion or a drain portion. Here, a NAND string structure is formed in which a plurality of cells sharing one source portion and the other drain portion of adjacent cells are connected in series.

  FIG. 3 is a top view showing an example of an arrangement configuration of the gate and the active area in the first embodiment. In FIG. 3, the block A is formed on the left side of the select gate line 20 (first wiring) of the select gate 21 and the block B is formed on the right side of the select gate line 22 (second wiring) of the select gate 23. Thus, the select gate lines 20 and 22 are formed on the substrate so as to be parallel to each other.

  In the block A, word lines 10a, 10b... For each page are formed. Similarly, in the block B, word lines 12a, 12b... For each page are formed. One page is constituted by a plurality of memory cells connected to the same word line in one block. That is, a plurality of gates 11a are connected to the word line 10a toward the back side of the drawing, and a plurality of gates 11b are connected to the word line 10b toward the back side of the drawing. A plurality of gates 13a are connected to the word line 12a toward the back side of the drawing, and a plurality of gates 13b are connected to the word line 12b toward the back side of the drawing. Then, a plurality of active areas 30 (active regions) are formed in the direction perpendicular to the word lines, with the element isolation regions 32 interposed therebetween. The active area 30 becomes a source part or a drain part of each memory cell.

  A plurality of select gates 21 are arranged in the longitudinal direction of the select gate line 20 with the element isolation region 32 interposed therebetween. Similarly, a plurality of select gates 23 are arranged in the longitudinal direction of the select gate line 22 with the element isolation region 32 interposed therebetween. Then, for example, one bit line contact is formed on each active area 30 located between the select gate lines 20 and 22. Hereinafter, the process of forming the bit line contact will be described.

  FIG. 4 is a process sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 4 shows from the conformal insulating film A formation step (S106) to the polishing step (S114) in FIG. Subsequent steps will be described later.

4A, as the conformal insulating film A forming step (S106), each word line 10 including a gate and select gate lines 20 and 22 including a select gate are formed on a semiconductor substrate 202 including a tunnel insulating film. An insulating film 260 (insulating film A: first insulating film) is formed conformally so as to cover it. For example, it may be formed by a chemical vapor deposition (CVD) method. Here, the space between the select gate line 20 and the select gate line 22 is not filled completely, and the space 151 (recessed portion) is formed conformally between the select gate lines 20 and 22. The formation of the space 151 can be achieved by setting the film thickness of the insulating film 260 to a film thickness less than or equal to one half of the distance between the select gate lines 20 and 22 (the groove width of the opening 160). Thereby, a groove-shaped space 151 is formed along a direction parallel to the side surfaces of the select gate lines 20 and 22 (longitudinal direction in which the select gate lines 20 and 22 extend). As the insulating film 260, for example, a SiO ₂ film is suitable. The width of the space 151 is preferably 10 nm to 100 nm, for example.

  In FIG. 4B, as the insulating film B forming step (S112), the space 151 between the select gate lines 20 and 22 generated by forming the insulating film 260 conformally is embedded on the insulating film 260. An insulating film 262 (insulating film B: second insulating film) made of a material different from that of the insulating film 260 is formed. For example, it may be formed by a CVD method. As a material for the insulating film 262, a material having higher etching resistance than the material for the insulating film 260 may be used. In other words, as the material of the insulating film 260, a material having a higher etching selectivity than the material of the insulating film 262 may be used. As a material of the insulating film 262, for example, silicon nitride (SiN), amorphous silicon (a-Si), or the like is preferable. Here, for example, a SiN film is formed.

  In FIG. 4C, as the polishing step (S114), the insulating film 262 is polished and removed by using a chemical mechanical polishing (CMP) method until the insulating film 260 is exposed. In other words, the upper surface of the insulating film 262 is retracted until the excess insulating film 262 protruding from the space 151 is removed by polishing, so that the insulating film 260 is exposed. At that time, the insulating layer on the gate may be adjusted to a desired film thickness. Note that in order to recede the upper surface of the insulating film 262, etch back using a dry etching method may be performed.

  FIG. 5 is a process cross-sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 5 shows the amorphous silicon (a-Si) film forming step (S116) of FIG. Subsequent steps will be described later.

  In FIG. 5, as an amorphous silicon (a-Si) film forming step (S <b> 116), a serving as a hard mask material for forming a contact hole is formed on the exposed insulating film 260 and on the insulating film 262 embedded in the space 151. A Si film 270 is formed.

  Here, when the material of the insulating film 262 is a-Si, an SiN film may be used instead of the a-Si film 270.

  FIG. 6 shows a top view and a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 shows the resist pattern forming step (S118) of FIG. Subsequent steps will be described later.

  In FIG. 6B, as a resist pattern formation step (S118), first, after forming a resist film 280 on the a-Si film 270, bits arranged between the select gate lines 20 and 22 by using a lithography technique. A resist pattern in which a plurality of contact hole patterns 152 and 154 for line contact are opened is formed. As shown in FIG. 6A, here, a plurality of contact hole patterns 152a, 152b, 152c, 152d, 152e, zigzag on a plurality of active areas arranged along the longitudinal direction of the select gate lines 20, 22 are arranged. 152f, ..., 154a, 154b, 154c, 154d, 154e, 154f, ... are formed. The contact hole pattern 152 is formed on the active area along the select gate lines 20 and 22 and toward the select gate line 20 while skipping the active areas one by one. The contact hole pattern 154 is formed on the select gate line 20. , 22 and toward the select gate line 22 side, the contact hole pattern 152 is formed on the skipped active area. That is, the contact hole patterns 152 and 154 are formed in a staggered arrangement by being formed along the select gate lines 20 and 22 while shifting every other active area. In other words, in the contact hole patterns 152 and 154, one of the contact hole patterns 152 is positioned between two adjacent hole patterns of the plurality of contact hole patterns 154, and two adjacent contact hole patterns 152 are arranged. The positions are shifted from each other along the direction in which the select gate lines 20 and 22 extend so that one of the contact hole patterns 154 is located between the hole patterns.

  The contact hole pattern 152 is patterned at a position where the insulating film 262 overlaps a part of the contact hole pattern 152 (here, a part of the left side) as viewed from above. On the other hand, the contact hole pattern 154 is patterned at a position where the insulating film 262 overlaps a part of the contact hole pattern 154 (here, a part on the right side) as viewed from above.

  Here, elliptical patterns are shown as the contact hole patterns 152 and 154, but the contact hole patterns 152 and 154 are not limited to this, and may be circular, rectangular such as square or rectangular, and the like. Of course, other polygons may be used.

  FIG. 7 is a process sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 7 shows the hard mask formation step (S120) of FIG. Subsequent steps will be described later.

  In FIG. 7, as a hard mask formation step (S 120), the a-Si film 270 is etched using the formed resist pattern as a mask to form contact hole patterns 152 and 154 in the a-Si film 270. By this etching, a hard mask of the a-Si film 270 is formed, and the contact hole patterns 152 and 154 opened in the hard mask have a bottom diameter smaller than that of the upper surface, so that the contact hole diameter can be reduced. Therefore, even when exposure is performed with a pattern diameter at the resolution limit of lithography, the diameter of the bottom of the contact hole opened in the hard mask can be formed smaller than the diameter dimension at the resolution limit. For example, when the pattern diameter during exposure is 50 to 60 nm, the diameter of the bottom of the contact hole opened in the hard mask can be reduced to about 20 nm.

  FIG. 8 is a process cross-sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 8 shows from the hole forming step (S122) to the polishing step (S126) in FIG.

  8A, as a hole forming step (S122), etching using the a-Si film 270 having the contact hole patterns 152 and 154 opened as a hard mask is performed on the insulating film 260 and the select gate line in the insulating film 262. A contact hole 153 (first hole) in which one side surface on the 20 side is included in a part of the side wall, and a contact hole 155 (in which the other side surface on the select gate line 22 side in the insulating film 262 is included in a part of the side wall) A second hole). Here, a plurality of contact holes 153 (first holes) and a plurality of contact holes 155 (a first hole) and a plurality of contact holes 155 ( Second holes) are formed on the select gate line 20 (first wiring) and select gate line 22 (second wiring) side with respect to the insulating film 262 remaining in the space.

  Next, as a conductive material embedding step (S124), a conductive material is deposited so that the plurality of contact holes 153 and the plurality of contact holes 155 are embedded. As the conductive material, for example, polysilicon, aluminum (Al), tungsten (W), copper (Cu), or the like is suitable.

  Then, as shown in FIG. 8B, in the polishing step (S126), excess conductive material protruding from the contact holes 153 and 155 is removed by polishing using the CMP method, whereby staggered bit line contacts are arranged. 40 (first contact) and bit line contact 42 (second contact) are formed. In addition, the insulating film 262 comes into contact with the insulating film 260 at the bottom surface and both side surfaces at portions other than the portions that are in contact with the bit line contacts 40 and 42. In the subsequent process (not shown), bit lines (not shown) may be formed on the bit line contacts 40 and 42, respectively.

  FIG. 9 is a top view showing an example of the semiconductor device in which the bit line contact is formed in the first embodiment and a comparative example thereof. FIG. 9B shows a case where the bit line contact in the first embodiment is formed. In the first embodiment, the bit line contact 40 formed so as to penetrate through the insulating film between the select gate lines 20 and 22 contacts one of the both side surfaces (here, the right side surface) of the insulating film 262. To do. In addition, the bit line contact 42 formed so as to penetrate through the insulating film between the select gate lines 20 and 22 is in contact with the other of the both side surfaces (here, the left side surface) of the insulating film 262. Further, the bit line contacts 40 and 42 are arranged so as to be displaced from each other along the direction in which the select gate lines 20 and 22 extend.

  On the other hand, FIG. 9A shows a case where bit line contacts are formed by patterning contact holes for bit line contacts in a staggered arrangement without sandwiching the insulating film 262 therebetween. When patterning contact holes in a staggered arrangement without sandwiching the insulating film 262, if the actual back-to-back distance is too close, variations in the back-to-back distance and overlap between contact holes may occur, reducing the litho margin. Occur. Therefore, as shown in FIG. 9A, the distance D (back-to-back distance) between the adjacent bit line contacts 44 and 46 must be increased. For example, a back-to-back distance of about 60 nm is necessary to avoid such a problem. Further, if the hole diameter is reduced in order to reduce the distance D between the bit line contacts 44 and 46, an unopened hole may be formed and contact may not be possible. As a result, the select gate line distance L1 is increased.

On the other hand, in the first embodiment, as shown in FIG. 9B, an insulating film 262 disposed at a predetermined position between the select gate lines 20 and 22 is sandwiched between the insulating film 262 and the insulating film is insulated on both sides. By patterning the contact hole so that it partially overlaps with the film 262, the insulating film 262 that is not opened functions as a hole separation film, and even if the contact holes are brought as close as possible, adjacent contact holes are prevented from overlapping. it can. The contact holes may not be patterned so as to protrude from both sides of the insulating film 262. Thereby, the distance between the bit line contacts 40 and 42 can be reduced. Therefore, the distance between the bit line contacts 40 and 42 finally formed can be reduced to the width of the insulating film 262. For example, it can be about 10 nm. In addition, since a part of the opening area of the contact hole pattern is blocked by the insulating film 262, the diameter of the hole actually formed can be reduced. As a result, the distance L2 between the select gate lines 20 and 22 can be reduced. That is, the width between the select gates can be reduced.
Here, the case where both of the bit line contacts 40 and 42 are in contact with the insulating film 262 on both sides of the insulating film 262 is shown. However, the bit line contacts 40 and 42 are not aligned due to misalignment during patterning of the contact holes. At least one of them may be formed away from the insulating film 262. That is, the bit line contacts 40 and 42 formed through the insulating film between the select gate lines 20 and 22 do not protrude on both sides of the insulating film 262, and the select gates on the select gate lines 20 and 22 side with respect to the insulating film 262, respectively. It may be positioned so as not to contact the lines 20 and 22, and may or may not be in contact with the insulating film 262.

  As described above, according to the first embodiment, the inter-gate distance can be formed smaller in the contact arrangement between the gates. Therefore, the chip size can be reduced. As a result, even when a bit line contact having a pattern below the resolution limit is desired, it is possible to form a pattern without increasing the hole diameter or the distance between the holes.

(Second Embodiment)
In the first embodiment, the space 151 is formed between the select gate lines 20 and 22 by forming the insulating film 260 conformally, but the method of forming the space is not limited to this.

  FIG. 10 is a flowchart showing main steps of the semiconductor device manufacturing method according to the second embodiment. In FIG. 10, in the method of manufacturing the semiconductor device in the second embodiment, an insulating film A forming step (S108) and an opening forming step (S110) are added instead of the conformal insulating film A forming step (S106). Except for this point, the configuration is the same as that of FIG. In the following, the contents other than those specifically described are the same as those in the first embodiment.

  The process from the gate formation process (S102) including the element isolation process to the ion implantation process (S104) is the same as in the first embodiment.

  FIG. 11 is a process cross-sectional view of the semiconductor device manufacturing method according to the second embodiment. FIG. 11 shows from the insulating film A forming step (S108) to the insulating film B forming step (S112) in FIG.

In FIG. 11A, as the insulating film A forming step (S108), the word line 10 including the gate and the select gate lines 20 and 22 including the select gate are covered on the semiconductor substrate 202 including the tunnel insulating film. Then, an insulating film 260 (first insulating film) is formed. For example, it may be formed by a chemical vapor deposition (CVD) method. Here, the insulating film 260 is formed so as to be embedded between the select gate line 20 and the select gate line 22. As the insulating film 260, for example, a SiO ₂ film is suitable.

  In FIG. 11B, as an opening forming step (S110), a groove-like space 161 (groove or opening) is formed in the insulating film 260 at a position between the select gate lines 20 and 22 by a lithography method and an etching method (not shown). Example). Here, a groove parallel to the extending direction (longitudinal direction) of the select gate lines 20 and 22 is opened. Although the insulating film 260 is penetrated here, it may be kept halfway without being penetrated. The width of the space 161 is preferably 10 nm to 100 nm, for example.

  In FIG. 11C, as the insulating film B forming step (S112), an insulating film 262 (second insulating film) is formed on the insulating film 260 so as to fill the space 161 of the insulating film 260.

  FIG. 12 is a process cross-sectional view of the semiconductor device manufacturing method according to the second embodiment. FIG. 12 shows from the polishing step (S114) to the polishing step (S126) of FIG.

  Then, as in the first embodiment, as shown in FIG. 12A, the insulating film 262 is removed by polishing until the insulating film 260 is exposed as a polishing step (S114). Hereinafter, the same as in the first embodiment. By performing these steps, a staggered bit line contact 40 (first contact) and bit line contact 42 (second contact) are formed as shown in FIG.

  As described above, even when the space 161 for embedding the insulating film 262 is formed by etching as in the second embodiment, the same effect as in the first embodiment can be exhibited. In addition, the width of the space 161 can be easily adjusted by using a lithography method and an etching method.

(Third embodiment)
In the above-described embodiment, the contact holes are formed in the two-stage staggered arrangement in which the two arrangement positions are alternately arranged for each active area in the bit line direction. However, the present invention is not limited to this. The contact holes may be formed by repeatedly arranging the n positions (n> 2) with respect to the bit line direction while sequentially shifting the positions for each active area. The manufacturing method of the semiconductor device in the third embodiment is the same as that of the second embodiment described above except for the following points.

  FIG. 13 is a view corresponding to FIG. 12A showing a cross-sectional view of one step of the method of manufacturing the semiconductor device according to the third embodiment. In FIG. 13, between the select gate lines 20 and 22, insulating films 262 are arranged at a plurality of locations in parallel with the extending direction (longitudinal direction) of the select gate lines 20 and 22. In order to realize this, a plurality of spaces are formed when the spaces 161 are formed in the insulating film 260 between the select gate lines 20 and 22 in the opening forming step (S110). Then, in the insulating film B forming step (S112), the insulating film 262 is formed on the insulating film 260 so as to embed each space 161 of the insulating film 260.

  FIG. 14 is a top view showing an example of a semiconductor device in which the bit line contact is formed in the third embodiment. FIG. 14 shows an example in which bit line contacts 40, 42, and 44 are formed by opening a plurality of contact holes that are repeatedly arranged while sequentially shifting the arrangement positions of the three stages for each active area. . In the case of shifting to n positions (n> 2), the number of separation films may be one less than the number of arrangement positions. Here, insulating films 262a and 262b are formed as the separation films. ing.

  As described above, even in the case where a plurality of contact holes are formed by repeatedly arranging the n positions (n> 2) in the bit line direction while sequentially shifting the positions for each active area, the third implementation is performed. According to the embodiment, the distance between the contacts can be reduced in the contact arrangement between the gates, and as a result, the distance between the gates can be further reduced. Therefore, the chip size can be reduced.

  The embodiment has been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  In addition, the film thickness of each film and the size, shape, number, and the like of the opening can be appropriately selected from those required for semiconductor integrated circuits and various semiconductor elements.

  In addition, all semiconductor devices that include the elements of the present invention and whose design can be appropriately changed by those skilled in the art and methods for manufacturing the semiconductor devices are included in the scope of the present invention.

  Further, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques may be included.

20, 22 Select gate line, 21, 23 Select gate, 40, 42, 44 Bit line contact, 151, 161 space, 153, 155 contact hole, 260, 262 Insulating film

Claims (5)

Forming first and second wirings parallel to each other on a substrate;
Forming a first insulating film conformally so as to cover the first and second wirings;
Forming a second insulating film on the first insulating film so as to fill a hollow portion between the first and second wirings generated by forming the first insulating film conformally. When,
Retreating the upper surface of the second insulating film until the first insulating film is exposed;
The first insulating film is positioned on the first wiring side with respect to the second insulating film remaining in the recessed portion while being shifted from each other along the direction in which the first and second wirings extend. Forming a first hole located and a second hole located on the second wiring side with respect to the second insulating film remaining in the recessed portion;
Embedding a conductive material film in the first hole and the second hole;
A method for manufacturing a semiconductor device, comprising: Forming first and second wirings parallel to each other on a substrate;
Forming a first insulating film so as to cover the first and second wirings;
Forming a groove in the first insulating film at a position between the first and second wirings;
Forming a second insulating film in the trench;
The first wiring side with respect to the second insulating film formed in the groove while shifting the position of the first insulating film along the direction in which the first and second wirings extend. Forming a first hole located in the groove and a second hole located on the second wiring side with respect to the second insulating film formed in the groove;
Embedding a conductive material film in the first hole and the second hole;
A method for manufacturing a semiconductor device, comprising: The first wiring is one select gate line of two adjacent blocks in the NAND flash memory device,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second wiring is the other select gate line of the two blocks. First and second wirings formed on the substrate so as to be parallel to each other;
A first insulating film formed to cover the first and second wirings;
A second insulating film made of a material different from that of the first insulating film, formed to extend in parallel with the first and second wirings at a predetermined position between the first and second wirings;
A first contact formed between the first and second wirings through the first insulating film located on the first wiring side with respect to the second insulating film;
While the first contact and the second wiring are displaced from each other along the direction in which the first and second wirings extend, the second contact with respect to the second insulating film A second contact formed through the first insulating film located on the wiring side;
A semiconductor device comprising:   5. The second insulating film is disposed so as to fill a recessed portion formed in the first insulating film at the predetermined position between the first and second wirings. Semiconductor device.

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