JP2013105852A5

JP2013105852A5 -

Info

Publication number: JP2013105852A5
Application number: JP2011247912A
Authority: JP
Filing date: 2011-11-11
Publication date: 2014-12-18
Anticipated expiration: 2031-11-11

Claims

An oxide semiconductor layer over an insulating surface;
A gate insulating layer on the oxide semiconductor layer;
A first gate electrode layer provided on the gate insulating layer and having a region overlapping with the oxide semiconductor layer;
A second gate electrode layer provided on the gate insulating layer and having a region in contact with the first gate electrode layer;
A sidewall insulating layer on the second gate electrode layer;
An insulating layer on the gate insulating layer, on the first gate electrode layer, on the second gate electrode layer, and on the sidewall insulating layer;
A source electrode layer provided on the insulating layer and having a region in contact with the oxide semiconductor layer through a first opening provided in the insulating layer and the gate insulating layer;
A drain electrode layer provided on the insulating layer and having a region in contact with the oxide semiconductor layer through a second opening provided in the insulating layer and the gate insulating layer;
The oxide semiconductor layer includes a first region containing an impurity element, a second region containing the impurity element, and a channel formation region between the first region and the second region. And
The second gate electrode layer includes a region overlapping with the first region, a region overlapping with the second region, and a region in contact with a side surface of the first gate electrode layer in the channel length direction. And
The side wall insulating layer includes a region facing the side surface of the first gate electrode layer through the second gate electrode layer, and a top surface of the gate insulating layer through the second gate electrode layer. And a region facing the portion.

In claim 1 ,
A source wiring layer having a region in contact with the upper surface of the source electrode layer ;
A drain wiring layer having a region in contact with the upper surface of the drain electrode layer ,
In the channel length direction, distance between the source electrode layer and the drain electrode layer, wherein a smaller than the distance between the source wiring layer and the drain wiring layers.

In claim 1 or 2 ,
The film thickness of the region in contact with the first gate electrode layer of the gate insulating layer, wherein a greater than the thickness of the region in contact with the second gate electrode of the gate insulating layer.

In any one of Claims 1 thru | or 3 ,
2. The semiconductor device according to claim 1, wherein a thickness of a region of the gate insulating layer in contact with the second gate electrode layer is larger than a thickness of a region of the gate insulating layer in contact with the insulating layer.

In any one of Claims 1 thru | or 4 ,
It said sidewall insulating layer is a semiconductor device which comprises an oxynitride silicon down.

Forming an oxide semiconductor layer over the insulating surface;
The oxide semiconductor layer to form a gate insulating layer I covering,
On the gate insulating layer, forming the oxide semiconductor layer and a gate electrode layer having a heavy Naru region,
By introducing an impurity element before Symbol oxide semiconductor layer as a mask the gate electrode layer, a first region containing the impurity element in the oxide semiconductor layer, and a second area including the impurity element, Form the
Forming a conductive film on the gate insulating layer and the gate electrode layer;
Forming an insulating film on the conductive film;
The insulating film is etched, and forming a sidewall insulating layer on the conductive film,
Wherein the conductive film, I the row was etching mask sidewall insulating layer, a method for manufacturing a semiconductor device forming a second gate electrode layer.

Forming an oxide semiconductor layer over the insulating surface;
The oxide semiconductor layer to form a gate insulating layer I covering,
On the gate insulating layer, forming the oxide semiconductor layer and a gate electrode layer having a heavy Naru region,
By introducing an impurity element before Symbol oxide semiconductor layer as a mask the gate electrode layer, a first realm containing the impurity element in the oxide semiconductor layer, a second realm containing the impurity element And form,
Forming a first conductive film on the gate insulating layer and the gate electrode layer;
Forming an insulating film on the first conductive film;
The insulating film is etched to form a sidewall insulation layer on the first conductive film,
Wherein the first conductive film, I the row was etching mask sidewall insulating layer, forming a second gate electrode layer,
Forming an insulating layer on the gate insulating layer, on the first gate electrode layer, on the sidewall insulating layer, and on the second gate electrode layer;
Before Symbol insulating layer and by etching the gate insulating layer, forming a first opening reaching the first realm, and a second opening reaching the second realm, the,
Forming a second conductive film on the insulating layer so as to fill the first opening and the second opening;
And removing the second conductive film polishing treatment provided on the insulating layer I line to the second conductive film, wherein the first source electrode layer in the opening, the second in the opening a drain electrode layer, was formed,
A method for manufacturing a semiconductor device , comprising: forming a source wiring layer having a region in contact with the source electrode layer; and a drain wiring layer having a region in contact with the drain electrode layer .