JP2013102282A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has such a doubler as has a simple circuit configuration and ensures action of a comparator by resolving a problem caused by, for example, a variation of the delay time of a delay circuit.SOLUTION: The semiconductor device includes: a doubler 20 for comparing the phases of a delayed clock signal CLKD that is an input clock signal CLK delayed in a variable delay unit 16 and the input clock signal in a phase comparator 18 to generate a double clock signal CLKX2 that is the input clock signal CLK doubled in frequency; a comparator 10 for performing a magnitude comparison action on input signals when the double clock signal CLKX2 from the doubler 20 is at a first logic level, and stopping the comparison action when the double clock signal CLKX2 is at a second logic level; and a first circuit 12, 14 for monitoring outputs of the comparator 10, and generating a trigger signal DLCLK on detecting that the comparator 10 has output a comparison result.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a configuration suitable for application to, for example, a comparator that inputs a doubled clock signal.

  A comparator that performs a comparison operation based on a doubled clock signal (CLKX2) obtained by multiplying the frequency of the clock signal (CLK) by 2 is used (see FIG. 11B). This comparator is used as a comparator that compares the voltage levels of two signals in an analog-digital converter (ADC) that converts an analog signal into a digital signal, for example (see FIG. 11A).

  FIG. 12 is a diagram illustrating an example of a typical circuit configuration using a PLL (Phase Locked Loop) as a doubler (Frequency Doubler) that supplies a doubled clock signal to the comparator. The double PLL 30 generates a double clock signal CLKX2 obtained by multiplying the frequency of the clock signal CLK supplied from a clock generation circuit such as an oscillation circuit (4 in FIG. 11B) by 2 and supplies the clock signal CLKX2. Although not particularly limited, the comparator 10 receives the first and second input signals INP and INN, and the first and second input signals INP and INN when the doubled clock signal CLKX2 is High (for example, power supply potential). When the doubled clock signal CLKX2 is low (for example, ground potential), both the first and second outputs COP and CON are both compared to the first and second outputs COP and CON. Reset to High level (power supply voltage).

  In the example of FIG. 12, the SR latch (SR Latch) 11 receives the first and second outputs COP and CON of the comparator 10 at the set input terminal ￣S and the reset input terminal ￣R, and outputs complementary outputs Q and QB. Is output. The SR latch 11 is set to (Q, QB) = (High, Low) when (￣S, ￣R) = (Low, High), and (￣S, ￣R) = (High, Low). (Q, QB) = (Low, High), and when (￣S, ￣R) = (High, High), (Q, QB) holds the previous state. In FIG. 12, the bars (￣) above the terminals S and R indicate that the signal input to the terminals is active at the low level. In response to the output (COP, CON) = (Low, High) of the comparator 10, the output of the SR latch 11 is set to (Q, QB) = (High, Low), and (COP, CON) = (High, In response to (Low), (Q, QB) is reset to (Low, High). When (COP, CON) = (High, High), (Q, QB) holds the previous state. Hereinafter, the SR latch 11 of the other drawings has the same configuration as the SR latch 11 of FIG.

  In FIG. 12, although the internal configuration of the double PLL 30 is not shown, the PLL is, for example, a VCO (Voltage Controlled Oscillator) that varies the oscillation frequency with a control voltage. A divider for dividing the oscillation signal of the VCO, a phase comparator for detecting the phase difference between the output of the divider and the input clock signal (PD: Phase Detector or PFD: Phase Frequency Detector), It has a charge pump (CP: Charge Pump) that receives and outputs the capacity of the comparator and a loop filter (LPF: Loop Filter) that smoothes the voltage of the charge pump. The output voltage of the loop filter is used as the control voltage. Provided for VCO Be paid. In the double PLL 30, as a frequency divider that divides the oscillation signal of the VCO, for example, the first frequency divider generates the doubled clock signal CLKX2, and the doubled clock signal CLKX2 is further divided by two to obtain the clock signal CLK. Is generated and input to the phase comparator. The double PLL 30 generates a multiplied clock signal CLKX2 that is phase-synchronized with the input clock signal CLK. The PLL may be a complete digital PLL (ADPLL: All Digital PLL).

  In the case of the configuration of FIG. 12 using a PLL as a doubler, the circuit area increases and the power increases.

  As a simpler circuit configuration, a doubler using a time delay technique (Time-Delay Technique) is known. FIG. 13 is a diagram illustrating a typical circuit configuration of a doubler using a time delay technique (Time-Delay Technique). For details of Time-Delay Technique, see Non-Patent Document 1, for example.

  Referring to FIG. 13, the doubler 20 ′ includes an exclusive OR (Exclusive OR) functioning as a delay circuit 19 (Delay) having a delay τ of T / 4 (where T is the period of CLK) and a phase comparator. ) Circuit 18. The doubler 20 ′ in FIG. 13 is the same as that shown in FIG. 1 and newly created in this application. In FIG. 13, the comparator 10 and the SR latch 11 are the same as those in FIG.

  In the doubler 20 ', the delay circuit 19 generates a clock signal (delayed clock signal) CLKD obtained by delaying the input clock signal CLK (duty = 50%) by τ = T / 4. The delayed clock signal CLKD and the input clock signal CLK are input to the exclusive OR circuit 18, and the doubled clock signal CLKX2 is output from the exclusive OR circuit 18. That is, the exclusive OR circuit 18 outputs Low when the input clock signal CLK and the delayed clock signal CLKD are at the same logic level (both High level or both Low level), and delays with the input clock signal CLK. When the clock signal CLKD has a different logic level, High is output. Note that FIG. 1, the delay circuit includes an integrator and a comparator. The integrator integrates the input clock signal CLK, which is a rectangular wave, and outputs a triangular wave. The comparator compares the triangular wave from the integrator with a reference voltage and outputs a triangular wave. Output a square wave delayed by T / 4. In FIG. 13, the delay circuit 19 is not limited to the configuration of the integrator and the comparator, and may be configured, for example, by connecting an even number of CMOS inverters.

  FIG. 14 shows timings of the input clock signal CLK, the output signal (delayed clock signal) CLKD of the delay circuit 10, and the doubled clock signal CLKX2 that is the output signal of the exclusive OR circuit 18 in the circuit of FIG. It is a figure which shows a waveform. Here, it is assumed that the period of the clock signal CLK is T, the duty is 50%, and the delay τ of the delay circuit 19 is T / 4. By comparing the input clock signal CLK with the delayed clock signal CLKD obtained by delaying the input clock signal CLK by τ = T / 4 by the delay circuit 19 and the exclusive OR circuit 18, the delayed clock signal CLKD and the input clock signal CLK are compared. When the logic levels are different, the double clock signal CLKX2 that becomes High is generated. As shown in FIG. 14, a pulse that rises to High in response to the rising edge and falling edge of the input clock signal CLK (pulse width = T / 4), and the doubled clock signal CLKX2 having a period = T / 2 is generated. The In FIG. 14, the duty of the double clock signal CLKX2 is 50%.

  The doubler 20 ′ in FIG. 13 includes a delay circuit 19 and one logic gate (Exclusive OR), and the circuit configuration is simplified. Compared with the configuration including the double PLL 30 in FIG. Circuit area and power consumption can be reduced.

Brad R. Jackson and Carlos E. Saavedra, "An L-Band CMOS Frequency Doubler using a Time-Delay Technique" Silicon Monolithic Integrated Circuits in RF Systems, Jan. 2006

  The following is an analysis of the related art performed by the present inventors.

  As described above, the configuration including the double PLL shown in FIG. 12 as the double multiplier can generate the double clock signal CLKX2 that is phase-synchronized with the input clock signal CLK. Since it is larger and more complex than a comparator or the like, there is a problem that both area and power increase.

  On the other hand, in the case of the doubler 20 ′ in FIG. 13, the delay time τ of the delay circuit 19 varies depending on the manufacturing process, power supply voltage fluctuation, temperature, and the like.

  FIG. 15 is a diagram for explaining a problem in the timing operation of the configuration of FIG. 15A and 15B show timing waveforms of the input clock signal CLK, the delayed clock signal CLKD, and the doubled clock signal CLKX2 of FIG. 13, and in FIG. The state (CMP state) of the comparator 10 is shown. “Operation” in the state of the comparator 10 (CMP state) indicates that the comparator 10 is in an operation state for comparing the voltages of INP and INN, and “stop” in the CMP state indicates that the comparator 10 is in the state of INP and INN. The voltage comparison operation is stopped. The comparator 10 requires time CMP_Delay after the doubled clock signal CLKX2 becomes High until the values (comparison results) of the first and second outputs COP and CON are determined.

  FIG. 15A is a diagram for explaining a first problem of the configuration of FIG. The first problem occurs when the delay τ of the delay circuit 19 is smaller than the determination operation time of the comparator 10. In the case of FIG. 15A, the delay τ ′ of the delay circuit 19 is shorter than τ = T / 4 (T is one cycle of the clock signal CLK), and the time interval (CMP_Delay) necessary for determining the comparison operation of the comparator 10. Shorter than. That is, the delayed clock signal CLKD rises from Low to High with a delay τ ′ from the rising edge of the input clock signal CLK from Low to High. The double clock signal CLKX2 that becomes High at the rising edge of the input clock signal CLK rises from High to Low at the timing of the broken line in FIG. 15A in response to the rising edge of the delayed clock signal CLKD from Low to High. Go down. The high pulse period (comparator operation period) of the doubled clock signal CLKX2 is shorter than the time interval (= CMP_Delay) necessary for determining the comparison operation of the comparator 10. As a result, as shown in “CMP state” in FIG. 15A, before the comparison result of the comparator 10 is confirmed, CLKD becomes High and CLKX2 becomes Low, so the comparator 10 stops the comparison operation. End up. As a result, correct comparison results are not output to the first and second outputs COP and CON of the comparator 10.

  FIG. 15B is a diagram for explaining a second problem of the configuration of FIG. When the delay τ ′ of the delay circuit 19 of FIG. 13 becomes larger than the half cycle (= T / 2) of the input clock signal CLK, the doubled clock signal CLKX2 is a doubled waveform necessary for the comparator 10 to operate correctly. It will not be. In FIG. 15B, the delayed clock signal CLKD rises from Low to High after the input clock signal CLK rises from Low to High and then falls from High to Low (τ ′> T / 2). . For this reason, the double clock signal CLKX2 becomes High at the rising edge of the input clock signal CLK, becomes Low at the falling edge of the input clock signal CLK after T / 2, and is delayed after the time interval (τ′−T / 2). It becomes High at the rising edge of the clock signal CLKD and becomes High until the input clock signal CLK of the next cycle rises from Low to High. The waveform of this CLKX2 is that the pulse width of the first High pulse of two consecutive High pulses is T / 2 within one period (= T) of the input clock signal CLK, and the time (τ′−T / It becomes Low during 2), and the next High pulse becomes the time interval (T−τ ′) High until the rising edge of the input clock signal CLK in the next cycle. In the waveform of CLKX2 in FIG. 15B, since the Low period between two consecutive high pulses is short, the time required for the reset operation of the comparator 10 may not be ensured.

  Therefore, the present invention has been made in view of the above-described problems caused by delay time variations of delay circuits, and the object thereof is to simplify the circuit configuration and to solve the above problems. An object of the present invention is to provide a semiconductor device including a doubler that eliminates the problem and guarantees the operation of the comparator.

  In order to solve the above-described problems, a semiconductor device having the following general configuration is provided (but is not limited to the following).

According to the present invention, the delayed clock signal obtained by delaying the input clock signal by the first delay circuit and the input clock signal are input to the phase comparator, and the doubled clock obtained by multiplying the frequency of the input clock signal by two. A doubler circuit for generating a signal;
When the double clock signal from the double circuit is received and the double clock signal is at the first logic level, the first and second input signals are compared in magnitude, and the double clock signal is A comparator that stops the comparison operation at the second logic level;
A first circuit that monitors the output of the comparator and outputs a trigger signal when it is detected that the comparator has completed the comparison operation, and the first delay circuit includes the input clock signal, There is provided a semiconductor device including a variable delay device that delays at least the time point when the trigger signal is output from the first circuit and outputs the delayed signal as the delayed clock signal.

  According to the present invention, it is possible to simplify the circuit configuration, eliminate the above-described problems caused by variations in delay time of the delay circuit, and guarantee the operation of the comparator.

It is a figure which shows the structure of one Embodiment of this invention. It is a timing diagram for demonstrating operation | movement of one Embodiment of this invention. It is a figure which shows the structure of Example 1 of this invention. It is a timing diagram for demonstrating operation | movement of Example 1 of this invention. It is a figure which shows the structure of Example 2 of this invention. In Example 1 (2), it is a figure which shows the waveform of CLKX2 when Duty error arises in the clock signal CLK. It is a figure which shows the structure of Example 3 of this invention. It is a figure which shows the structure of Example 4 of this invention. It is a figure which shows the structural example of a comparator. It is a figure which shows an example of the semiconductor chip which mounts a frequency doubler. (A) is a figure which shows the circuit which uses the frequency doubler for the comparator clock of ADC. (B) shows a circuit using a frequency doubler for the clock of the comparator alone. It is a figure which shows the related technique which uses a PLL doubler as a doubler for a comparator clock. It is a figure which shows the related technique which uses the 2 time multiplier of Time-Delay Technique as a 2 times multiplier for a comparator clock. It is a timing diagram for demonstrating operation | movement of the doubler of FIG. (A), (B) is a timing diagram for demonstrating the problem of the doubler of FIG.

  According to one of the preferred embodiments of the present invention, a delay clock signal (CLKD) obtained by delaying an input clock signal (CLK) by a first delay circuit (for example, the variable delay device 16 in FIG. 1), and an input clock signal ( The phase of (CLK) is compared by a phase comparator (for example, 18 in FIG. 1) to generate a doubled clock signal (CLKX2) by multiplying the frequency of the input clock signal (CLK) by 2 (for example, FIG. 1). 2) and a double clock signal (CLKX2) from the double circuit (20 in FIG. 1), and when the double clock signal (CLKX2) is at the first logic level (for example, High level), A comparator (10) that performs a comparison operation and stops the comparison operation when the doubled clock signal (CLKX2) is at a second logic level (for example, a low level); A circuit for generating a trigger signal (DLCLK) (for example, 12, 14 in FIG. 1 or FIG. 3) at the time when it is confirmed that the output of the comparator (10) is output and the comparison result of the comparator (10) is output. 13). The first delay circuit (16 in FIG. 1) receives at least the input clock signal until the trigger signal (DLCLK) is output from the first circuit (12, 14 in FIG. 1, or 13 in FIG. 3). A signal obtained by variably delaying (CLK) is output as the delayed clock signal (CLKD). When the delayed clock signal (CLKD) and the input clock signal (CLK) have different logic levels, the phase comparator (18 in FIG. 1) outputs a first logic level (for example, High level), and the delayed clock signal ( When the CLKD) and the input clock signal (CLK) have the same logic level, a second logic level (for example, a Low level) is output.

  The double clock signal (CLLX2) is in response to a transition from the second logic level (Low level) to the first logic level (High level) of the input clock signal (CLK). In response to the transition to the first logic level (High level) of the delayed clock signal (CLKD) obtained by delaying the input clock signal (CLK) until the trigger signal (DLCLK) is output. 2 logic level (Low level). For this reason, the comparator (10) stops the comparison operation after the comparison operation is confirmed (completed). For this reason, the period of the first logic level of the multiplied clock signal is narrowed due to variations in the delay circuit due to variations in the manufacturing process, power supply voltage variations, temperature variations, etc., and the comparator (10) stops before confirming the comparison operation. This solves the first problem associated with the circuit of FIG.

  The double clock signal (CLLX2) changes to the first logic level when the input clock signal (CLK) changes from the second logic level to the first logic level, and the comparator (10) performs the comparison operation. Since the control is performed so as to shift to the second logic level at the time of confirmation, the second problem relating to the circuit of FIG. 13 is solved. In the circuit of FIG. 13, the doubled clock signal (CLLX2) is changed to the first logic level at the transition from the second logic level (for example, Low) to the first logic level (for example, High) of the input clock signal (CLK). And the second logic level after the delay τ of the delay circuit (19). On the other hand, in the circuit of FIG. 13, the comparison operation of the comparator (10) is determined when the doubled clock signal (CLLX2) transitions from the first logic level (High level) to the second logic level (Low level). It is irrelevant to the time. A description will be given below according to the embodiment.

<Embodiment>
FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, the present embodiment includes a comparator 10, an output monitor circuit 12, a trigger generation circuit 14, a variable delay device 16, and a phase comparator 18. The variable delay device 16 and the phase comparator 18 constitute a doubler 20. The comparator 10 has the same configuration as that described with reference to FIGS. 12 and 13. When the double clock signal CLKX2 is High, the comparator 10 compares the voltages of the input signals INP and INN, and the double clock signal CLKX2 is When High goes to Low, the comparison operation is stopped. Although not particularly limited, the output COP / N is precharged to a high level while the doubled clock signal CLKX2 is low.

  The output monitor circuit 12 and the trigger generation circuit 14 monitor the output COP / N of the comparator 10 and, when detecting that the comparator 10 has output a comparison result, output the trigger signal DLCLK. Of course, the output monitor circuit 12 and the trigger generation circuit 14 may be configured by one circuit block or logic gate.

  The variable delay unit 16 receives the input clock signal CLK, and outputs a delayed clock signal CLKD obtained by delaying the rising edge of the input clock signal CLK until the output timing of the trigger signal DLCLK (the timing of rising of DLCLK from Low to High). To do.

  The phase comparator 18 compares the phases of the input clock signal CLK and the delayed clock signal CLKD, and outputs a High pulse having a pulse width corresponding to the phase difference (the phase difference when one is High and the other is Low).

  FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. FIG. 2 shows an example of timing waveforms of the input clock signal CLK, the double clock signal CLKX2, the comparator output COP / N COP, the trigger signal DLCLK, and the delayed clock signal CLKD of FIG. In the COP waveform, a section surrounded by a frame schematically represents a determination section of the comparator. The operation of the present embodiment will be described with reference to FIGS.

  First, when the input clock signal CLK rises from Low to High, if the delayed clock signal CLKD is Low, there is a phase error, so that the double clock signal CLKX2 that is the output of the phase comparator 18 becomes High.

  Receiving High of the double clock signal CLKX2, the comparator 10 starts the operation of comparing the voltages of INP and INN.

  When the output monitor circuit 12 and the trigger generation circuit 14 that monitor the output of the comparator 10 detect the output of the comparison result of the comparator 10, the trigger signal DLCLK is activated (for example, high level).

  The variable delay unit 16 receives the rising edge of the trigger signal DLCLK from Low to High, and delays the edge (for example, the rising edge) of the input clock signal CLK to the rising edge of the trigger signal DLCLK. In response to the rising edge of the trigger signal DLCLK, the delayed clock signal CLKD output from the variable delay device 16 becomes High.

  When the delayed clock signal CLKD changes from Low to High, both the input lock signal CLK and the delayed clock signal CLKD are High, so that there is no phase difference between these signals, and the phase comparator 18 outputs the doubled clock signal as its output. CLKX2 is set to Low.

  Subsequently, when the input lock signal CLK falls from High to Low, since the delayed clock signal CLKD is High, the doubled clock signal CLKX2 output from the phase comparator 18 becomes High. Receiving High of the double clock signal CLKX2, the comparator 10 starts the operation of comparing the voltages of INP and INN. In the subsequent operation, the above-described operation is repeated.

  According to the present embodiment, the trigger signal DLCLK is activated based on the detection result of the end of the comparison operation (comparison result confirmation) in the comparator 10, and the delayed clock signal is corresponding to the activation timing of the trigger signal DLCLK. A rising edge of CLKD is generated, and the phase comparator 18 compares the phase of the delayed clock signal CLKD with the input clock signal CLK to generate a doubled clock signal CLKX2. For this reason, the problem described in FIGS. 15A and 15B is solved, and the operation of the comparator 10 is guaranteed.

<Example 1>
FIG. 3 is a diagram illustrating a specific configuration example of FIG. 1 as the first embodiment. Referring to FIG. 3, a comparator 10, an SR latch 11, an output monitor & trigger generation circuit 13 composed of a NAND circuit (negative AND circuit), a variable delay device (D Latch) 16, and a phase comparator (exclusive (OR circuit) 18. The output monitor & trigger generation circuit (NAND circuit) 13 of the first embodiment corresponds to the output monitor circuit 12 and the trigger generation circuit 14 of FIG. 1, and the output monitor circuit 12 and the trigger generation circuit 14 of FIG. It is a summary. The variable delay device 16 in FIG. 1 inputs an input clock signal CLK to a data terminal, inputs a trigger signal to the clock terminal, and captures and outputs the signal value of the data terminal at the rising edge of the clock terminal. It is composed of a latch (D Latch). The D-type latch may be composed of an edge-triggered D-type flip-flop. The phase comparator 18 is configured by an exclusive OR circuit (EXOR) as in FIG. In the following, for simplicity of explanation, the D-type latch constituting the variable delay device may be referred to by reference numeral 16 and the exclusive OR circuit constituting the phase comparator may be referred to by reference numeral 18. FIG. 4 is a timing waveform diagram for explaining the operation example of FIG.

  The operation when the voltage levels of the first and second input signals INP and INN input to the comparator 10 are INP <INN will be described with reference to FIGS.

  The comparator 10 is reset while the double clock signal CLKX2 is Low, and both the first and second outputs COP and CON are set to High.

  When the input clock signal CLK rises from Low to High when the delay clock signal CLKD is at Low level, the doubled clock signal CLKX2 that is the output of the phase comparator 18 responds to the rise of the input clock signal CLK to High. Stand up to High.

  When the double clock signal CLKX2 becomes High, the comparator 10 performs a comparison operation for comparing the voltage levels of the first and second input signals INP and INN.

  According to the time required for the comparison judgment of the comparator 10 (CMP_Delay in FIG. 15A), the first output COP corresponds to INP <INN after a while after the double clock signal CLKX2 rises from Low to High. From High to Low. The second output CON remains High and the comparison operation ends. When INP> INN, the second output CON changes from High to Low for a while after the doubled clock signal CLKX2 rises from Low to High, and the first output COP remains High and does not change. Ends.

  Corresponding to INP <INN, the first output COP of the comparator 10 changes from High to Low and the second output CON remains High. Therefore, the NAND circuit inputs the first and second outputs COP and CON. The trigger signal DLCLK, which is an output signal of 13, changes from Low to High. In response to the rising edge of the trigger signal DLCLK from Low to High, the D-type latch 16 captures the input clock signal CLK (High level at that time) and outputs High. That is, the delayed clock signal CLKD that is the output signal of the D-type latch 16 becomes High.

  Since the input clock signal CLK is High when the delay clock signal CLKD changes from Low to High, both inputs of the phase comparator 18 become High, and the doubled clock signal CLKX2 output from the phase comparator 18 is High. Changes from low to low. Receiving the Low of the double clock signal CLKX2, the comparator 10 is reset, and the first output COP of the comparator 10 changes from Low to High. The second output CON remains high.

  According to the first embodiment, the rising edge of the delayed clock signal CLKD is delayed by delaying the rising edge of the input clock signal CLK until the time when the values of the first and second outputs COP and CON of the comparator 10 change (when the comparison result is determined). Since the edge is generated and the multiplied clock signal CLKX2 is generated based on the input clock signal CLK and the delayed clock signal CLKD, the problem of the related art is solved.

<Example 2>
Next, Example 2 will be described. FIG. 5 is a diagram illustrating the configuration of the second embodiment. Referring to FIG. 5, in the second embodiment, in the configuration of the first embodiment shown in FIG. Has been. In FIG. 3, assuming that the delay time from the first and second outputs COP and CON of the comparator 10 to the double clock signal CLKX2 is 0 sec (that is, no delay), at the end of the comparison operation of the comparator 10 There is a possibility that the trigger signal DLCLK rises to High, the double clock signal CLKX2 immediately falls to Low, the comparator 10 is reset, and the first and second outputs COP and CON are reset to High. In this case, the first and second outputs COP and CON of the comparator 10 are not correctly transmitted to the SR latch 11 and the like at the subsequent stage.

  In this embodiment, as shown in FIG. 5, the delay circuit 15 is inserted between the variable delay device (D-type latch) 16 and the phase comparator 18, and immediately after the comparison operation of the comparator 10 is completed, the doubled clock is supplied. The occurrence of a situation in which the signal CLKX2 falls to Low and the comparator 10 is reset is avoided. The delay circuit 15 may have a configuration in which a plurality of CMOS inverters are connected, or a configuration using wiring delay or the like. According to the present embodiment, it is possible to reliably avoid resetting the comparator 10 and resetting the first and second outputs COP and CON to High at the end of the comparison operation of the comparator 10. .

<Example 3>
Next, Example 3 will be described. FIG. 6 is a diagram illustrating an example of a waveform of the doubled clock signal CLKX2 of the first embodiment of FIG. 3 when an error occurs in the duty of the input clock signal CLK. In the first embodiment, the doubler 20 uses the rising and falling edges of the input clock signal CLK to generate the doubled clock signal CLKX2. For this reason, when a duty error occurs in the input clock signal CLK, the frequency of the double clock signal CLKX2 is shifted due to the difference between the high period and the low period of the input clock signal CLK. For example, as shown in FIG. 6, when the High period of the input clock signal CLK is short, the time interval of two High pulses of the double clock signal CLKX2 generated in response to the rising and falling edges of the input clock signal CLK is reduced. The time interval between the high pulse of the double clock signal CLKX2 generated in response to the next rise of CLK is narrowed.

  FIG. 7 is a diagram illustrating the configuration of the third embodiment. In the third embodiment, in order to solve this problem, as shown in FIG. 7, in the configuration of FIG. 3, the input clock signal CLK is input and a duty correction circuit 17 for correcting the duty is provided. Are input to the phase comparator 18 and the D-type latch 16. In the duty correction circuit 17, the signal corrected so that the duty of the input clock signal CLK is 50% (the High period and the Low period are equal) is input to the phase comparator 18, and the rising edge and the rising edge of the signal whose duty is corrected are input. In response to the falling edge, the rising edge of the double clock signal CLKX2 is generated. For this reason, a waveform like CLKX2 in FIG. 6 is avoided. The duty correction circuit 17 corrects the duty of the input clock signal CLK so as to approach 50%, for example, and any known configuration can be used. According to the present embodiment, the duty of the input clock signal CLK is corrected so as to approach 50%, for example, so that even when a duty error occurs in the input clock signal CLK, the doubled clock signal CLKX2 as shown in FIG. 6 is output. Can be avoided.

<Example 4>
FIG. 8 is a diagram illustrating a configuration of the fourth embodiment. As shown in FIG. 8, the present embodiment includes the delay circuit 15 of the second embodiment and the duty correction circuit 17 of the third embodiment in the configuration of the first embodiment of FIG. The fourth embodiment has both the effects of the second embodiment and the third embodiment.

<Example 5>
FIG. 9 is a diagram illustrating an example of the configuration of the comparator 10 described in the embodiment and each example. Of course, the configuration of the comparator 10 is not limited to the configuration of FIG. Referring to FIG.
An NMOS transistor NM1 having a source connected to GND (or VSS: 0V) and a gate connected to the INP terminal;
An NMOS transistor NM2 having a source connected to GND (or VSS) and a gate connected to the INN terminal;
An NMOS transistor NM3 having a source connected to the drain of the NMOS transistor NM1 and a gate connected to the COP terminal;
An NMOS transistor NM4 having a source connected to the drain of the NMOS transistor NM2 and a gate connected to the CON terminal;
An NMOS transistor NM5 having a source connected to the drain of the NMOS transistor NM3 and a gate connected to the CLKX2 terminal;
An NMOS transistor NM6 having a source connected to the drain of the NMOS transistor NM4 and a gate connected to the CLKX2 terminal;
A PMOS transistor PM1 having a source connected to the power supply VDD, a drain connected to the drain of the NMOS transistor NM5, and a gate connected to the CLKX2 terminal;
A PMOS transistor PM2 having a source connected to the power supply VDD, a drain connected to the drain of the NMOS transistor NM5, and a gate connected to the COP terminal;
A PMOS transistor PM3 having a source connected to the power supply VDD, a drain connected to the drain of the NMOS transistor NM6, and a gate connected to the CON terminal;
A PMOS transistor PM4 having a source connected to the power supply VDD, a drain connected to the drain of the NMOS transistor NM6, and a gate connected to the CLKX2 terminal.

  When the CLKX2 terminal is Low (when the comparator 10 is reset), the PMOS transistors PM1 and PM4 are turned on (conductive), and the NMOS transistors NM5 and NM6 are turned off (non-conductive). It is charged to (VDD: High level). When both the CON and COP terminals are charged to the power supply voltage VDD, the PMOS transistors PM2 and PM3 are turned off. Since the NMOS transistors NM5 and NM6 are in the off (non-conducting) state, the current path between the power supply VDD and GND is cut off.

  From this state, when the CLKX2 terminal becomes High, the PMOS transistors PM1 and PM4 are turned off (non-conductive), and the NMOS transistors NM5 and NM6 are turned on (conductive). At this time, since COP and CON are High, the NMOS transistors NM3 and NM4 are turned on (conductive), and the PMOS transistors PM2 and PM3 are turned off (non-conductive). At this time, when the voltage levels of the INP and INN terminals are INP <INN, the NMOS transistor NM2 whose gate is connected to the INN terminal is turned on, and the charge at the COP terminal is connected to the GND via the NMOS transistors MN4 and MN6 in the on state. The COP terminal falls from High to Low. When the COP terminal falls to the Low side, the NMOS transistor NM3 whose gate is connected to the COP terminal is turned off, and the path between the CON terminal and the NMOS transistors NM5, NM3, NM1, and GND is cut off. Therefore, even if the voltage of INP is equal to or higher than the threshold voltage of the NMOS transistor NM1, and the NMOS transistor NM1 whose gate is connected to INN is in the on state, the CON terminal is held at the high level. In response to the low level of the COP terminal, the PMOS transistor PM2 is turned on and charges the CON terminal to High (power supply voltage VDD). Since the CON terminal is held high, the NMOS transistor NM4 is held in the on state. The PMOS transistors PM2 and PM3 whose gates are cross-connected to the drains (COP and CON terminals) and the NMOS transistors NM3 and NM4 whose gates are cross-connected to the COP and CON terminals are compared in the comparison operation (when CLKX2 is High). It functions as a differential latch that differentially amplifies and holds the comparison result of the INP and INN terminals by the transistors NM1 and NM2.

  On the other hand, when the voltage level of the INP and INN terminals is INP> INN, the NMOS transistor NM1 whose gate is connected to the INP terminal is turned on, and the charge of the CON terminal is discharged to GND through the NMOS transistors MN3 and MN5 in the on state. Then, the CON terminal falls from High to Low. When the CON terminal falls to the Low side, the NMOS transistor NM4 is turned off, and the path between the COP terminal and the NMOS transistors NM6, NM5, NM2, and GND is cut off. Therefore, even if the voltage of INN is equal to or higher than the threshold voltage of the NMOS transistor NM2, and the NMOS transistor NM2 whose gate is connected to INN is in the on state, the COP terminal is held at the high level. Further, the PMOS transistor PM3 is turned on in response to Low of the CON terminal, and charges the COP terminal to High (power supply voltage). Since the COP terminal is held high, the NMOS transistor NM3 is held in the on state.

<Example 6>
Example 6 discloses a semiconductor device including the comparator 10 of the above-described embodiment and examples. 10A and 10B are diagrams illustrating a semiconductor chip on which a doubler 20 that doubles a clock frequency is mounted. In the example of FIG. 10A, the oscillation circuit 4 outputs the clock signal CLK, and the clock signal multiplied by 2 by the double multiplier (X2) 20 is supplied to the analog-digital converter (ADC) 3 and the comparator 10. . In FIG. 10B, the oscillation circuit 4 outputs a clock signal CLK, and the clock signals multiplied by the first and second doublers (X2) 20 are the analog-digital converter (ADC) 3 and the comparator 10 respectively. Has been supplied to.

  In FIG. 10, when the doublers 30 and 20 of the related technology shown in FIGS. 12 and 13 are used as the doubler (X2) 20 for supplying the double clock signal to the comparator 10, refer to FIG. It has the above-mentioned problems described above. On the other hand, in FIG. 10, the doubler (X2) 20 that supplies the doubled clock signal to the comparator 10 is configured as shown in FIG. 3, for example, and an output monitor & trigger generation circuit for monitoring the output of the comparator 10 is added. Thus, the effects described in the above embodiments can be achieved. In FIG. 10, the semiconductor chip 1 includes the oscillation circuit 4. However, this may be a clock generation circuit that receives an external clock signal and generates an internal clock signal CLK. In FIG. 10, a CPU (Central Processing Unit) 2, a sensor 5, an ADC 3, and the like are provided on the same chip, but the present invention is not limited to such a configuration. Further, the semiconductor device is not limited to the configuration in which the ADC 3, the CPU 2, and the like are mounted on the same chip, and may be configured to be mounted on a substrate or the like.

  FIG. 11A illustrates an example of the ADC 3 including the comparator 10 that inputs the clock signal CLKX2 obtained by multiplying the clock signal CLK from the oscillation circuit 4 by the doubler 20. Although not particularly limited, the ADC 3 is composed of, for example, a successive approximation ADC, compares an analog voltage obtained by sampling the input signal with the comparison voltage and the comparator 10, narrows down the next search range according to the magnitude of the comparison result, and Is converted into a digital signal by a successive approximation algorithm for generating a comparison voltage of.

  FIG. 11B illustrates the comparator 10 that receives the clock signal CLKX2 obtained by multiplying the clock signal CLK from the oscillation circuit 4 by the doubler 20. The doubler (X2) 20 that supplies the doubled clock signal to the comparator 10 is configured as shown in FIG. 3, and an output monitor & trigger generation circuit that monitors the output of the comparator 10 is added, and this is described in the above embodiment. An effect can be produced.

  10 and 11 illustrate a semiconductor chip including a comparator, an ADC including a comparator, and a single comparator, but the present invention is of course not limited to such a configuration.

  Each disclosure of the non-patent literature is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 Semiconductor chip 2 CPU
3 ADC
4 Oscillation circuit 5 Sensor 10 Comparator 11 SR latch 12 Output monitor circuit 13 Output monitor and trigger generation circuit (NAND circuit)
14 Trigger Generation Circuit 15 Delay Circuit 16 Variable Delay Device (D Type Latch)
17 Duty correction circuit 18 Phase comparator (exclusive OR circuit)
19 Delay circuit 20, 20 ′ Double multiplier 30 Double multiplier PLL

Claims (10)

A delayed clock signal obtained by delaying an input clock signal by a first delay circuit and the input clock signal are input to a phase comparator, and a doubled clock obtained by multiplying the frequency of the input clock signal by 2 from the phase comparator. A doubler circuit for outputting a signal;
When the double clock signal from the double circuit is received and the double clock signal is at the first logic level, the first and second input signals are compared in magnitude, and the double clock signal is A comparator that stops the comparison operation at the second logic level;
A first circuit that monitors the output of the comparator and outputs a trigger signal when the comparator detects that the comparison operation has been completed;
With
The first delay circuit includes a variable delay device that delays the input clock signal at least until the trigger signal is output from the first circuit and outputs the delayed signal as the delayed clock signal. A semiconductor device. The comparator outputs either one of the first and second outputs set in common to a predetermined first potential according to the comparison result of the first and second input signals. Set to the second potential,
The first circuit inputs the first and second outputs of the comparator, and outputs an output when detecting that one of the first or second outputs becomes the second potential. The semiconductor device according to claim 1, further comprising a circuit that is activated and outputs the trigger signal.   The variable delay device includes a circuit that captures and outputs the input clock signal in response to a transition of the trigger signal from an inactive state to an active state. The semiconductor device described.   4. The semiconductor device according to claim 1, further comprising a second delay circuit between an output of the first delay circuit and the phase comparator. 5. A duty correction circuit for correcting the duty of the input clock signal;
5. The signal according to claim 1, wherein a signal obtained by correcting the duty of the input clock signal by the duty correction circuit is input to the first delay circuit and the phase comparator. 6. The semiconductor device described. A first delay circuit for outputting a delayed clock signal obtained by delaying an input clock signal;
When the input clock signal and the delayed clock signal are input, and these signals have different logic levels, the first logic gate that outputs the first and second logic levels, respectively, when the signals have the same logic level, Including a phase comparator;
A double circuit for generating a double clock signal obtained by multiplying the frequency of the input clock signal by two from the phase comparator;
When the double clock signal from the double circuit is received and the double clock signal is at the first logic level, the first and second input signals are compared in magnitude, and the double clock signal is When the second logic level, the comparison operation is stopped,
When the doubled clock signal is at the second logic level, the first and second outputs are commonly set to a voltage corresponding to a predetermined one of the first and second logic levels. When the doubled clock signal is at the first logic level, one of the first and second outputs is set to the other logic level according to the comparison result of the voltages of the first and second input signals. A comparator that sets the voltage corresponding to
A second output that inputs the first and second outputs of the comparator and activates the output as the trigger signal when it is detected that the first and second outputs have different logic levels; A first circuit comprising a logic gate of
With
The first delay circuit includes a circuit that captures and outputs the input clock signal in response to the activation timing of the trigger signal output from the first circuit. Semiconductor device.   The semiconductor device according to claim 6, further comprising a second delay circuit between an output of the first delay circuit and the phase comparator. A duty correction circuit for correcting the duty of the input clock signal;
8. The semiconductor device according to claim 6, wherein a signal obtained by correcting the duty of the input clock signal by the duty correction circuit is input to the first delay circuit and the phase comparator.   A precharge circuit for precharging the first and second outputs to a first power supply voltage corresponding to the first logic level when the doubled clock signal is at the second logic level; When the double clock signal is at the first logic level, the precharge circuit is inactivated, the first and second input signals are differentially latched, and the first and second outputs are output. 9. The semiconductor device according to claim 6, further comprising a circuit that sets one to a second power supply potential corresponding to the second logic level. 10.   9. The semiconductor device according to claim 2, further comprising a set / reset type latch circuit that inputs the first and second outputs of the comparator to a set terminal and a reset terminal.

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