JP2013098514A5 - - Google Patents
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- JP2013098514A5 JP2013098514A5 JP2011243132A JP2011243132A JP2013098514A5 JP 2013098514 A5 JP2013098514 A5 JP 2013098514A5 JP 2011243132 A JP2011243132 A JP 2011243132A JP 2011243132 A JP2011243132 A JP 2011243132A JP 2013098514 A5 JP2013098514 A5 JP 2013098514A5
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- JP
- Japan
- Prior art keywords
- substrate
- electrode
- bump
- semiconductor device
- conductive portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims 16
- 239000004065 semiconductor Substances 0.000 claims 7
- 239000000463 material Substances 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Claims (6)
前記第２の基板は、前記バンプを囲う環状導電部を有し、
前記貫通電極と前記バンプとを接続すると共に、前記第１の基板の周縁部を前記環状導電部に埋入させる実装工程と、
前記実装工程の後で、前記第１の基板に空洞部を形成するエッチング工程と、を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device by connecting a first substrate having a through electrode and a second substrate having a bump to each other,
The second substrate has an annular conductive portion surrounding the bump,
With connecting the before and SL through electrode bumps, and embedded makes the mounting process the peripheral portion of the first substrate to the annular conductive portion,
And a step of etching after the mounting step to form a cavity in the first substrate .
前記実装工程では、前記凹部の内側に前記バンプの先端部を入れた状態で前記貫通電極と前記バンプとを接続することを特徴とする請求項１に記載の半導体装置の製造方法。 Before the mounting step, further comprising a recess forming step of forming a recess on the surface of the through electrode connected to the bump,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the mounting step, the through electrode and the bump are connected in a state in which a tip of the bump is placed inside the recess.
前記第１の基板は、
第１の面及び該第１の面の反対側の第２の面を有し、前記第１の面側に空洞部が設けられた第１の基材と、
前記第１の基材の前記第１の面と前記第２の面との間を貫通する貫通電極と、を有し、
前記第２の基板は、
前記第２の面と対向する第３の面を有する第２の基材と、
前記第２の基材の前記第３の面側に設けられ、前記貫通電極に接続されたバンプと、
前記第２の基材の前記第３の面側に設けられ、前記バンプを囲む環状導電部と、を有し、
前記第１の基板の周縁部が前記環状導電部に埋入していることを特徴とする半導体装置。 The first substrate and the second substrate is a semiconductor device connected to each other,
The first substrate is
A first substrate having a first surface and a second surface opposite to the first surface, wherein a cavity is provided on the first surface side;
A through electrode penetrating between the first surface and the second surface of the first substrate ,
Before Symbol second substrate,
A second substrate having a third surface facing the second surface;
A bump provided on the third surface side of the second base material and connected to the through electrode;
An annular conductive portion provided on the third surface side of the second base material and surrounding the bump,
A semiconductor device, wherein a peripheral portion of the first substrate is embedded in the annular conductive portion.
前記第１の基材の前記第１の面と前記第２の面との間であって、前記貫通電極よりも前記周縁部に近い位置を貫通する第２の貫通電極、をさらに有し、
前記第２の貫通電極と前記環状導電部とが接続されていることを特徴とする請求項３に記載の半導体装置。 The first substrate is
A second through electrode penetrating a position between the first surface and the second surface of the first base material and closer to the peripheral edge than the through electrode;
The semiconductor device according to claim 3 in which the pre-Symbol second through electrode and the annular conductive portion is characterized in that it is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011243132A JP2013098514A (en) | 2011-11-07 | 2011-11-07 | Semiconductor device manufacturing method, semiconductor device and electronic apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011243132A JP2013098514A (en) | 2011-11-07 | 2011-11-07 | Semiconductor device manufacturing method, semiconductor device and electronic apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013098514A JP2013098514A (en) | 2013-05-20 |
| JP2013098514A5 true JP2013098514A5 (en) | 2014-12-11 |
Family
ID=48620122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011243132A Withdrawn JP2013098514A (en) | 2011-11-07 | 2011-11-07 | Semiconductor device manufacturing method, semiconductor device and electronic apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2013098514A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150171039A1 (en) * | 2013-12-13 | 2015-06-18 | Chipmos Technologies Inc. | Redistribution layer alloy structure and manufacturing method thereof |
| TW201838094A (en) * | 2017-02-16 | 2018-10-16 | 學校法人慶應義塾 | Multilayer semiconductor integrated circuit device |
| US20240113066A1 (en) * | 2021-02-19 | 2024-04-04 | Sony Semiconductor Solutions Corporation | Electronic device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4000045B2 (en) * | 2002-10-30 | 2007-10-31 | 京セラ株式会社 | Surface acoustic wave device and manufacturing method thereof |
| US6835589B2 (en) * | 2002-11-14 | 2004-12-28 | International Business Machines Corporation | Three-dimensional integrated CMOS-MEMS device and process for making the same |
| DE60235267D1 (en) * | 2002-12-20 | 2010-03-18 | Ibm | METHOD OF MANUFACTURING A THREE-DIMENSIONAL DEVICE |
| JP4744213B2 (en) * | 2005-07-11 | 2011-08-10 | 日本電波工業株式会社 | Manufacturing method of electronic parts |
| JP2007318143A (en) * | 2006-05-22 | 2007-12-06 | Samsung Electronics Co Ltd | Semiconductor structure, and its manufacturing method |
| KR20100020718A (en) * | 2008-08-13 | 2010-02-23 | 삼성전자주식회사 | Semiconductor chip, stack structure, and methods of fabricating the semiconductor chip and the stack structure |
| US8618670B2 (en) * | 2008-08-15 | 2013-12-31 | Qualcomm Incorporated | Corrosion control of stacked integrated circuits |
| US8749027B2 (en) * | 2009-01-07 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust TSV structure |
-
2011
- 2011-11-07 JP JP2011243132A patent/JP2013098514A/en not_active Withdrawn
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