JP2013098183A - Semiconductor device manufacturing method and wafer polishing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can sufficiently inhibit adverse effects by rigidity deterioration of a polishing pad caused by wearing of the polishing pad.SOLUTION: A wafer polishing apparatus comprises: a polishing pad 2 provided on a polishing table 1; a polishing head 4 relatively transferring a wafer 3 with respect to the polishing pad 2 in a state where the wafer 3 touches the polishing pad 2 to polish the wafer 3; and a temperature control part 6 controlling a temperature of the polishing pad 2 depending on a thickness of the polishing pad 2 after polishing.

Description

  The present invention relates to a semiconductor device manufacturing method and a wafer polishing apparatus.

  In the field of manufacturing semiconductor devices, a wafer polishing apparatus that polishes a wafer is used. A typical wafer polishing apparatus is a CMP apparatus that performs CMP (Chemical Mechanical Polish) on a wafer.

  The CMP apparatus includes a polishing table (polishing surface plate), a polishing pad provided on the polishing table, and a polishing head that holds the wafer face down. For polishing the wafer, for example, the polishing table is rotated in the horizontal plane while the polishing head is rotated in the horizontal plane together with the wafer while the surface to be polished of the wafer held by the polishing pad is in contact with the polishing pad. To do.

  Here, the polishing pad is not a rigid body but an elastic body. For this reason, the polishing pad may bend during CMP and a phenomenon called dishing may occur.

  In Patent Document 1, CMP is performed using a polishing pad having a hard layer for polishing a wafer and a high thermal conductive layer disposed under the hard layer, whereby the surface temperature of the hard layer is reduced to a softening point. There is a description that rising to the vicinity can be suppressed and dishing can be suppressed.

JP 2003-297784 A

However, the decrease in rigidity of the polishing pad occurs not only due to an increase in temperature but also due to wear of the polishing pad.
With the technique of Patent Document 1, it is difficult to sufficiently suppress the adverse effects due to the decrease in rigidity of the polishing pad due to abrasion of the polishing pad.

The present invention includes a step of polishing a wafer with a polishing pad,
In the step of polishing the wafer, the temperature of the polishing pad is controlled in accordance with the thickness after the abrasion of the polishing pad.

  According to this manufacturing method, the rigidity of the polishing pad can be adjusted by controlling the temperature of the polishing pad in accordance with the thickness of the polishing pad after wear. Can be adjusted to an appropriate rigidity. Therefore, it is possible to sufficiently suppress an adverse effect due to a decrease in rigidity of the polishing pad due to wear of the polishing pad. Thereby, for example, the occurrence of dishing can be suppressed.

The present invention also provides a polishing table;
A polishing pad provided on the polishing table;
A polishing head for polishing the wafer by moving the wafer relative to the polishing pad in a state where the wafer is in contact with the polishing pad;
A temperature control unit for controlling the temperature of the polishing pad according to the thickness after wear of the polishing pad;
There is provided a wafer polishing apparatus characterized by comprising:

  According to the present invention, it is possible to sufficiently suppress an adverse effect due to a decrease in rigidity of the polishing pad due to wear of the polishing pad.

It is a mimetic diagram showing a wafer polish device concerning an embodiment. It is sectional drawing which shows a series of processes of the manufacturing method of the semiconductor device which concerns on embodiment. It is a flowchart which shows operation | movement of the wafer polishing apparatus which concerns on embodiment. 3 is a time chart of a method for manufacturing a semiconductor device according to an embodiment. It is a figure which shows the relationship between the temperature and elastic modulus of the polishing pad which concerns on embodiment. It is a figure which shows the relationship between the temperature and elastic modulus of the polishing pad of a modification.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

FIG. 1 is a schematic view showing a wafer polishing apparatus 100 according to the embodiment.
The wafer polishing apparatus 100 according to the present embodiment uses the polishing table 1, the polishing pad 2 provided on the polishing table 1, and the wafer 3 as the polishing pad 2 in a state where the wafer 3 is in contact with the polishing pad 2. And a polishing head 4 that moves relative to the polishing head 4 to polish the wafer 3, and a temperature control unit (control unit 6) that controls the temperature of the polishing pad 2 in accordance with the thickness of the polishing pad 2 after wear. . Details will be described below.

  The polishing table 1 includes a plate-like table main body 11 having a flat upper surface and a horizontal surface, and a shaft portion 12 protruding downward from the central portion of the table main body 11. A polishing pad 2 is disposed on the upper surface of the table body 11.

The polishing pad 2 includes, for example, an upper layer pad (first layer) 21 that contacts the wafer 3 and polishes the wafer 3 and a lower layer pad (second layer) 22 positioned below the upper layer pad 21. It has a structure. The upper layer pad 21 and the lower layer pad 22 are each formed in a flat plate shape.
Specifically, for example, the polishing pad 2 has a two-layer structure of an upper layer pad 21 and a lower layer pad 22.

The upper layer pad 21 has a larger elastic modulus (harder) than the lower layer pad 22. The upper layer pad 21 has a function of directly contacting the wafer 3 to polish the wafer 3, and greatly contributes to polishing the wafer 3 with good flatness.
Here, normally, the wafer 3 before CMP has a global level difference of a film to be polished formed in advance, and this level difference is eliminated by CMP. The degree of elimination of this level difference, that is, the finish level of CMP is called flatness.

  On the other hand, the lower layer pad 22 has a smaller elastic modulus (softer) than the upper layer pad 21. The lower layer pad 22 greatly contributes to polishing the wafer 3 with good uniformity. Here, the uniformity is an index representing the degree of uniformity of the film thickness within the surface of the wafer 3. Good uniformity means that the film thickness within the surface of the wafer 3 is uniform.

The upper layer pad 21 is made of, for example, urethane resin (polyurethane). More specifically, this urethane resin is represented by the following general formula:-[OCONHR1NHCOO-R2] m- [OCONHR1NHCOO-R3] n-
It is represented by
Here, R1 to R3 are hydrocarbon chains, and m and n are arbitrary integers.
The upper layer pad 21 is made of, for example, a urethane resin having a glass transition point of less than 60 ° C. The glass transition point of this urethane resin is, for example, 20 ° C. or higher. More specifically, the glass transition point of this urethane resin is 50 ° C. or less.
The upper layer pad 21 has a tensile modulus of about 240 MPa to 300 MPa, for example.
The upper layer pad 21 may be made of polybutadiene.

  The lower layer pad 22 is made of, for example, polyethylene or polyurethane. A polishing pad 2 (single-layer polishing pad 2) that does not have the lower layer pad 22 may be used.

  The polishing head 4 has a retainer ring 7 that holds the wafer 3 on the lower surface side. The polishing head 4 holds the wafer 3 held by the retainer ring 7 face down, and brings the surface to be polished (lower surface in FIG. 1) into contact with the upper surface of the polishing pad 2 (upper surface of the upper layer pad 21). .

  The wafer polishing apparatus 100 further includes a cooling unit 5 that cools the polishing pad 2. The cooling unit 5 is an apparatus called a chiller, for example, and supplies cooling water to the outside. The cooling unit 5 changes the supply amount of the cooling water and the temperature of the cooling water under the control of the control unit 6 described later.

  The wafer polishing apparatus 100 further includes a supply pipe 51 for supplying cooling water from the cooling unit 5 to the polishing table 1, a cooling pipe 52 routed in the polishing table 1, and cooling water from the polishing table 1 to the cooling unit. And a pipe 53 to return to 5.

  One end of the supply pipe 51 is connected to the cooling unit 5, and the other end of the supply pipe 51 is connected to one end of the cooling pipe 52. One end of the cooling pipe 52 is located at the lower end of the shaft portion 12 of the polishing table 1, for example. The cooling pipe 52 is routed from the lower end of the shaft portion 12 to the upper end of the shaft portion 12, and is further routed to the upper portion of the table body 11. The cooling pipe 52 is routed in the upper part of the table body 11 in a circulation path that can uniformly cool the upper part of the table body 11. Further, the cooling pipe 52 is routed from the upper portion of the table body 11 to the lower end (the upper end of the shaft portion 12), and is routed from the upper end to the lower end of the shaft portion 12. The other end of the cooling pipe 52 is located at the lower end of the shaft portion 12 and is connected to one end of the pipe 53. The other end of the pipe 53 is connected to the cooling unit 5.

  The cooling unit 5 supplies cooling water to the cooling pipe 52 in the polishing table 1 through the supply pipe 51. The cooling water is introduced into the cooling pipe 52 from one end of the cooling pipe 52 and flows to the other end side of the cooling pipe 52. That is, the cooling water circulates in the polishing table 1. Thereafter, the cooling water is returned to the cooling unit 5 from the other end of the cooling pipe 52 through the pipe 53.

  The cooling unit 5 includes a cooling mechanism that cools the cooling water and a pump that pumps the cooling water to the supply pipe 51.

  The control unit 6 adjusts the temperature of the cooling water and the supply amount of the cooling water by controlling the cooling mechanism and the pump of the cooling unit 5.

As described above, the cooling water circulates in the polishing table 1 to cool the polishing table 1. As the polishing table 1 is cooled, the polishing pad 2 provided on the polishing table 1 is also cooled.
The controller 6 can control the temperature of the polishing pad 2 by controlling the cooling unit 5 and adjusting the temperature and the supply amount of the cooling water.
The polishing pad 2 changes its rigidity according to the temperature change.

  Here, the wafer polishing apparatus 100 also preferably includes a temperature detection unit (temperature sensor) (not shown) that detects the temperature of the polishing pad 2. In this case, the temperature detection result by the temperature detection unit is input to the control unit 6, and the control unit 6 controls the temperature of the polishing pad 2 according to the detection result.

The thickness of the polishing pad 2 decreases as the use time (operation time) becomes longer. The thickness of the polishing pad 2 is reduced by polishing the wafer 3 with the polishing pad 2 or conditioning the polishing pad 2 with a conditioner.
In the polishing pad 2, the portion where the thickness decreases due to wear is the upper layer pad 21 that is a portion that contacts the wafer 3.
The rigidity of the polishing pad 2 decreases as the thickness (for example, the thickness of the upper layer pad 21) decreases due to wear.
When the rigidity of the polishing pad 2 decreases, it becomes difficult to polish the wafer 3 with good flatness.

  Therefore, in the present embodiment, the rigidity of the polishing pad 2 is adjusted by controlling the temperature of the polishing pad 2 in accordance with the thickness of the polishing pad 2 after wear. Thereby, even if the polishing pad 2 is worn, the polishing pad 2 can be adjusted to an appropriate rigidity. Therefore, it is possible to suppress an adverse effect due to a decrease in rigidity of the polishing pad 2 due to wear of the polishing pad 2. For example, the occurrence of dishing during polishing of the wafer 3 can be suppressed.

The wafer polishing apparatus 100 further includes a polishing table rotation actuator (not shown) such as a motor for rotating the polishing table 1 and a polishing head rotation actuator (not shown) such as a motor for rotating the polishing head 4. ing.
In addition, the wafer polishing apparatus 100 further supplies a slurry reservoir (not shown) for storing the slurry, a slurry nozzle (not shown) for discharging the slurry onto the polishing pad 2, and pumps the slurry in the slurry reservoir to the slurry nozzle. It has a slurry supply actuator (not shown) such as a pump or a motor, a conditioner (not shown) for conditioning the polishing surface of the polishing pad 2, and a conditioner drive actuator (not shown) for operating the conditioner.

The control unit 6 includes a CPU (Central Processing Unit) that performs various control processes, a ROM (Read Only Memory) that stores a program for operating the CPU, and a RAM (Random Access Memory) that functions as a work area of the CPU. ).
The control unit 6 controls the operation of the cooling unit 5, the polishing table rotation actuator, the polishing head rotation actuator, the slurry supply actuator, the conditioner drive actuator, and the like.

Polishing (specifically, for example, CMP) of the wafer 3 by the wafer polishing apparatus 100 configured as described above can be performed as follows.
That is, with the wafer 3 held by the retainer ring 7 of the polishing head 4, the polishing surface of the wafer 3 is pressed against the upper surface of the upper layer pad 21 of the polishing pad 2, and the slurry is dropped onto the polishing pad 2 from the slurry nozzle. Then, the polishing head 4 and the polishing table 1 are rotated.
As a result, the surface to be polished of the wafer 3 moves relative to the upper surface in a state of being in contact with the upper surface of the upper layer pad 21, so that the surface to be polished of the wafer 3 is polished.
During operation of the wafer polishing apparatus 100, the temperature of the polishing pad 2 is controlled at any time.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
FIG. 2 is a cross-sectional view showing a series of steps of the method of manufacturing a semiconductor device according to the embodiment.
This manufacturing method includes a step of polishing the wafer 3 with the polishing pad 2. In the step of polishing the wafer 3, the temperature of the polishing pad 2 is controlled according to the thickness after polishing of the polishing pad 2. By this temperature control, the rigidity of the polishing pad 2 is adjusted. Details will be described below.

  In this embodiment, although not shown, a substrate in which a semiconductor element such as a transistor is formed on a semiconductor substrate and an interlayer insulating film is formed thereon is used as a base substrate. A wiring structure for connecting the semiconductor elements is formed on the base substrate. As the semiconductor substrate, a silicon substrate or the like can be used.

First, as shown in FIG. 2A, an interlayer insulating film 201 is formed on a silicon substrate (not shown). A resist pattern is formed on the interlayer insulating film 201 by a normal exposure method, and then dry etching is performed to form a plurality of wiring grooves 202 in the interlayer insulating film 201.
Next, a barrier metal film 203 is formed on the interlayer insulating film 201 and inside the wiring trench 202. In order to form the barrier metal film 203, for example, a sputtering method or the like can be used. As the barrier metal film 203, for example, a Ta film is used.
Next, a Cu seed film (not shown) is formed on the barrier metal film 203 by sputtering. Next, a Cu plating film 204 is formed by electrolytic plating using the Cu seed film as a cathode.
In this way, a metal film can be formed so as to fill the wiring groove 202.

  Next, as shown in FIG. 2B, planarization by CMP is performed. Thereby, Cu wiring (Cu plating film 206) is formed in the wiring groove 202. Excess Cu plating film 204 outside the wiring trench 202 is removed.

  As described above, the semiconductor device 200 having the wiring structure shown in FIG. 2B is obtained. Thereafter, a semiconductor device having a multilayer wiring structure of two or more layers may be formed by repeating the above-described steps.

  Here, in the method of manufacturing a semiconductor device according to the present embodiment, planarization by CMP (step of FIG. 2B) is performed using the above-described wafer polishing apparatus 100, for example.

As described above, as the use time (operation time) of the polishing pad 2 increases, the thickness thereof decreases due to wear and the rigidity thereof decreases. As a result, since the rigidity of the polishing pad 2 is insufficient, it becomes difficult to polish the wafer 3 with good flatness.
In particular, when a metal film is embedded in the wiring groove 202 by polishing the wafer 3, dishing is likely to occur.

  Here, the polishing pad 2 at the time of CMP makes contact with the surface of the embedded structure while bending with the stopper layer 205 (FIG. 2) beside the embedded structure (Cu plating film 206) as a fulcrum. For this reason, dishing occurs.

  Therefore, in the present embodiment, when the polishing pad 2 is worn, the rigidity of the polishing pad 2 is increased by lowering the temperature of the polishing pad 2, thereby suppressing the occurrence of adverse effects such as dishing and the long life of the polishing pad 2. Plan

  That is, the control unit 6 determines whether or not the thickness of the polishing pad 2 is less than a predetermined thickness due to wear, and when determining that the thickness of the polishing pad 2 is less than a predetermined thickness, The polishing pad 2 is controlled at a lower temperature than when the thickness of the polishing pad 2 is equal to or greater than a predetermined thickness.

Here, the determination of whether or not the thickness of the polishing pad 2 is less than a predetermined thickness is made based on, for example, the number of CMP processes performed by the same polishing pad 2. For example, the number of CMP processes (hereinafter, the upper limit number of processes) in which the thickness of the polishing pad 2 becomes a predetermined thickness is checked in advance. Then, when the number of CMP processes using the same polishing pad 2 exceeds the upper limit number of processes, it is determined that the thickness of the polishing pad 2 has become less than a predetermined thickness.
The determination as to whether or not the thickness of the polishing pad 2 is less than a predetermined thickness may be made based on the operating time of the same polishing pad 2.
Alternatively, it may be determined whether or not the thickness of the polishing pad 2 is less than a predetermined thickness based on the measured value of the thickness of the polishing pad 2.
In addition, here, “the thickness of the polishing pad 2 becomes a predetermined thickness” means, for example, “the layer thickness of the upper layer pad 21 of the polishing pad 2 is 60 to 70% of the initial value” and the like. means.

  More specifically, when the thickness of the polishing pad 2 is equal to or greater than a predetermined thickness, the control unit 6 controls the temperature of the polishing pad 2 to be equal to or higher than the glass transition point of the upper layer pad 21 of the polishing pad 2. When the thickness of the polishing pad 2 becomes less than a predetermined thickness, the temperature of the polishing pad 2 is controlled to a temperature lower than the glass transition point of the upper layer pad 21 of the polishing pad 2.

FIG. 3 is a flowchart showing the operation of the control unit 6 of the wafer polishing apparatus 100. The process of FIG. 3 is performed by the control unit 6 at any time (for example, repeatedly every predetermined time) while the wafer polishing apparatus 100 is in operation, for example.
FIG. 4 is a time chart of the semiconductor device manufacturing method according to the present embodiment. In FIG. 4, the dotted line graph indicates the temperature of the polishing pad 2, and the solid line graph indicates the rigidity of the polishing pad 2. The horizontal axis in FIG. 4 represents the amount of wear of the polishing pad 2, and the vertical axis represents the temperature or rigidity of the polishing pad 2.

As shown in FIG. 3, the controller 6 first determines whether or not the thickness of the polishing pad 2 after wear has become less than a predetermined thickness (step S1).
If the thickness of the polishing pad 2 is equal to or greater than the predetermined thickness (N in Step S1), the controller 6 determines that the temperature of the polishing pad 2 is equal to or higher than the glass transition point of the upper layer pad 21 (preferably, the glass The cooling unit 5 is controlled so that the temperature is higher than the transition point (step S2).
On the other hand, if the thickness of the polishing pad 2 is less than the predetermined thickness (Y in Step S1), the control unit 6 causes the temperature of the polishing pad 2 to be lower than the glass transition point of the upper layer pad 21. Thus, the cooling unit 5 is controlled (step S3).

  As a result of performing such control, as shown in FIG. 4, when the wear amount of the polishing pad 2 is a predetermined amount M or less, that is, when the thickness of the polishing pad 2 is equal to or larger than the predetermined thickness, the polishing pad 2 Is maintained at a temperature equal to or higher than the glass transition point of the upper layer pad 21. When the wear amount of the polishing pad 2 exceeds a predetermined amount M, that is, when the thickness after wear of the polishing pad 2 is less than the predetermined thickness, the temperature of the polishing pad 2 is the glass of the upper layer pad 21. Maintained at a temperature below the transition point.

Here, FIG. 5 is a diagram (solid line graph in FIG. 5) showing the relationship between the temperature of the polishing pad 2 of the wafer polishing apparatus 100 according to the embodiment and the elastic modulus of the upper layer pad 21 of the polishing pad 2. Further, in FIG. 5, for comparison, the relationship between the temperature of the polishing pad of the modified example and the elastic modulus of the upper layer pad is indicated by a dotted line.
FIG. 6 is a diagram showing the relationship between the temperature of the polishing pad of the modification and the elastic modulus of the upper layer pad.

The polishing pad of the modified example is a polishing pad that is currently generally used in a CMP apparatus. The material of the upper layer pad of this polishing pad is urethane resin (polyurethane). Urethane resin has a glass transition point Tg (softening point). The glass transition point Tg of this urethane resin is about 60 ° C. This urethane resin has a lower elastic modulus and becomes softer at a temperature equal to or higher than the glass transition point Tg.
As shown in FIG. 6, this polishing pad is used in a temperature range T3 below the glass transition point Tg. Since the temperature at the time of polishing using this polishing pad is sufficiently lower than the glass transition point, the elastic modulus of the polishing pad will not be insufficient. However, as the polishing pad wears, the pad rigidity decreases.

On the other hand, the glass transition point Tg (softening point) of the upper layer pad 21 of the polishing pad 2 according to the present embodiment is lower than the glass transition point Tg of the upper layer pad of the polishing pad of the modified example, as shown in FIG.
The upper layer pad 21 of the polishing pad 2 according to the present embodiment has a modulus of elasticity equivalent to that of the upper layer pad of the polishing pad of the modified example even in the temperature range T1 above the glass transition point Tg.
The elastic modulus of the upper layer pad 21 of the polishing pad 2 according to this embodiment is larger than the elastic modulus in the temperature range T1 in the temperature range T2 at a temperature lower than the glass transition point Tg.
The elastic modulus of the upper layer pad 21 of the polishing pad 2 according to the present embodiment has a higher elastic modulus than the upper layer pad of the polishing pad of the modification in the temperature range T2.

As shown in FIG. 4, at the beginning of use of the polishing pad 2, the temperature of the polishing pad 2 is controlled to be higher than the glass transition point Tg of the upper layer pad 21 (temperature in the temperature range T <b> 1 in FIG. 5).
The rigidity of the polishing pad 2 decreases as the number of CMP processes performed by the polishing pad 2 increases and the amount of wear of the polishing pad 2 increases (the thickness of the polishing pad 2 after wear decreases).

  Thereafter, when the wear amount of the polishing pad 2 exceeds a predetermined amount M (FIG. 4), that is, when the thickness after the wear of the polishing pad 2 becomes less than the predetermined thickness, the temperature of the polishing pad 2 is set to the upper layer. The temperature is lowered to a temperature lower than the glass transition point of pad 21 (temperature in temperature range T2 in FIG. 5) (cooling A in FIG. 4 is performed). Thereby, the rigidity of the polishing pad 2 can be improved once (the rigidity improvement B in FIG. 4 occurs).

That is, even if the polishing pad 2 is worn, the polishing pad 2 can be adjusted to an appropriate rigidity. Therefore, it is possible to suppress an adverse effect (such as dishing due to CMP) due to a decrease in rigidity of the polishing pad 2 due to wear of the polishing pad 2.
Further, since polishing can be performed under appropriate conditions for a long period of time, the life of the polishing pad 2 can be extended, the operating rate of the wafer polishing apparatus 100 can be improved, and the manufacturing cost of the semiconductor device can be reduced. It is.

  According to the embodiment as described above, the rigidity of the polishing pad 2 is adjusted by controlling the temperature of the polishing pad 2 according to the thickness of the polishing pad 2 after wear. In addition, the polishing pad 2 can be adjusted to an appropriate rigidity. Therefore, it is possible to sufficiently suppress an adverse effect due to a decrease in rigidity of the polishing pad 2 due to wear of the polishing pad 2. Thereby, the occurrence of dishing or the like during polishing of the wafer 3 can be suppressed. Therefore, for example, as a resistance value of a wiring formed by a metal embedded structure, a value as designed can be obtained with high accuracy, and a semiconductor device with excellent yield can be manufactured.

<Modification>
In the above embodiment, the example using the polishing pad 2 having the characteristics shown by the solid line in FIG. 5 (for example, the upper pad 21 having the characteristics shown by the solid line in FIG. 5) has been described. Alternatively, a polishing pad having the characteristics shown by the dotted line (for example, the upper layer pad having the characteristics shown by the dotted line in FIG. 5) may be used.
In the case of a general polishing pad (that is, a polishing pad of a modified example), even when the polishing pad is worn to such an extent that the polishing pad needs to be replaced with a new one, the upper layer pad can polish the wafer. It has a certain thickness (however, since the rigidity is insufficient, it is difficult to polish the wafer with good flatness).
Therefore, also in the case of this modification, when the thickness of the polishing pad after wear becomes less than a predetermined thickness, the polishing pad is cooled to a lower temperature than when the polishing pad is thicker than the predetermined thickness. By controlling, the same effect as described above can be obtained.
That is, when the thickness of the polishing pad is equal to or greater than a predetermined thickness, the temperature of the polishing pad is controlled to, for example, the temperature range T1 in FIG. 5, and when the thickness of the polishing pad becomes less than the predetermined thickness, For example, the temperature of the polishing pad may be controlled to a temperature range T2 in FIG.

DESCRIPTION OF SYMBOLS 1 Polishing table 11 Table main body 12 Shaft part 2 Polishing pad 21 Upper layer pad 22 Lower layer pad 3 Wafer 4 Polishing head 5 Cooling part 51 Supply pipe 52 Cooling pipe 53 Pipe 6 Control part 7 Retainer ring 100 Wafer polisher 200 Semiconductor device 201 Interlayer insulation Film 202 Wiring groove 203 Barrier metal film 204 Cu plating film 205 Stopper layer 206 Cu plating film

Claims (5)

A step of polishing the wafer with a polishing pad;
In the step of polishing the wafer, the temperature of the polishing pad is controlled in accordance with the thickness after wear of the polishing pad.   When the thickness of the polishing pad is less than a predetermined thickness, the polishing pad is controlled at a lower temperature than when the thickness of the polishing pad is equal to or greater than the predetermined thickness. Item 14. A method for manufacturing a semiconductor device according to Item 1. When the thickness of the polishing pad is equal to or greater than the predetermined thickness, the temperature of the polishing pad is controlled to a temperature equal to or higher than the glass transition point of the polishing pad,
The temperature of the polishing pad is controlled to a temperature lower than the glass transition point of the polishing pad when the thickness of the polishing pad becomes less than the predetermined thickness. A method for manufacturing a semiconductor device. A polishing table;
A polishing pad provided on the polishing table;
A polishing head for polishing the wafer by moving the wafer relative to the polishing pad in a state where the wafer is in contact with the polishing pad;
A temperature control unit for controlling the temperature of the polishing pad according to the thickness after wear of the polishing pad;
A wafer polishing apparatus comprising: A cooling unit for cooling the polishing pad;
The wafer polishing apparatus according to claim 4, wherein the temperature controller controls the temperature of the polishing pad by controlling the cooling unit.

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