JP2013093809A - Correction circuit and communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times when characteristic correction value of same value is continuously read out from a memory element storing characteristic correction value corresponding to characteristic change of an electric circuit caused by a change in a physical quantity.SOLUTION: A correction circuit 34 includes: a memory 40 in which a correction value and a designation value specifying validity of reading of the correction value from an address to be read next are stored in a plurality of addresses defining a read order; an address generation circuit 41 for generating a reading address of the memory 40 according to the read order; and an enable control circuit 50 for invalidating an enable signal updating a read data of the memory 40 on the basis of a designation value corresponding to a first address when the reading address is changed from the first address to a second address.

Description

  The embodiments discussed herein relate to a correction circuit that corrects a characteristic that an action amount of an electric circuit on an electric signal changes due to a change in a specific physical quantity, and a communication apparatus that uses such a correction circuit.

  The amount of action that an electric circuit exerts on an electric signal has a characteristic that changes due to a change in a specific physical quantity. Examples of such an electric circuit, amount of action, and characteristics include a frequency characteristic of a pass gain of an analog filter, a temperature characteristic of a gain of an analog circuit, and a distortion characteristic of a gain of an output amplifier.

  With respect to such an amount of action, if the characteristic with respect to a change in physical quantity is known, the characteristic can be corrected by multiplying the electrical signal by a correction value having a characteristic opposite to this characteristic. In the present specification, a correction value used for correcting a characteristic of an action amount that an electric circuit has on an electric signal, which changes due to a change in a specific physical quantity, may be referred to as a “characteristic correction value”.

  For example, a radio apparatus having a correction value storage unit that stores a correction value corresponding to the frequency characteristic of an analog circuit and a correction unit that multiplies the correction value by a subcarrier signal is known.

JP 2007-329539 A

  In the case of the above-described wireless device, if the rate of change in the action amount relative to the change in the physical quantity is small, the same correction value may be read continuously when a plurality of correction values for different physical quantities are read from the correction value storage unit. Arise. In such a case, power consumption can be reduced if it is possible to omit reading the same correction value continuously from the memory.

  The disclosed apparatus is intended to reduce the chance that the same correction value is continuously read from a storage element that stores a correction value according to a change in characteristics of an electric circuit caused by a change in a specific physical quantity. To do.

  According to one aspect of the apparatus, a correction circuit is provided. The correction circuit stores a correction value and a designated value for designating whether or not another correction value can be read from at least one address following the address in each of a plurality of addresses for which a reading order is determined, An address generation circuit for generating a read address of the memory according to the read order, and a specified value read from the first address when the read address changes to at least one second address following the first address And an enable control circuit for invalidating an enable signal for updating read data of the memory.

  According to another aspect of the device, a communication device is provided. The communication device includes an analog circuit through which a communication signal that is one of a transmission signal and a reception signal passes, a correction value that corrects the frequency characteristics of the analog circuit in each subcarrier, and a plurality of addresses for which a reading order is determined A memory that stores a specified value that specifies whether or not to read another correction value from at least one address following the address, an address generation circuit that generates a read address of the memory according to the reading order, and a correction value read from the memory A correction circuit that corrects the signal components of the communication signals mapped to the subcarriers, and when the read address changes to at least one second address following the first address, the read signal is read from the first address. Enable to update memory read data based on specified value Comprising an enable control circuit to disable the signal.

  According to another aspect of the device, a communication device is provided. In the communication apparatus, correction values for correcting the frequency characteristics of the analog circuit in each subcarrier are stored in a plurality of addresses arranged in the order of the arrangement of the analog circuit and the subcarrier through which the communication signal that is either the transmission signal or the reception signal passes. A correction circuit that corrects each signal component of the communication signal mapped to the subcarrier based on the correction value read from the memory, and the correction value in the first subcarrier and the second subcarrier adjacent to the first subcarrier An enable control circuit is provided that disables an enable signal for reading the correction value of the second subcarrier from the memory following the correction value of the first subcarrier when the difference from the correction value of the carrier is within a predetermined range.

  According to the correction circuit or the communication device of the present disclosure, the same value of the correction value is continuously read from the storage element that stores the correction value according to the change in the characteristic of the electric circuit caused by the change in the specific physical quantity. Can be reduced.

It is a figure which shows an example of the hardware constitutions of a mobile station apparatus. It is a figure which shows the 1st example of a structural example of a mobile station apparatus. It is a frequency characteristic figure of the passage gain of an analog filter. It is a figure which shows the 1st example of a frequency characteristic correction | amendment part. It is a figure which shows an example of a correction coefficient table. It is a time chart of the signal of each part of the frequency characteristic correction | amendment part of FIG. It is a figure which shows an example of a correction coefficient rewriting part. It is a figure which shows the 2nd example of a frequency characteristic correction | amendment part. It is a time chart of the signal of each part of the frequency characteristic correction | amendment part of FIG. It is a figure which shows the 2nd example of a structural example of a mobile station apparatus. It is a figure which shows an example of the hardware constitutions of a base station apparatus. It is a figure which shows the 1st example of a structural example of a base station apparatus. It is a figure which shows the 2nd example of a structural example of a base station apparatus.

  Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, a characteristic correction circuit that uses a correction coefficient for correcting the frequency characteristic of an analog circuit of a communication device through which a transmission signal or a reception signal passes will be described as an example of a correction value. In the description of an embodiment, a characteristic correction circuit using a correction coefficient for correcting the frequency characteristic of an analog filter that filters a transmission signal or a reception signal will be described more specifically. However, the characteristic correction circuit disclosed in the present specification is not limited to the embodiments described below, and is a circuit that corrects various electric circuit characteristics that change due to a change in a specific physical quantity. Applicable.

  Below, the Example applied to a mobile station apparatus is demonstrated as an example of the apparatus to which the correction circuit of this application is applied. FIG. 1 is a diagram illustrating an example of a hardware configuration of a disclosed mobile station apparatus. The mobile station apparatus 1 modulates a transmission signal in accordance with an SC-FDMA (Single-Carrier Frequency-Division Multiple Access) scheme and demodulates a reception signal in accordance with an OFDMA (Orthogonal Frequency Division Multiple Access) scheme.

  The mobile station apparatus 1 includes an antenna 2, an RF unit (radio unit) 3, a system control unit 4, an application unit 5, and an input / output unit 6. In the accompanying drawings and the following description, the radio frequency may be expressed as “RF”. The antenna 2 receives radio waves coming from the base station apparatus and inputs them to the RF unit 3. The antenna 2 transmits a radio frequency signal output from the RF unit 3 into the space.

  The RF unit 3 converts the digital baseband signal input from the system control unit 4 into an analog signal, converts it into a radio frequency signal, and supplies it to the antenna 2. Further, the RF unit 3 reproduces a baseband signal by converting the frequency of the radio frequency signal input from the antenna 2 and then converting it to a digital signal. The RF unit 3 inputs the reproduced baseband signal to the system control unit 4. The RF unit 3 includes an RF signal processing circuit 10, a low noise amplifier 11, a power amplifier 12, and a switch 13. In the accompanying drawings and the following description, the low noise amplifier, the power amplifier, and the switch may be referred to as “LNA”, “PA”, and “SW”, respectively.

  The RF signal processing circuit 10 performs frequency conversion and filtering of the signal. The LNA 11 and the PA 12 amplify the power of the reception signal and the transmission signal, respectively. The SW 13 switches between transmission and reception by the antenna 2 by time division. The system control unit 4 performs signal processing on digital baseband signals to be transmitted and received, and encoding and decoding of audio signals, image signals, and video signals to be transmitted and received. In the accompanying drawings and the following description, the baseband may be referred to as “BB”. The system control unit 4 includes a BB processing circuit 14 and a multimedia processor 15.

  The BB processing circuit 14 performs signal processing on digital baseband signals to be transmitted and received. In an embodiment, the BB processing circuit 14 may perform signal processing described below by a logic circuit. Such a logic circuit may be realized by, for example, a large scale integrated circuit LSI (Large Scale Integration), an FPGA (Field-Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit). The BB processing circuit 14 may be realized by a processor that executes signal processing described below and a memory that stores a program executed by the processor. The BB processing circuit 14 executes primary modulation / demodulation processing of the baseband signal, modulation processing according to the SC-FDMA scheme, and demodulation processing according to the OFDMA scheme.

  The application unit 5 performs information processing related to user data transmitted and received by the mobile station device 1. The application unit 5 includes an application processor 16 that executes information processing of user data, and a storage unit 17 that stores an application program executed by the application processor 16.

  The input / output unit 6 accepts input of user data to the mobile station apparatus 1 or outputs user data from the mobile station apparatus 1. The input / output unit 6 includes, for example, a microphone 18, a keypad 19, a camera 20, a speaker 21, a display device 22, a memory card slot 23, a GPS (Global Positioning System) device 24, a non-contact IC (integrated circuit) card or reading thereof. A device 25 may be provided.

  FIG. 2 is a diagram illustrating a first example of a configuration example of the mobile station apparatus 1 realized by the hardware illustrated in FIG. Note that FIG. 2 mainly shows functions related to the following description. The mobile station apparatus 1 includes an encoding unit 30, a modulation unit 31, a discrete Fourier transform unit 32, a mapping unit 33, a frequency characteristic correction unit 34, a correction coefficient rewriting unit 35, and an inverse fast Fourier transform unit 36. The processing of these components 30 to 36 is executed by the BB processing circuit 14 shown in FIG. The RF signal processing circuit 10 includes an analog filter 37 for filtering the transmission signal. In the accompanying drawings and the following description, the discrete Fourier transform and the inverse fast Fourier transform may be referred to as “DFT” and “IFFT”, respectively.

  The encoding unit 30 performs channel encoding of the transmission signal. The modulation unit 31 performs primary modulation of the encoded signal. The DFT unit 32 converts the primary modulated transmission signal into a frequency domain signal by DFT processing. The mapping unit 33 maps the frequency domain signal output from the DFT unit 32 to a pre-assigned subcarrier.

  The frequency characteristic correction unit 34 stores a correction coefficient for the frequency characteristic of the pass gain of the analog filter 37. With reference to FIG. 3, the frequency characteristic of the pass gain of the analog filter 37 and its correction coefficient will be described. The magnitude of the passing gain of the signal passing through the analog filter 37 varies depending on the frequency of the passing signal. In FIG. 3, the frequency characteristic of the pass gain is indicated by a solid line.

  The frequency characteristic correction unit 34 stores a correction coefficient for each subcarrier frequency in the built-in memory. The value of the correction coefficient is determined so that the frequency characteristic of the correction coefficient has a characteristic opposite to that of the analog filter 37. In FIG. 3, the frequency characteristic of the correction coefficient is indicated by a one-dot chain line. By multiplying the signal of each subcarrier by this correction coefficient, the gain provided by the frequency characteristic correction unit 34 and the analog filter 37 can be made uniform regardless of the subcarrier.

  Please refer to FIG. The frequency characteristic correction unit 34 corrects the frequency characteristic of the analog filter 37 by multiplying the frequency domain signal by a correction coefficient for each subcarrier.

  The correction coefficient rewriting unit 35 writes the correction coefficient in the built-in memory of the frequency characteristic correction unit 34 when the operation of the mobile station apparatus 1 is started. Alternatively, the correction coefficient rewriting unit 35 rewrites the correction coefficient stored in the built-in memory of the frequency characteristic correction unit 34 when the use frequency band of the mobile station device 1 is changed. The IFFT unit 36 converts the frequency domain signal of each subcarrier corrected by the frequency characteristic correcting unit 34 into a time domain signal by IFFT processing. The time domain signal output from the IFFT unit 36 is filtered by the analog filter 37 and then transmitted to the space via the antenna 2.

  FIG. 4 is a diagram illustrating a first example of the frequency characteristic correction unit 34. The frequency characteristic correction unit 34 includes a memory 40, an address generation unit 41, flip-flops 42i, 42q, 43, 45i, 45q, 47i and 47q, multipliers 44i and 44q, bit cutout units 46i and 46q, a mask signal generation unit 50, and An AND circuit 51 is provided. In the accompanying drawings and the following description, the flip-flop may be referred to as “FF”. The clock signal CLK is given to the address generator 41 and the flip-flops 42i, 42q, 43, 45i, 45q, 47i, and 47q, which are not shown in FIG.

  The n-bit I component signal and Q component signal of the frequency domain signal output from the mapping unit 33 are input to the frequency characteristic correction unit 34 in the order of subcarrier arrangement. The input I component signal and Q component signal are latched by FFs 42i and 42q, respectively. The memory 40 stores correction coefficients to be multiplied for each subcarrier in the order of subcarrier arrangement.

  FIG. 5 is a diagram illustrating an example of a correction coefficient table stored in the memory 40 and storing correction coefficients to be multiplied for each subcarrier. The correction coefficient table may include information elements “subcarrier”, “correction coefficient”, and “specified value”. The information element “subcarrier” indicates an identifier of each subcarrier of the frequency domain signal output from the mapping unit 33.

  The information element “correction coefficient” indicates a correction coefficient to be multiplied to each subcarrier. The information element “designated value” indicates a designated value that designates whether or not the correction coefficient is read from the address next to the storage address of the correction coefficient corresponding to the designated value. In the example of FIG. 5, for example, the value of the correction coefficient multiplied by the first subcarrier to which the identifier “0” is assigned is “a0”. Also, the value of the designated value stored in the correction coefficient table corresponding to this correction coefficient is “v0”. The designated value “v0” indicates whether or not the next address at which this correction coefficient is stored, that is, whether or not the correction coefficient to be multiplied by the first subcarrier to which the identifier “1” is assigned can be read. In this embodiment, the number of bits of each of the information elements “correction coefficient” and “specified value” is m bits and 1 bit.

  For example, the specified value may be flag information indicating whether or not the read is possible by values corresponding to the logical values “L” and “H”, respectively. For example, the specified value has the value “H” when the correction coefficient stored in correspondence with the specified value is the same as the correction coefficient stored at the address next to the storage address of the correction coefficient. Otherwise, it may have the value “L”.

  Please refer to FIG. While the I component signal and the Q component signal are input, the enable signal EN having the value “H” is input to the frequency characteristic correction unit 34. Further, when a pulse signal having a value “H” is input as the timing pulse signal TOP, the timing at which the I component signal and the Q component signal mapped to the leading subcarrier are input is indicated. The address generation unit 41 increments the value of the read address ADD of the memory 40 by the clock signal while the enable signal EN is “H”. When the timing pulse signal TOP is received at the load terminal LD and the I component signal and the Q component signal mapped to the first subcarrier are input, the value of the address ADD is reset to “0”.

  The address ADD output from the address generation unit 41 is input to the address terminal of the memory 40. When the read enable signal REN is “H”, the correction coefficient and the specified value output as data DATA from the memory 40 are updated according to the change of the address. The correction coefficient read from the memory 40 is latched in the FF 43 and is multiplied by the I component signal and the Q component signal by the multipliers 44i and 44q in the next clock cycle.

  The number of effective bits of the I component signal and the Q component signal corrected by multiplying by the correction coefficient increases to k bits, but is then input to the bit extractors 46i and 46q via the FFs 45i and 45q. The number of bits of the I component signal and the Q component signal is reduced by the bit extractors 46i and 46q, and is output from the frequency characteristic correction unit 34 via the FFs 47i and 47q.

  The specified value read from the memory 40 is input to the mask signal generation unit 50. The mask signal generation unit 50 generates a mask signal that invalidates the read enable signal REN of the memory 40 based on the specified value. When the values of the mask signal are “H” and “L”, the read enable signal REN of the memory 40 becomes invalid and valid, respectively. The AND circuit 51 generates a logical product signal of the enable signal EN and the inverted signal of the mask signal generated by the mask signal generation unit 50 as the read enable signal REN. That is, the AND circuit 51 invalidates the read enable signal REN by the mask signal.

  The mask signal generation unit 50 includes an OR operation circuit 52, an AND operation circuit 53, and an FF 54. The OR operation circuit 52 generates a logical sum signal of the timing pulse signal TOP and the mask signal output from the FF 54 to the AND circuit 51. The AND operation circuit 53 generates a logical product signal between the logical sum signal and the logical value designated by the designated value as a mask signal for invalidating the read enable signal REN in a clock cycle for reading data at the next address. .

  When the read enable signal REN is invalidated, the data output from the memory 40 is not updated even if the address ADD output from the address generator 41 changes. Therefore, when the same correction coefficient is stored in consecutive addresses, the reading of the same correction coefficient is avoided by invalidating the read enable signal REN in a period in which the correction coefficient is read from the second address.

  When the value of the timing pulse signal TOP or the mask signal currently invalidating the read enable signal REN is “H” by the OR signal generated by the OR operation circuit 52, the mask signal latched in the FF 54 The value of is reset to “L”. In other cases, if the specified value is “H”, the value of the mask signal latched in the FF 54 is set to “H”.

  The reason why the mask signal is reset to “L” according to the value of the timing pulse signal TOP is that the correction coefficient is always read from the memory 40 when the first subcarrier is input first at the start of the operation. The reason why the mask signal is reset to “L” when the current mask signal value is “H” is to prevent the mask signal value from being fixed to “H”. That is, while the mask signal invalidates the read enable signal REN, the value of the designated value output from the memory 40 is not updated with the previous value “H” indicating that reading is impossible. For this reason, the mask signal generation unit 50 resets the value of the mask signal latched by the FF 54 to “L” during the period when the value of the mask signal output from the FF 54 is “H”.

  Next, a time chart of signals of each part of the frequency characteristic correction unit 34 will be described with reference to FIG. The signals of the first to fourth stages, the seventh stage, and the eighth stage of the timing chart are the clock signal CLK, the timing pulse signal TOP, the enable signal EN, the generation address ADD of the address generation unit 41, the mask signal, and the read enable, respectively. Signal REN is shown. The signals of the fifth stage and the sixth stage of the timing chart indicate the correction coefficient and the designated value stored in the address ADD of the fourth stage.

  Now, frequency domain signals mapped to the first to 1200th subcarriers in the periods T0, T1,... T1199 are input to the frequency characteristic correction unit 34, respectively. In a cycle T (−1) preceding the cycle T0, a timing pulse signal TOP for designating the input timing of the first subcarrier signal is input. Further, the enable signal EN has a value “H” during the periods T0 to T1199 in which the frequency domain signal is input. By the reset by the timing pulse signal TOP and the input of the enable signal EN, the value of the generation address ADD of the address generation unit 41 becomes “0” to “1199” in the periods T0 to T1199, respectively.

  As indicated by the correction coefficient values in the fifth stage, the addresses “0”, “1”, “2”, “3”, “4”, “5”,. 91, “0.92,” “0.92,” “0.93,” “0.93,” “0.93,” and so on are stored. Further, as indicated by the designated value in the sixth row, the addresses “0”, “1”, “2”, “3”, “4”, “5”,. , “H”, “L”, “H”, “H”, “L”... Are stored.

  The same correction coefficient “0.92” is stored in the addresses “1” and “2”. For this reason, the designated value stored at the address “1” is set to “H” so as to stop reading the same correction coefficient as the correction coefficient read from the address “1” in the period T2. Further, the same correction coefficient “0.93” is stored in the addresses “3” to “5”. For this reason, the designated values stored in the addresses “3” and “4” are set to “H”.

  Referring to the seventh stage, the value of the mask signal output from the mask signal generation unit 50 in the periods T2 and T4 is set to “H” due to the designated value “H” read in the periods T1 and T3. Is done. Since the value of the mask signal in period T4 is “H”, the mask signal in period T5 is reset by the OR signal generated by the OR operation circuit 52, and the value of the mask signal becomes “L”.

  Referring to the eighth stage, the read enable signal REN is invalidated and the read enable signal REN is invalidated in the periods T2, T4, T7... In which the mask signal is “H” in the period in which the enable signal EN is “H”. The value of becomes “L”.

  Next, the configuration and processing of the correction coefficient rewriting unit 35 will be described. FIG. 7 is a diagram illustrating an example of the correction coefficient rewriting unit 35. When the mobile station apparatus 1 starts operation or changes the frequency band to be used, the correction coefficient rewriting unit 35 uses the frequency characteristic table storing the compensation coefficient of the frequency characteristic of the analog filter 37 to determine the mobile station apparatus 1. Read the compensation coefficient of the used band. The correction coefficient rewriting unit 35 converts the read compensation coefficient into a correction coefficient that the frequency characteristic correction unit 34 multiplies to the frequency domain signal, and stores the correction coefficient in the correction coefficient table in the memory 40.

  The correction coefficient rewriting unit 35 includes a nonvolatile memory 63, an interpolation unit 60, a coefficient conversion unit 61, and a designated value determination unit 62. The nonvolatile memory 63 stores a frequency characteristic table. The interpolating unit 60 reads out a compensation coefficient corresponding to the range of the used band of the mobile station apparatus 1 from the compensation coefficients c0 to cM of the frequencies f0 to fM stored in the frequency characteristic table. The interpolation unit 60 calculates the compensation coefficient in the subcarrier located between the frequencies for which the compensation coefficient is stored in the frequency characteristic table by linear interpolation.

  The coefficient conversion unit 61 determines the correction coefficient by converting the compensation coefficient calculated by the interpolation unit 60 from a decibel format to a linear value. The converted correction coefficient is stored in a correction coefficient table. The designated value determining unit 62 determines a designated value based on the correction coefficient converted by the coefficient converting unit 61 and stores it in the correction coefficient table.

  According to the present embodiment, when the correction coefficients for the respective subcarriers are sequentially read from the memory 40, if the correction coefficients for the adjacent subcarriers are the same value, it may be omitted to continuously read the same characteristic correction value. it can. As a result, according to the present embodiment, power consumption can be reduced.

  Further, since the correction coefficient for each subcarrier is stored in the memory 40, the correction coefficient can be appropriately rewritten according to individual differences of the analog circuit of the mobile station apparatus 1, for example, the analog filter 37. According to the present embodiment, among the correction coefficients stored in the memory 40, the specified value for specifying which correction coefficient to be read out is also stored in the memory 40. For this reason, the address at which reading of the correction coefficient stored in the memory 40 is omitted can be appropriately changed according to the correction coefficient written in the memory 40.

  Further, the correction coefficient rewriting unit 35 rewrites the correction coefficient stored in the memory 40 in accordance with the change of the use frequency band of the mobile station device 1. According to the present embodiment, by storing the specified value in the memory 40, it is possible to appropriately change which address in the memory 40 the reading of the correction coefficient is omitted when the correction coefficient is rewritten. it can.

  Next, another example of the frequency characteristic correction unit 34 will be described. In the example of the frequency characteristic correction unit 34 described above with reference to FIG. 4, the specified value of the correction coefficient table specifies whether or not to read the correction coefficient from the address next to the storage address of a certain correction coefficient. For example, it is specified whether a certain correction coefficient and the correction coefficient stored at the address next to the storage address have the same value. For this reason, it is possible to omit reading at most once by a designated value stored in one address.

The specified value in the embodiment of the frequency characteristic correcting unit 34 described below specifies one or more addresses following the storage address of a certain correction coefficient, and specifies the number of addresses from which the correction coefficient is not read. For example, the designated value is one or more addresses following a storage address of a certain correction coefficient, and designates the number of addresses in which a correction coefficient having the same value as a certain correction coefficient is stored. If the specified value of K bits is used, the number of addresses from which reading is omitted can be specified in the range of 0 to (2 ^K −1).

  FIG. 8 is a diagram illustrating a second example of the frequency characteristic correction unit 34. Constituent elements similar to those of the frequency characteristic correction unit 34 shown in FIG. 4 are denoted by the same reference numerals as those used in FIG. 4, and description of the same functions is omitted. In the example shown, a specified value of 2 bits is used, but it is easy for those skilled in the art to modify FIG. 8 so that a specified number larger than 2 bits can be used.

  The mask signal generation unit includes AND circuits 54 and 55, OR circuits 56 and 58, and a counter 57. Although the clock signal CLK is given to the counter 57, the illustration is omitted in FIG. The AND circuits 54 and 55 generate logical product signals of the first bit and the second bit of the designated value and the timing pulse signal TOP, respectively, and input them to the count number input terminals D0 and D1 of the counter 57.

  Each time the clock signal is input, the counter 57 counts down by the specified value input to the count number input terminals D0 and D1. The counter 57 outputs the current count value from the output terminals Q0 and Q1. The OR circuit 58 generates a logical sum signal of Q0 and Q1 as a mask signal.

  During counting by the counter 57, since at least one of the outputs Q0 and Q1 is "H", the value of the mask signal is set to "H". As a result, the read enable signal REN is invalidated. When the count ends, the values of Q0 and Q1 both become “L” after the count ends, and the value of the mask signal is set to “L”. As a result, the read enable signal REN is validated. When the timing pulse signal TOP is input, the values of the count number input terminals D0 and D1 are both set to “L”, and the count number of the counter 57 is reset to “0”. Is set to “L”.

  With reference to FIG. 9, the time chart of the signal of each part of the frequency characteristic correction | amendment part 34 of FIG. 8 is demonstrated. The first to fourth stage signals in the timing chart indicate the clock signal CLK, the timing pulse signal TOP, the enable signal EN, and the generation address ADD of the address generation unit 41, respectively. The signals of the fifth stage and the sixth stage of the timing chart indicate the correction coefficient and the designated value stored in the address ADD of the fourth stage. The seventh to ninth stages of the timing chart show the output of the counter 57, the mask signal, and the read enable signal REN, respectively.

  Similar to the description of FIG. 6, the timing pulse signal TOP is input in the period T (−1). Further, the enable signal EN has a value “H” during the periods T0 to T1199 in which the frequency domain signal is input. The value of the generation address ADD of the address generation unit 41 is “0” to “1199” in the periods T0 to T1199, respectively.

  As indicated by the value of the fifth-stage correction coefficient, each of the addresses “0”, “1”, “2”, “3”, “4”, and “5” in the memory 40 has a correction coefficient “0.91”. ”,“ 0.92 ”,“ 0.92 ”,“ 0.93 ”,“ 0.93 ”, and“ 0.93 ”are stored. Further, the correction coefficient “0.94” is stored in the addresses “6”, “7”, “8”, “9”, “10”.

  As shown in the designated values in the sixth row, the addresses “0”, “1”, “3” and “6” of the memory 40 are respectively represented by “00”, “01”, “10” and “00” in binary notation. A designated value of “11” is stored. The decimal values of these designated values are “0”, “1”, “2”, and “3”, respectively.

  The correction coefficient stored at the address “0” is different from the correction coefficient stored at the next address “1”. Therefore, the designated value “00” is stored in the address “0” so that the counter 57 counts after the address “0” and the value of the mask signal does not become “H”.

  In one address “2” following the address “1”, the same correction coefficient as the correction coefficient “0.92” of the address “1” is stored. Therefore, after the address “1”, the counter 57 counts for one clock period, and the specified value “01” is stored in the address “1” so that the value of the mask signal becomes “H” only during that period. Yes.

  In addition, the same correction coefficient as the correction coefficient “0.93” of the address “3” is stored in the two addresses “4” and “5” following the address “3”. Therefore, after address “3”, counter 57 counts for two clock cycles, and the specified value “10” is stored in address “3” so that the value of the mask signal becomes “H” only during that period. Yes.

  Further, the same correction coefficient as the correction coefficient “0.94” of the address “6” is stored in the four addresses “7” to “10” following the address “6”. However, since the maximum number that can be expressed is “3”, the counter 57 counts for 3 clock cycles after the address “6”, and the address of the mask signal becomes “H” only during that period. In “6”, a specified value “11” is stored.

  Referring to the seventh stage, the next periods T1, T2, T4, and T7 after the periods T0, T1, T3, and T6 in which the designated values “00”, “01”, “10”, and “11” are input to the counter 57 are referred to. The output of the counter 57 is “0”, “1”, “2”, and “3”, respectively. For this reason, as a result of the countdown by the counter 57, the outputs of the counter 57 in the periods T3, T5, T6, T8, T9 and T10 are “0”, “1”, “0”, “2”, “1” and “1”, respectively. “0”.

  Referring to the eighth stage, the value of the mask signal is set to “H” in periods T2, T4, T5, T7, T8 and T9 where the output of the counter 57 is not “0”. Referring to the ninth stage, the read enable signal REN is invalidated in the periods T2, T4, T5, T7, T8, and T9 during the period in which the enable signal EN is “H”, and the value of the read enable signal REN is “ L ".

According to the present embodiment, by using a designated value of K bits, reading of a maximum of (2 ^K −1) addresses can be omitted with respect to a designated value stored in one address. For this reason, it is possible to further reduce the number of readings and reduce power consumption.

  Next, another embodiment of the mobile station device 1 will be described. In the mobile station apparatus 1 described above with reference to FIG. 2, the frequency characteristic correction unit 34 corrects the frequency characteristic of the action that the analog circuit through which the transmission signal passes has on the transmission signal. The mobile station apparatus 1 described below includes a frequency characteristic correction unit that corrects a frequency characteristic of an action that an analog circuit through which a reception signal passes has an effect on the reception signal.

  FIG. 10 is a diagram illustrating a second example of the configuration example of the mobile station apparatus 1. FIG. 10 mainly shows functions related to the following description. The mobile station device 1 includes a fast Fourier transform unit 64, a frequency characteristic correction unit 65, a demodulation unit 66, a decoding unit 67, and a correction coefficient rewriting unit 68. The processing of these components 64 to 68 is executed by the BB processing circuit 14 shown in FIG. Further, the RF signal processing circuit 10 includes an analog filter 63 for filtering the received signal. In the accompanying drawings and the following description, the fast Fourier transform may be expressed as “FFT”.

  The FFT unit 64 reproduces the frequency domain signal mapped to the subcarrier from the OFDMA signal received by the antenna 2 and passed through the analog filter 63. The frequency characteristic correction unit 34 corrects the frequency characteristic of the analog filter 63 by multiplying the frequency domain signal by a correction coefficient for each subcarrier. The demodulator 66 reproduces the channel-encoded signal by performing demodulation processing corresponding to the primary modulation on the corrected frequency domain signal. The decoding unit 67 reproduces the received signal by decoding this signal.

  The correction coefficient rewriting unit 68 writes the correction coefficient in the built-in memory of the frequency characteristic correction unit 65 at the start of use of the mobile station device 1 or when the use frequency band is changed. The configuration and processing of the frequency characteristic correction unit 65 and the correction coefficient rewriting unit 68 may be the same as the configuration and processing of the frequency characteristic correction unit 34 and the correction coefficient rewriting unit 35 described above.

  As shown in the present embodiment, the characteristic correction circuit and its processing disclosed in this specification can be applied not only to the transmission circuit but also to the reception circuit.

  Next, another embodiment of the communication device will be described. The characteristic correction circuit and its processing disclosed in this specification can be applied not only to the mobile station apparatus 1 but also to a communication circuit that transmits and receives radio signals in the base station apparatus.

  FIG. 11 is a diagram illustrating an example of a hardware configuration of the base station apparatus. Base station apparatus 70 demodulates the received signal according to the SC-FDMA scheme, and modulates the transmission signal according to the OFDMA scheme. The base station device 70 includes an antenna 71, an RF unit 72, a BB processing unit 73, a control unit 74, and a network interface 75.

  The antenna 71 receives radio waves coming from the mobile station apparatus 1 and inputs them to the RF unit 72. The antenna 71 transmits a radio frequency signal output from the RF unit 72 into the space. The RF unit 72 converts the digital BB signal input from the BB processing unit 73 into an analog signal, converts the signal into a radio frequency signal, and supplies the signal to the antenna 71. Further, the RF unit 72 reproduces the BB signal by converting the frequency of the radio frequency signal input from the antenna 71 and then converting it to a digital signal. The RF unit 72 inputs the reproduced BB signal to the BB processing unit 73. The RF unit 72 includes an RF signal processing circuit 76, an LNA 77, a PA 78, and an SW 79. The functions of these components 76 to 79 are the same as those of the RF signal processing circuit 10, LNA 11, PA 12, and SW 13 in FIG.

  The BB processing unit 73 performs signal processing on digital baseband signals to be transmitted and received. In an embodiment, the BB processing unit 73 may perform signal processing described below using a logic circuit. Such a logic circuit may be realized by, for example, a large scale integrated circuit LSI (Large Scale Integration), an FPGA (Field-Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit). The BB processing unit 73 may be realized by a processor that executes signal processing described below and a memory that stores a program executed by the processor. The BB processing unit 73 executes primary modulation / demodulation processing of the baseband signal, modulation processing according to the SC-FDMA scheme, and demodulation processing according to the OFDMA scheme.

  The control unit 74 performs control processing of the base station device 70 such as resource control processing assigned to each mobile station device 1, handover processing, call connection processing, and the like. In an embodiment, the control unit 74 may perform signal processing described below using a logic circuit. Such a logic circuit may be realized by, for example, a large scale integrated circuit LSI (Large Scale Integration), an FPGA (Field-Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit). The control unit 74 may be realized by a processor that executes signal processing described below and a memory that stores a program executed by the processor. The network interface 75 performs signal processing for transmission and reception of signals between the base station device 70 and other base station devices or higher-level network devices via a wired network.

  FIG. 12 is a diagram illustrating a first example of a configuration example of the base station apparatus 70. FIG. 12 mainly shows functions related to the following description. The BB processing unit 73 includes an encoding unit 85, a modulation unit 86, a frequency characteristic correction unit 87, an IFFT unit 88, and a correction coefficient rewriting unit 89. The RF signal processing circuit 76 includes an analog filter 90 for filtering the transmission signal.

  The encoding unit 85 performs channel encoding of the transmission signal. The modulation unit 86 performs primary modulation of the encoded signal. The frequency characteristic correction unit 87 corrects the frequency characteristic of the analog filter 90 by multiplying each frequency domain signal mapped to each subcarrier by a correction coefficient. The IFFT unit 88 generates an OFDMA signal by performing IFFT processing on the frequency domain signal. The OFDMA signal is transmitted from the antenna 71 after passing through the analog filter 90 of the RF signal processing circuit 76.

  The correction coefficient rewriting unit 89 rewrites the correction coefficient used by the frequency characteristic correction unit 87 when the use frequency band assigned to the mobile station apparatus 1 is changed at the start of use of the mobile station apparatus 1 as the transmission partner. The processing of the frequency characteristic correction unit 87 and the correction coefficient rewriting unit 89 may be the same as the processing of the frequency characteristic correction unit 34 and the correction coefficient rewriting unit 35 described above.

  As shown in the present embodiment, the characteristic correction circuit and its processing disclosed in the present specification can be applied not only to the mobile station apparatus but also to correction in the transmission circuit of the base station apparatus.

  Next, another embodiment of the base station device 70 will be described. The base station apparatus 70 may include a frequency characteristic correction unit that corrects a frequency characteristic of an action that the analog circuit through which the reception signal passes has an effect on the reception signal. FIG. 13 is a diagram illustrating a second example of the configuration example of the base station device 70. FIG. 13 mainly shows functions related to the following description. The base station device 70 includes an FFT unit 92, a frequency characteristic correction unit 93, a demapping unit 94, an inverse discrete Fourier transform unit 95, a demodulation unit 96, a decoding unit 97, and a correction coefficient rewriting unit 98. The RF signal processing circuit 76 includes an analog filter 91 for filtering the received signal. In the accompanying drawings and the following description, the inverse discrete Fourier transform may be expressed as “IDFT”.

  The FFT unit 92 reproduces the frequency domain signal mapped to the subcarrier from the SC-FDMA signal received by the antenna 71 and passed through the analog filter 91. The frequency characteristic correction unit 93 corrects the frequency characteristic of the analog filter 91 by multiplying the frequency domain signal by a correction coefficient for each subcarrier.

  The demapping unit 94 extracts a frequency domain signal assigned to each mobile station apparatus 1 from the frequency domain signals mapped to the subcarriers. The IDFT unit 95 converts the frequency domain signal extracted by performing the IDFT processing into a time domain signal. The demodulation unit 96 reproduces the channel-coded signal by performing demodulation processing corresponding to the primary modulation on the converted time domain signal. The decoding unit 97 reproduces the received signal by decoding this signal.

  The correction coefficient rewriting unit 98 rewrites the correction coefficient used by the frequency characteristic correction unit 93 at the start of use of the mobile station apparatus 1 that is the transmission partner or when the use frequency band assigned to the mobile station apparatus 1 is changed. . The processing of the frequency characteristic correction unit 93 and the correction coefficient rewriting unit 98 may be the same as the processing of the frequency characteristic correction unit 34 and the correction coefficient rewriting unit 35 described above.

  As shown in the present embodiment, the characteristic correction circuit and its processing disclosed in this specification can be applied not only to the transmission circuit of the base station apparatus but also to the reception circuit.

DESCRIPTION OF SYMBOLS 1 Mobile station apparatus 34 Frequency characteristic correction | amendment part 37 Analog filter 40 Memory 41 Address generation part 50 Mask signal generation part 70 Base station apparatus

Claims (9)

A memory in which a correction value and a specified value for designating whether or not to read the correction value from the next read address are stored in each of the plurality of addresses for which the reading order is determined,
An address generation circuit for generating a read address of the memory according to the read order; and
Enable control for invalidating an enable signal for updating read data of the memory based on a designated value corresponding to the first address when the read address changes to a second address read next to the first address circuit,
A correction circuit comprising:   The correction circuit according to claim 1, wherein the enable control circuit includes an enabling circuit that enables the enable signal when the read address changes after the enable signal is disabled. The specified value is a logical value indicating whether or not a correction value can be read from the second address next to the first address,
The enable control circuit includes a latch circuit that latches the designated value given as an input signal and outputs it as a mask signal of the enable signal,
The correction circuit according to claim 2, wherein the validation circuit includes a reset circuit that resets the input signal of the latch circuit according to the mask signal.   The specified value is a logical value indicating that the characteristic correction value stored at the first address is the same as the characteristic correction value stored at an address next to the first address. Item 4. The characteristic correction circuit according to any one of Items 1 to 3. The designated value designates the number of the second addresses from which correction values are not read,
A counter circuit that starts counting the number of changes in the read address corresponding to the value of the designated value when the read address changes to the second address; and
The correction circuit according to claim 2, further comprising a mask signal generation circuit that outputs a mask signal of the enable signal during counting by the counter circuit.   2. The designated value designates the number of addresses following the first address in which a characteristic correction value having the same value as the characteristic correction value stored in the first address is stored. The characteristic correction circuit according to any one of 2 and 5. The memory is a rewritable memory,
The correction circuit according to claim 1, further comprising a rewrite circuit that rewrites the correction value stored in the memory and the specified value. An analog circuit through which a communication signal that is either a transmission signal or a reception signal passes,
A correction value for correcting the frequency characteristic of the analog circuit in each subcarrier and a specified value for specifying whether or not to read the correction value from the next read address are stored in each of the plurality of addresses for which the reading order is determined. memory,
An address generation circuit for generating a read address of the memory according to the read order;
A correction circuit that corrects signal components of the communication signal mapped to subcarriers based on correction values read from the memory; and
Enable control for invalidating an enable signal for updating read data of the memory based on a designated value corresponding to the first address when the read address changes to a second address read next to the first address circuit,
A communication apparatus comprising: An analog circuit through which a communication signal that is either a transmission signal or a reception signal passes,
A memory in which correction values for correcting the frequency characteristics of the analog circuit in each subcarrier are stored in a plurality of addresses arranged in the order of subcarrier arrangement,
A correction circuit that corrects each signal component of the communication signal mapped to a subcarrier based on a correction value read from the memory; and
When the difference between the correction value in the first subcarrier and the correction value in the second subcarrier adjacent to the first subcarrier is within a predetermined range, the correction value in the first subcarrier is followed from the memory by the first subcarrier. An enable control circuit for disabling an enable signal for reading a correction value of two subcarriers;
A communication device comprising:

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