JP2013093508A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows stably exposing an electrode even if manufacturing variation occurs.SOLUTION: A semiconductor device according to the present embodiment in which a semiconductor chip is sealed and including a unit package having a first primary surface and a second primary surface facing the first primary surface is provided with a lead frame, in the unit package, having an electrode including a first portion provided on the first primary side and a second portion including a circular arc portion exposed from the second primary surface. The electrode is electrically connected to an electrode of the semiconductor chip.

Description

  Embodiments described herein relate generally to a semiconductor device.

  In a resin-encapsulated electronic component device having a semiconductor chip inside and having a second main surface facing the first main surface, the first main surface and the second main surface One having a plurality of external connection terminals arranged on each surface is known. For example, a plurality of external connection terminals integrally form a terminal upper part, a terminal intermediate part, and a terminal lower part, and are exposed to one main surface at least at the terminal upper part, and the terminal intermediate part is inclined with respect to one main surface. In this electronic component device, the upper part of the terminal and the lower part of the terminal are bent at both ends of the intermediate part of the terminal and are substantially parallel to one main surface.

JP 2009-152329 A

  The embodiment provides a semiconductor device that can stably expose an electrode even when manufacturing variation occurs.

  According to the semiconductor device of this embodiment, in the semiconductor device including a unit package that has a semiconductor chip sealed therein and has a first main surface and a second main surface opposite to the first main surface. A unit package includes a lead frame having an electrode provided with a first portion provided on the first main surface side and a second portion including an arc portion exposed from the second main surface, It is electrically connected to the electrode of the semiconductor chip.

1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment. FIG. 2A is a diagram illustrating a configuration of a unit package in the semiconductor device of the first embodiment, and FIG. 2B is a diagram illustrating XX in FIG. FIG. 3A is a side view showing the portion 35 of the first embodiment, and FIG. 3B is a top view showing the portion 35 of the first embodiment. 1 is a block diagram showing a configuration of a NAND flash memory according to a first embodiment. The figure which shows the threshold value distribution of the memory cell of 1st Embodiment. FIG. 6A is a top view showing the lead frame of the first embodiment, and FIG. 6B is a bottom view showing the lead frame of the first embodiment. FIG. 7A is a top view showing a state where the semiconductor chip is placed on the lead frame of the first embodiment, and FIG. 7B is a bottom view showing a state where the semiconductor chip is placed on the lead frame of the first embodiment. FIG. FIG. 6 is a view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 9A is a top view showing a plurality of unit packages connected together, and FIG. 9B is a bottom view showing the plurality of unit packages connected in FIG. 9A. The top view which shows the part 35 of the modification 1. FIG. The figure which shows the unit package of the modification 2. The figure which shows the correspondence of the voltage applied to the electrode of semiconductor chip 32a-32h, and the bonding part 31d in the modification 3. FIG. 9 is a correspondence table showing voltages applied to CADD0 and CADD1 of each semiconductor chip 32 in Modification 3. FIG. 11 is a side view showing a state where a semiconductor chip is placed on a lead frame in Modification 4;

(First embodiment)
Next, a first embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[Configuration of semiconductor device]
The semiconductor device according to the first embodiment will be described with reference to FIG.

  As illustrated in FIG. 1, for example, a BGA type semiconductor device 100 includes a glass epoxy substrate 10, solder balls 20, a plurality of unit packages, and 30 a to 30 d. As shown in FIG. 1, for example, the plurality of unit packages 30 a to 30 d are stacked on the glass epoxy substrate 10 in the vertical direction.

<Garaepo substrate>
The glass epoxy substrate 10 has a plurality of electrodes (not shown) on its surface. This electrode is electrically connected to the electrode of the unit package 30a. Inside the glass epoxy substrate 10, wiring for electrically connecting the electrodes of the glass epoxy substrate 10 and the solder balls 20 is provided.

<Unit package>
The configuration and connection relationship of the unit packages 30a to 30d of the present embodiment will be described with reference to FIGS. 2A is a cross-sectional view showing only the unit package 30a of FIG. 1, for example, and FIG. 2B is a cross-sectional view showing an XX cross section of FIG. 2A.

  As shown in FIGS. 1 and 2, the unit packages 30a to 30d include a lead frame 31 (wiring 31a, electrode first portion 31b, electrode second portion 31c, bonding portion 31d), and a plurality of semiconductor chips 32a to 32h. (For convenience of explanation, when a semiconductor chip is generally shown, it is described as a semiconductor chip 32), a bonding wire 33, and a mold resin 34 are provided.

  As shown in FIG. 1, the lead frame 31 includes a wiring 31a, an electrode first portion (P1) 31b, an electrode second portion (P2) 31c, and a bonding portion 31d.

  For example, the wiring 31 a is disposed below the plurality of semiconductor chips 32. The first portion 31b of the electrode is connected to one end of the wiring 31a. The second part (P2) 31c of the electrode is connected to one end of the wiring 31a in common with the first part 31b. On the other hand, the bonding portion 31d is connected to the other end of the wiring 31a.

  The wiring 31a is integrated with the first portion 31b, the second portion 31c, and the bonding portion 31d. Further, the wiring 31a extends in the X direction in FIG. 2A, and is separated at a desired pitch in the Y direction as shown in FIG. 2B. The wiring 31a and the bonding portion 31d are formed at a desired distance above the first main surface of the unit packages 30a to 30d. The surface on the second main surface side of the wiring 31a and the bonding portion 31d and the surface on the second main surface side of the lead frame 31b are formed flush with each other.

  The first portion 31b and the bonding portion 31d form a line in the Y direction in FIG. For example, in FIG. 2, the first portion 31b is arranged in the depth direction (positive direction in the Y direction) with respect to the bonding 31d. In FIG. 2, the mold resin just below the bonding 31 d is omitted for the sake of clarity.

  Mold resin is formed between the wiring 31a, the bonding portion 31d, and the first main surfaces of the unit packages 30a to 30d (first resin holding portion 36 in FIG. 2A). When the lead frame 31 is placed on a mold (details will be described later) before forming the mold resin, a space is formed. In the step of forming the mold resin, the mold resin flows into this space and becomes the resin holding portion 36.

  The first portion 31b is formed on the first main surface side of each of the unit packages 30a to 30d and exposed to the outside.

  Moreover, it has the circular part exposed from the 2nd part 31c and a 2nd main surface, and it extends in a Z direction and a X direction. That is, the second portion 31c extends in the X direction when extending from the first main surface side to the second main surface side of the unit packages 30a to 30d, and is inclined with respect to the first portion 31b or the bonding portion 31d. It is formed. The angle formed by this inclination and the first portion 31b or the bonding portion 31d is preferably 45 degrees or less. When the angle formed by the first portion 31b or the bonding portion 31d and the second portion 31c is 45 degrees or less, when the second portion 31c and the mold die come into contact with each other in the step of forming the mold resin, the second portion 31c It is easy to reduce the bending height variation of the second portion 31c and the stop position variation of the mold surface. However, the present invention is not limited to this, and the second portion 31c may be inclined in any form as long as it gently extends toward the second main surface.

  As described above, the second portion 31c has an arc portion exposed from the second main surface of each of the unit packages 30a to 30d.

  A specific configuration of the portion 35 including the second portion 31c and the first portion 31b in FIG. 2A will be described with reference to FIG. FIG. 3B is a top view of the portion 35 shown corresponding to the side view of FIG.

  As shown in FIG. 3B, the first portions 31b and the second portions 31c are alternately arranged in the Y direction. The first portion 31b and the second portion 31c are connected to one end of the wiring 31a. The bonding part 31d is arranged in a part different from the first part 31b and the second part 31c.

  As shown in FIG. 1, the bonding portion 31d is connected to the electrodes of the plurality of semiconductor chips 32 through wires. The bonding part 31d is connected to the first part 31b via the wiring 31a. As a result, each electrode of the semiconductor chip 32 is electrically connected to the solder ball 20.

  The second part 31c of the unit package 30a is connected to the first part 31b of the unit package 30b. Similarly, the second portions 31c of the unit packages 30b and 30c are connected to the first portions 31b of the unit packages 30c and 30d, respectively. As shown in FIG. 1, the unit package 30d has no second portion of the electrodes.

  Although omitted in FIG. 1, each of the unit packages 30a to 30d also includes an electrode including a third portion having the same shape as the first portion and a fourth portion having the same shape as the second portion. The electrode including the third portion and the fourth portion is different from the electrode including the first portion and the second portion in that the electrode is not connected to the wiring 31a.

  When the semiconductor chips 32 in the unit packages 30a to 30d are divided into a plurality of groups and operated independently for each group, a chip enable signal (CE), a ready / busy signal (R / B) etc. are different from chip enable signals (CE), ready / busy signals (R / B), etc. of other groups. In order to input a different signal for each group, it is necessary to connect to different solder balls 20.

  For example, the electrode including the third part and the fourth part in the unit package 30c is supplied with the chip enable signal (CE) and the ready / busy signal (R / B) of the unit package 30d above the unit package 30c. It has a function of relaying to the lower unit package 30b.

  For example, the chip enable signal (CE) of the unit package 30 d is input from a certain solder ball 20. The chip enable signal (CE) is electrically connected to the electrodes including the fourth portion and the third portion of the unit package 30a electrically connected to the solder ball 20 via the glass epoxy substrate 10 and the electrodes. Electrode including the fourth part and the third part of the unit package 30b, an electrode including the fourth part and the third part of the unit package 30c electrically connected to the electrode, and an electrode including the first part 31b of the unit package 30d Is input to the unit package 30d.

<< Semiconductor chip >>
Next, the semiconductor chip 32 of the present embodiment will be described using a NAND flash memory as an example with reference to the block diagram of FIG.

  As shown in FIG. 4, the NAND flash memory 32 includes a memory cell array 1000, row data 2000, a driver circuit 3000, a voltage generation circuit 4000, a data input / output circuit 5000, a control unit 6000, a source line driver circuit 7000, and a sense amplifier 8000. Have.

4-1. Configuration example of memory cell array 1000
The memory cell array 1000 includes blocks BLK0 to BLKs including a plurality of nonvolatile memory cell transistors MT (s is a natural number). Each of the blocks BLK0 to BLKs includes a plurality of NAND strings 1001 in which nonvolatile memory cell transistors MT are connected in series. Each of the NAND strings 1001 includes, for example, 64 memory cell transistors MT and select transistors ST1 and ST2.

  The memory cell transistor MT can hold data of two or more values. The memory cell transistor MT has a floating gate (charge conductive layer) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween, and a control formed on the floating gate with an inter-gate insulating film interposed. An FG structure including a gate. The structure of the memory cell transistor MT may be a MONOS type. The MONOS type includes a charge storage layer (for example, an insulating film) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film (hereinafter, referred to as a dielectric constant higher than the charge storage layer). And a control gate formed on the block layer.

  The control gate of the memory cell transistor MT is electrically connected to the word line WL, the drain is electrically connected to the bit line BL, and the source is electrically connected to the source line SL. Memory cell transistor MT is an n-channel MOS transistor. The number of memory cell transistors MT is not limited to 64, but may be 128, 256, 512, etc., and the number is not limited.

  The adjacent memory cell transistors MT share the source and drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cell transistors MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to any one of the word lines WL0 to WL63, and the gate electrodes of the select transistors ST1 and ST2 of the memory cell transistors MT in the same row are select gate lines SGD1, Commonly connected to SGS1. For simplification of description, the word lines WL0 to WL63 may be simply referred to as word lines WL in the following when they are not distinguished. Further, the drains of the select transistors ST1 in the same column in the memory cell array 1 are commonly connected to any one of the bit lines BL1 to BL (n + 1). Hereinafter, the bit lines BL1 to BL (n + 1) are collectively referred to as a bit line BL (n: natural number) unless they are distinguished. The sources of the selection transistors ST2 are commonly connected to the source line SL.

  Data is collectively written in the plurality of memory cell transistors MT connected to the same word line WL, and this unit is called a page. Further, data is erased from the plurality of memory cell transistors MT in a unit of block BLK.

4-2. Threshold distribution of memory cell transistor MT
The threshold distribution of the memory cell transistor MT will be described with reference to FIG. FIG. 5 is a graph in which the horizontal axis indicates the threshold distribution (voltage) and the vertical axis indicates the number of memory cell transistors MT.

  As shown in the drawing, each memory cell transistor MT can hold, for example, binary (2-levels) data (1-bit data). That is, the memory cell transistor MT can hold two types of data “1” and “0” in ascending order of the threshold voltage Vth.

  The threshold voltage Vth0 of “1” data in the memory cell transistor MT is Vth0 <V01. The threshold voltage Vth1 of “0” data is V01 <Vth1. As described above, the memory cell transistor MT can hold 1-bit data of “0” data and “1” data according to the threshold value. The memory cell transistor MT is set to “1” data (for example, negative voltage) in the erased state, and is set to a positive threshold voltage by writing data and injecting charge into the charge storage layer.

4-3. About Row Decoder 2000
Returning to FIG. 4, the row decoder 2000 will be described. The row decoder 2000 includes a block decoder 2004 and transfer transistors (N-channel MOS transistors) 2001 to 2003. The block decoder 2004 decodes the block address given from the control unit 6000 at the time of data write operation, read operation, and erase, and selects the block BLK based on the result. A block selection signal is transferred from the block decoder 2004 to the transfer transistors 2001 to 2003. As a result, the transfer transistors 2001 to 2003 are turned on. Thus, based on the block selection signal supplied from the block decoder 2004, the row decoder 2000 transfers the voltages supplied from the driver circuit 3 to the select gate lines SGD1 and SGS1 and the word lines WL0 to WL63, respectively.

4-4. About Driver Circuit 3000 The driver circuit 3000 includes select gate line drivers 3001 and 3002 provided for the select gate lines SGD1 and SGS1, and a word line driver 3003 provided for each word line WL. In the present embodiment, the word line driver 3003 and the select gate line drivers 3001 and 3002 are provided in the blocks BLK0 to BLKs.

  The select gate line driver 3001 transfers, for example, a signal sgd to the gate of the select transistor ST1 via the select gate line SGD1 when data is written, read, erased, and further when data is verified. The signal sgd is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD (for example, 1.8 [V]) when the signal is at the “H” level.

  Similarly to the select gate line driver 3001, the select gate line driver 3002 passes through the select gate line SGS1 of the selected block BLK, for example, through the select gate line SGS1 at the time of data writing, reading, and data verification. The signal sgs is transferred to the gate of the selection transistor ST2. The signal sgs is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD when the signal is at the “H” level.

4-4. Voltage Generation Circuit 4000 The voltage generation circuit 4000 generates a voltage necessary for data programming, reading, and erasing by stepping up or down a voltage applied from the outside. The generated voltage is supplied to the driver circuit 3000.

4-5. About the data input / output circuit 5000 The data input / output circuit 5000 receives an address (row address, column address, block address; row address and column address) supplied from, for example, a host outside the NAND flash memory 32 via an electrode (not shown). Are also referred to as page addresses) and commands are output to the control unit 6000. The data input / output circuit 5000 outputs write data to the sense amplifier 8000 via the data line Dline.

  In addition, when outputting data read from the memory cell array 1000 to the outside of the NAND flash memory 32, the data input / output circuit 5000 converts the data amplified by the sense amplifier 8000 to the data line under the control of the control unit 6000. After receiving the data via Dline, the data is output to the outside of the NAND flash memory 32 via the electrode.

4-6. Control Unit 6000 The control unit 6000 controls the operation of the entire NAND flash memory 32. That is, the operation sequence in the data write operation, read operation, and erase operation is executed based on the address and command given from the outside of the NAND flash memory 32 via the data input / output circuit 5000. The controller 6000 generates a block selection signal, a column selection signal, and a row selection signal based on the address and the operation sequence.

  The control unit 6000 outputs the above-described block selection signal and row selection signal to the row decoder 2000. In addition, the control unit 6000 outputs a column selection signal to a column decoder (not shown). The column selection signal is a signal for selecting the column direction of the sense amplifier 8000.

  The control unit 6000 is given a control signal supplied from a memory controller connected to the outside of the NAND flash memory 32. The control unit 6000 distinguishes whether the signal supplied from the outside of the NAND flash memory 32 via the electrode to the data input / output circuit 5 is an address or data based on the supplied control signal.

4-7. Sense Amplifier 8000 The sense amplifier 8000 senses and amplifies data read from the memory cell transistor MT to the bit line BL when reading data. Specifically, after precharging the bit line BL to a predetermined voltage, the bit line BL is discharged by the NAND string 11 selected by the row decoder 2000, and the discharge state of the bit line BL is sensed. That is, the sense amplifier 8000 amplifies the voltage of the bit line BL and senses data stored in the memory cell transistor MT.

  At the time of data writing, write data is transferred to the corresponding bit line BL.

4-8. About Column Decoder A column decoder (not shown) decodes a column address given from the control unit 6000 and outputs a column selection signal to the sense amplifier 8000. Based on this column selection signal, a desired latch circuit in the sense amplifier 8000 is selected.

<< Mold resin >>
The mold resin 34 is obtained by curing an epoxy resin, for example. Since the mold resin is composed of an epoxy resin, for example, a functional group such as a hydroxyl group, an aldehyde group, or a methyl group is included.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. FIG. 6A is a top view showing the lead frame of the first embodiment, and FIG. 6B is a bottom view showing the lead frame of the first embodiment.

  (1) First, a lead frame 31 as shown in FIG. 6 is prepared. FIG. 6A shows an example in which four unit packages 30 are formed. In addition, it is not limited to the case where four unit packages 30 are formed, For example, you may form 8, 16, 32 pieces simultaneously.

  As shown in FIG. 6A, the lead frame 31 has a region 37a on which a plurality of semiconductor chips 32 are placed, an outer side of the region 37a, and a region 37b used on the unit package 30 and a region outside the region 37b. 37c.

  As shown in FIG. 6, for example, the wiring 31a is arranged in the region 37a. Further, the electrodes (first portion 31b, second portion 31c) and bonding portion 31d of the unit package 30 are arranged in the region 37b.

  Further, as shown in FIG. 6B, on the back surface of the lead frame 31, there is a space that becomes a resin reservoir 41 in the region 37c after filling with mold resin. This space is indicated by the hatched portion in FIG. A portion corresponding to the resin reservoir 41 becomes a space when the lead frame 31 is placed before the molding resin is formed. When the mold resin is filled in this space in the step of forming the mold resin, a resin reservoir 41 is formed.

  The space serving as the resin reservoir 41 is connected to the resin holding portion 36 via the flow path 42. That is, when the lead frame 31 is placed before forming the mold resin, the space that becomes the resin holding portion 36, the resin reservoir 41, and the flow path 42 is integrally formed. When forming the mold resin, the mold resin filled in the space that becomes the resin holding portion 36 flows into the flow path 42 when the space that becomes the resin holding portion 36 overflows with the mold resin. As a result, the mold resin finally flows into the space that becomes the resin reservoir 41.

  The resin reservoir 41 is formed in the region 37 c and is not a portion that becomes the unit package 30. In the step of forming the mold resin, the air in the mold die collected in the resin holding portion 36 can be discharged together with the mold resin to the resin reservoir 41 through the flow path 42. As a result, air does not enter the resin holding portion 36 constituting the unit package 30, and no shape distortion or the like is formed. Therefore, the reliability of the unit package 30 of the present embodiment can be improved.

  A method for forming the shape of the lead frame 31 will be briefly described.

  In general, a lead frame is manufactured by pressing or etching, but as shown in FIG. 6, a lead frame 31 having 31a and 31d parts processed thinner than other leads cannot be manufactured by pressing. , Manufactured by etching.

  On the second main surface side of the lead frame material, a photoresist to which the pattern of the leads 31a, 31b, 31c, 31d is transferred is formed.

On the other hand, only the patterns of the leads 31b and 31c are transferred to the first main surface side.

For 31a and 31d thinner than the other leads, the lead pattern is not transferred to the first main surface side,
The entire areas 31a and 31d are large openings for photoresist.

  If the lead pattern is not as fine as this embodiment, it is possible to form all the lead patterns 31a, 31b, 31c, 31d including the leads 31a, 31d by a single etching process, including the leads 31a, 31d. .

  However, in this embodiment, the leads 31a and 31d become thin while the entire first main surface side of the 31a and 31d areas is thinly etched, so that the etching process is performed in two steps.

  First, a protective sheet is affixed to the second main surface side, and the entire opening areas 31a and 31d on the first main surface side and 31b and 31c are etched by about 1/4 of the material thickness. Thereafter, the protective sheet is peeled off and etched from both the first main surface side and the second main surface side. The lead frame 31 for this embodiment is completed by removing the photoresist.

  (2) Next, as shown in FIG. 7, a plurality of semiconductor chips 32 are mounted on the wiring 31a of the lead frame 31 having a desired shape. 7A is a top view showing a state where the semiconductor chip is placed on the lead frame of the first embodiment, and FIG. 7B is a state where the semiconductor chip is placed on the lead frame of the first embodiment. It is a bottom view shown.

  For example, as shown to Fig.7 (a), several semiconductor chips 32a-32h are shifted and laminated | stacked through an adhesive agent so that each electrode of semiconductor chips 32a-32h may be exposed.

  After the plurality of semiconductor chips 32 a to 32 h are stacked, the electrodes of the semiconductor chips 32 a to 32 h are connected to the corresponding bonding portions 31 d of the lead frame 31.

(3) Then, as shown in FIG. 8, the lead frame 31 on which the plurality of semiconductor chips 32 a to 32 h are placed is set in the mold dies 51 to 53. FIG. 8 is a diagram illustrating the method for manufacturing the semiconductor device of the first embodiment. In FIG. 8, a compression mold will be described as an example. For example, a transfer mold may be used.

  The mold 51 is fixed, and mold resin is formed by moving the molds 52 and 53. The lead frame 31 on which the plurality of semiconductor chips 32 a to 32 h are placed is adsorbed by the vacuum hole 54.

  Mold resin is put in a state where the mold dies 52 and 53 are sufficiently separated from the mold 51 (in FIG. 8, the mold dies 52 and 53 are lowered). After that, the mold dies 52, 53 are raised toward the mold dies 51, and the lead frame 31 is clamped with the mold dies 51, 53. The mold 53 stops when it reaches the lead frame 31. After that, the mold die 52 is further raised, and the mold die 52 stops when the mold resin is filled in the space surrounded by the mold dies 51 to 53.

  When the mold 52 stops, the height of the second portion 31c is controlled so that the second portion 31c contacts the inner surface of the mold 52. That is, the second portion 31 c is set to such a height that the second portion 31 c comes into contact with the inner surface of the mold 52 even if the position where the mold die 52 stops varies.

  Therefore, when the mold die 52 stops, the second portion 31 c comes into contact with the inner surface of the mold die 52.

  Then, mold curing is performed to cure the mold resin. Thereafter, the mold dies 52 and 53 are lowered, and the suction of the vacuum holes 54 is stopped to take out the unit package 30.

(4) Therefore, as shown in FIG. 9, a plurality of unit packages connected to each other are formed. The electrode P1 is exposed and formed on the first main surface of the connected plurality of unit packages, and the electrode P2 is formed on the second main surface as shown in FIG. 9B.

  A dicing process is performed on the connected unit packages to separate the unit packages 30a to 30d.

  (5) The unit packages 30 a to 30 d are stacked on the glass epoxy substrate 10. Also, solder balls 20 are formed under the glass epoxy substrate 10 (the surface opposite to the surface on which the unit packages 30a to 30d are stacked).

[Effect of the first embodiment]
As described above, the embodiment can provide a semiconductor device that can stably expose an electrode even if manufacturing variation occurs. This will be specifically described below.

  In the semiconductor device of this embodiment, a plurality of external connection terminals integrally form a terminal upper part, a terminal intermediate part, and a terminal lower part, and are exposed to at least one main surface at the terminal upper part, and the terminal intermediate part is one main part. Comparison is made with an electronic component device (comparative example) which is inclined with respect to the surface, and the terminal upper portion and the terminal lower portion are bent at both ends of the terminal intermediate portion and substantially parallel to one main surface.

  In the electronic component device of the comparative example, the upper portion of the terminal is formed substantially parallel to the main surface. In the process of molding the resin as shown in FIG. 8 of the present embodiment, the distance that one mold die 52, 53 approaches the other mold die 51 has manufacturing variations. In particular, since the stop position of the mold 52 changes depending on the amount of mold resin put in the mold, the manufacturing variation increases.

  Similarly, the height of the second portion and the degree of bending also have manufacturing variations. Therefore, when this molding process is performed in the manufacturing process of the electronic component device of Comparative Example 1, due to these manufacturing variations, the approaching mold die 52 stops without contacting the terminal upper part, and the upper terminal part is covered with the mold resin. Or when the mold die is brought closer until the distance between the mold die 52 and the terminal lower portion becomes smaller than the distance from the terminal lower portion to the terminal upper portion in the electronic component device, the terminal upper portion is inclined with respect to the resin surface. There is a case. As a result, most of the upper portion of the terminal is not exposed, and the electrode cannot be stably exposed against manufacturing variations.

  However, in this embodiment, since the part where the mold die 52 and the second part 31c contact is an arc portion, when the mold die 52 and the second part 31c contact each other, the second part 31c is in the X direction in FIG. Slip. Although the exposure position of the second portion with respect to the unit package differs depending on the amount of sliding in the X direction, the exposed area is almost the same because the exposed portion is always an arc portion. The second part can be reliably exposed. As a result, the second portion 31c can be stably exposed.

  In consideration of variations in the exposed position of the arc portion, the first portion 31b soldered to the arc portion is rectangular in advance. Does not affect package stacking.

  Therefore, the present embodiment can provide a semiconductor device that can stably expose the electrodes even when manufacturing variations occur.

  Further, if the amount of mold resin input to the mold is adjusted to be small and the stop position of the mold 52 is raised, the contact between the second portion 31c, the mold 52 and the release film 55 becomes stronger. The second portion 31 c is more likely to bite into the release film 55. By increasing the amount of biting into the release film 55, the exposed height and exposed area of the second portion 31c can be increased. Therefore, in Comparative Example 1, the distance from the mold die 52 to the lower part of the terminal must be controlled to be equal to the distance from the lower part of the terminal to the upper part of the terminal in the electronic component device. do not have to. As a result, the controllability of the molding process can be improved.

  Furthermore, in this embodiment, the 1st resin holding part 36, the 2nd resin holding part 41, and the flow path 42 are formed. As a result, in the step of forming the mold resin, after covering the plurality of semiconductor chips 32, the mold resin is filled into a space that contacts the first resin holding portion 36. In this embodiment, even if the air in the cavities of the mold dies 51 to 53 gathers in the space that hits the first resin holding portion 36, the resin reservoir 41 and the flow path 42 are formed, so that the air is sufficiently I can escape. Accordingly, it is possible to prevent the appearance defects such as the back surfaces of the unit packages 30a to 30d being recessed.

(Modification 1)
Next, a semiconductor device of Modification 1 will be described with reference to a top view of FIG. As shown in FIG. 10, the first modification is different from the first embodiment in that the arrangement of the portions 35 is changed for each adjacent unit package 30, and the rest is the same as the first embodiment.

  As shown in FIG. 10, for example, in the arrangement of the portions 35 of the unit packages 30a and 30c, the second portion 31c, the first portion 31b, the second portion 31c, the first portion 31b, the second portion 31c, and the first portion from the left. It is arranged in order with 31b. On the other hand, for example, in the arrangement of the portion 35 of the unit package 30b, the first portion 31b, the second portion 31c, the first portion 31b, the second portion 31c, the first portion 31b, and the second portion 31c are arranged in this order from the left. Since it is not necessary to expose 31c on the second main surface side of the unit package 30d, as with 30b, the first portion 31b, the second portion 31c, the first portion 31b, the second portion 31c, The first part 31b and the second part 31c are arranged in this order, and only the bending process of 31c is not performed, or only 31b is arranged at the same position as 30b.

  As a result, when the unit package 30a and the unit package 30b are stacked, the second portion 31c of the unit package 30a is connected to the first portion 31b of the unit package 30b. The second portion 31c of the unit package 30b is connected to the first portion 31b of the unit package 30c. The unit packages 30c and 30d are similarly connected.

  Therefore, for example, when the unit packages 30a to 30d are stacked with the arrangement of the portions 35 in all the unit packages 30a to 30d being the same, for example, the unit package 30b has the first portion 31b and the second portion 31c with respect to the unit package 30a. It is necessary to offset by the interval. Similarly, each of the unit packages 30c and 30d needs to be offset by an interval between the first portion 31b and the second portion 31c with respect to the unit packages 30b and 30c. Therefore, the number of unit packages stacked is offset, and the area of the semiconductor device increases.

  However, in the unit packages 30a to 30d of the first modification, the arrangement of the portions 35 of the adjacent unit packages 30a to 30d is symmetric, so that the unit packages 30a to 30d are offset by the interval between the first portion 31b and the second portion 31c. Without being formed. As a result, an increase in the area of the semiconductor device can be prevented.

  In addition, even if it is the modification 1, there exists the effect of 1st Embodiment similarly.

(Modification 2)
Next, a semiconductor device of Modification 2 will be described with reference to FIG. The second modification is the same as the first embodiment except that the support (support) 60 is formed on the resin holding portion 36 of the first embodiment, for example.

  As shown in FIG. 11, the support body 60 is provided, for example, under the wiring 31a. The support 60 is formed integrally with the wiring 31a. The support 60 may be formed in a pattern including the support 60 when a photoresist is applied to the back surface of the lead frame 31 and a desired pattern is formed by photolithography.

  Compared with the case where the support body 60 is not formed in the same process as the wiring 31a, not only can the number of processes be reduced, but also manufacturing variations such as the height of the support body 60 can be reduced.

  In the first embodiment, when the mold die 52 is brought close to the mold die 51 in the step of forming the mold resin in FIG. 8, pressure is applied from the mold resin to the plurality of semiconductor chips 32 (pressure in the direction of the arrow in FIG. 8). Takes). For this reason, the resin holding | maintenance part 36 may become narrow with the pressure, or may be cut off.

  However, in the modification 2, since the support body 60 is formed, possibility that the resin holding part 36 will become narrow or cut off by the pressure can be reduced.

  As a result, the mold resin can be sufficiently filled, and voids can be prevented from remaining in the unit packages 30a to 30d.

  Even in the second modification, the effect of the first embodiment is similarly achieved. Modification 1 and Modification 2 may be combined.

(Modification 3)
Next, a semiconductor device of Modification 3 will be described with reference to FIG. The third modification shows a case where a plurality of semiconductor chips 32a to 32h in the unit packages 30a to 30d of the first embodiment are grouped and used.

  An example of having eight semiconductor chips 32a to 32h in each of the unit packages 30a to 30d will be described with reference to FIG. FIG. 12 is a diagram illustrating a correspondence relationship between the electrodes of the semiconductor chips 32a to 32h and the voltage applied to the bonding portion 31d.

  For convenience of explanation, the bonding portion 31d will be described using 31d (1) to 31d (11) as shown in FIG.

  As shown in FIG. 12, the electrodes CADD1 of the semiconductor chips 32a, 32b, 32e, and 32f are commonly connected to the bonding portion 31d (1). The electrodes CADD0 of the semiconductor chips 32a, 32c, 32e, and 32g are commonly connected to the bonding portion 31d (2). The electrodes VCC and electrodes RE of the semiconductor chips 32a to 32h are common to all the semiconductor chips 32a to 32h, and are connected to the bonding portions 31d (2) and 31d (7).

  The electrodes RB and CE of the semiconductor chips 32a to 32h are common to the semiconductor chips G1 (32a and 32b), G2 (32c and 32d), G3 (32e and 32f), and G4 (32g and 32h). Connect to 31d.

  Specifically, the electrode RB of the semiconductor chip G1 is commonly connected to the bonding portion 31 (6). The electrode RB of the semiconductor chip G2 is commonly connected to the bonding part 31 (5). Commonly connected to the electrode RB of the semiconductor chip G3 and the bonding part 31 (4). The electrode RB of the semiconductor chip G4 is commonly connected to the bonding part 31 (3). Further, the electrode CE of the semiconductor chip G1 is commonly connected to the bonding portion 31 (8). The electrode CE of the semiconductor chip G2 is commonly connected to the bonding part 31 (9). Commonly connected to the electrode CE and the bonding part 31 (10) of the semiconductor chip G3. The electrode CE of the semiconductor chip G4 is commonly connected to the bonding part 31 (11).

  For example, in the case of grouping for each of the two semiconductor chips 32 (Case 1 in FIG. 12), Vss (NC; not connected) is supplied to the bonding unit 31d (1), and the bonding unit 31d (2 As a result, Vss (NC) is supplied to the electrode CADD1 connected to the bonding part 31d (1), and the electrode CADD0 connected to the bonding part 31d (2) is supplied to the electrode CADD0 connected to the bonding part 31d (1). As a result, in each semiconductor chip 32, the semiconductor chip in the group can be identified by whether the electrode CADD0 is either Vss or VCC (see FIG. 13).

  In the case of grouping separately for each of the four semiconductor chips 32 (Case 2 in FIG. 12), VCC is supplied to the bonding unit 31d (1), and VCC is also supplied to the bonding unit 31d (2). As a result, VCC is supplied to the electrode CADD1 connected to the bonding part 31d (1), and VCC is also supplied to the electrode CADD0 connected to the bonding part 31d (2). In 32, the intra-group semiconductor chip can be identified based on whether the electrode CADD1 and the electrode CADD0 are either Vss or VCC (see FIG. 13).

  The address is input to the control unit 6000 via the data input / output circuit 5000. The semiconductor chip 32 in the unit packages 30a to 30d is selected by associating this address with the semiconductor chip 32 in the group.

  While a semiconductor chip 32 of a certain group is performing a data read operation or a write operation, a data read operation or a write operation can be prepared for another group of semiconductor chips 32. As a result, the larger the number of groups, the faster the read operation and write operation. The smaller the number of groups, the better the controllability of the control unit 6000.

  Since the number of groups can be appropriately changed according to a request from the user or the like, the convenience of the user and manufacturer is improved in the semiconductor device of the third modification.

  Even in the third modification, the effect of the first embodiment is similarly achieved. Modifications 1 to 3 may be combined.

(Modification 4)
Next, the semiconductor device of the modification 4 is demonstrated using FIG. The first embodiment is different from Modifications 1 to 3 in that the lead frame 31 is formed by press working. Other configurations are the same as those of the first embodiment.

  In order to form a space that becomes the resin holding portion 36, a part of the lead frame 31 is extruded to the main surface side. As shown in FIG. 14, the support body 60 is also formed integrally with the lead frame 31 by pressing.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 10 ... Glass epoxy board 20 ... Solder ball 30a-30d ... Unit package 31a ... Wiring 31b ... 1st part 31c ... 2nd part 32 32a-32h ... Semiconductor chip 33 ... Bonding wire 34 ... Mold resin 36 ... Resin holding part 41 ... Resin Pool 42 ... Flow path 100 ... Semiconductor device 1000 ... Memory cell array 2000 ... Row decoder 3000 ... Driver circuit 4000 ... Voltage generation circuit 5000 ... Data input / output circuit 6000 ... Control unit 7000 ... Source line driver circuit 8000 ... Sense amplifier MT ... Memory cell ST1, ST2 ... selection transistor

Claims (5)

In a semiconductor device including a unit package that has a semiconductor chip sealed therein and has a first main surface and a second main surface opposite to the first main surface.
In the unit package,
A lead frame having an electrode provided with a first portion provided on the first main surface side and a second portion including an arc portion exposed from the second main surface;
The semiconductor device, wherein the electrode is electrically connected to an electrode of the semiconductor chip. The lead frame is
A bonding part connected to the electrode of the semiconductor chip via a wire;
And further comprising a wiring connecting the bonding part and the electrode,
2. The unit package according to claim 1, further comprising: a resin holding portion in which resin is provided at least under the wiring, and the resin holding portion is exposed on the first main surface side. Semiconductor device. The semiconductor device according to claim 2, wherein a support portion that supports the wiring is provided in the first resin holding portion. 4. A resin reservoir is further provided in a region of the lead frame that does not constitute the unit package, and the resin holding portion and the resin reservoir are connected via a flow path. The semiconductor device described. The unit package has a plurality of semiconductor chips inside,
5. The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are divided into a plurality of groups and operate independently for each of the groups.

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