JP2013093434A - Method for analyzing semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine presence or absence of a DZ in a semiconductor substrate having the DZ thereon.SOLUTION: The method for analyzing the semiconductor substrate includes: measuring a lifetime τin a primary mode of a first sample of which a surface recombination rate has been adjusted to 1×10cm/sec or more, in a semiconductor substrate having a DZ thereon and an IG layer therein; determining a bulk lifetime τof the IG layer using the lifetime τin the primary mode and the following formula; measuring a lifetime τin a primary mode of a second sample of which a surface recombination rate has been adjusted to 1×10cm/sec or more with respect to the first sample; comparing the lifetime τin the primary mode with the bulk lifetime τof the IG layer; and determining that the DZ has disappeared when a difference between the lifetime τin the primary mode and the bulk lifetime τof the IG layer becomes 0.

Description

  The technical field relates to a method for analyzing a semiconductor substrate. Further, the present invention relates to a method for manufacturing an SOI substrate.

As a method for analyzing a silicon substrate having a single-layer structure, the lifetime of minority carriers in the silicon substrate (bulk life) is obtained from the time change (decay curve) of excess carrier density obtained by the μ-PCD (Microwave-Photo Conductive Decay) method. There is known a method for measuring time τ _b (see Patent Document 1).

  The bulk lifetime is one of the indices indicating the level of levels (collectively referred to as defect levels) caused by defects and impurities in the semiconductor energy gap. In particular, the defect level existing deep in the energy gap has a strong nature as a carrier recombination center. The bulk lifetime is a measure of the time (lifetime) from when carriers are generated until they disappear through recombination via their levels. Since the frequency of recombination increases as the number of defect levels increases, the bulk lifetime decreases.

  In addition, for example, the surface of a single crystal silicon substrate is where the crystal periodicity is broken, and there are defect levels associated with surface dangling bonds and the like. The surface recombination velocity is one of the indexes indicating the magnitude of the defect level on the surface.

  The μ-PCD method is an effective method for measuring a bulk lifetime because it can measure a sample such as a semiconductor substrate in a non-destructive and non-contact manner. The principle will be described below.

The surface of the sample is irradiated with laser and microwave (also referred to as μ wave) at the same time. Excess carriers are generated in the sample by laser irradiation. When the laser irradiation is stopped, the carrier density returns to a thermal equilibrium state after a certain time due to recombination via defect levels in the energy gap. Here, by utilizing the correlation between the carrier density and the reflectance of the μ wave and detecting the reflected microwave, the time change of the carrier density during attenuation can be followed. When a sufficient time has passed after the laser irradiation is stopped, only the mode with the longest time constant remains for the carrier density attenuation, and the attenuation curve is represented by one exponential function. The longest time constant is called the primary mode lifetime τ ₁ .

Here, the lifetime τ ₁ of the primary mode obtained from the μ-PCD method is generally shorter than the bulk lifetime τ _b of the sample. This is because the lifetime τ ₁ of the primary mode includes both the contribution of the surface recombination velocity (carrier annihilation on the surface) and the contribution of the bulk lifetime (carrier annihilation in the bulk).

In order to measure the bulk lifetime using the μ-PCD method, the surface recombination rate is made as close to 0 as possible to eliminate the influence of the surface, and the lifetime τ ₁ of the first-order mode is changed to the bulk lifetime τ _b . An approach called S-lowering is known. In this method, for example, surface treatment such as thermal oxide film formation or chemical passivation is employed.

JP 59-55013 A

  When the silicon substrate is annealed in an inert gas atmosphere such as argon and a part of the formed DZ (Denuded Zone) is transferred to a glass substrate, silicon substrate, sapphire substrate, etc. DZ is thinned and eventually disappears.

  On the other hand, there have been few attempts to analyze a semiconductor substrate having a multi-layer structure (also referred to as a multilayer structure) using the μ-PCD method. A method for measuring the thickness of DZ has not been proposed for a semiconductor substrate having DZ near the surface and having an IG (Intrinsic Gettering) layer inside.

  Thus, an object of one embodiment of the present invention is to determine whether or not DZ remains in a semiconductor substrate having DZ on the surface.

One embodiment of the present invention is a primary mode of a first sample in which a surface recombination velocity is adjusted to 1 × 10 ⁴ cm / sec or more with respect to a semiconductor substrate having DZ near the surface and having an IG layer therein. The lifetime τ ₁₁ of the first sample is measured, and the bulk lifetime τ _IG of the IG layer is determined using the lifetime τ _{11 of the} primary mode and the following formula, and the surface recombination velocity of the first sample is 1 × 10 ² cm / The lifetime τ ₁₂ of the primary mode of the second sample adjusted to sec or less is measured, the lifetime τ _{12 of the} primary mode and the bulk lifetime τ _IG of the IG layer are compared, and the lifetime τ _{12 of the} primary mode and IG This is a semiconductor substrate analysis method for determining that DZ has disappeared when the difference in the bulk lifetime τ _IG of the layers becomes zero.

（ただし、数式中、Ｄは少数キャリア拡散定数、τ_１１は一次モードのライフタイム、τ_ＩＧはＩＧ層のバルクライフタイム、Ｗは半導体基板の厚さをそれぞれ表す。）

(Wherein, D is the minority carrier diffusion constant, τ ₁₁ is the lifetime of the primary mode, τ _IG is the bulk lifetime of the IG layer, and W is the thickness of the semiconductor substrate.)

Another embodiment of the present invention is the first sample in which the surface recombination rate is adjusted to 1 × 10 ⁴ cm / sec or more with respect to a semiconductor substrate having DZ near the surface and having an IG layer inside. The primary mode lifetime τ ₁₁ is measured, the primary mode lifetime τ ₁₁ and the following formula are used to determine the bulk lifetime τ _IG of the IG layer, and the surface recombination rate of the first sample is 1 × 10 ^2. The lifetime τ ₁₂ of the primary mode of the second sample adjusted to be cm / sec or less is measured, the lifetime τ _{12 of the} primary mode is compared with the bulk lifetime τ _IG of the IG layer, and the lifetime τ _{12 of the} primary mode is compared. solution of the semiconductor substrate is determined that DZ are insignificant when the difference of the bulk lifetime tau _IG of IG layer is the bulk lifetime tau _IG of the IG layer, and the following ratio was set to It is a method.

（ただし、数式中、Ｄは少数キャリア拡散定数、τ_１１は一次モードのライフタイム、τ_ＩＧはＩＧ層のバルクライフタイム、Ｗは半導体基板の厚さをそれぞれ表す。）

(Wherein, D is the minority carrier diffusion constant, τ ₁₁ is the lifetime of the primary mode, τ _IG is the bulk lifetime of the IG layer, and W is the thickness of the semiconductor substrate.)

Here, the magnitude relationship between τ _IG and τ ₁₂ is τ _IG <τ ₁₂ . This is because the primary mode lifetime τ ₁₂ of the second sample contributes to the bulk lifetime τ _{DZ of DZ} that is overwhelmingly larger than τ _IG . Also, the surface contribution in the second sample is controlled to a surface recombination rate such that it can be ignored.

Here, the transition of τ _IG and τ ₁₂ due to the decrease in the DZ width accompanying the repetition of the reprinting process will be described using numerical simulation results. FIG. 3 is an example of a multilayer model calculation assuming a layer structure in which DZ is present outside the IG layer. Here, τ _IG = 1 μsec and τ _DZ = 1 msec. The white circle is τ _IG approximately estimated by substituting τ ₁₁ obtained from the μ-PCD simulation into Equation 1 with the surface recombination velocity S = 1 × 10 ⁵ cm / sec. The black circle is τ ₁₂ obtained from the μ-PCD simulation with the surface recombination velocity S = 10 cm / sec. It can be confirmed that τ _IG approaches τ ₁₂ as DZ thinning proceeds.

As shown in FIG. 3, τ ₁₂ decreases and approaches τ _IG due to the thinning of DZ, and when DZ disappears completely, τ ₁₂ substantially matches τ _IG .

It is possible to determine that DZ has disappeared when τ _IG and τ ₁₂ are acquired using the above analysis for each reprinting process and the difference (τ ₁₂ −τ _IG ) becomes 0. In the present specification, the expression “the difference between τ ₁₂ and τ _IG is 0” includes the meaning that the difference between τ ₁₂ and τ _IG is almost zero.

Further, when DZ has disappeared, if the next transfer process is performed as it is, the semiconductor layer transferred to another substrate may include an IG layer containing many crystal defects, so (τ ₁₂ −τ _IG ) Is less than a set ratio with respect to τ _IG (for example, 0.05 or less in the first embodiment), it is more preferable to determine that DZ is very small.

  In another embodiment of the present invention, the DZ of the semiconductor substrate may be formed by annealing the semiconductor substrate in an inert atmosphere or a hydrogen atmosphere.

  In another embodiment of the present invention, a silicon substrate may be used as the semiconductor substrate.

In another embodiment of the present invention, the primary mode lifetime τ ₁₁ and the primary mode lifetime τ ₁₂ may be measured using the μ-PCD method.

  According to one embodiment of the present invention, the presence or absence of DZ can be determined by analyzing the above method.

  In addition, according to another embodiment of the present invention, it is possible to determine that DZ is scarce by analyzing with the above method.

8A and 8B illustrate an example of a semiconductor device analysis method. 10A and 10B illustrate a method for manufacturing an SOI substrate. The figure which shows thinning of DZ by a reprinting process.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
In the present embodiment, an analysis method for determining whether or not DZ remains in a semiconductor substrate having DZ on the surface and an analysis method for determining that the remaining DZ is scarce will be described. FIG. 1 of the present embodiment shows an analysis method for determining that the remaining DZ is very small. The analysis is performed by the following steps A to G.

<Process A: Preparation of Semiconductor Substrate (corresponding to Step 101 in FIG. 1)>
A semiconductor substrate used for analysis is prepared. As the semiconductor substrate, for example, a crystalline semiconductor substrate containing a Group 14 element such as silicon, germanium, silicon germanium, or silicon carbide may be used.

  If the thickness of the semiconductor substrate used in this embodiment is too thin, handling at the time of substrate processing or measurement becomes difficult.

<Process B: DZ and IG layer formation (corresponding to step 102 in FIG. 1)>
Next, DZ is formed by annealing the semiconductor substrate in an inert atmosphere such as argon, helium, or nitrogen, or in a hydrogen atmosphere. By performing the annealing, oxygen or the like in the vicinity of the surface of the semiconductor substrate is diffused outward, and a layer (DZ) with few crystal defects can be formed in the vicinity of the surface. The formation method of DZ is not limited to this.

  In addition, a layer (IG layer) having an overwhelming number of crystal defects compared to DZ is formed on the inner side (inner side of DZ) from the vicinity of the surface. That is, the semiconductor substrate has DZ near the surface and an IG layer inside.

  Note that the semiconductor substrate used in this embodiment is a silicon substrate, and the film thickness of DZ (generally 10 μm to 100 μm) is compared with the film thickness of the silicon substrate (generally 500 μm to 1 mm). Thin enough.

<Process C: Acquisition of Lifetime τ ₁₁ of Primary Mode in Semiconductor Substrate (corresponding to Step 103 in FIG. 1)>
Next, the surface recombination speed on the surface of the semiconductor substrate is adjusted to 1 × 10 ⁴ cm / sec or more. This is the first sample. As a method for adjusting, for example, a natural oxide film may be formed on the surface of the semiconductor substrate. Natural oxide films generally have a very large surface recombination rate of the order of tens of thousands. Then, the lifetime τ ₁₁ of the primary mode is measured by the μ-PCD method.

  The natural oxide film formed on the surface of the semiconductor substrate may be a natural oxide film formed at the stage of preparing the semiconductor substrate, or the natural oxide film is removed with hydrofluoric acid and washed with pure water. After that, a natural oxide film may be formed again. Note that the thickness of the natural oxide film to be formed is not particularly limited.

<Process D: Acquisition of Bulk Lifetime τ _IG of IG Layer in Semiconductor Substrate (corresponding to Step 104 in FIG. 1)>
Next, the bulk lifetime τ _IG of the IG layer in the semiconductor substrate is obtained.

Here, in Step C, when the surface recombination velocity on the surface of the semiconductor substrate is 1 × 10 ⁴ cm / sec or more, the lifetime τ ₁₁ of the first-order mode can be approximated by the following mathematical formula.

（ただし、数式中、Ｄは少数キャリア拡散定数、τ_１１は一次モードのライフタイム、τ_ＩＧはＩＧ層のバルクライフタイム、Ｗは半導体基板の厚さをそれぞれ表す。）

(Wherein, D is the minority carrier diffusion constant, τ ₁₁ is the lifetime of the primary mode, τ _IG is the bulk lifetime of the IG layer, and W is the thickness of the semiconductor substrate.)

The bulk lifetime τ _IG of the IG layer is calculated using the obtained primary mode lifetime τ ₁₁ and the above formula.

After calculating the bulk lifetime τ _IG of the IG layer, the film on the surface of the semiconductor substrate having a surface recombination rate of 1 × 10 ⁴ cm / sec or more is removed. The natural oxide film may be removed with, for example, hydrofluoric acid.

<Process E: Measurement of Lifetime τ ₁₂ of Primary Mode of Semiconductor Substrate (corresponding to Step 105 in FIG. 1)>
Next, the surface recombination speed of the semiconductor substrate surface of the first sample is adjusted to 1 × 10 ² cm / sec or less. This is the second sample. As an adjustment method, for example, a thermal oxide film or a chemical passivation film may be formed on the surface of the semiconductor substrate.

  In particular, the chemical passivation film can reduce the surface recombination rate of the semiconductor substrate. Specifically, the surface recombination rate can be 1 cm / sec or more and 10 cm / sec or less.

In addition, as a method for adjusting the surface recombination speed of the semiconductor substrate surface to 1 × 10 ² cm / sec or less, silicon nitride formed by a chemical vapor deposition method (also referred to as a CVD method) is used as a main component. A film, a film mainly containing aluminum oxide, a film mainly containing amorphous silicon, or the like can be used. For example, a film containing amorphous silicon as a main component can be manufactured at a temperature of about 200 ° C. by RF plasma CVD using SiH ₄ and H ₂ .

Next, the lifetime τ ₁₂ of the primary mode is measured. In the present embodiment, the lifetime τ ₁₂ of the primary mode is measured by the μ-PCD method.

<Process F: Determination (corresponding to Step 106 in FIG. 1)>
Next, the bulk lifetime τ _IG of the IG layer obtained in the process D and the lifetime τ _{12 of the} primary mode measured in the process E are compared.

As a result of comparing the bulk lifetime τ _IG of the IG layer and the lifetime τ _{12 of the} primary mode, the difference (τ ₁₂ −τ _IG ) is equal to or less than a set ratio with respect to τ _IG (in this embodiment, 0). .05 or less), it is determined that the remaining DZ is very small. If the next transfer process is performed as it is, the semiconductor layer transferred to another substrate may include an IG layer containing many crystal defects, so that it is necessary to form DZ again.

  If it is determined by the above determination method that the remaining DZ is very small, the process returns to step 102, where annealing is performed in an inert gas atmosphere such as argon to form DZ again.

  If it is determined that the DZ is still sufficient and transfer is possible by the above determination method, after performing the transfer process, the process returns to Step 103 and the same analysis is performed again.

Although not shown in FIG. 1, as a result of comparing the bulk lifetime τ _IG of the IG layer and the lifetime τ _{12 of the} primary mode, DZ disappears when the difference (τ ₁₂ −τ _IG ) is zero. Can be determined.

By performing the above steps, it is possible to very easily determine whether or not DZ remains on the surface of the semiconductor substrate only by the calculated bulk lifetime τ _IG and the measured primary mode lifetime τ ₁₂ . Since the transfer of many IG layers onto another substrate can be prevented, an improvement in yield can be expected.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment mode, a method for manufacturing an SOI (Silicon On Insulator) substrate using the semiconductor substrate analyzed by the method of Embodiment Mode 1 is described.

  First, the semiconductor substrate 201 is prepared (see FIG. 2A). As the semiconductor substrate 201, one that has been analyzed by the method of Embodiment 1 and has been confirmed to have sufficient DZ is used.

  Next, the semiconductor substrate 201 is irradiated with ions 203 to form a damaged region 205 at a predetermined depth (see FIG. 2B).

  The damaged region 205 can be formed by irradiating the semiconductor substrate 201 with ions (ion beam) 203 accelerated by an electric field and introducing the ions 203 to a predetermined depth from the surface of the semiconductor substrate 201.

  Irradiation with the ions 203 can be performed by an ion doping method or an ion implantation method using ions such as hydrogen, an inert element (eg, helium), or a halogen (eg, fluorine).

  The above-mentioned “ion doping method” means that the ionized gas generated from the source gas is not mass-separated, and is accelerated by an electric field as it is to irradiate the object, so that the ionized gas element is included in the object. Refers to the method. In addition, the above-mentioned “ion implantation method” means that a source gas is turned into plasma, ion species contained in the plasma are extracted, mass separation is performed, ion species having a predetermined mass is accelerated, and an ion beam is obtained. It is a method of injecting into an object.

  Next, a support substrate 207 is prepared (see FIG. 2C).

  As the supporting substrate 207, a substrate made of an insulator such as glass, plastic, ceramic, quartz, or sapphire, a substrate made of a semiconductor such as silicon, or a substrate made of a conductor such as metal or stainless steel can be used.

  Next, the semiconductor substrate 201 and the supporting substrate 207 are attached to each other with the insulating layer 209 interposed therebetween (see FIG. 2D). Bonding is performed using the side into which the ions 203 are introduced when the damaged region 205 of the semiconductor substrate 201 is formed as a bonding surface (also referred to as a bonding surface).

  The insulating layer 209 functions as a bonding layer for bonding two substrates, and may be formed over the semiconductor substrate 201 or may be formed over the support substrate 207. In the case where the insulating layer 209 is formed over the semiconductor substrate 201, the insulating layer 209 may be formed before the ion 203 irradiation.

  The insulating layer 209 may be formed by a single layer or a stack of oxides, nitrides, or the like by a thermal oxide film or a CVD method. Specific examples of the material include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide.

  Note that in this specification, “oxynitride” such as silicon oxynitride indicates a composition having a higher oxygen content than nitrogen.

  Note that in this specification, “nitride oxide” such as silicon nitride oxide indicates a composition having a higher nitrogen content than oxygen.

  Here, the content is compared based on the measurement results of the Rutherford backscattering method and the hydrogen forward scattering method.

  Further, before bonding, surface treatment such as cleaning or plasma treatment may be performed on the bonding surfaces of the two substrates. By performing the surface treatment, hydrophilicity or cleanliness is improved, and the bonding strength at the time of bonding can be improved. Note that the surface treatment may be performed on at least one of the two substrates. In the case where surface treatment is performed on a substrate over which the insulating layer 209 is formed, the surface of the insulating layer 209 is performed.

  Next, heat treatment is performed, and the semiconductor substrate 201 is separated (also referred to as division) in the damaged region 205 (see FIG. 2E). By the separation, the insulating layer 209 and the semiconductor layer 211 including a part of the semiconductor substrate 201 can be sequentially provided over the supporting substrate 207. That is, the semiconductor layer 211 including a part of the semiconductor substrate 201 can be transferred onto the support substrate 207.

  Note that the heat treatment may be performed at a temperature of 300 ° C. or higher and lower than the strain point of the support substrate 207.

  In this manner, the SOI substrate 213 can be manufactured.

  By using the analysis method of the first embodiment, it is possible to determine in advance the presence or absence of DZ of the semiconductor substrate. Then, by forming a damaged region inside the DZ and transferring a part of the DZ, a semiconductor layer with few crystal defects can be obtained.

  Note that an SOI substrate is a general term for a semiconductor substrate provided with an insulating layer on a supporting substrate, and is not limited to a substrate having a silicon layer.

  Then, a semiconductor device such as a transistor or a diode can be manufactured using this SOI substrate.

  In addition, various electronic devices can be manufactured using the semiconductor element. Examples of the electronic device include a display device such as a television, a personal computer, a video camera, a digital camera, a navigation system, or a portable information terminal (such as a mobile phone, an electronic book, or a portable game machine). A circuit using the semiconductor element can be provided in a display portion or a peripheral portion of these display devices.

  As another example of the electronic device, a display unit may not be essential, and examples thereof include various devices such as a wireless tag, an authentication device, a lighting device, and an air conditioner. A circuit using the semiconductor element can be provided in these devices.

  Examples of the circuit include a circuit that can use the semiconductor element, such as a pixel circuit, a driver circuit, an arithmetic circuit, a sensor circuit, a power supply circuit, or a memory circuit.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

101 Step 102 Step 103 Step 104 Step 105 Step 106 Step 201 Semiconductor substrate 203 Ion 205 Damaged region 207 Support substrate 209 Insulating layer 211 Semiconductor layer 213 SOI substrate

Claims (5)

Measurement of the primary mode lifetime τ ₁₁ of the first sample with the surface recombination rate adjusted to 1 × 10 ⁴ cm / sec or more for a semiconductor substrate having DZ in the vicinity of the surface and having an IG layer inside. And
Using the primary mode lifetime τ ₁₁ and the following equation, the bulk lifetime τ _IG of the IG layer is determined,
Measuring the lifetime τ ₁₂ of the first mode of the second sample in which the surface recombination rate of the first sample is adjusted to 1 × 10 ² cm / sec or less;
Comparing the primary mode lifetime τ ₁₂ with the bulk lifetime τ _IG of the IG layer;
A semiconductor substrate analysis method for determining that DZ has disappeared when a difference between the lifetime τ _{12 of the} primary mode and the bulk lifetime τ _IG of the IG layer becomes zero.

(Wherein, D is the minority carrier diffusion constant, τ ₁₁ is the lifetime of the primary mode, τ _IG is the bulk lifetime of the IG layer, and W is the thickness of the semiconductor substrate.) Measurement of the primary mode lifetime τ ₁₁ of the first sample with the surface recombination rate adjusted to 1 × 10 ⁴ cm / sec or more for a semiconductor substrate having DZ in the vicinity of the surface and having an IG layer inside. And
Using the primary mode lifetime τ ₁₁ and the following equation, the bulk lifetime τ _IG of the IG layer is determined,
Measuring the lifetime τ ₁₂ of the first mode of the second sample in which the surface recombination rate of the first sample is adjusted to 1 × 10 ² cm / sec or less;
Comparing the primary mode lifetime τ ₁₂ with the bulk lifetime τ _IG of the IG layer;
When the difference between the lifetime τ _{12 of the} primary mode and the bulk lifetime τ _IG of the IG layer is equal to or less than a set ratio with respect to the bulk lifetime τ _IG of the IG layer, the DZ is determined to be small Semiconductor substrate analysis method.

(Wherein, D is the minority carrier diffusion constant, τ ₁₁ is the lifetime of the primary mode, τ _IG is the bulk lifetime of the IG layer, and W is the thickness of the semiconductor substrate.)   The method of analyzing a semiconductor substrate according to claim 1, wherein the DZ is formed by annealing the semiconductor substrate in an inert atmosphere or a hydrogen atmosphere.   The semiconductor substrate analysis method according to claim 1, wherein the semiconductor substrate is a silicon substrate. 5. The semiconductor substrate analysis method according to claim 1, wherein the primary mode lifetime τ ₁₁ and the primary mode lifetime τ ₁₂ are measured using a μ-PCD method. 6.

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