JP2013093041A - Circuit verification device and circuit verification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a configuration in which parameters required for simulating a semiconductor device are read.SOLUTION: A circuit verification device comprises: means (140) that inputs a signal for emulation of a semiconductor device (102), on which a logic circuit based on a hardware description language is formed, to the device; means (110) that executes simulation by the hardware description language corresponding to the logic circuit; means (107) that obtains parameters related to the simulation from the device; means (111) that applies the obtained parameters to a simulator; and means (130) that corrects the logic circuit before obtaining the parameters. In correction of the logic circuit, the following are added: bypass wiring (101A), which allows storage elements storing the parameters in the logic circuit to operate as ring-type shift registers; and a read part (101B), which reads parameters of each of the storage elements via the bypass wiring.

Description

  The present invention relates to a semiconductor device verification technique, and more particularly to a technique for verifying the operation of a device in which a logic circuit based on a hardware description language is formed.

  Advances in semiconductor technology have improved the degree of integration of logic LSIs (Large Scale Integrated circuits) in semiconductor devices year by year, enabling large-scale systems to be integrated on a single chip. In addition, the manufacturing cost of the semiconductor device is extremely expensive and requires one month or more for the manufacturing period. Therefore, it is important to perform sufficient verification before manufacturing.

  Verification of semiconductor devices is performed in various phases of design. The design process handles logical information according to each level from the abstract level in the initial design to the detailed manufacturing level in the final stage. For example, in the initial design stage, abstract level logic information that determines the degree of input / output relation is handled, and in the function design stage, function level logic information that determines the function of each logic part is handled. In the final detailed design stage, structure level logical information for determining the logical structure is handled. The above-described logical information at each design stage can be expressed by various commonly used hardware description languages (SystemC, SystemVerilog, Verilog-HDL, VHDL, etc.).

  There are two types of logic verification methods for semiconductor devices and systems using a plurality of semiconductor devices: a software simulator, a hardware emulator, and an actual semiconductor device.

  Since the software simulator executes logic information described in a hardware description language as a computer program, it can be used in various design stages, and it can easily observe variables of the hardware description language used. Have advantages.

  On the other hand, since verification by an actual semiconductor device and a hardware emulator use hardware, logic verification can be executed faster than a software simulator. The hardware emulator is generally composed of an FPGA (Field Programmable Gate Array), an FPID (Field Programmable Interconnect Device), or the like, and can organize a desired logical structure by an external input signal.

  Specific examples of the software simulator include VCS (trademark) of Nippon Synopsys, Inc. and ModelSim (trademark) of Mentor Graphics Japan. Examples of hardware emulators include FPGA emulators represented by Patent Document 1 and Patent Document 2. Patent Document 3 discloses a logic verification device combining a software simulator and a hardware emulator.

  The problem with software simulators is that their operating speed is slow. This is because all the values that change every clock cycle must be calculated in order to realize the operation of the entire circuit by a computer program. In recent years, the operation speed of the CPU has been increased, but since the circuit scale to be verified is also increased, the speed of the software simulator has only been reduced, and recently, the maximum is about 100 Hz. If the actual LSI operating speed is 1 GHz, for example, the speed of the simulation is 1 / 10,000,000 of the LSI. Therefore, in order to simulate the operation of this LSI for 1 second, 10,000,000 seconds = about 115 days are required.

  On the other hand, verification using an actual semiconductor device and a hardware emulator using an FPGA have a problem that the observability of the internal signal of the circuit is poor, that is, it is difficult to observe the state of the signal in the circuit from the outside. In the case of an actual semiconductor device, if only a part of the signal is observed, the signal may be output from an external pin, but it is difficult to change the signal to be observed. This is because it means remanufacturing of the semiconductor device and is not practical in terms of cost.

  Further, in the case of a hardware emulator using FPGA, it is possible to observe at the same speed as the circuit is operated if only a specific signal is observed. However, during the operation of the circuit, for example, it is difficult to add a signal to be observed or change the value of the signal. Because of this, it is necessary to modify the hardware description language, synthesize (work to make the contents described in the hardware description language into a netlist), and place and route (work to make the netlist into a form for mounting on an FPGA). This is because a huge amount of time is required for the work.

  A technique for dealing with these problems is described in Patent Document 4, for example. The technique described in Patent Document 4 dumps the value of the memory element of the emulation device at a predetermined interval during emulation, and when a malfunction occurs in the operation of the circuit, reads the dumped data into the simulation device and starts the simulation. That's it.

JP 2000-132420 A JP 2001-209556 A JP 2000-215226 A Japanese Patent Laid-Open No. 11-249930 Japanese Patent Application No. 2006-553063, paragraph 0085

Xilinx Corporation, Virtex-4 Configuration Guide, published June 21, 2007

  In the method of Patent Document 4, the above operation is realized by adding a scan flip-flop (SFF) to a storage element necessary for simulation. However, the simulation of a semiconductor device requires parameters of all the memory elements in the device. Therefore, in the method of Patent Document 4, the number of flip-flops in the circuit is twice the original number. As a result, the scale of the circuit increases, which may affect the original circuit layout.

  An object of the present invention is to simplify a configuration for reading parameters necessary for simulation of a semiconductor device.

  A circuit verification apparatus according to the present invention is a circuit verification apparatus for a semiconductor device in which a logic circuit based on a hardware description language is formed, and includes a control signal including a signal for executing emulation of the semiconductor device. An emulation unit for inputting to the simulation unit, a simulation unit for executing a simulation of the logic circuit using a hardware description language corresponding to the logic circuit of the semiconductor device, and acquiring parameters relating to the simulation from the semiconductor device after starting the emulation of the semiconductor device An acquisition unit, a setting unit that applies a parameter acquired by the acquisition unit to a simulation by the simulation unit, and a circuit correction unit that corrects the logic circuit of the semiconductor device before the parameter acquisition by the acquisition unit. The circuit correction unit, when correcting a logic circuit of the semiconductor device, a bypass wiring for a memory element that stores parameters in the logic circuit to operate as a ring-type shift register by the control signal, and the bypass wiring And a reading unit that reads out the parameter of the storage element and outputs the parameter to the acquisition unit via the interface.

  In the circuit verification method according to the present invention, in a semiconductor device in which a logic circuit based on a hardware description language is formed, a wiring for operating a storage element for storing a parameter relating to the simulation of the semiconductor device as a ring type shift register is provided. Added to the logic circuit, starts emulation of the semiconductor device, and after starting the emulation, operates the memory element as a shift register to read the parameters of the memory element, and supports hardware corresponding to the logic circuit of the semiconductor device This is a method of executing the simulation of the logic circuit by applying the read parameter to the hardware description language.

  ADVANTAGE OF THE INVENTION According to this invention, the structure for reading the parameter required for the simulation of a semiconductor device can be simplified. Thereby, an increase in the size of the logic circuit can be prevented.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is explanatory drawing regarding the operation example (before correction) of the circuit correction part in embodiment of this invention. It is explanatory drawing regarding the operation example (after correction) of the circuit correction part in embodiment of this invention. It is a flowchart regarding the operation | movement of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the 3rd Embodiment of this invention. It is a flowchart regarding the operation | movement of the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the 4th Embodiment of this invention. It is a block diagram which shows the structure of the 1st specific example of embodiment of this invention. It is a block diagram which shows the structure of the 2nd specific example of embodiment of this invention. It is a block diagram which shows the structure of the 2nd specific example of embodiment of this invention. It is a block diagram which shows the structure of the 2nd specific example of embodiment of this invention. It is a block diagram which shows the structure of the application example of embodiment of this invention.

  FIG. 1 shows the configuration of the first embodiment of the present invention. The circuit verification apparatus 1001 of this embodiment is an apparatus for verifying the operation of a semiconductor device in which a logic circuit based on a hardware description language is formed. The configuration shown excluding the semiconductor device 102 represents a functional configuration realized by a control IC (not shown) such as a CPU executing a program in the circuit verification apparatus 1001.

  The hardware description language 100 is a hardware description language such as SystemC, SystemVerilog, Verilog, or VHDL corresponding to the logic circuit of the semiconductor device 102. Note that circuit modules that are not subject to verification and unnecessary for simulation, such as JTAG (IEEE1149.1) and BIST (Build-In Self Test), may be excluded from the hardware description language 100.

  The logic circuit of the semiconductor device 102 is formed from mask data created based on a net list obtained by converting a circuit described in the hardware description language as described above into a net list. The logic circuit of the semiconductor device 102 only needs to have an operation defined by a hardware description language, and the formation process is not limited to the above. The logic circuit in the hardware description language operates according to an input signal or a clock signal from the emulation control unit 140 described later, whereby the semiconductor device 102 is emulated.

  In the circuit verification device 1001, the user I / F unit 120 is an interface for inputting an external instruction to the circuit verification device 1001. Examples of instructions from the outside include start / stop of operation of the semiconductor device 102, start of operation of the acquisition unit 107, start / stop of operation of the simulation unit 110, start / stop of operation of the setting unit 111, and the like. Further, the status of emulation and simulation of the semiconductor device 102 is displayed on a display device (not shown).

  The emulation control unit 140 corresponds to the emulation unit in the present invention, and is configured of an input signal control unit 104 and a clock signal control unit 105 in the present embodiment. The input signal control unit 104 inputs a signal necessary for emulation of the semiconductor device 102 based on preset input signal information 103. The clock signal control unit 105 controls input of a clock signal that is an operation reference of the semiconductor device 102.

  The acquisition unit 107 uses the reading unit 101B provided in the semiconductor device 102 by the circuit correction unit 130, which will be described later, to acquire parameters related to the operation during emulation from the semiconductor device 102 and store them as the read parameters 106.

  The control unit 108 controls the timing of the input signal and the clock signal so that the semiconductor device 102 operates properly, while receiving an instruction input from the user I / F unit 120, the input signal control unit 104, and the clock signal control unit 105. To the acquisition unit 107. Note that the control unit 108 may be omitted from the circuit verification device 1001. In that case, the input signal control unit 104 and the clock signal control unit 105 cooperate to provide an appropriate signal to the semiconductor device 102, and the acquisition unit 107 is directly controlled from the user I / F unit 120.

  The simulation unit 110 is a so-called software simulator represented by VCS (trademark) of Nippon Synopsys, Inc. and ModelSim (trademark) of Mentor Graphics Japan. The simulation unit 110 reads the hardware description language 100 and the input signal information 103, and executes a simulation from the time when the semiconductor device 102 stops operating.

  The setting unit 111 sets the read parameter 106 acquired from the semiconductor device 102 by the acquisition unit 107 as the parameter of the hardware description language 100 used by the simulation unit 110. As the setting unit 111, when the standard of the hardware description language 100 is, for example, Verilog, Verilog PLI (Programming Language Interface) defined by IEEE1164 can be applied. Even if the standard of the hardware description language 100 is other than the above, the setting unit 111 can be realized using an equivalent function of the simulation unit 110. For example, if the simulation unit 110 is ModelSim (trademark) of Mentor Graphics Japan, Signal Spy (trademark) may be used as the setting unit 111.

  The circuit correction unit 130 corrects the logic circuit of the semiconductor device 102 using the hardware description language 100 so that the acquisition unit 107 acquires the parameter (106) from the semiconductor device 102. In this correction, the circuit correction unit 130 adds a bypass wiring 101A and a reading unit 101B for operating a plurality of storage elements such as flip-flops, latches, and RAMs of the semiconductor device 102 as shift registers.

  With reference to FIG. 2 and FIG. 3, the correction of the circuit by the circuit correction unit 130 will be described with an example. FIG. 2 shows a configuration before correction around the memory element in the semiconductor device 102. In the configuration shown in the figure, the N memory elements 201-1 to 201-N are supplied with a common clock signal from the clock signal control unit 105 (FIG. 1), and are arranged in series with a combinational circuit interposed therebetween. ing. With respect to such a configuration, the circuit correction unit 130 performs correction as illustrated in FIG. 3 before the simulation of the semiconductor device 102 is started, for example, at the start of emulation.

  As shown in FIG. 3, a bypass wiring 101A (101A-1 to 101A-N) and a reading unit 101B are added to the semiconductor device 102 after correction. The storage elements 201-1 to 201-N are connected in a ring shape by bypassing each combinational circuit by the bypass wiring 101A. In addition, selectors 302-1 to 302-N for switching the input to the storage element under the control of the reading unit 101B are added to the preceding stage of each storage element (201-1 to 201-N). The operation of the semiconductor device 102 after the correction will be described later.

  The operation of the configuration of FIG. 1 will be described along the flowchart shown in FIG. In verifying the operation of the semiconductor device 102, the circuit verification apparatus 1001 first activates the circuit correction unit 130 and corrects the circuit around the storage element in the semiconductor device 102 using the hardware description language 100 (step S400). . Here, as an example, it is assumed that the configuration is corrected as shown in FIG.

  Next, in accordance with an instruction from the user I / F unit 120, the control unit 108 performs initial setting so that each unit of the circuit verification device 1001 operates appropriately (step S401). The initial setting is, for example, setting the start instruction to each unit and setting information necessary for start-up, and the reading unit 101B inputs the output from the combinational circuit to the storage elements (201-1 to 201-N). Each selector (302-1 to 302-N) is set.

  When the initial setting is completed, the control unit 108 controls the emulation control unit 140 according to the designation from the user I / F unit 120, and gives an appropriate input signal and clock signal to the semiconductor device 102. Thereby, emulation of the semiconductor device 102 starts (step S402). At this time, the input signal control unit 104 reads data from the input signal information 103 as an input signal and sets a value.

  After the emulation starts, the circuit verification apparatus 1001 performs a simulation on the operation up to a certain point in time or the operation from the certain point in time to verify the detailed operation state of the semiconductor device 102. The user I / F unit 120 can recognize the certain time point, that is, the simulation timing, for example, by an instruction from an operator or timer control. When recognizing that the simulation timing has arrived, the user I / F unit 120 notifies the control unit 108 to that effect.

  The control unit 108 instructs the emulation control unit 140 to stop the clock signal and input signal for emulation. Thereby, the emulation of the semiconductor device 102 is temporarily stopped (step S403).

  Subsequently, the control unit 108 activates the acquisition unit 107 and instructs the semiconductor device 102 to acquire the parameters currently stored in each storage element. Receiving the instruction, the acquisition unit 107 requests the reading unit 101B of the semiconductor device 102 to read parameters.

  Here, with reference to FIG. 3, an operation in which the reading unit 101B of the semiconductor device 102 reads the parameters of the storage elements (201-1 to 201-N) will be described. During the normal operation of the semiconductor device 102, that is, during emulation, the reading unit 101B receives each selector (302-1 to 302-) so as to input the output from the combinational circuit to the storage elements (201-1 to 201-N). N) is set.

  On the other hand, when the parameter read request is received from the acquisition unit 107 after the emulation starts, the read unit 101B selects the selectors (302-1 to 302-) so as to connect the storage elements 201-1 to 201-N by the bypass wiring 101A. Switch N). Thereby, the memory elements 201-1 to 201-N are connected in series in a ring shape via the bypass wiring 101A.

  Subsequently, the reading unit 101B operates the storage elements 201-1 to 201-N as a ring-type shift register, and sequentially outputs parameters from a specific storage element 201-N whose output end is connected to itself (101B). Read. In order to operate as a shift register, the reading unit 101B supplies a common clock signal to each storage element (201-1 to 201-N).

  Each memory element (201-1 to 201-N) supplies a parameter held by itself to the subsequent memory element via the bypass wiring 101A on the output side for each clock. The parameter is received via the input-side bypass wiring 101A. Thereby, in the ring-shaped storage elements 201-1 to 201 -N, the parameter storage locations are sequentially shifted.

  Therefore, by repeating the above clock operation N times, the parameters of the N storage elements (201-1 to 201-N) can be read from one storage element (201-N). As described above, since the storage elements 201-1 to 201-N are connected in a ring shape, for example, the parameter output from the leftmost storage element 201-1 in FIG. After reaching N, the circuit returns to the original storage element 201-1. Therefore, the parameter of each storage element is not changed after the parameter reading process.

  With the above operation, when the reading unit 101B sequentially reads parameters from the storage element, they are supplied to the acquisition unit 107. The acquisition unit 107 stores the parameter from the reading unit 101B as the reading parameter 106 (step S404).

  When saving of the read parameter 106 is completed, the user I / F unit 120 activates the simulation unit 110 and the setting unit 111. The activated simulation unit 110 reads the hardware description language 100 and prepares a simulation (step S405). The setting unit 111 sets the read parameter 106 from the semiconductor device 102 as the parameter of the hardware description language 100 read by the simulation unit 110 (step S406).

  The simulation unit 110 executes a simulation for the operation of the semiconductor device 102 using the set read parameter 106 (step S407). Thereby, the operation of the semiconductor device 102 from the start of emulation (S402) to the stop (S403) can be omitted, and further, the operation of the semiconductor device 102 after the emulation is stopped is simulated. The screen is displayed by the unit 120.

  Thus, in the present embodiment, the parameters of each storage element are read by operating the storage element of the semiconductor device 102 as a ring-type shift register. Therefore, an increase in the size of the logic circuit for parameter reading can be prevented. In addition, since both hardware emulation and software simulation are used together, it is possible to satisfy both the operating speed and the observability of the operation.

  In this embodiment, the case where there is one type of clock signal has been described, but the clock frequency may be different depending on the storage element. In this case, the original clock is distributed to each storage element during emulation, and a common clock is given when the value of each storage element is acquired. Accordingly, memory elements having different clock frequencies can be directly connected in a ring shape via the bypass wiring 101A.

  In addition, the storage element can be divided into a plurality of blocks, and a ring can be configured in units of blocks. By doing so, it is possible to move a plurality of rings at the same time when acquiring the parameters of the storage element, and it is possible to shorten the time until the parameters are acquired.

  A second embodiment of the present invention will be described. FIG. 5 shows the configuration of the circuit verification apparatus 1002 of this embodiment. The configuration of the circuit verification device 1002 corresponds to the circuit verification device 1001 (FIG. 1) described above with a stop determination unit 150 added. In the embodiment of FIG. 1, the stop timing of emulation of the semiconductor device 102 is instructed from the user I / F unit 120, but this embodiment is performed by the stop determination unit 150.

  The stop determination unit 150 determines to stop the emulation when the state of the semiconductor device 102 satisfies a predetermined condition after starting the emulation. Conditions for the determination are as follows: 1) When a certain signal value becomes a specific value, 2) When a certain signal value falls within or outside the specific value range, 3) The above 1) or When 2) occurs a predetermined number of times, 4) when a break occurs, 5) when 1) to 4) are combined with a plurality of signals, etc., the setting is appropriately made according to the contents of verification.

  In order to perform the above-described determination, the stop determination unit 150 acquires, for example, a signal indicating some parameters or operation states of the semiconductor device 102 through an external terminal of the device. Instead of providing the stop determination unit 150 outside the semiconductor device 102 as in the present embodiment, a function equivalent to the stop determination unit 150 may be formed in the semiconductor device 102.

  The operation of the circuit verification device 1002 is basically the same as that shown in FIG. 4 except for the following points. In the present embodiment, a stop condition is set in the stop determination unit 150 in the initial setting (step S400). Further, when the emulation is stopped because the condition is satisfied (step S402), the stop determination unit 150 instructs the emulation control unit 140 to stop the input signal and the clock signal to the semiconductor device 102.

  According to the present embodiment, the emulation stop timing can be determined according to the actual situation of the emulation.

  A third embodiment of the present invention will be described. FIG. 6 shows the configuration of the circuit verification apparatus 1003 of this embodiment. The configuration of the circuit verification apparatus 1003 corresponds to the circuit verification apparatus 1001 (FIG. 1) described above with a simulation determination unit 160 added. The simulation determination unit 160 determines the necessity of simulation using the read parameter 106 acquired from the semiconductor device 102 by the acquisition unit 107.

  The operation of the present embodiment will be described along the flowchart shown in FIG. After the circuit modification by the circuit modification unit 130, the emulation started at the semiconductor device 102 is stopped, and the procedure (steps S700 to S704) until the parameter is read from the semiconductor device 102 is the same as the above-described procedure (S400) shown in FIG. To S404), and description thereof is omitted.

  When the parameter acquisition is completed, the simulation determination unit 160 compares the read parameter 106 with a predetermined determination criterion and determines whether or not a simulation should be performed at this time (step S705). The determination criteria are, for example, when the value of the current read parameter 106 is 1) a specific value, 2) when the value is within or outside the range of the specific value, and 3) the above 1) or 2) When a predetermined number of times occur, 4) when a break occurs, 5) when 1) to 4) are combined with a plurality of signals, etc., the setting is made according to the verification contents. Is determined to perform a simulation.

  As a result of the above determination, when a simulation is performed (step S706: Yes), the simulation unit 110 is activated and a simulation based on the read parameter 106 is executed in the same manner as in the above-described embodiment (FIG. 4: S405 to S407) ( Step S707).

  On the other hand, when it is determined that the simulation is not performed (step S706: No), the simulation determination unit 160 instructs the emulation control unit 140 to resume emulation (step S708). As a result, the supply of the clock signal or the like to the semiconductor device 102 is resumed, and the emulation once stopped is resumed. Thereafter, when the emulation is stopped, the necessity of simulation is determined in the same procedure as described above.

  According to the present embodiment, whether or not to simulate can be determined according to the parameter state of the semiconductor device 102. As described above, when reading parameters from the semiconductor device 102, each storage element is operated as a ring-shaped shift register (FIG. 3), so that the storage state of each storage element is the same as before reading. Maintained. Therefore, when simulation is not performed, emulation can be resumed immediately.

  A fourth embodiment of the present invention will be described. FIG. 8 shows the configuration of the circuit verification apparatus 1004 of this embodiment. The circuit verification apparatus 1004 assumes a case where there are a plurality of semiconductor devices (102) to be verified. In the present embodiment, two semiconductor devices (102-1, 102-2) having different types of hardware description languages are verified. However, the number of verification targets is not limited to the one illustrated, and is three or more. There may be.

  The circuit verification apparatus 1004 includes a hardware description language 100-1 for the semiconductor device 102-1, an acquisition unit 107-1 and a read parameter 106-1, and a hardware description language 100-2 for the semiconductor device 102-2. An acquisition unit 107-2 and a read parameter 106-2.

  The configuration of FIG. 8 is a configuration in which the input signal and the clock signal are common to the two semiconductor devices (102-1, 102-2). Instead, the input signal and the clock signal are separately configured. Alternatively, the input signal may be separate but the clock signal may be common, or the input signal may be common but the clock signal may be separate. When individual signal supply is performed, the emulation control unit 140 is provided for each semiconductor device.

  In the operation of the present embodiment, the circuit verification apparatus 1004 executes the above-described procedure substantially along FIG. 4 for each semiconductor device (102-1, 102-2). In the present embodiment, since a plurality of hardware description languages (100-1, 100-2) are handled, it is desirable that the simulation unit 110 can determine in advance the hardware description language used for the simulation. For this purpose, for example, the hardware description language to be used is instructed from the user I / F unit 120 to the simulation unit 110, or the setting unit 111 instructs the simulation unit 110 to read the current read parameters (106-1, 106-2). ) May be notified of which hardware description language (100-1, 100-2) corresponds to.

  According to this embodiment, not only a single semiconductor device but also a plurality of semiconductor devices can be verified. As a result, a plurality of devices having different types of hardware description languages can be verified by a single circuit verification apparatus.

  Said 2nd-4th embodiment is not restricted to implementing separately, and may implement it combining suitably.

(Specific example 1)
A specific example is given about the structure of the said embodiment. FIG. 9 shows the configuration of the first specific example. In this configuration, a general computer 800 and a semiconductor test apparatus 806 are connected via a PCI (Peripheral Component Interconnect) bus 805 so as to be accessible to each other. The computer 800 includes a CPU 801, a RAM 802, a bridge 803, and an HDD 804. The computer 800 is connected to an input unit 809 and a display unit 810 that realize the above-described user I / F unit (120) via a bridge 803.

  The computer 800 realizes the functions of the above-described simulation unit (110), setting unit (111), and circuit correction unit (130). The HDD 804 or RAM 802 of the computer 800 stores the hardware description language (100) and the read parameter (106) acquired by the acquisition unit (107).

  In the semiconductor test apparatus 806, the control FPGA 807 corresponds to the above-described emulation control unit (140), control unit (108), and acquisition unit (107). The memory 808 is a storage unit that stores the above-described input signal information (103).

  In the configuration of FIG. 9, when the start of operation is designated by the user through the input unit 809, the CPU 801 executes initial setting by a program stored in the HDD 804 (FIG. 4: S401). In this initial setting, the input signal information (103) of the HDD 804 is transferred to the memory 808 on the semiconductor test apparatus 806. Further, as necessary, the control FPGA 807 is set with respect to the number of clocks, the frequency, and the phase relationship, and the setting regarding the input signal to be given to the semiconductor device 102 and the value of the memory 808.

  When the initial setting is completed, the display unit 810 displays that the semiconductor device 102 can be emulated, and waits until the user instructs execution of the next step.

  Thereafter, when the start of emulation of the semiconductor device 102 is instructed by an instruction from the user, the CPU 801 starts the operation of the semiconductor device 102 by the control FPGA 807 (FIG. 4: S402). Thereafter, the user gives an instruction to stop the operation of the semiconductor device 102 through the input unit 809 such as a keyboard and a mouse connected to the computer 800. When recognizing this instruction, the CPU 801 instructs the control FPGA 807 to stop the operation of the semiconductor device 102. As a result, the emulation of the semiconductor device 102 stops (FIG. 4: S403).

  When the CPU 801 recognizes that the emulation is stopped, the CPU 801 instructs the control FPGA 807 to read out parameters from each storage element of the semiconductor device 102. The control FPGA 807 operates the series of storage elements of the semiconductor device 102 as a shift register, thereby sequentially reading the parameters of each storage element and transferring them to the computer 800. The CPU 801 stores the parameter (106) from the control FPGA 807 in the HDD 804 or the RAM 802 (FIG. 4: S404). In consideration of the amount of data read from the semiconductor device 102, the parameters are preferably stored in the HDD 804 rather than the RAM 802.

  Subsequently, the CPU 801 activates the simulator (110) by executing the program of the simulation unit 110 stored in the HDD 804 (FIG. 4: S405). The activated simulator (110) reads the hardware description language (100) and the input signal information (103) in the HDD 804. Further, the parameter (106) read from the semiconductor device 102 is set as a simulation parameter (FIG. 4: S406). Then, simulation is executed (FIG. 4: S407).

(Specific example 2)
A general-purpose FPGA can be used as the semiconductor device 102. The configuration in this case corresponds to a configuration in which the semiconductor device 102 to be verified is replaced with an FPGA in the system of FIG. 9 described above. Generally, a semiconductor device has an operating frequency, voltage, input I / F (LVTTL (Low Voltage TTL), HSTL (High Speed Transceiver Logic), LVDS (Low Voltage Differential Signaling), etc.), a package (DIP (Dual Inline Package). ), BGA (Ball Grid Array), etc.) are different, and a dedicated board is often required for each standard. On the other hand, by emulating the semiconductor device 102 using FPGA, a dedicated board for each hardware description language becomes unnecessary.

  Regarding FPGAs, for example, Xilinx Corporation's FPGAs have a function for reading a memory element from terminals for JTAG and SelectMAP (trademark) (see Patent Document 5 and Non-Patent Document 1). When such an FPGA is used, the circuit correction (FIG. 4: S400) by the circuit correction unit 130 described above can be omitted. That is, if the acquisition unit 107 is configured to operate JTAG or SelectMAP, the value of the storage element in the FPGA can be read.

  FIG. 10 shows a configuration in which an FPGA is used as the semiconductor device 102. In the illustrated configuration, the semiconductor test apparatus 806 in the above-described specific example shown in FIG. 9 is replaced with an FPGA emulator 900, and a plurality of FPGAs 903.1 to 903.N are provided as verification targets. The operation of this configuration is the same as that of the fourth embodiment described with reference to FIG.

  Note that, as described above, a function corresponding to the reading unit (101B) of the present invention is implemented in an FPGA such as Xilinx Corporation. Therefore, in this case, for example, as shown in FIG. 11, by connecting FPGAs 903.1 to 903.N in series with JTAG and instructing the operation according to the shift register, all the FPGAs 903 are controlled by the control FPGA 901. Parameters can be read from .1 to 903.N.

  Further, instead of the configuration in FIG. 11, the parameters can be read from all the FPGAs 903.1 to 903.N by connecting the SelectMAP interface to the control FPGA 901 as shown in FIG.

  In the form in which the FPGA is used for the semiconductor device 102, when the FPGA has a specification that can change the initial value, the parameter at the end of the simulation may be set as a new initial value of the FPGA. In this case, using the new initial value, FPGA configuration data (configuration data) is created, and the configuration data is written to the FPGA. As a result, the operation verified by the simulation can be reproduced by the FPGA emulator.

  The present invention can also be applied to verification of a semiconductor device equipped with a PLL (Phase-Locked Loop) for generating a clock inside the device. The PLL is used in many semiconductor devices because it has a function of multiplying jitter and frequency present in the clock, a function of phase shifting, and the like. Since the PLL spontaneously generates a clock signal by an internal VCO (Voltage Controlled Oscillator), the frequency of the input signal is limited. In principle, the lower limit frequency is set to a value larger than 0 [Hz].

  However, once the emulation is stopped (FIG. 4: S403), the clock frequency becomes 0 [Hz], causing inconvenience in the PLL operation. In order to solve this problem, for example, a configuration as shown in FIG. 13 may be added to the semiconductor device 102.

  In the configuration of FIG. 13, external terminals 501 and 502 for directly accessing the selector are added in addition to the PLL external terminal 500. During emulation, the PLL is operated through the external terminal 500 to input a clock signal to the selector. Further, when reading out the parameters after stopping the emulation, the clock signal is directly inputted from the external terminal 501 to the selector. For this switching, for example, the input signal control unit 104 (FIG. 1) or the like gives a selection signal to the selector through the external terminal 502. As a result, even in the semiconductor device 102 equipped with a PLL, a clock signal can be properly supplied both during emulation and during parameter reading.

1001,1002,1003,1004 Circuit verification equipment
100: Hardware description language, 101A: Bypass wiring, 101B: Reading unit, 102: Semiconductor device, 103: Input signal information, 104: Input signal control unit, 105: Clock signal control unit, 106: Reading parameter, 107: Acquisition 108: Control unit 110: Simulation unit 111: Setting unit 120: User I / F unit 130: Circuit correction unit 140: Emulation control unit 150: Stop determination unit 160: Simulation determination unit 201 -1 to 201-N: storage element, 301-1 to 301-N: selector,

Claims (8)

A circuit verification device having an FPGA (Field Programmable Gate Array) having a logic circuit based on a hardware description language and having means for reading a parameter from a storage element of the logic circuit,
An emulation unit that inputs a control signal including a signal for executing emulation of the FPGA to the FPGA; a simulation unit that performs simulation of the logic circuit using a hardware description language corresponding to the logic circuit of the FPGA; A circuit verification comprising: an acquisition unit that acquires a parameter relating to simulation from a storage element of the FPGA after emulation of the FPGA starts; and a setting unit that applies the parameter acquired by the acquisition unit to simulation by the simulation unit apparatus. And a stop determination unit that issues a stop instruction for the emulation to the emulation unit when the signal of the FPGA satisfies a predetermined condition during the emulation of the FPGA.
The circuit verification device according to claim 1, wherein the acquisition unit acquires a parameter from the FPGA when a stop instruction is issued by the stop determination unit.   The circuit verification apparatus according to claim 1, further comprising a simulation determination unit that determines whether or not to execute the simulation by the simulation unit by comparing the parameter acquired by the acquisition unit with a predetermined condition. .   2. The apparatus according to claim 1, further comprising means for converting a parameter obtained by simulation of the simulation unit or a parameter acquired by the acquisition unit into configuration data of the FPGA and setting the FPGA. 4. The circuit verification device according to any one of 3 above. Emulation is performed using an FPGA (Field Programmable Gate Array) having a logic circuit based on a hardware description language and having means for reading parameters from a memory element of the logic circuit,
After starting the emulation, obtain the parameters of the storage element from the FPGA,
A circuit verification method, wherein a simulation of the logic circuit is executed by applying the acquired parameter to a hardware description language corresponding to the logic circuit of the FPGA. Further, when the FPGA signal satisfies a predetermined condition during emulation of the FPGA, a stop instruction for the emulation is issued to the emulation unit,
6. The circuit verification method according to claim 5, wherein a parameter is acquired from the FPGA when the stop instruction is issued.   The circuit verification method according to claim 5, further comprising determining whether or not to execute the simulation by comparing the acquired parameter with a predetermined condition.   The parameter obtained by the simulation or the parameter acquired by the acquisition unit is converted into configuration data of the FPGA and set in the FPGA. The circuit verification method described in 1.

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