JP2013092895A - Resampling device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resampling device that realizes high-speed resampling by a parallel switching operation while avoiding random access of a memory and especially has an advantage when the number of particles is small.SOLUTION: A resampling device 1 comprises: cumulative likelihood value calculation means for calculating a cumulative likelihood value at the time of inputting a likelihood value; uniform random number generation means 13 for generating a uniform random number less than the maximum cumulative likelihood value; plural comparison means 14 for comparing multiple cumulative likelihood values with the uniform random number every time the uniform random number is generated; a priority encoder 15 for selecting the maximum cumulative likelihood value from the cumulative likelihood values that are determined to be equal to or less than the uniform random number by the comparison means 14, and generating a code showing a hypothesis corresponding to the likelihood value input in the cumulative likelihood value calculation means when the maximum cumulative likelihood value is calculated; and a matrix switch 18 for outputting multiple resampled hypotheses by controlling contact points corresponding to the hypotheses shown by multiple codes.

Description

  The present invention relates to parameter estimation by a sequential Monte Carlo method, and relates to a resampling apparatus that resamples hypotheses according to weighting.

  As a method of estimating state quantities (parameters) based on observation information and a model that probabilistically and statistically represents the relationship between observed quantities and state quantities, a sequential Monte Carlo method (particle filter, particle filter or CONDENSATION Etc.). In the sequential Monte Carlo method, the probability density distribution of state quantities is discretized (sampled) in the spatial direction, and thus stochastic behavior in a multidimensional state space can be efficiently simulated. In the sequential Monte Carlo method, the quantity in the discretized state space is called a hypothesis (particle), and the probability density distribution is approximated by a plurality of finite particles.

  In the sequential Monte Carlo method, it is widely performed to weight each particle. Thereby, the probability density is expressed by the product of the density and weight of the particles in the state space. Thus, in the sequential Monte Carlo method, weighting each particle increases the degree of freedom of expression, so that the probability density function can be approximated with higher accuracy.

  On the other hand, in the sequential Monte Carlo method, if the number of particles with a small weight increases, a large number of particles with little contribution are present, resulting in waste. Therefore, an operation of omitting particles with little contribution is performed by reorganizing new particles (weighting is made more uniform) so that the appearance frequency corresponds to the weighting. This operation is called resampling (or resampling) (see, for example, paragraph 0002 and non-patent document 1 of Patent Document 1).

JP 2010-117865 A

A Doucet, N de Freitas and N Gordon: "Sequential Monte Carlo Methods in Practice," Springer, 2001. ISBN 978-0387951461.

 However, the resampling process requires a special random number generator that occurs at a frequency according to the weighting. Note that “occurs at a frequency according to weighting” means that the more highly weighted particles have a higher probability of generating random numbers. A special random number that occurs at a frequency according to such weighting can be generated by, for example, considering the cumulative weight density distribution as a cumulative probability density distribution and substituting a uniform random number for its inverse function. Conventionally, the operation is performed by software processing, and it has not been considered to realize the above functions at high speed by hardware processing using a logic circuit or a sequential circuit.

  Further, in the conventional sequential Monte Carlo method, it is usual to perform calculations using a very large number of particles (for example, about 1,000 to 100,000). Re-sampling was realized by random access by addressing with random numbers. Therefore, in the conventional sequential Monte Carlo method, random access to the memory occurs as many times as the product of the number of dimensions and the number of particles, which is a bottleneck for computation especially when the state quantity dimension (that is, particle dimension) is high. It was.

  On the other hand, depending on applications such as image processing, the number of particles may be relatively small. However, when the state space is extremely high, or a large number of sequential Monte Carlo methods must be executed in parallel. There is a case. In such applications, random access of memory increases in proportion to the number of dimensions and the number of parallel processes, so there is an advantage when the number of particles is small (for example, an advantage such as speeding up by resampling) ) Could not be saved.

  The present invention has been made in view of the above points, and an object of the present invention is to realize high-speed resampling by parallel switching operation while avoiding random access of a memory, and is particularly advantageous when the number of particles is small. It is an object to provide a simple resampling apparatus.

  In order to solve the above-described problem, the resampling apparatus according to claim 1 is configured such that a plurality of hypotheses that are candidates for the solution of the parameter used when estimating the parameter of the model by the sequential Monte Carlo method are displayed. A re-sampling device that re-samples according to a likelihood value indicating a configuration, comprising a cumulative likelihood value calculation means, a uniform random number generation means, a plurality of comparison means, a priority encoder, and a matrix switch It was.

  Accordingly, the resampling apparatus sequentially inputs likelihood values corresponding to a plurality of hypotheses to the cumulative likelihood value calculating unit, and the cumulative value at the time when the likelihood value is input by the cumulative likelihood value calculating unit. A likelihood value is calculated each time the likelihood value is input. Further, the resampling device generates a uniform random number less than the maximum cumulative likelihood value calculated by the cumulative likelihood value calculating unit by the uniform random number generating unit a predetermined number of times at predetermined time intervals. . Note that the uniform random number means a random number that can be regarded as uniform within a specified interval, that is, a random number such that all the numbers appear with the same probability within a predetermined interval.

  Further, the resampling device uses each of the plurality of cumulative likelihood values calculated in the cumulative likelihood value calculating unit and the uniform random number generated by the uniform random number generating unit by the plurality of comparing units. Compare each time a uniform random number is generated. Further, the resampling device selects the maximum cumulative likelihood value from among the cumulative likelihood values determined by the priority encoder to be equal to or less than the uniform random number in the plurality of comparison means, and the maximum cumulative likelihood A code indicating a hypothesis corresponding to the likelihood value input to the cumulative likelihood value calculation means when the value is calculated is generated each time a comparison result is input from a plurality of comparison means. The re-sampling apparatus controls a contact corresponding to a plurality of hypotheses indicated by a plurality of codes generated in the priority encoder by the matrix switch, wherein a plurality of hypotheses are input to the matrix switch including the plurality of contacts. Outputs a plurality of resampled hypotheses.

  As described above, the resampling apparatus determines a plurality of hypotheses to be resampled by a series of processes in the cumulative likelihood value calculating means, the uniform random number generating means, the plurality of comparison means, and the priority encoder. When a plurality of hypotheses are input to the matrix switch, a plurality of resampled hypotheses determined by the above-described series of processes are output from the matrix switch at a time. Therefore, according to the resampling apparatus, since it is not necessary to store a plurality of hypotheses (particles) in the memory, random access to the memory does not occur. Further, according to the resampling device, when a plurality of hypotheses before sampling are input to the matrix switch, a parallel switching operation in which a plurality of hypotheses after resampling are output at a time can be realized. .

  The resampling apparatus according to claim 2 is the resampling apparatus according to claim 1, wherein the cumulative likelihood value calculating means includes an adding means and a shift register.

  As a result, the resampling apparatus sequentially inputs a plurality of likelihood values corresponding to a plurality of hypotheses to the adding means, and sequentially adds the plurality of likelihood values by the adding means. A plurality of cumulative likelihood values corresponding to the number of values are calculated. Further, cumulative likelihood values are sequentially input from the adding means to the shift register, and a plurality of cumulative likelihood values are simultaneously output to the plurality of comparing means by the shift register.

  In this way, the resampling device converts the input likelihood value sequence into a cumulative likelihood value sequence by the adding means and the shift register, and calculates a plurality of cumulative likelihood sequences constituting the cumulative likelihood value sequence. It can output simultaneously with respect to several comparison means.

  According to the first and second aspects of the invention, it is not necessary to store hypotheses (particles) in a memory by performing hardware processing using a logic circuit or a sequential circuit, and a plurality of hypotheses (particles) ) Can be resampled at a time, and high-speed resampling can be realized by parallel switching operations while avoiding random access of the memory. Further, according to the inventions according to claim 1 and claim 2, since the processing can be performed in parallel even when the state space is higher order, the number of dimensions is reduced when the number of particles is small. Regardless, resampling can be performed at high speed.

It is a block diagram which shows the structural example of the resampling apparatus which concerns on this invention. It is a block diagram which shows the structural example of the shift register with which the resampling apparatus which concerns on this invention is provided. It is a block diagram which shows the structural example of the addition means with which the resampling apparatus which concerns on this invention is provided. It is a timing chart which shows the input / output timing of the resampling apparatus which concerns on this invention. It is a block diagram which shows the structural example of the uniform random number generation means with which the resampling apparatus which concerns on this invention is provided. It is a timing chart which shows the input timing of the uniform random number generation means with which the resampling apparatus which concerns on this invention is equipped.

  A resampling apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the following description, the same configuration is given the same name and symbol, and detailed description is omitted.

  The resampling apparatus 1 resamples a plurality of hypotheses used when estimating parameters of a model by the sequential Monte Carlo method according to likelihood values corresponding to the hypotheses. Here, the hypothesis means a candidate for the solution of the model parameter described above. The likelihood value means a value indicating the likelihood of each hypothesis.

  For example, in the case of tracking (tracking) the posture (position, orientation) of a human face in an image, the resampling apparatus 1 positions the human face in the image (two-dimensional) and size (one-dimensional). , Embedded in a parameter estimation device for estimating a face posture parameter or the like having a direction (three dimensions). This parameter estimation apparatus first creates a plurality of hypotheses of the face posture parameters described above, and evaluates how likely each hypothesis is for the image of the current frame (likelihood evaluation). Then, the parameter estimation device performs final posture parameter estimation using the likelihood of each hypothesis. In such a parameter estimation device, the resampling device 1 performs resampling of hypotheses according to the above-described likelihood, and performs processing to omit hypotheses with little contribution.

  Here, the resampling apparatus 1 includes a shift register 10, an adding means 12, a uniform random number generating means 13, a comparing means 14, a priority encoder 15, a counting means 16, and a matrix, as shown in FIG. Control means 17 and matrix switch 18 are provided. Then, as shown in FIG. 1, the resampling apparatus 1 converts a plurality of hypotheses (particles) 1 to H input from the external hypothesis (particle) generation unit (not shown) to the matrix switch 18 into an external likelihood (not shown). Resample into hypotheses (particles) 1 to K based on a plurality of likelihood values input from the degree evaluation means to the adding means 12 and the uniform random numbers generated by the uniform random number generating means 13. . Note that the shift register 10 and the adding unit 12 included in the resampling apparatus 1 function as a cumulative likelihood value calculating unit for calculating a cumulative likelihood value from a likelihood value input from the outside, as will be described later. . Further, the above-mentioned “H” and “K” mean integers of 2 or more, and they may be either the same number or not the same number.

  The shift register 10 holds data while shifting it internally in synchronization with a predetermined clock. Specifically, as shown in FIG. 1, the shift register 10 holds each of a plurality of cumulative likelihood values sequentially input from the adding unit 12, and stores each of the cumulative likelihood values with respect to a plurality of comparing units 14 to be described later. Output likelihood values simultaneously. As shown in FIG. 1, the shift register 10 includes a plurality of delay units 11-1, 11-2, 11-3,..., 11-H. That is, as shown in FIG. 1, the shift register 10 is configured by cascaded delay means for H stages.

As shown in FIG. 1, the cumulative likelihood value is sequentially input from the adding means 12 to the shift register 10 at the timing of the clock φ ₁ . This cumulative likelihood value is obtained by sequentially adding likelihood values sequentially input from an external likelihood evaluation unit (not shown), and the value increases as it is input later. Then, as shown in FIG. 1, the shift register 10 converts the cumulative likelihood values sequentially input into delay means 11-H,..., Delay means 11-3, delay means 11-2, delay means 11-1. Are sequentially shifted upward, and the delay means 11-1, 11-2, 11-3,..., 11-H hold the cumulative likelihood values. In the following description, a plurality of delay units 11-1, 11-2, 11-3,..., 11-H are included, and “delay unit 11-h (h is an integer of 1 to H”). ) ".

The delay means 11-h holds the input numerical value at the clock input timing and discards the numerical value at the reset input timing. The numerical value held or discarded by the delay unit 11-h may be an integer, a fixed point, or a floating point. Delay means 11-h, as specifically shown in FIG. 1, the cumulative likelihood value input from the addition unit 12 to be described later, at clock phi ₁ of the timing input from an external clock generator (not shown) At the same time, it is discarded at the timing of a reset input R input from an external reset generation means (not shown) and a value of zero is output.

Here, as described above, the cumulative likelihood value is obtained by adding a plurality of likelihood values input from an external likelihood evaluation unit (not shown). For example, when likelihood values L ₁ , likelihood values L ₂ , likelihood values L _3, and likelihood values L ₄ are input in this order to the adding means 12 of the resampling apparatus 1, Every time a frequency value is input, the cumulative likelihood value A ₁ (= L ₁ ), the cumulative likelihood value A ₂ (= L ₁ + L ₂ ), and the cumulative likelihood value A ₃ (= L ₁ + L ₂ + L ₃ ) and cumulative likelihood value A ₄ (= L ₁ + L ₂ + L ₃ + L ₄ )) are sequentially calculated and sequentially input to the delay means 11-h (here, h = 4). In this way, the cumulative likelihood value is calculated by the adding means by the same number as the number of likelihood values input from an external likelihood evaluating means (not shown), and sequentially input to the delay means 11-h.

  Specifically, the delay unit 11-h can be realized by a D (Delay) flip-flop with a reset input as shown in FIG. Here, the number of stages in the vertical direction of the delay means 11-h corresponds to the number H of likelihood values (or particles) input to the resampling apparatus 1, as shown in FIG. That is, when the number H of likelihood values input to the resampling apparatus 1 is four, for example, the delay unit 11-h is arranged in at least four stages in the vertical direction.

  The number of stages in the left-right direction of the delay unit 11-h is the number H of likelihood values input to the resampling apparatus 1 and the range of likelihood values (for example, the number of bits when the likelihood values are expressed in binary numbers). ). In other words, the delay means 11-h has four likelihood values H input to the resampling apparatus 1 when, for example, a binary number is input, and the range of the respective likelihood values is If it is 0 or more and 255 or less (that is, 8 bits or less in binary), at least 10 stages are arranged in the left-right direction. For example, the likelihood value “255” is input to the adding unit 12 of the resampling apparatus 1 four times, and the cumulative likelihood value “1020” is input from the adding unit 12 to the delay unit 11-h. This is to prevent the digits from overflowing even if “(that is, 10 bits in binary)” is input.

As shown in FIG. 1, the delay means 11-h sequentially receives cumulative likelihood values A ₁ , A ₂ , A ₃ ,..., A _H from an adder means 12 to be described later in synchronization with the clock φ _1. Entered. The delay means 11-h at the timing of the rising edge of the clock phi _1, towards the delay means 11-1 uppermost from the bottom of the delay means 11-H, cumulative likelihood values _A 1, _{A 2} , A ₃ ,..., A _H are sequentially shifted and held one step at a time. The delay means 11-h, the comparison means 14-1,14-2, ···, 14- (H- 1) relative to the cumulative likelihood values _{A 1, A 2, A 3} , ··· Are simultaneously output, and the maximum cumulative likelihood value A _H is output to the uniform random number generation means 13. In the following description, a plurality of cumulative likelihood values A ₁ , A ₂ , A ₃ ,..., A _H are comprehensively expressed as “cumulative likelihood value A _h (h is an integer of 1 or more and H or less). May be written.

The adding means 12 adds the input numerical values. Note that the two numerical values added by the adding means 12 may be an integer, a fixed point, or a floating point. As shown in FIG. 1, the adding means 12 receives likelihood values L ₁ , L ₂ , L ₃ ,..., L _H sequentially from an external likelihood evaluation means (not shown) in synchronization with the clock φ _1. In addition to the input, cumulative likelihood values are sequentially input from the delay means 11 -H arranged at the bottom of the shift register 10 in synchronization with the clock φ ₁ . Here, the likelihood values L ₁ , L ₂ , L ₃ ,..., L _H are input to a plurality of hypotheses (particles) 1 to _H to be resampled, which are input to the matrix switch 18 described later. It corresponds.

Then, the adding unit 12 further calculates the cumulative likelihood value by adding both, and outputs this to the delay unit 11-H. That is, the addition means 12, the likelihood value _{L 1, L 2, L 3} , ···, whenever _{the L H} is input, the likelihood values _{L 1, L 2, L 3} , ···, L The cumulative likelihood value at the time when _H is input is calculated, and the cumulative likelihood value is output to the delay unit 11-H. In the following description, a plurality of likelihood values L ₁ , L ₂ , L ₃ ,..., L _H are comprehensively expressed as “likelihood value L _h (h is an integer from 1 to H)”. May be written.

The adding means 12 can be realized by, for example, one or more half adders and zero or more full adders when the two input numerical values are expressed as integers or binary numbers with a fixed point. However, specific configuration of the adding means 12 is dependent range of values of the likelihood values L _h input from the outside of the likelihood evaluation unit (not shown). For example, one of the values input to the adding means 12, that is, when the range of the likelihood values L _h input from the outside of the likelihood evaluation unit (not shown) is an integer value of 0 ≦ m ≦ M, input to the adding means 12 The other value, that is, the cumulative likelihood value input from the delay means 11-H is an integer value of 0 or more and M × (H−1) or less. Therefore, in this case, the minimum number of half adders constituting the adding means 12 can be calculated by the following expression (1), and the minimum number constituting the adding means 12 can be calculated by the following expression (2). The number of full adders can be calculated.

The adding means 12 has a range of likelihood values L _h inputted from an external likelihood evaluating means (not shown), for example, of 0 or more and 255 or less, and is inputted to the stage number H of the shift register 10, that is, the resampling device 1. When the number H of likelihood values is 8, as shown in FIG. 3, the likelihood value can be composed of at least 5 half adders and 7 full adders. In FIG. 3, a block having terminals A, B, S and C represents a half adder, and a block having terminals A, B, X, S and C represents a full adder. ing. The symbols of the terminals of the half adder and full adder in FIG. 3 are A and B for the adder input, X for the carry input, S for the addition result output, and C for the carry output.

In the resampling apparatus 1, the shift register 10 and the adding means 12, that is, the cumulative likelihood value calculating means are configured as described above, so that the delay means 11-1 at the uppermost stage changes to the delay means 11-H at the lowermost stage. The cumulative likelihood values A _h appear in the direction. That is, in the resampling apparatus 1, a likelihood sequence (likelihood values L ₁ , L ₂ , L ₃ ,..., L _H ) is input from an external likelihood evaluation unit (not shown) to the adding unit 12. Then, the cumulative likelihood sequence (cumulative likelihood values A ₁ , A ₂ , A ₃ ,..., A _H ) is output from the delay unit 11-h.

Hereinafter, operations of the delay unit 11-h and the addition unit 12 will be briefly described with reference to FIG. In the following description, the case of the four the number H of likelihood values L _h inputted to the resampling apparatus 1 (i.e. four stages of stages H delay means 11-h) is described. Further, the interrupted portions in the timing chart of FIG. 4 indicate that intermediate operations are omitted.

First, when the likelihood value L ₁ is input from the outside at the timing of the _first rising edge of the clock φ ₁ , the adding unit 12 uses the accumulated likelihood value A ₁ as the cumulative likelihood value A _1. For convenience of explanation, it is output to “delay means 11-4”). Then, the delay unit 11-4 holds the cumulative likelihood value A ₁ (= likelihood value L ₁ ) input from the addition unit 12.

Next, the adder 12 receives the likelihood value L ₂ from the outside at the timing of the _second rising edge of the clock φ _{1 and also} the accumulated likelihood value A ₁ (= likelihood value) from the delay unit 11-4. When L ₁ ) is input, the cumulative likelihood value A ₂ (= likelihood value L ₁ + L ₂ ) is calculated by adding both, and this is output to the delay means 11-4. Then, the delay unit 11-4 shifts the cumulative likelihood value A ₁ (= likelihood value L ₁ ) to the upper delay unit 11-3, and the cumulative likelihood value A input from the addition unit 12. ₂ (= likelihood value L ₁ + L ₂ ) is held.

Next, the addition unit 12, along with the likelihood value L ₃ is input from the outside at a timing of the third clock phi ₁ rising edge, delay means 11-4 cumulative likelihood value A ₂ from ₍₌ likelihood value When L ₁ + L ₂ ) is input, the cumulative likelihood value A ₃ (= likelihood value L ₁ + L ₂ + L ₃ ) is calculated by adding both, and this is output to the delay means 11-4. Then, the delay unit 11-4 shifts the cumulative likelihood value A ₂ (= likelihood value L ₁ + L ₂ ) to the upper delay unit 11-3, and the cumulative likelihood input from the addition unit 12 The value A ₃ (= likelihood value L ₁ + L ₂ + L ₃ ) is held. The delay means 11-3 shifts the cumulative likelihood value A ₁ (= likelihood value L ₁ ) to the upper delay means 11-2, and the cumulative likelihood input from the delay means 11-4. The value A ₂ (= likelihood value L ₁ + L ₂ ) is held.

Then, the addition means 12, together with the likelihood value L ₄ is input from the outside at a timing of the fourth clock phi ₁ of the rising edge, the cumulative likelihood value A ₃ from the delay unit 11-4 ₍₌ likelihood value When L ₁ + L ₂ + L ₃ ) is input, the two are added to calculate a cumulative likelihood value A ₄ (= likelihood value L ₁ + L ₂ + L ₃ + L ₄ ), and this is sent to the delay means 11-4. Output. Then, the delay unit 11-4 shifts the cumulative likelihood value A ₃ (= likelihood value L ₁ + L ₂ + L ₃ ) to the upper delay unit 11-3, and the cumulative value input from the addition unit 12 The likelihood value A ₄ (= likelihood value L ₁ + L ₂ + L ₃ + L ₄ ) is held. The delay unit 11-3 shifts the cumulative likelihood value A ₂ (= likelihood value L ₁ + L ₂ ) to the upper delay unit 11-2, and the cumulative value input from the delay unit 11-4. The likelihood value A ₃ (= likelihood value L ₁ + L ₂ + L ₃ ) is held. The delay unit 11-2 shifts the cumulative likelihood value A ₁ (= likelihood value L ₁ ) to the upper delay unit 11-1, and the cumulative likelihood input from the delay unit 11-3. The value A ₂ (= likelihood value L ₁ + L ₂ ) is held.

By the operation as described above, the cumulative likelihood calculating means synchronizes with the clock φ ₁ , and the cumulative likelihood value A corresponding to the number of likelihood values L ₁ , L ₂ , L ₃ , L ₄ by the adding means 12. ₁ , A ₂ , A ₃ , A ₄ are calculated, and the cumulative likelihood values A ₁ , A ₂ , A ₃ , A ₄ are respectively held by the delay means 11-1, 11-2, 11-3, 11-4. To do. Then, in synchronism with the clock phi _2, delay means 11-4 outputs the cumulative likelihood value _{A 4} against the uniform random number generator 13, a delay unit 11-1, 11-2, Outputs the cumulative likelihood values A ₁ , A ₂ , A ₃ to the plurality of comparison means 14. Hereinafter, the remaining configuration of the resampling apparatus 1 will be described.

The uniform random number generation means 13 generates a uniform random number. As described above, the uniform random number means a random number that can be regarded as uniform within a specified section. Uniform random number generator 13, as shown in FIG. 1, each uniform random number of a predetermined time interval, i.e. with generating each clock phi _2, a predetermined number of times, i.e., the same K occurrences and the number of the output particles Let As shown in FIG. 1, the uniform random number generating means 13 receives the cumulative likelihood value A _H from the delay means 11 -H arranged at the lowest stage of the shift register 10. The uniform random number generator 13, based on the cumulative likelihood value A _H, to generate a uniform random number in the range from 0 to less than A _H. That is, uniform random number generator 13 generates a maximum uniform random number less than the cumulative likelihood value A _H of which is calculated by the addition means 12.

The uniform random number generation means 13 is for a random value s generated by a pseudo-random number generation circuit such as an M series or a PN series (the minimum value that s can take is 0 and the maximum value is A _H or more). Te, it can be realized by providing a remainder operation by cumulative likelihood value a _H input from the delay unit 11-H. Therefore, as shown in FIG. 5, the uniform random number generation means 13 includes a pseudo random number generation circuit 20, a shift register 21, a switching circuit 22, a latch circuit 23, a subtraction circuit 24, and a shift register. 25 and the latch circuit 26.

  The pseudo random number generation circuit 20 generates pseudo random numbers. As described above, the pseudo-random number generation circuit 20 can be configured by, for example, an M-sequence or PN-sequence random number generation circuit. Here, as shown in FIG. 5, the shift register 21 has three exclusive OR gates. It consists of a connected M-sequence generation circuit with a period of 65535.

The shift register 21 is the remaining structure of the uniform random number generator 13, switching circuit 22, a latch circuit 23, subtraction circuit 24 and the shift register 25, remainder operation for performing residue operation by cumulative likelihood value A _H described above It constitutes a circuit. Since these configurations are general, detailed descriptions are omitted.

  Hereinafter, the operation of the uniform random number generation means 13 will be briefly described with reference to FIG. 6 (refer to FIG. 5 as appropriate). Further, the interrupted portions in the timing chart of FIG. 6 indicate that intermediate operations are omitted.

First, as shown in FIG. 6, the uniform random number generation means 13 updates the pseudo random number value s of the pseudo random number generation circuit 20 by the clock φ ₃ . Next, as shown in FIG. 6, the uniform random number generation means 13 sets the control signal c ₁ to a low level, so that the switch group of the switching circuit 22 is brought down to the pseudo random number generation circuit 20 side while shifting to the shift register 25. To clear. Next, as shown in FIG. 6, the uniform random number generation means 13 gives the first positive pulse to the clock φ ₄ , and the pseudo random number value s generated by the pseudo random number generation circuit 20 in the latch circuit 23. Latch. Then, the uniform random number generator 13, as shown in FIG. 6, in a state where the control signal c ₂ and the low level, the clock phi ₅ to give the first positive pulse, H-th cumulative likelihood value It sets the output value (cumulative likelihood value output from the bottom of delay means 11-H of the shift register 10 a _H) to the shift register 25, then the control signal c ₂ to a high level.

Then, the uniform random number generator 13, as shown in FIG. 6, the clock phi ₄ and the clock phi _5, until the second through (bit width -1) th (15-th in the example of FIG. 5), alternately It gives a positive pulse (provided that precede the clock phi ₄ to the clock phi _5). Thus, the result of subtracting "an integral multiple of A _H" maximum that can pull from the random number value s of the pseudo-random number (i.e., remainder upon dividing the s in A _H (R = s% A _H)) is a subtraction circuit Appears in 24 outputs. The uniform random number generator 13, as shown in FIG. 6, the last by giving a positive pulse to the clock phi _2, 0 or A _H less than an integer of uniform random numbers R (hereinafter, referred to simply as the random number R ) Is latched in the latch circuit 26 to obtain a random number output. Thus, the uniform random number generator 13 generates a random number R for each clock phi _2, as shown in FIG. 1, in each case outputs the random number R to a plurality of comparing means 14.

Note that “A _H-1 is the maximum value of the random number R” in the timing chart of FIG. 6 means that the maximum value of the random number R compared with the cumulative likelihood value is substantially A in the comparison means 14 described later. It shows that it is _H-1 . That is, uniform random number generator 13 is capable of generating a random number R from 0 to less than A _H as described above, as shown in FIG. 1, disposed at the bottom of the shift register 10 to the comparator 14 delay means 11-H from the cumulative likelihood value A _H is not input. Therefore, if the random number R between A _{H-1 and} A _H is generated by the uniform random number generation means 13 and the random number R is input to the comparison means 14, the value of the comparison result D _h described later is always 0. Become. Therefore, “A _H−1 becomes the maximum value of the random number R” in the timing chart of FIG. 6 indicates that the substantial maximum value of the random number R is A _H−1 .

  The comparing means 14 compares the magnitudes of the two input numerical values. As shown in FIG. 1, the comparison unit 14 includes a plurality of comparison units 14-1, 14-2,..., 14-(H−1). That is, as shown in FIG. 1, the comparison means 14 is configured by cascade connection of H-1 stages, although the comparison means is one less than the number H of delay means constituting the shift register 10.

As shown in FIG. 1, the cumulative likelihood values A _h are simultaneously input to the plurality of comparison means 14 from the delay means 11-h excluding the delay means 11-H, and from the uniform random number generation means 13. A random number R is input simultaneously. Then, each time the uniform random number R is generated and inputted by the uniform random number generating means 13, the comparing means 14, as shown in the following formula (3), the cumulative likelihood value A _h and the random number R comparing the magnitude of the, and outputs the comparison result D _h in the priority encoder 15. That is, as shown in the following formula (3), the comparison unit 14 outputs “comparison result D _h = 0” when the cumulative likelihood value A _h is larger than the random number R, and the cumulative likelihood value A _h is If it is less than or equal to the random number R, “comparison result D _h = 1” is output.

Here, “output comparison result D _h ” means that, for example, H likelihood values L ₁ , L ₂ , L ₃ ,..., L _H are input to the adding means 12 of the resampling apparatus 1. In this case, the comparison unit 14 outputs the H-1 comparison results D ₁ , D ₂ , D ₃ ,..., D _H-1 which is one less than the input likelihood value L _h to the priority encoder 15. Is output to. In the above equation (3), the value of D _h "0" is read as a low level, the value of D _h "1" may be read as a high level.

For example, if the number H of the likelihood values L _h inputted to the adding means 12 of the resampling apparatus 1 is four (i.e. delay means 11-h of stages H 4 stages), the comparison means 14-1 the cumulative likelihood value _{a 1} from the delay unit 11-1 is input to the comparison means 14-2, the cumulative likelihood value _{a 2} from the delay unit 11-2 is input. Then, (for convenience of explanation, a "comparison means 14-3") lowermost comparing means 14, the cumulative likelihood value A ₃ from the delay unit 11-3 lowermost is input. At the same time, the comparison means 14-1, 14-2, 14-3, the random number R are input in synchronism with the clock phi _2.

Then, comparison means 14-1, the comparison result _{D 1} of the cumulative likelihood value _{A 1} and the random number R output to the priority encoder 15, the comparison means 14-2, the cumulative likelihood value _{A 2} and the random number R the comparison result _{D 2} and outputs the priority encoder 15, the comparison means 14-3 outputs the comparison result _{D 3} between the cumulative likelihood value _{a 3} and the random number R to the priority encoder 15. Thus, when four likelihood values L ₁ , L ₂ , L ₃ , and L ₄ are input to the adding means 12 of the resampling apparatus 1, the three comparison results D ₁ and D are input to the priority encoder 15. _2, so that _{the D 3} are input at the same time.

For example, the comparison unit 14 is implemented as a subtraction circuit that calculates the difference between the cumulative likelihood value A _h and the random number R, and the borrow flag of the most significant bit that appears as a result of calculating R−A _h is set as the comparison result D _h. Can do.

The priority encoder 15 outputs a code corresponding to the input with the highest priority. The priority encoder 15, specifically as shown in FIG. 1, a plurality of comparison means 14-1, 14-2, ..., a comparison result _{D h} from each 14- (H-1) is input The This comparison result D _h is composed of a numerical value (flag) of 0 or 1 as shown in the above-described equation (3). The priority encoder 15 then selects D _h = 1 (random number R) among the plurality of comparison results D _h input from the plurality of comparison units 14-1, 14-2,..., 14-(H−1). The comparison result determined to be the following is selected, and the largest “h” is selected from the comparison results D _h having a value of 1. When D _h = 0 for all h, it is assumed that the maximum “h” is 0.

Here, among the above-described plurality of comparison results D _h , those that satisfy D _h = 1 (comparison results determined to be equal to or less than the random number R) are selected, and among the comparison results D _h whose value is 1. In other words, “the largest“ h ”is selected” is an accumulation determined by the plurality of comparison means 14-1, 14-2,..., 14-(H−1) to be equal to or less than the random number R. elect that the likelihood value a _h, from these cumulative likelihood value a _h, with selecting a maximum cumulative likelihood value a _h, index (subscript of the cumulative likelihood value a _h ) That is “h” is selected.

Then, the priority encoder 15 outputs (h + 1) obtained by adding 1 to the selected h to the matrix control means 17 as the sample point P. Here, in other words, the sample point P corresponds to the likelihood value L _h input to the adding means 12 (cumulative likelihood value calculating means) when the above-mentioned maximum cumulative likelihood value A _h is calculated. It means a code that indicates a hypothesis to be performed. Incidentally, the priority encoder 15, a plurality of comparing means 14-1 and 14-2 described above, ..., each time the comparison result _{D h} is input from 14- (H-1), code (sample point P) Is generated and output to the matrix control means 17.

For example, if the number H of the likelihood values L _h inputted to the resampling apparatus 1 is four (i.e. delay means 11-h of stages H 4 stages), the priority encoder 15, comparison means 14 1 comparison results _{D 1} is the comparison result _{D 2} from the comparison means 14-1, (for convenience of explanation, a "comparison means 14-3") lowermost comparison result _{D 3} from the input of the comparator means 14 . For example, when the values of the comparison results D ₁ , D ₂ , and D ₃ are “D ₁ = 1, D ₂ = 1, and D ₃ = 0”, the priority encoder 15 compares the values of 1. “2” which is the maximum “h” (index, subscript number) of the results D ₁ and D ₂ is selected, and a code (sample point P) of “3” obtained by adding 1 to “2” is selected. It outputs to the matrix control means 17.

Here, the sampling point P generated by the priority encoder 15 indicates a hypothesis to be resampled. Therefore, in the above-described example, the process of selecting “3” by adding 1 to the maximum “h” of the comparison results D ₁ and D ₂ having a value of 1 by the priority encoder 15 is performed by the comparing means 14- 3. After selecting the largest cumulative likelihood value A ₂ among the cumulative likelihood values A ₁ and A ₂ determined to be equal to or less than the random number R by 3, the cumulative likelihood that is one step larger than the cumulative likelihood value A ₂ select degree value a _3, will correspond to a process that selects the hypothesis corresponding to the likelihood value L ₃ which is input to the adding means 12 when the accumulated likelihood value a ₃ is calculated.

As a result of the above processing, the sampling point P of “h” in which the 1 (high level) bit is set out of the comparison result D _h of the comparison means 14 is converted into an approximately uniform random number R by the inverse of the cumulative likelihood function. It approximates the result assigned to the function. That is, the sample point P occurs with a probability that is approximately proportional to the cumulative likelihood function.

Counting means 16 is a counter for counting at the timing of the clock phi ₂ to 1 to K. As shown in FIG. 1, K is the number of particles after re-sampling (natural number), and is set in advance as an arbitrary number. Counting means 16, for example, may be used the binary counter, as shown in FIG. 1, in synchronism with the clock phi _2, and outputs the count value k in the matrix control unit 17.

  The matrix control unit 17 controls the connection / disconnection of the matrix switch 18 based on the sample point P (code) input from the priority encoder 15 and the count value k input from the counting unit 16. . Specifically, as shown in FIG. 1, the matrix control means 17 receives the Pth input (in FIG. 1, the line number in FIG. 1) when the sample point P is inputted from the priority encoder 15 and the count value k is inputted from the counting means 16. ) And the kth output (column in FIG. 1) are closed, and the contact between the input other than the Pth (row in FIG. 1) and the kth output (column in FIG. 1) is opened. A signal is generated and output to the matrix switch 18. Thereby, the matrix control means 17 connects the output of each of the 1st to Kth particles (hypothesis) to one input among the inputs of the 1st to Hth particles as shown in FIG. As a result, the H particles input to the matrix switch 18 can be mapped to K particles after resampling and output.

  The matrix switch 18 resamples a plurality of hypotheses (particles) input from the outside into a plurality of hypotheses (particles) by a switching operation. As shown in FIG. 1, the matrix switch 18 has contacts arranged in a grid pattern, and is configured to close or open these contacts in accordance with a contact control signal input from the matrix control means 17. Further, as shown in FIG. 1, the contacts provided in the matrix switch 18 include a plurality of hypotheses (particles) 1 to H before re-sampling input from the outside and a plurality of hypotheses after re-sampling output to the outside. (Particles) 1 to K. The matrix switch 18 can be realized by a switch made of, for example, CMOS (Complementary Metal Oxide Semiconductor).

  As shown in FIG. 1, a plurality of hypotheses (particles) 1 to H before re-sampling are input to the matrix switch 18 from an external hypothesis (particle) generation unit (not shown). A control signal is input. The contact control signal includes information on the sample point P (code) generated by the priority encoder 15 and the count value k counted by the counting means 16. Then, the matrix switch 18 outputs a plurality of hypotheses (particles) 1 to K after re-sampling by controlling the contacts shown in FIG. 1 based on the contact control signal. By such processing, the relationship between the particle input and the particle output in the matrix switch 18 becomes the relationship between the particles before resampling and the particles after resampling. That is, when a plurality of particle state quantities (a plurality of hypotheses 1 to H) are input to the matrix switch 18, re-sampling is immediately performed, and a plurality of particle state quantities after the re-sampling (a plurality of hypotheses 1 to 1). K) is output.

  The resampling apparatus 1 having the above configuration includes a series of processes in the cumulative likelihood value calculating means (the adding means 12 and the shift register 10), the uniform random number generating means 13, the plurality of comparing means 14, and the priority encoder 15. To determine a plurality of hypotheses to be resampled. When a plurality of hypotheses are input to the matrix switch 18, a plurality of resampled hypotheses determined by the above-described series of processes are output from the matrix switch 18 at a time. Therefore, according to the resampling apparatus 1, since it is not necessary to store a plurality of hypotheses (particles) in the memory, random access to the memory does not occur. Further, according to the resampling apparatus 1, when a plurality of hypotheses before sampling are input to the matrix switch 18, a parallel switching operation is realized in which a plurality of hypotheses after resampling are output at a time. Can do.

  Therefore, according to the resampling apparatus 1, it is not necessary to store hypotheses (particles) in a memory by performing hardware processing using a logic circuit or a sequential circuit, and a plurality of hypotheses (particles) are once stored. Therefore, high-speed re-sampling can be realized by parallel switching operation while avoiding random access of the memory. Also, according to the resampling apparatus 1, even when the state space is high-order, processing can be performed in parallel, so that when the number of particles is small, re-sampling can be performed at high speed regardless of the number of dimensions. Sampling can be performed.

  The resampling apparatus according to the present invention has been specifically described above with reference to the embodiments for carrying out the invention. However, the gist of the present invention is not limited to these descriptions, and the description of the claims Should be widely interpreted on the basis. Needless to say, various changes and modifications based on these descriptions are also included in the spirit of the present invention.

1 Resampler 10 Shift registers 11-1, 11-2, 11-3, 11-H, 11-h Delay means 12 Adder means 13 Uniform random number generator means 14, 14-1, 14-2, 14- (H-1) Comparison means 15 Priority encoder 16 Count means 17 Matrix control means 18 Matrix switch 20 Pseudo random number generation circuit 21 Shift register 22 Switching circuit 23 Latch circuit 24 Subtraction circuit 25 Shift register 26 Latch circuit

Claims (2)

A re-sampling device that re-samples a plurality of hypotheses that are candidates for a solution of the parameter used when estimating a parameter of the model by a sequential Monte Carlo method according to a likelihood value indicating the likelihood of the hypothesis,
Cumulative likelihood value calculation means for sequentially calculating the likelihood values corresponding to the plurality of hypotheses and calculating the cumulative likelihood value at the time when the likelihood value is input each time the likelihood value is input. When,
Uniform random number generating means for generating a uniform random number less than the maximum cumulative likelihood value calculated by the cumulative likelihood value calculating means for a predetermined number of times at a predetermined time interval;
Each of the plurality of cumulative likelihood values calculated by the cumulative likelihood value calculating unit and the uniform random number generated by the uniform random number generating unit are compared each time the uniform random number is generated. A plurality of comparison means,
The maximum cumulative likelihood value is selected from the cumulative likelihood values determined by the plurality of comparison means to be equal to or less than the uniform random number, and the cumulative cumulative value is calculated when the maximum cumulative likelihood value is calculated. A priority encoder that generates a code indicating a hypothesis corresponding to the likelihood value input to the likelihood value calculation means each time a comparison result is input from the plurality of comparison means;
The plurality of hypotheses are input, a plurality of contacts corresponding to the plurality of hypotheses are provided, and the contacts corresponding to the plurality of hypotheses indicated by the plurality of codes generated by the priority encoder are controlled, A matrix switch that outputs a number of resampled hypotheses;
A re-sampling device comprising: The cumulative likelihood calculating means includes
The plurality of likelihood values corresponding to the plurality of hypotheses are sequentially input, and the plurality of likelihood values corresponding to the number of input likelihood values are sequentially added by sequentially adding the plurality of likelihood values. Adding means for calculating
The cumulative likelihood value is sequentially input from the adding means, and a shift register that outputs a plurality of the cumulative likelihood values simultaneously to the plurality of comparing means;
The resampling apparatus according to claim 1, further comprising:

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