JP2013090504A - Motor drive and control system including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motor drive capable of reducing ripples of a power supply current.SOLUTION: A motor drive 70 includes two inverters 10, 20 which supply currents from a common battery 40 to the stator coils M1, M2 of a motor 30, respectively, and a control unit 50 which makes the timing of the inverter 10 for supplying a current to the stator coil M1 and the timing of the inverter 20 for supplying a current to the stator coil M2 different from each other. The control unit 50 delays a drive signal for turning the switching elements Q7-Q12 in the inverter 20 on/off behind a drive signal for turning the switching elements Q1-Q6 in the inverter 10 on/off.

Description

  The present invention relates to a motor driving device including a plurality of inverter units that supply current to a motor and a control system including the motor driving device.

  As a conventional technique, a motor driving device including a first inverter unit that supplies current to a first winding group that drives a motor and a second inverter unit that supplies current to a second winding group that drives the motor. It is known (see, for example, Patent Document 1). In this motor drive device, the current supply to the first winding set and the current supply to the second winding set start almost simultaneously.

JP 2011-142744 A

  However, the current is supplied to the winding group at the same time in the first inverter unit and the second inverter unit. In the above-described prior art, the current is drawn from the power source to the two inverter units at the same timing. The current peak at the time increases. For this reason, the ripple of the power supply current may increase as in the case where the inverter unit has one system. Further, for example, when a large LC filter or the like is used in order to suppress the ripple of the power supply current, there is a problem in terms of installation space and cost.

  Accordingly, an object of the present invention is to provide a motor drive device and a control system including the motor drive device that can reduce ripples in the power supply current.

In order to achieve the above object, a motor drive device according to the present invention includes:
A plurality of inverter units for supplying current to the motor from a common power source;
And a control unit that shifts current supply timings of the plurality of inverter units from each other.

  In order to achieve the above object, a control system according to the present invention includes a motor and a motor drive device according to the present invention.

  According to the present invention, ripple of the power supply current can be reduced.

1 is a configuration diagram of an electric power steering apparatus 100 that is an embodiment of a control system according to the present invention. FIG. It is an on / off waveform of the high-side switching elements Q1, Q3, Q5, Q7, Q9, Q11 that are switched and driven by the control unit 50 at a cycle T. 2 is a configuration diagram of an electric power steering apparatus having a control circuit 50A which is a first configuration example of a control unit 50. FIG. 3 is a configuration diagram of an electric power steering apparatus having a control circuit 50B that is a second configuration example of a control unit 50. FIG. 3 is a block diagram of a pre-driver 54. FIG. 3 is a block diagram of a delay circuit 60A that is a first configuration example of a delay unit 60. FIG. It is an operation | movement waveform of each part of the delay circuit 60A. 6 is a block diagram of a delay circuit 60B that is a second configuration example of the delay unit 60. FIG. 10 is a block diagram of a delay circuit 60C as a third configuration example of the delay unit 60. FIG. FIG. 10 is a block diagram of a delay circuit 60D that is a fourth configuration example of the delay unit 60. 3 is a circuit model that simulates the operation of the motor drive device 70. If the I ₁ and _{I 2} and driven in phase with the (waveform a), when the delayed 25μs only _{I 2} relative to _{I 1} of the (waveform b), the simulation results of _{I B.} If the I ₁ and _{I 2} and driven in phase with the (waveform c), when the 1/4 inductance and the inductor L to delay the _{I 2} 25 .mu.s respect _{I 1} (waveform d), the simulation of _{I B} It is a result.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of an electric power steering apparatus 100 which is an embodiment of a control system according to the present invention. The electric power steering device 100 is a vehicle motor control system that includes a motor 30 and a motor drive device 70 that drives the motor 30. The electric power steering device 100 transmits assist torque generated by the rotation of the motor 30 to a steering operation transmission mechanism (for example, a steering shaft, a rack bar, etc.) between the wheels and the steering hole via a gear. The electric power steering apparatus 100 can assist the driver's steering operation.

  The motor 30 is a brushless motor in which a stator coil is divided into a plurality of systems for fail-safe support. That is, no matter which stator coil is energized, the assist torque can be generated in the motor 30, so that even if one system fails, for example, the steering operation can be prevented from being affected. FIG. 1 shows that the motor 30 has two stator coils M1 and M2. Stator coils M1, M2 are all three-phase windings.

  The motor drive device 70 includes two inverter units 10 and 20 connected in parallel, a control unit 50 that controls the operation of the inverter units 10 and 20, a first LC filter that includes an inductor L and a capacitor C1, A second LC filter including an inductor L and a capacitor C2 is provided.

  The inverter units 10 and 20 supply current from the battery 40 to the motor 30. The battery 40 is a power source common to the inverter units 10 and 20. The inverter unit 10 supplies current from the battery 40 to the stator coil M1 of the motor 30, and the inverter unit 20 supplies current from the battery 40 to the stator coil M2 of the motor 30. The inverter unit 10 includes a bridge circuit having switching elements Q1 to Q6 that are switched by the control unit 50, and the inverter unit 20 includes a bridge circuit having switching elements Q7 to Q12 that are switched by the control unit 50. Specific examples of the switching elements Q1 to Q12 include semiconductor elements such as power MOSFETs and IGBTs.

  As is well known, a three-phase alternating current is generated by the switching operation of the switching elements Q1 to Q6, and the motor 30 rotates when the three-phase alternating current flows through the stator coil M1. Similarly, a three-phase alternating current is generated by the switching operation of switching elements Q7 to Q12, and the three-phase alternating current flows through stator coil M2, thereby rotating motor 30. The rotation of the motor 30 generates torque that assists the driver's steering operation.

  The first LC filter is connected to the power input unit of the inverter unit 10 so as to be inserted between the battery 40 and the inverter unit 10, and the second LC filter is connected between the battery 40 and the inverter unit 20. Is connected to the power input section of the inverter section 20. The inductor L shared by the first LC filter and the second LC filter is inserted in the power supply path so as to be connected to the battery 40 in series. The inductor L may be provided separately for the first LC filter and the second LC filter. Capacitors C1 and C2 are inserted between positive and negative power supply paths so as to be connected to battery 40 in parallel.

  The first LC filter suppresses the ripple of the power supply current flowing between the battery 40 and the inverter unit 10, and the second LC filter suppresses the ripple of the power supply current flowing between the battery 40 and the inverter unit 20. Is done. By suppressing power supply current ripple, radio noise can be reduced.

  The control unit 50 outputs drive signals for controlling the on / off timings of the switching elements Q1 to Q12 so that the inverter units 10 and 20 supply current to the motor 30 from each other. Output to each gate.

  The control unit 50 shifts the on / off timings of the U-phase switching elements Q1, Q2 of the inverter unit 10 from the on / off timings of the U-phase switching elements Q7, Q8 of the inverter unit 20. Further, the control unit 50 shifts the on / off timings of the V-phase switching elements Q3, Q4 of the inverter unit 10 and the on / off timings of the V-phase switching elements Q9, Q10 of the inverter unit 20. Further, control unit 50 shifts the on / off timings of W-phase switching elements Q5 and Q6 of inverter unit 10 and the on / off timings of W-phase switching elements Q11 and Q12 of inverter unit 20 from each other.

  FIG. 2 shows ON / OFF waveforms of the high-side switching elements Q1, Q3, Q5, Q7, Q9, and Q11 that are switched and driven by the control unit 50 at the cycle T. The on / off waveforms of the low-side switching elements Q2, Q4, Q6, Q8, Q10, and Q12 are waveforms obtained by adding a dead time to the on / off waveforms of the corresponding high-side switching elements. I will omit it.

  The control unit 50 delays the on / off timing of the switching elements Q7 to Q12 of each phase of the inverter unit 20 with respect to the on / off timing of the switching elements Q1 to Q6 of each phase of the inverter unit 10 by a delay time Td. Yes. It is preferable that the ON timings of the switching elements Q1 to Q12 are shifted from each other, and the OFF timings of the switching elements Q1 to Q12 are preferably shifted from each other. Further, it is more preferable that the on timing and the off timing of each of the switching elements Q1 to Q12 are shifted from each other. Thus, since the power supply current drawn from the battery 40 to each of the inverter units 10 and 20 can be dispersed by shifting the current supply timings of the inverter units 10 and 20 from each other, for example, without using a large LC filter. However, the ripple of the power supply current can be reduced.

  Next, a configuration example of the control unit 50 will be described.

  FIG. 3 is a configuration diagram of an electric power steering apparatus having a control circuit 50 </ b> A that is a first configuration example of the control unit 50. The control circuit 50A includes a CPU 53, a predriver 51, and a predriver 52. The pre-driver 51 is an integrated circuit that outputs a signal for driving the inverter unit 10 in accordance with a first control signal supplied from the CPU 53. The pre-driver 52 is an integrated circuit that outputs a signal for driving the inverter unit 20 in accordance with a second control signal supplied from the CPU 53. A specific example of the first control signal and the second control signal is a PWM signal.

  The CPU 53 includes a first control signal output unit that outputs a first control signal supplied to the pre-driver 51 and a second control signal output unit that outputs a second control signal supplied to the pre-driver 52. An arithmetic processing unit. Six first control signals for turning on / off the switching elements Q1 to Q6 of the inverter unit 10 are output from the six output terminals of the first control signal output unit. Six second control signals for turning on / off the switching elements Q7 to Q12 of the inverter unit 20 are output from the six output terminals of the second control signal output unit.

  The pre-driver 51 is a first drive signal output unit that outputs a first drive signal supplied to the inverter unit 10 in accordance with a first control signal supplied from the CPU 53. The pre-driver 51 outputs six input terminals to which a first control signal for each of the switching elements Q1 to Q6 of the inverter unit 10 is input and a first drive signal for turning on / off the switching elements Q1 to Q6. 12 output terminals.

  The pre-driver 52 is a second drive signal output unit that outputs a second drive signal supplied to the inverter unit 20 in accordance with a second control signal supplied from the CPU 53. The pre-driver 52 outputs six input terminals to which the second control signal for each of the switching elements Q7 to Q12 of the inverter unit 20 is input and a second drive signal for turning on / off the switching elements Q7 to Q12. 12 output terminals.

  In the pre-drivers 51 and 52, the input terminal UH receives a control signal for controlling on / off of the U-phase high-side switching element, and the input terminal UL turns on / off the U-phase low-side switching element. A control signal to be controlled is input. The same applies to the other input terminals of the V phase and the W phase.

  In the pre-drivers 51 and 52, the output terminal UHG is connected to the gate of the U-phase high-side switching element, and the output terminal UHS is connected to the source of the U-phase high-side switching element. The output terminal ULG is connected to the gate of the U-phase low-side switching element, and the output terminal ULS is connected to the source of the U-phase low-side switching element. The same applies to the other output terminals of the V phase and the W phase. By connecting not only the gate but also the source in this way, it is possible to prevent an on / off malfunction of each switching element even if the current flowing through each switching element is large.

  The CPU 53 supplies the pre-driver 52 so that the second drive signal output from the pre-driver 52 to the inverter unit 20 is delayed from the first drive signal output from the pre-drive 51 to the inverter unit 10. The second control signal is delayed from the first control signal supplied to the pre-driver 51. That is, the first control signal and the second control signal supplied from the CPU 53 are output in energization patterns that are shifted in advance from each other. Thus, since the power supply current drawn from the battery 40 to each of the inverter units 10 and 20 can be dispersed by shifting the current supply timings of the inverter units 10 and 20 from each other, for example, without using a large LC filter. However, the ripple of the power supply current can be reduced.

  FIG. 4 is a configuration diagram of an electric power steering apparatus having a control circuit 50B which is a second configuration example of the control unit 50. The control circuit 50B includes a CPU 55, a pre-driver 51, and a pre-driver 54. The pre-driver 51 is an integrated circuit that outputs a signal for driving the inverter unit 10 in accordance with a control signal supplied from the CPU 55 (hereinafter referred to as “control signal dl_in”). The pre-driver 54 is an integrated circuit that outputs a signal for driving the inverter unit 20 in accordance with the control signal dl_in and a delay signal (hereinafter referred to as “delay signal”) supplied from the CPU 55. The control signal dl_in is a common control signal shared between the pre-driver 51 that drives the inverter unit 10 and the pre-driver 54 that drives the inverter unit 20. A specific example of the control signal dl_in is a PWM signal.

  The CPU 55 is an arithmetic processing unit including a control signal output unit that outputs a control signal dl_in supplied to both the pre-driver 51 and the pre-driver 54, and a delay signal output unit that outputs a delay signal supplied only to the pre-driver 54. is there. Six control signals dl_in for turning on / off the switching elements Q1 to Q12 of the inverter units 10 and 20 are output from the six output terminals of the control signal output unit. The delay signal is output from one output terminal of the delay signal output unit. The delay signal is a signal for delaying the second drive signal supplied from the pre-driver 54 to the inverter unit 20 with respect to the first drive signal supplied from the pre-driver 51 to the inverter unit 10.

  The pre-driver 51 is a first drive signal output unit that outputs a first drive signal supplied to the inverter unit 10 in accordance with a control signal dl_in supplied from the CPU 55. The pre-driver 51 includes six input terminals to which a control signal dl_in is input and twelve output terminals to which a first drive signal for turning on / off the switching elements Q1 to Q6 is output.

  The pre-driver 54 is a second drive signal output unit that outputs a second drive signal supplied to the inverter unit 20 in accordance with the control signal dl_in and delay signal supplied from the CPU 55. The pre-driver 54 outputs six input terminals to which the control signal dl_in is input, one input terminal to which the delay signal is input, and a second drive signal for turning on / off the switching elements Q7 to Q12. 12 output terminals. The pre-driver 54 delays the control signal dl_in input to the pre-driver 54 by a delay signal, thereby delaying the control signal dl_in by an arbitrary time corresponding to the delay signal as compared with the first drive signal that drives the inverter 10. The second drive signal is output to the inverter unit 20.

  In the pre-drivers 51 and 54, the relationship between the input terminal UH, the output terminal UHG, etc. and the input / output signals is the same as described above.

  In this way, by using the delay signal, the control signal for driving the inverter units 10 and 20 (that is, the control signal dl_in) can be shared between the inverter units 10 and 20. As a result, the CPU 55 can reduce the number of terminals that output control signals for driving the inverter units 10 and 20.

  FIG. 5 is a block diagram of the pre-driver 54. The pre-driver 54 includes an OSC 61, a delay unit 60, and a buffer 62. The OSC 61 is an oscillation circuit that generates a constant clock signal ck. The delay unit 60 is a phase delay circuit that outputs a drive signal dl_out obtained by delaying the control signal dl_in according to the delay signal and the clock signal ck. The buffer 62 is an amplifier circuit that converts the drive signal dl_out into a second drive signal for driving the switching elements Q7 to Q12 of the inverter unit 20 and outputs the second drive signal. The delay unit 60 and the buffer 62 are provided for every six control signals dl_in. “** G” represents an output terminal connected to each gate of the switching element of the inverter unit 20. “** S” represents an output terminal connected to each source of the switching element of the inverter unit 20.

  Next, a configuration example of the delay unit 60 will be described.

  FIG. 6 is a block diagram of a delay circuit 60 </ b> A that is a first configuration example of the delay unit 60. FIG. 7 is an operation waveform of each part of the delay circuit 60A. The delay circuit 60A includes an OSC 61, a delay counter 63, a data latch 64, an H counter 65, an L counter 66, and an RS flip-flop 67.

  The delay counter 63 counts the pulse width (high level time) from the rising edge to the falling edge of the delay signal according to the clock signal ck. Each time the count value of the delay counter 63 is updated to zero, the data latch 64 latches and outputs the maximum value of the count value.

  On the other hand, the H counter 65 counts the elapsed time from the rising edge of the control signal dl_in according to the clock signal ck. The H counter 65 outputs the first pulse at a timing delayed from the timing of the rising edge of the control signal dl_in corresponding to the latch data output from the data latch 64. The L counter 66 counts the elapsed time from the falling edge of the control signal dl_in according to the clock signal ck. The L counter 65 outputs the second pulse at a timing delayed from the timing of the falling edge of the control signal dl_in corresponding to the latch data output from the data latch 64.

  The RS flip-flop 67 sets the level of the drive signal dl_out to a high level when the first pulse of the H counter 65 is input to the set terminal S, and the second pulse of the L counter 66 is applied to the reset terminal R. By being input, the level of the drive signal dl_out is set to a low level. As a result, the control signal dl_in can be converted into a drive signal dl_out delayed by a time corresponding to the delay signal and output.

  Therefore, in this way, the CPU 55 replaces an arbitrary delay time with the pulse width of the delay signal and outputs it, thereby delaying the signal for driving the inverter unit 20 by the arbitrary delay time. Can be realized with less circuit. As a result, such a delay circuit can be easily built in the pre-driver 54.

  For example, even if the OSC 61 is inferior in terms of the accuracy and stability of the oscillation frequency compared to the clock of the CPU 55, this configuration is a system that always calibrates with the delay signal sent from the CPU 55, so there is a problem in performance. There is no. Even if the frequency of the clock signal ck of the OSC 61 varies at 10 to 20 MHz or temperature drifts, the delay time can be set with a resolution of 0.05 to 0.1 μs.

  FIG. 8 is a block diagram of a delay circuit 60 </ b> B that is a second configuration example of the delay unit 60. The delay circuit 60B has a configuration in which the clock signal ck is supplied from a CPU outside the pre-driver. According to such a configuration, the delay circuit 60B or the pre-driver incorporating the delay circuit 60B can be downsized by eliminating the oscillation circuit.

  FIG. 9 is a block diagram of a delay circuit 60 </ b> C that is a third configuration example of the delay unit 60. The delay circuit 60C includes a synchronous communication circuit 68 in place of the delay counter and the data latch described above. The CPU serially communicates serial data sdata corresponding to the time for delaying the signal for driving the inverter unit 20 in synchronization with the clock signal sclk. The synchronous communication circuit 68 converts the serial data sdata into parallel data Dout and outputs it to the H counter 65 and the L counter 66. According to such a configuration, if communication is performed only when the delay time is changed, the drive signal of the inverter unit 20 can be delayed by the delay time.

  FIG. 10 is a block diagram of a delay circuit 60 </ b> D that is a fourth configuration example of the delay unit 60. The delay circuit 60D includes an OSC 61 that generates the clock signal ck using the resonator 69 as a resonator. The oscillator 69 is externally attached to the delay circuit 60D or a pre-driver incorporating the delay circuit 60D via the Xin terminal on the input side and the Xout terminal on the output side. Thus, an oscillator may be used to generate the clock signal ck.

  Next, experimental results of the effect of reducing the power supply current ripple will be described.

FIG. 11 is a circuit model that simulates the operation of the motor driving device 70. I _B corresponds to the power supply current flowing through the battery 40, I ₁ corresponds to the current flowing through the inverter unit 10, and I ₂ corresponds to the current flowing through the inverter unit 20.

12, when driven in phase with _{I 1} and _{I 2} and (waveform a), when the delayed 25μs only _{I 2} relative to _{I 1} of the (waveform b), the simulation results of _{I B.} As shown in FIG. 12, the ripple of the power source current I _B shown by the waveform b is, as compared with the waveform a, which is improved by about 1/4.

Moreover, if the allowable value of the ripple of the power supply current is about the value at the time of in-phase driving, the LC filter can be further reduced in size and cost. FIG. 13 shows a case where I ₁ and I ₂ are driven in the same phase (waveform c), and a case where I ₂ is delayed by 25 μs relative to I ₁ and the inductance of the inductor L is ¼ (waveform d). it is a simulation result of I _B. Ripple of the power source current I _B which inductance is indicated by waveform d of 0.5μH, the inductance as compared with the case of the waveform b in Figure 12 of 2MyuH, but slightly larger, smaller than that of the waveform c of the in-phase drive. Thus, even if the inductance of the inductor L is reduced, the ripple of the power supply current can be reduced by shifting the current supply timing of the inverter units 10 and 20 from each other.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, in the above-described embodiment, since the number of stator coils of the motor is two, an example in which two inverter units are provided has been described. However, since it is only necessary to have a plurality of inverter portions for each stator coil of the motor, when driving a motor having three or more stator coils, the number of motor driving devices is the same as the number of stator coils built in the motor. It suffices to have an inverter part.

  The present invention can also be applied to other motor control systems other than the electric power steering device.

10, 20 Inverter section 30 Motor 40 Battery 50 Control section 50A, 50B Control circuit 51, 52, 54 Pre-driver 53, 55 CPU
60 delay unit 60A-60D delay circuit 61 OSC (oscillation circuit)
62 Buffer 70 Motor drive device 100 Electric power steering device M1, M2 Stator coil Q1-Q12 Switching element

Claims (8)

A plurality of inverter units for supplying current to the motor from a common power source;
A motor drive apparatus comprising: a control unit that shifts current supply timings of the plurality of inverter units from each other.   The motor according to claim 1, wherein the control unit delays a drive signal of a part of the inverter units constituting the plurality of inverter units from a drive signal of an inverter unit different from the part of the inverter units. Drive device. The controller is
A control signal output unit that outputs a common control signal among the plurality of inverter units;
A delay signal output unit that outputs a delay signal for delaying a drive signal of the part of the inverter unit from a drive signal of the other inverter unit;
A first drive signal output unit that outputs a drive signal of the another inverter unit according to the control signal;
The motor drive device according to claim 2, further comprising: a second drive signal output unit that outputs a drive signal of the partial inverter unit according to the control signal and the delay signal.   4. The motor drive device according to claim 3, wherein the second drive signal output unit outputs a drive signal of the partial inverter unit by delaying the control signal by the delay signal. 5. The second drive signal output unit includes:
A first pulse output unit that outputs a first pulse delayed according to the delay signal with respect to a rising edge of the control signal;
A second pulse output unit that outputs a second pulse delayed according to the delay signal with respect to a falling edge of the control signal;
5. The motor drive device according to claim 4, further comprising: a flip-flop unit that outputs a drive signal of the partial inverter unit in response to the first pulse and the second pulse.   6. The motor drive device according to claim 3, wherein a delay time of the drive signal of the part of the inverter units changes in accordance with a pulse width of the delay signal.   The motor driving apparatus according to claim 1, wherein the motor generates a torque that assists a driver's steering operation.   A control system provided with the said motor and the motor drive device as described in any one of Claim 1 to 7.

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