JP2013090009A - Demodulator and radio communications system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a demodulator while keeping demodulation adequate.SOLUTION: A demodulator 101 comprises switches 21a-21f and 22a-22f for executing and stopping supplying electric power to an amplifier 3, a mixer 4, a filter 5, an amplifier 6, a rectifier 7, and comparator 8. A synchronization unit 11 extracts a symbol period from reception data. A timing controller 12 sets only a part of the symbol period extracted at the time of demodulation of data in a packet as an active period, and turns on the switches 21a-21f and 22a-22f during the active period.

Description

  The present invention is a radio communication demodulator using an OOK (On / Off Keying) modulation method which is a kind of ASK (Amplitude Shift Keying) modulation, and in particular, can effectively reduce power consumption and perform proper demodulation. The present invention relates to a demodulation device and a wireless communication system including the demodulation device.

  A wireless network in which a large number of wireless sensor nodes having a wireless communication function are arranged and information is collected by configuring a network between these wireless sensor nodes is referred to as a wireless sensor network. Expected to contribute to a safe, secure and comfortable human life in environmental monitoring, automatic meter reading, structure monitoring, home security, etc. by arranging a large number of wireless sensor nodes distributed indoors and outdoors. Has been.

  Since the wireless sensor network is composed of an extremely large number of wireless sensor nodes, it is required to reduce the body cost and running cost of the wireless sensor network. In order to satisfy this requirement, it is necessary that the wireless sensor node itself is low-cost and that maintenance such as battery replacement is infrequent. In order to reduce the frequency of maintenance, it is essential to reduce the power consumption of the wireless sensor node itself.

  One of the digital modulation methods for such a wireless sensor network is an OOK modulation method. FIG. 14 is a diagram illustrating a data transmission method using the OOK modulation method.

  As shown in FIG. 14, the OOK modulation scheme is the most basic digital radio modulation scheme that transmits 1-bit data represented by “0” and “1” in the presence or absence of radio waves. The OOK modulation method has the disadvantage that the amount of data that can be transmitted per frequency bandwidth is the smallest among the digital modulation methods due to such characteristics, but has the advantage that it has the highest resistance to noise and fading. Modulation method. In addition, since the OOK modulation method performs communication only with or without radio waves, it does not require detection of absolute values of amplitude and phase, so that the transmission / reception system is simplified and is suitable for low power consumption. Have.

  Most of the power in the wireless sensor node is consumed to drive the wireless device. Thus, as a method for reducing power consumption during standby when actual communication is not performed, a sleep function and intermittent reception of a wireless device can be cited.

  For example, Patent Document 1 discloses a low-power wireless communication system that employs such a method. This low-power radio communication system includes a master station that functions as a control station and a slave station that functions as a non-control station. The master station collects the communication schedule information of the slave station stored in the slave station communication schedule storage table from all the slave stations at a predetermined time. Further, the master station creates a master station communication schedule table corresponding to all the communication schedules of the collected slave stations, and notifies the master station communication schedule information to the slave stations under its control. After that, both the master station and the slave station are required to operate only the minimum necessary circuits of the communication timer unit and the communication control unit and to be described in the communication schedule table until the communication scheduled time of each station comes. Communication is performed by operating a circuit necessary for communication only at a proper communication time. In this manner, power consumption can be reduced by putting the wireless device in the sleep state at times other than the scheduled communication time.

  The above low power wireless communication system reduces power consumption during the standby time, but does not reduce power consumption during the communication period at all. Therefore, the power control performed in such a low power wireless communication system is effective in the case where communication is periodically performed with a low frequency.

  However, if the communication frequency increases for some reason, it is important to reduce power consumption during the communication period. For example, wireless sensor networks are intended for environmental monitoring, automatic meter reading, structure monitoring, home security, etc., so regular and low-frequency communication may be performed during normal times, but irregularly after an emergency such as an accident. And frequent communication is required. Therefore, reducing power consumption during communication is also important for reducing power consumption.

  As a technique for reducing the power consumption during communication, a technique disclosed in Non-Patent Document 1 can be cited. Non-Patent Document 1 shows a configuration that reduces the power consumption of the amplifier because the amplifier has the largest power consumption in the analog front end on the receiver side. FIG. 15 is a circuit diagram showing an input amplifier used as a front-end amplifier described in Non-Patent Document 1.

  As shown in FIG. 15, switches 1004 and 1005 for performing power gating are inserted between power supply lines 1001 and 1002 to which power supply voltages VDD and VSS are applied, respectively, and an amplifier 1003. When power is supplied to the amplifier 1003 over the entire communication time, power consumption increases. However, considering the purpose of digital wireless communication, it is only necessary that the received signal can be finally demodulated into digital “0” and “1” signals.

  Therefore, in the above-described input amplifier, power supply to the amplifier 1003 outside the demodulation period is stopped by gating using the switches 1004 and 1005 to reduce power consumption. By adopting such a configuration, it is possible to reduce the power consumption of the receiver during communication.

JP 2007-5991 A (published January 11, 2007) Atit Tamtrakarn et al., “A 1-V 299μW Flashing UWB Transceiver Based on Double Thresholding Scheme”, IEEE, 2006 Symposium on VLSI Circuits Digest of Technical Papers

  FIG. 16 is a diagram illustrating the relationship between the active period Tact and the symbol period Tsym (symbol length) in the internal circuit of the demodulator.

  When power gating is performed on the internal circuit of the demodulator as described above, if the active period Tact deviates from the symbol period, the active period Tact extends over two symbol periods Tsym as shown in FIG. In this state, the modulated data cannot be demodulated correctly.

  In addition, it is necessary to determine the signal synchronism in the part that specifies the symbol period and the part that generates the active period of power gating. For this reason, these parts are most preferably configured by a circuit technique such as PLL (Phase Locked Loop) or CDR (Clock Data Recovery). However, these circuit methods are not suitable for reducing the power consumption of the demodulating device because of the large power consumption.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce power consumption of the demodulation device while appropriately maintaining demodulation.

  In order to solve the above problems, a demodulator according to the present invention includes a demodulation processing unit that demodulates a radio signal obtained by performing OOK (On / Off Keying) modulation on a packet composed of a synchronization word and data. Clock generating means for generating a clock; symbol period extracting means for extracting a symbol period of the radio signal demodulated by the demodulation processing section with reference to the clock; and power supply and power supply to the demodulation processing section A power supply / supply stop unit for stopping and an active period for enabling the power supply by the power supply / supply stop unit are set, and an operation of supplying power to the power supply / supply stop unit based on the active period Power supply control means for causing the power supply / supply stop means to stop the power supply operation during a period other than the active period. And the power supply control means sets the whole period of the extracted symbol period as the active period in the demodulation of the synchronization word, and only a part of the extracted symbol period in the demodulation of the data. The active period is set.

  In the above configuration, the symbol period extraction unit extracts the symbol period from the demodulated radio signal with reference to the clock generated by the clock generation unit. When demodulating the synchronization word added to the head of the packet, the entire period of the extracted symbol period is set as the active period by the power supply control means. As a result, the power supply / supply stop unit operates to supply power to the demodulation processing unit, so that demodulation processing by the demodulation processing unit is performed. On the other hand, when demodulating the packet data, only a part of the extracted symbol period is set as the active period by the power supply control means. Thereby, the power supply to the demodulation processing unit becomes effective, and the demodulation processing by the demodulation processing unit is performed as in the above case.

  In this way, by setting the active period, the active period does not extend over two symbol periods. Therefore, the received radio signal can be correctly demodulated. In addition, power supply to the demodulation processing unit is stopped outside the active period. Therefore, power consumption during the communication period can be reduced.

  In the demodulator, the power supply control means preferably sets the active period to the center of the extracted symbol period with reference to the clock.

  In the above configuration, the power supply control means sets the active period at the center of the symbol period with reference to the clock. As a result, if the operation clock frequency of the receiving device has a frequency deviation with respect to the operation clock frequency of the transmitting device, the active period is not affected even if the processing is performed free-running without using a synchronization method such as PLL. Never span two symbols. Therefore, the radio signal can be demodulated more correctly.

  In the demodulator, the power supply control means includes a counter that counts the clock, and, in the demodulation of the data, at a timing when the count value of the counter reaches a count value corresponding to a start time and an end time of the active period. It is preferable to have power supply operation means for causing the power supply / supply stop means to perform power supply during a specified period.

  In the above configuration, the power supply control means has a counter, so that the power supply operation means can supply power to the power supply / supply stop means without using a high power consumption synchronization method such as PLL or CDR. It is possible to determine the period for which Therefore, power consumption can be reduced.

  In the demodulating device, the symbol period extracting means detects a change point of the output signal of the demodulation processing unit as a boundary of the symbol period based on the clock and a counter that counts the clock, and detects the boundary. It is preferable to have edge detection means for storing the count value of the counter at the timing as the boundary of the symbol period.

  In the above configuration, the symbol period extraction unit includes a counter, so that the symbol period can be extracted by the edge detection unit without using a power-consuming synchronization method such as PLL or CDR. Therefore, power consumption can be reduced.

  In the demodulating device, the symbol period extracting means has a shift register composed of a two-stage register for shifting and storing with the clock, and the edge detecting means sends the output signal of the demodulation processing section to the register at the first stage. Preferably, the boundary between the symbol periods is detected based on the difference between the two systems of data input and stored in each register.

  In the above configuration, since the change point of the symbol period is detected based on the difference between the two data stored in the two-stage register of the shift register, the boundary of the symbol period can be detected without using a complicated circuit configuration. It becomes possible to do.

  The symbol period extraction unit includes a shift register including at least six stages of registers that are shifted and stored by the clock, and the edge detection unit inputs an output signal of the demodulation processing unit to the register of the first stage, and Based on the difference between the data stored in at least three registers at the front stage of the shift register and the data stored in at least three registers at the rear stage of the shift register, the boundary of the symbol period is determined. It is preferable to detect.

  In the above configuration, two systems of data stored in each register in the front stage and each register in the rear stage of at least six stages of the shift register, as in the demodulator having the shift register composed of the previous two stages of registers. Since the boundary of the symbol period is detected based on the difference, the change point can be detected without using a complicated circuit configuration. In addition, since the output signals of at least three systems of each register in the front stage part and the output signals of at least three systems of the register in the rear stage part are used for boundary detection, the change point is determined based on the majority vote or the average value. I can do it. As a result, the influence of instantaneous disturbances such as fading and noise can be suppressed and the change point can be accurately determined.

  A wireless communication system according to the present invention includes a plurality of communication terminals including any of the above-described demodulation devices, and performs wireless communication between the communication terminals.

  As a result, the receiving device can correctly demodulate the received radio signal and reduce power consumption during the communication period.

  Another wireless communication system of the present invention includes a plurality of communication terminals including the demodulation device in which the power supply control means has the count or the demodulation device in which the power supply control means has the counter, and wirelessly communicates between the communication terminals. A wireless communication system that performs communication, based on an upper limit value of a frequency tolerance of the clock generation unit on the transmission side and the clock generation unit on the reception side, in the communication terminal on the transmission side and the communication terminal on the reception side The packet length of the packet is determined in advance so that the accumulated error in which the difference in clock period per cycle is accumulated up to the final symbol of the packet is within a predetermined range.

  With the above configuration, similarly to the above-described wireless communication system, it is possible to correctly demodulate the received wireless signal and reduce the power consumption during the communication period in the receiving device.

  Further, since the power supply control means and the power supply control means have a counter, as described above, there is no need to use a synchronization method such as PLL or CDR. However, the active period shifts with respect to the symbol period determined by the transmitting device in the demodulating apparatus of the receiving device, depending on the frequency tolerance (PPM) of the clock that is the reference for the operation of the transmitting device and the receiving device.

  The accumulated error in which the difference in clock period per cycle in the communication terminal on the transmission side and the communication terminal on the reception side is accumulated up to the final symbol of the packet is the product of the above difference and the number of symbols, that is, the packet length. Further, the accumulated error varies depending on the frequency tolerance of the receiving device (see FIG. 10). In addition, the shift amount during the active period is proportional to this cumulative error.

  Therefore, when designing and setting communication between communication terminals, the packet length is determined in advance by an upper limit value of a frequency tolerance (PPM) of a clock used in the receiving device in a predetermined method. Specifically, when the frequency allowable deviation (PPM) is large, the accumulated error also increases. Therefore, the packet length is shortened. When the frequency allowable deviation (PPM) is small, the accumulated error also decreases. Make it smaller. For this reason, since the maximum value of the frequency tolerance (PPM) is known from the performance of the clock generation means, the packet length is determined in advance according to the upper limit value obtained by adding a margin to this maximum value. In this way, since the packet length is determined according to the upper limit value of the frequency tolerance (PPM), the accumulated error can be suppressed within a predetermined range.

  As a result, even if the active period is shifted by the clock frequency tolerance (PPM), the shift amount can be suppressed to be small, so that the active period does not extend over two symbols. Therefore, the received radio signal can be correctly demodulated.

  The demodulator according to the present invention, which is configured as described above, has an effect that the power consumption of the demodulator can be reduced while appropriately maintaining the demodulation.

It is a block diagram which shows the structure of the radio | wireless communications system which concerns on embodiment of this invention. It is a figure which shows the structure of the packet communicated between the terminals in the said radio | wireless communications system. It is a block diagram which shows the structure of the principal part of the receiver contained in the said terminal. It is a block diagram which shows the structure of the synchronizer and timing controller of the demodulation apparatus in the said receiver. It is a figure which shows the state of the communication between terminals using the wake-up function in the said radio | wireless communications system. It is a figure which shows the setting state of each active period at the time of reception of a synchronous word and data. It is a timing chart for demonstrating operation | movement of the said synchronizer. It is a figure which shows the timing of the clock of the transmission side terminal in the said radio | wireless communications system, and the clock of the reception side terminal. It is a figure which shows the position of the active period of the power gating by which the symbol period is each determined by the clock of the said transmission side terminal, and the RF signal determined by the clock of the said reception side terminal. It is a graph which shows the relationship between the packet length of the packet comprised by N symbol, and the accumulation | storage error of the clock of the transmission side terminal and receiving side terminal in the last symbol of the said packet. It is a figure which shows the determination method of the center time of the said active period. It is a figure which shows the production | generation of the said active period based on the count value of the counter in the said synchronous part. (A) And (b) is a block diagram which shows the structure of the shift register contained in the said synchronous part. It is a figure which shows the data transmission method by an OOK modulation system. It is a circuit diagram which shows the input amplifier used as a conventional front end amplifier. It is a figure which shows the relationship between the active period and symbol period (symbol length) in the internal circuit of the conventional demodulator.

  Embodiments according to the present invention will be described below with reference to FIGS.

[Wireless communication system]
FIG. 1 is a block diagram illustrating a configuration of a wireless communication system 10 according to the present embodiment. FIG. 2 is a diagram illustrating a configuration of a packet 200 communicated between the terminals 1 and 2 in the wireless communication system 10.

  As shown in FIG. 1, the wireless communication system 10 includes terminals 1 and 2 as a plurality of communication terminals. The terminals 1 and 2 are communication devices each having a wireless communication function and can communicate with each other. Data is transmitted and received between the terminals 1 and 2 by the packet 200 shown in FIG.

  As shown in FIG. 2, the packet 200 is composed of a synchronization word 201 and data 202. In the synchronization word 201, “0” and “1” are alternately arranged. In the period “1”, a symbol period Tsym is defined as shown in an enlarged manner in FIG. In the data 202, “0” and “1” are arranged at intervals according to the data value.

  Since the wireless communication system 10 constitutes a wireless sensor network, the wireless communication system 10 originally includes a very large number of communication terminals, but only the terminals 1 and 2 are referred to here for convenience of explanation.

[Receiving machine]
[Configuration of receiver]
FIG. 3 is a block diagram illustrating a configuration of a main part of the receiver 100 included in the terminals 1 and 2 described above. FIG. 4 is a block diagram illustrating the configuration of the synchronization unit 11 and the timing controller 12 of the demodulation device 101 in the receiver 100.

  As shown in FIG. 3, the receiver 100 includes a demodulation device 101 and an antenna 102. The receiver 100 constitutes a reception function unit of the terminals 1 and 2.

<< Configuration of Demodulator >>
The demodulator 101 demodulates a radio signal obtained by modulating the above-described packet 200 with OOK (On / Off Keying). The demodulator 101 includes an amplifier 3, a mixer 4, a filter 5, an amplifier 6, a rectifier 7, a comparator 8, a synchronization unit 11, a timing controller 12, a clock generator 13, and switches 21a to 21f and 22a to 22f. .

<Demodulation processing section>
The amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7, and the comparator 8 constitute a demodulation processing unit 103 that performs demodulation processing.

  In the demodulation processing unit 103, received data is output by sequentially demodulating the RF signal received by the antenna 102 by the amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7 and the comparator 8. .

  When demodulation processing is performed, switches 21a to 21f and 22a to 22f, which will be described later, are closed, whereby each unit of the demodulation processing unit 103 is connected to the power supply line and the ground line. As a result, each unit of the demodulation processing unit 103 operates with power supplied during demodulation. On the other hand, when demodulation processing is not performed, the switches 21a to 21f and 22a to 22f are opened, so that each unit of the demodulation processing unit 103 is disconnected from the power supply line and the ground line, and thus operates without being supplied with power. Stop.

<switch>
The switches 21a to 21f (power supply / supply stop means) are open / close switches for connecting or disconnecting the power supply line and the amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7, and the comparator 8, respectively. The switches 22a to 22f (power supply / supply stop means) are open / close switches for connecting or disconnecting the ground line and the amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7 and the comparator 8, respectively.

  The switches 21a to 21f and 22a to 22f are controlled to be opened and closed by the timing controller 12. As described above, the switches 21a to 21f and 22a to 22f are controlled to be closed when demodulated and opened when not demodulated.

  In the following description, when common to the switches 21a to 21f and 22a to 22f, the switches 21 and 22 are simply referred to.

<Synchronization part>
The synchronization unit 11 (symbol period extracting means) extracts the symbol period of the output signal by detecting the changing point of the output signal (received data) from the comparator 8. Since the output signal from the comparator 8 is the result of demodulating the OOK-modulated RF signal, it becomes a signal represented by “0” or “1”, and its change point becomes a rising edge or a falling edge. Each edge timing is detected based on the clock generated by the clock generator 13. As shown in FIG. 4, the synchronization unit 11 includes a shift register 111, a counter 112, and an edge detector 113.

  The shift register 111 shifts the output signal of the comparator 8 by a predetermined amount, and outputs two systems of signals with different shift amounts. Details of the shift register 111 will be described later.

  The shift register 111 shifts and stores the output signal of the comparator 8 with the clock generated by the clock generator 13. Details of the shift register 111 will be described later.

  The counter 112 counts the clock generated by the clock generator 13.

  The edge detector 113 (edge detection means) detects rising and falling edges (change points) based on the output signal of the comparator 8 stored in the shift register 111. Specifically, the edge detector 113 detects an edge based on the logic level states of the two systems of signals stored in the preceding-stage register group and the latter-half register group constituting the shift register 111. Further, the edge detector 113 stores the count value of the counter 112 at the timing of detecting an edge. The detected / stored edge becomes the boundary of the symbol period of the received signal detected by the synchronization unit 11.

<Timing controller>
The timing controller 12 (power supply control means) turns on / off the power gating switches 21 and 22 based on the symbol period extracted by the edge detector 113 of the synchronization unit 11 and the clock from the clock generator 13. Control. As shown in FIG. 4, the timing controller 12 includes a counter 121 and a gating signal generator 122.

  The counter 121 counts the clock from the clock generator 13. Since this counter 121 does not operate simultaneously with the counter 112, it may be shared with the counter 112. The counter 121 is provided for generating the timing of a symbol period that is a reference for demodulation. Therefore, the counter value of the counter 121 is reset to 0 at the rising and falling edge timings detected by the synchronization unit 11.

  In the demodulation of the synchronization word 201, the gating signal generator 122 sets the entire symbol period as an active period in which the switches 21 and 22 are turned ON (power supply is enabled). In addition, the gating signal generator 122 sets only a partial period of the symbol as an active period in the demodulation of the data 202. The gating signal generator 122 sets the active period based on the edge detected by the edge detector 113.

  The gating signal generator 122 (power supply operation means) generates a gating signal for turning the switches 21 and 22 ON / OFF. In particular, the gating signal generator 122 generates a gating signal for turning on the switches 21 and 22 during the active period based on the count value of the counter 121.

<Configuration of clock generator>
The clock generator 13 (clock generation means) is a circuit that generates a clock to be supplied to the synchronization unit 11, the timing controller 12, and the mixer 4. The clock generator 13 includes an oscillation circuit such as a crystal oscillation circuit.

[Receiver operation]
<Normal reception (demodulation) operation>
First, the basic operation of the demodulation device 101 at the time of demodulation in the receiver 100 will be described. In this state, the switches 21 and 22 are closed, and power is supplied to the amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7 and the comparator 8.

  When the RF signal is received by the antenna 102, it is amplified by the amplifier 3. The amplified RF signal is converted into an IF signal by the mixer 4, and then only a desired wave is extracted by the filter 5. The extracted wave is amplified by the amplifier 6 and further rectified by the rectifier 7. Further, the comparator 8 determines whether or not the output of the rectifier 7 is larger than the reference voltage Vref (threshold value) of the reference voltage source 23 to determine the presence or absence of radio waves. As a result, the RF signal is demodulated into digital data composed of “0” and “1”, whereby reception data is output.

<< Communication using the sleep function >>
Next, a reception operation when intermittent reception is performed in the sleep state will be described.

  Here, it is assumed that the terminal 2 operates to perform intermittent reception in the sleep state, and is woken up by the terminal 1 by the wakeup function. Thereby, the terminal 1 becomes a transmission side and the terminal 2 becomes a reception side.

  FIG. 5 is a diagram illustrating a state of communication between the terminals 1 and 2 using the wake-up function. FIG. 6 is a diagram illustrating a setting state of each active period at the time of reception of a synchronization word and data. FIG. 7 is a timing chart for explaining the operation of the synchronization unit 11.

  FIG. 7 shows electromagnetic waves, comparator outputs, shift register outputs, count values, and clocks. An electromagnetic wave is an RF signal received as an electromagnetic wave. The comparator output is the output of the comparator 8, and the shift register output is the output of the shift register 111. The count value is the number that the counter 112 counts the clock. This clock is a clock generated by the clock generator 13.

  Here, as shown in FIG. 5, a case where the terminal 1 requests data transmission to the terminal 2 in the sleep state will be described as an example.

<Operation from sleep state to communication start>
First, in the terminal 2 in the sleep state, the timing controller 12 of the receiver 100 turns on the switches 21 and 22 in the reception periods 31a, 31b, 31c,... (Active period) as shown in FIG. Turn off in periods other than. As a result, intermittent reception is possible in which reception is performed only in the reception periods 31a, 31b, 31c,. On the other hand, the terminal 1 transmits a wake-up signal 30 to the terminal 2. When the terminal 2 in the sleep state receives the wakeup signal 30 in the reception period 31c, the terminal 2 wakes up and transmits the ACK signal 32 to the terminal 1. As a result, the terminal 1 can wake up the terminal 2 and transmit the packet 200 to the terminal 2.

<Sync word reception operation>
In the terminal 2, when the timing controller 12 of the demodulating apparatus 101 gives an instruction to transmit the ACK signal 32 to the terminal 1 as described above to the transmission unit of the terminal 2, the ACK signal 32 is transmitted from the transmission unit and synchronized. The period for receiving word 201 begins.

  When the terminal 2 transmits the ACK signal 32, it functions as a receiving terminal, and when the terminal 1 receives the ACK signal 32, it functions as a transmitting terminal. Therefore, in the following description, the terminal 1 is referred to as a transmitting terminal and the terminal 2 is referred to as a receiving terminal.

  At the same time when the period for receiving the synchronization word 201 starts as described above, the timing controller 12 sets an active period 33b in which the switches 21 and 22 are always ON as shown in FIG. As a result, in the demodulator 101, since the switches 21 and 22 are turned on, the amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7 and the comparator 8 are operated, and the RF signal (electromagnetic wave) output from the transmission side terminal is operated. Always receive. When all the electromagnetic waves of the synchronization word 201 are received, the synchronization unit 11 extracts the symbol period Tsym from the synchronization word 201.

  The timing controller 12 activates the counter 112 at the same time as the switches 21 and 22 are turned ON. In the synchronization unit 11, when the counter 112 starts the counting operation, the clock output from the clock generator 13 is counted. The output signal of the comparator 8 is shifted in synchronization with the clock by the shift register 111.

  As shown in FIG. 7, when the electromagnetic wave received by the receiving terminal changes from “0” to “1”, the output signal of the comparator 8 also changes from “0” to “1”. Then, in the synchronization unit 11, the edge detector 113 detects an edge from the output of the shift register 111 and stores the count value Ns of the counter 112 at the timing when the edge is detected. Even when the electromagnetic wave changes from “1” to “0”, the edge detector 113 detects an edge from the output of the shift register 111 and stores the count value Ne of the counter 112 at the timing when the edge is detected.

  Accordingly, the synchronization unit 11 acquires the count values Ns and Ne as the timing of the edge (boundary) of the symbol period Tsym with the clock output from the clock generator 13 as a time reference. Further, the synchronization unit 11 calculates (Ns + Ne) / 2 by using the count values Ns and Ne, thereby detecting this value as the timing at the center of the symbol period.

  In the above example, the edge timing of the symbol “1” has been described. However, in the case of the symbol “0”, “0” and “1” are interchanged unlike the above case. As a result, the edge detector 113 stores the count value Ns when the symbol “1” changes to the symbol “0”, and stores the count value Ne when the symbol “0” changes to the symbol “1”.

  Since the count value Ne of the current symbol corresponds to the count value Ns of the next symbol, the edge (boundary) between the symbol “0” and the symbol “1” is always repeatedly detected while the synchronization word 201 is being received. Will be.

  The above process is repeated until a predetermined pattern of the synchronization word 201 is completed.

<Data reception operation>
As described above, when the reception of the synchronization word 201 is completed, the receiving side terminal shifts to a data 202 reception operation.

  The synchronization word 201 is predetermined as a communication protocol. In the transmitting side terminal and the receiving side terminal, both the transmitter and the receiver 100 store the synchronization word pattern. The receiver 100 of the receiving terminal compares the stored synchronization word pattern with the received signal pattern and determines that they do not match, thereby recognizing that the synchronization word 201 is changed to the data 202. . Alternatively, as shown in FIG. 6, in the case of the synchronization word 201 in which “0” and “1” are alternately arranged, the receiver 100 determines in advance a count value obtained by counting the number of “0” and “1”. When the set value is reached, it may be recognized that the synchronization word 201 is changed to the data 202.

  As shown in FIG. 7, the timing of the boundary where “0” and “1” change in the electromagnetic wave is determined by the timing of the clock generated by the clock generator 13 of the transmitting terminal. On the other hand, the clock shown in FIG. 7 is a clock generated by the clock generator 13 of the receiving terminal. If the oscillation frequency of the oscillation circuit constituting both clock generators 13 is slightly different between the transmission side terminal and the reception side terminal, the timings of the count values Ns and Ne may be different for each symbol.

  In such a case, the synchronization unit 11 calculates the average of the symbol period length (Ne−Ns) detected for each symbol. Thereby, it becomes possible to suppress the influence of a subtle difference in oscillation frequency. Further, the synchronization unit 11 stores the symbol period length (Ne−Ns) calculated in this manner and uses it for setting an active period in data reception.

  When demodulating the data 202, the timing controller 12 of the demodulator 101 sets an active period 33a for turning on the switches 21 and 22, as shown in FIG. As a result, the demodulator 101 demodulates the RF signal only during the active period 33a, so that the power consumed by the amplifier 3, the mixer 4, the filter 5, the amplifier 6, the rectifier 7 and the comparator 8 when receiving the data 202 is reduced. It is possible to reduce. The effect of reducing power consumption is determined by the ratio of the symbol period length, which is the length of the symbol period Tsym, to the active period 33a.

  The timing controller 12 activates the counter 121 at the same time as changing from the synchronization word 201 to the data 202. When the counter 121 starts the counting operation, the counter 121 counts the clock output from the clock generator 13. The cycle of the counter 121 is set according to the symbol period length (Ne−Ns) calculated and stored by the synchronization unit 11. Specifically, the counter 121 is reset to 0 when the counter value reaches (Ne−Ns−1). When the counter 121 is operated in this way, the time when the count value of the counter 121 reaches (Ns + Ne) / 2 is the center of the symbol period.

  The gating signal generator 122 generates and outputs a gating signal that turns off the switches 21 and 22 simultaneously with the activation of the counter 121. Then, the gating signal generator 122 generates and outputs a gating signal for turning on the switches 21 and 22 only during the active period 33a shown in FIG. 6 with reference to the timing generated by the counter 121. Specifically, the gating signal generator 122 sets count values corresponding to the start time and end time of the active period 33a, and at the timing when the count value of the counter 121 reaches the set count value. The gating signal is generated in the defined active period 33a.

[Setting the active period]
Next, the setting of the active period 33a will be described in detail.

<Effect of clock frequency error / deviation>
FIG. 8 is a diagram illustrating timings of the transmission side clock CLKa of the transmission side terminal and the reception side clocks CLKb to CLKd of the reception side terminal. FIG. 9 shows the positions of the RF signal (transmission data) whose symbol period is determined by the clock CLKa of the transmitting terminal and the active period 33a determined by the clocks CLKb to CLKd of the receiving terminal (normally, left shift, right FIG.

  The timing controller 12 sets the active period 33a at the center of the communication symbol period. The setting accuracy of the active period 33a is determined by the frequency error / frequency deviation (PPM) as a frequency tolerance generated in the clock of the clock generator 13 of the transmitting terminal and the receiving terminal and the data length.

  The symbol period of the transmission data is determined by the transmission side clock CLKa of the transmission side terminal. When the reception side clock frequency matches the transmission side clock frequency, even if the timing of the reception side clock CLKb is different from the timing of the transmission side clock CLKa as shown in FIG. Therefore, the distance between the two is kept constant. In this case, as shown in FIG. 9, the active period 33a of the timing controller 12 of the demodulator 101 does not shift with time with respect to the symbol period Tsym of the transmission data.

  Next, when the reception side clock frequency is higher than the transmission side clock frequency, the clock cycle of the reception side terminal is shorter than the clock cycle of the transmission side terminal. Therefore, as shown in FIG. 8, when the transmission side clock CLKa is used as a reference, the reception side clock CLKc is shifted to the left. The RF signal subjected to OOK modulation in which the symbol period Tsym is determined by the transmission side clock CLKa is demodulated by power gating in which the active period 33a is determined by the reception side clock CLKc shifted to the left side as described above. In this case, the active period 33a is also shifted to the left as shown in FIG. 9 with reference to the transmission data of the RF signal shown in FIG.

  Conversely, when the receiving clock frequency is lower than the transmitting clock frequency, the clock cycle of the receiving terminal is longer than the clock cycle of the transmitting terminal. Therefore, as shown in FIG. 8, when the transmission side clock CLKa is used as a reference, the reception side clock CLKd is shifted to the right side. In response to this, the active period 33a is also shifted to the right as shown in FIG. 9 with respect to the RF signal transmission data shown in FIG.

  In the case of 0 PPM in which the clock frequency errors and deviations of the transmission side terminal and the reception side terminal completely match, the relationship between the symbol period Tsym of the transmission data and the active period 33a is always constant. Therefore, the timing controller 12 can arbitrarily set the active period 33a within a range not extending over the two symbol periods Tsym.

  When the frequency errors and deviations of the clocks of the transmitting terminal and the receiving terminal do not completely match, the timing controller 12 sets the active period 33a to the center of the communication symbol period Tsym. The accuracy of the setting is determined by the product of the shift amount of the active period 33a per symbol determined by the frequency error / deviation of the clock and the length of the packet 200.

  Here, the frequency and period of the clock of the transmitting terminal are respectively Fs and Ts, the frequency and period of the clock of the receiving terminal are respectively Fs ′ and Ts ′, and the frequency Fs ′ is a frequency error of α with respect to the frequency Fs. Suppose you have a deviation. Then, the period of the receiving clock is expressed as shown in Equation (1).

  The difference δTs in the clock period per cycle between the transmitting side terminal and the receiving side terminal is expressed by the following equation (2) because α << 1 if the frequency error / deviation α is in the order of PPM. .

  When the packet length of the packet 200 is composed of N symbols, the clock accumulation error of the transmitting terminal and the receiving terminal in the final symbol of the packet 200 is N × δTs. FIG. 10 is a graph showing the relationship between the packet length and the accumulated error.

  Here, as an example, consider a case where the frequency error / deviation is 100 ppm. If the packet length is 2000 symbols, the accumulation error is 0.2 Tsym, and if the packet length is 5000 symbols, the accumulated error is 0.5 Tsym. In this state, when the receiver 100 receives a transmission signal having a packet length of 2000 symbols, the active period 33a generated by the timing controller 12 of the demodulator 101 is also shifted by 0.2 Tsym as a whole.

  In order to reduce the accumulated error, it is preferable to shorten the packet length as much as possible within a range in which transmission is not hindered with respect to the maximum value of the clock frequency error / deviation at the receiving terminal. Therefore, when designing and setting communication between terminals, the accumulated error determined from the upper limit value of the frequency error / deviation of the clock generated by the clock generator 13 employed in the transmitting terminal and the receiving terminal is reduced. The packet length may be determined as follows.

  Specifically, as shown in FIG. 10, since the accumulated error also increases when the frequency error / deviation is large, the packet length is shortened, and when the frequency error / deviation is small, the accumulated error also decreases. Reduce the packet length. For this reason, if the maximum value of the frequency error / deviation is known, a value equal to or greater than this maximum value is set as the upper limit value, and the packet length is set as desired so that the accumulated error falls within a predetermined range according to the upper limit value. decide.

  For example, when the allowable deviation is ± 50 ppm, the worst case occurs when one allowable deviation of the transmitting / receiving terminal is +50 ppm and the other allowable deviation is −50 ppm, and the maximum frequency error / deviation between the transmitting and receiving terminals is 100 ppm. Therefore, if the margin is m, the upper limit value is 100 + m (ppm). In this case, if it is necessary to suppress the accumulation error to 0.2 Tsym or less, from the proportional relationship between the packet length and the accumulated error as shown in FIG. 10 when the frequency error / deviation is 100 + m (ppm), 0.2 Tsym The packet length is determined within the following range. FIG. 10 does not show the above relationship when the frequency error / deviation is 100 + m (ppm), but it is assumed that the proportional relationship is known for each value of the frequency error / deviation.

  Here, the upper limit value is set to a value equal to or greater than the maximum value because the frequency error / deviation of the clock is determined by the crystal used as a vibrator in the oscillation circuit of the clock generator 13, and therefore the frequency error This is to provide a margin for the maximum deviation.

  In the above example, the packet length is determined according to the upper limit value set based on the maximum value of the frequency error / deviation, but the method for determining the packet length is not limited to this. For example, a desired packet length may be determined first, an upper limit value may be determined accordingly, and a crystal that satisfies the upper limit value may be employed.

  Thus, since the packet length is determined according to the upper limit value of the frequency error / deviation, even if a difference in frequency error / deviation occurs between the clocks of the transmitting terminal and the receiving terminal, transmission based on the difference is performed. The clock accumulation error of the side terminal and the receiving side terminal can be suppressed within a predetermined range. Thereby, the shift amount of the active period 33a due to the frequency error / deviation can be reduced. Therefore, since the active period 33a is accurately set at the center of the symbol period Tsym, the active period 33a does not extend over two symbol periods.

  Note that Tsym represents a symbol length (symbol period).

<Determining the central time of the active period>
FIG. 11 is a diagram illustrating a method of determining the center time t0 of the active period 33a.

  As shown in FIG. 11, the gating signal generator 122 sets the center time t0 of the active period 33a within the symbol length. Therefore, the center time t0 satisfies 0 ≦ t0 ≦ Tsym. When the packet length is N symbols, the accumulated error due to the clock frequency error / deviation is ± NδTs as shown in FIG. Therefore, when the demodulating apparatus 101 performs demodulation processing in a state where there is a frequency error / deviation in the clock at the transmitting terminal and the receiving terminal, the center time t0 of the active period 33a generated by the gating signal generator 122 is Satisfy 3). As a result, even if the timing controller 12 is operated in a free-run state in which no clock frequency error / deviation is corrected, the active period 33a always remains within the same symbol period in the packet period, and does not extend over two symbol periods. Absent.

  Therefore, the demodulator 101 can receive data without any problem while performing power gating in the active period 33a. The range of the center time t0 of the active period 33a is determined by the equation (3) when the number of symbols N of the data 200 (packet length), the clock frequency error / deviation α, and the active period length Ta.

<Setting the start time and end time of the active period>
Here, the gating signal generator 122 sets the start time of the active period 33a as Nas and sets the end time of the active period 33a as Nae as described above with reference to the count value of the counter 121. Further, the clock cycle Ts ′ of the receiving terminal, the clock cycle difference (clock cycle difference) δTs per cycle between the transmitting terminal and the receiving terminal, and the number N of symbols are used. Thereby, the relationship of Formula (4) and Formula (5) is obtained.

  If Expression (4) and Expression (5) are satisfied, the active period 33a does not extend over two symbols even if there is a frequency error / deviation α in the clocks of the transmitting terminal and the receiving terminal. The clock cycle difference δTs is set to twice the worst value of the frequency error / deviation α of the oscillation circuit constituting the clock generator 13. Here, the reason why the frequency is doubled is that the frequency error / deviation α is generally defined to be about ± 50 ppm. Therefore, the frequency error / deviation α is +50 ppm at the transmitting terminal and −50 ppm at the receiving terminal. In some cases, the frequency error / deviation α at the transmission / reception terminal is 100 ppm. Considering the case where the sign is reversed, it is “twice the worst value of the frequency deviation”. For example, in the case of a crystal oscillation circuit, the allowable deviation of the oscillation frequency is determined by the allowable deviation (PPM) of the crystal.

  Since the power consumption is reduced as the active period (Nae-Nas) is shorter, not only the expressions (4) and (5) are easily satisfied, but also the frequency of the clock generated between the transmitting terminal and the receiving terminal. It becomes difficult to be affected by the error / deviation α. However, when each unit of the demodulator 101 has the shortest processing time necessary for performing a desired process, it is necessary to set the length of the active period 33a to a value longer than the shortest processing time. For example, in the filter 5, the time (delay time) from when an input signal is input to when a signal with a significant output is output differs depending on the frequency characteristics and configuration. Therefore, for the filter 5, the delay time of the filter 5 is the shortest processing time.

  Thus, in setting the start time Nas and end time Nae of the active period 33a, the worst value of frequency deviation, the shortest processing time, power consumption, and the like are in a trade-off relationship. Therefore, these values are selected as values optimized for the target communication by simulation or evaluation by a prototype.

  The gating signal generator 122 generates and outputs a power gating signal in which the switches 21 and 22 are turned on only during the active period 33a (Nas to Nae) with reference to the counter value of the counter 121. In addition, the gating signal generator 122 generates and outputs a power gating signal in which the switches 21 and 22 are OFF during the period other than the active period 33a. As a result, during reception of the data 202, the active period 33a can be set as shown in FIG.

<Adjustment of active period>
FIG. 12 is a diagram illustrating generation of the active period 33 a based on the count value of the counter 112.

  The synchronization unit 11 measures both ends of the symbol period Tsym with the counter 112 as shown in FIG. In this case, as shown in FIG. 12, the symbol period cannot be accurately measured, and the measurement error is about the clock cycle Tclk. However, as described above, if the active period 33a satisfies Expression (3), the demodulator 101 can receive data without any problem while performing power gating.

  Therefore, in consideration of the fact that the control unit of time is determined by the count value of the counter 112, the synchronization unit 11 sets the packet length N, the clock frequency error / deviation α, so that the active period 33a satisfies Equation (3). The active period length Ta is adjusted. Then, the synchronization unit 11 can extract the symbol period with low power consumption and the accuracy required for the present invention when the demodulation device 101 demodulates the synchronization word 201 without using a circuit such as PLL or CDR. .

  When the demodulator 101 demodulates the data 202, the timing controller 12 generates a center time t0 of the active period 33a with a counter as shown in FIG. In this case, the active period 33a is generated at an interval of the clock cycle Tclk. Also in this case, if the timing generated by the counter and the active period 33a satisfy Expression (3), the demodulator 101 can demodulate data without any problem while performing power gating.

[Details of synchronization section]
Further, the synchronization unit 11 will be described in detail.

  FIGS. 13A and 13B are block diagrams showing the configuration of the shift registers 111a and 111b.

<< First shift register >>
A shift register 111a illustrated in FIG. 13A is provided in the synchronization unit 11 as a shift register. The shift register 111a includes two stages of registers 114a and 114b.

<Configuration of shift register>
The register 114 a operates with the clock from the clock generator 13. Here, the clock generator 13 generates a clock having a cycle shorter than the symbol length.

  The first stage register 114a captures the output signal of the comparator 8 at the rising or falling edge of the clock, stores the captured data until the timing of capturing at the next edge, and maintains the output of the same value. The subsequent stage register 114b captures and stores the output signal 115a of the register 114a in the same manner as the register 114a, and outputs it as the output signal 115b. The output signals 115a and 115b are given to the edge detector 113.

<Operation of synchronization unit>
When receiving the synchronization word 201, the timing controller 12 of the demodulating apparatus 101 sets the active period 33a in which the switches 21 and 22 are always turned on as shown in FIG. As a result, the demodulation apparatus 101 always receives the RF signal output from the transmission side terminal, and outputs it as output data (output signal) from the comparator 8.

  The register 114a outputs an output signal 115a obtained by delaying the input output signal of the comparator 8 by one cycle of the clock. The register 114b outputs an output signal 115b obtained by delaying the output signal 115a of the register 114a by one clock cycle.

  The edge detector 113 utilizes the fact that the output signals 115a and 115b are data obtained by shifting the output signal of the same comparator 8 in units of one cycle of the clock, and the output signal 115a during the shifted period. , 115b, the edge timing of the output signal of the comparator 8 is detected based on the difference in logic level. Specifically, the edge detector 113 detects a rising edge when the output signal 115a is High and the output signal 115b is Lo. Conversely, the edge detector 113 detects the falling edge when the output signal 115a is Lo and the output signal 115b is High.

  The edge detector 113 detects a rising edge when the count value of the counter 112 reaches Ns, detects a falling edge when the count value of the counter 112 reaches Ne, and stores these edges. deep. As a result, the synchronization unit 11 detects the timing of the rising edge and the falling edge that are boundaries of each symbol in the synchronization word 201 of the received signal, and outputs the detected timing to the timing controller 12.

<< Second shift register >>
In order to reduce the influence of disturbance such as noise and fading, for example, a shift register 111b having a six-stage configuration shown in FIG. 13B may be used instead of the shift register 111a having the two-stage configuration.

  The shift register 111b has a configuration in which registers 114c to 114f are further added to the registers 114a and 114b. The registers 114a to 114f are cascade-connected and all operate with a clock. The output signals of the registers 114a to 114c are output as output signals 115a, and the output signals of the registers 114d to 114f are output as output signals 115b.

  Accordingly, the edge detector 113 may be configured to detect edges by signal processing and statistical processing for suppressing the influence of disturbance, including majority processing of the output signals 115a and 115b. If the purpose of suppressing the influence of the disturbance is achieved, the number of stages of the shift register is not limited to two or six.

<Effect of disturbance>
Here, the disturbance will be described.

  When a radio wave is received in an actual environment, there is a case where “0” and “1” of received data are inverted at the stage of the received wave due to the influence of fading, noise, and the like. Here, this is called disturbance.

  For example, in the case of the two-stage shift register 111a shown in FIG. 13A, the edge detector 113 has a state where the output signal 115a is “1” and the output signal 115b is “0”, or the output signal 115a. Is “0” and the output signal 115b is detected as “1”, it is determined that it is the boundary (edge) of the symbol period. However, it is difficult to distinguish whether this is a correct decision about the boundary of the actual symbol period or an incorrect decision due to disturbance.

  On the other hand, in the case of the six-stage shift register 111b shown in FIG. 13B, the edge detector 113 has all the output signals of the registers 114a to 114c being “1” and all the output signals of the registers 114d to 114f are “ If a state of 0 ″ is detected, it is determined that the boundary is a symbol period. Even in this case, such a state may occur due to disturbance, but the probability of occurrence is small. Further, when the edge detector 113 detects that the output signals of the registers 114a and 114c are “1” and the output signals of the registers 114b and 114d to 114f are “0”, the output signal of the register 114b is disturbed. It is determined that “1” has changed to “0”. As a result, the edge detector 113 can correctly determine the boundary of the symbol period.

  In this way, when the shift register has a multi-stage configuration, the influence of instantaneous disturbance is suppressed by the majority and average values of “0” and “1” in the output signals 115a and 115b, and “0” and “1”. It is possible to accurately determine the change point. In order to make such a determination, it is preferable that at least three registers 114a to 114c are provided at the front stage and at least three registers 114d to 114f are provided at the rear stage as in the shift register 111b.

  Judgment based on the above majority vote and average is statistically measured when the observed quantity with variance σ ^ 2 is measured N times and averaged, the average variance decreases to σ ^ 2 / N The effect of doing is used.

  When a multistage shift register is used, the method for determining the boundary is not limited to majority voting and averaging. If the same effect can be obtained, other statistical / signal processing-like methods can be used. Processing may be introduced.

[Realization of synchronization unit and timing controller]
Each block of the synchronization unit 11 and the timing controller 12 may be configured by hardware logic, or may be realized by software (control program) using a CPU as described below.

  Each of the above blocks includes a CPU (Central Processing Unit) that executes instructions of a program that realizes each function, a ROM (Read Only Memory) that stores the program, a RAM (Random Access Memory) that expands the program, a program, and various types A storage device (recording medium) such as a memory for storing data is provided. An object of the present invention is to supply a recording medium in which a program code (execution format program, intermediate code program, source program) of software that realizes the above-described functions is readable by a computer to the receiver 100, and a CPU Can also be achieved by reading and executing the program code recorded on the recording medium.

  Examples of the recording medium include magnetic tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks / hard disks, and optical disks such as CD-ROM / MO / MD / BD / DVD / CD-R. Can be used, such as a disk system including IC, a card system such as an IC card (including a memory card) / optical card, or a semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  The receiver 100 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

[Additional Notes]
The above-described embodiment is an example of the present invention, and the demodulation device 101 includes the synchronization unit 11 and the timing controller 12. Further, the synchronization unit 11 extracts a symbol period, supplies power to the internal circuit of the demodulator 101 only in the active period 33a generated by the timing controller 12, and the timing controller 12 generates the active period 33a by a predetermined method. Further, the synchronization unit 11 and the timing controller 12 are constituted by counters. If these characteristics are satisfied, the RF signal processing is performed in the configuration in which the OOK-modulated RF signal is demodulated into digital data “0” and “1”. The processing of the RF signal shown in FIG. The processing is not limited to the processing performed by the rectifier 7 and the comparator 8.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The demodulation device according to the present invention is configured by a wireless sensor node having a wireless communication function, and is preferably used for performing demodulation of OOK wireless communication used in a wireless sensor network for collecting information with low power consumption. it can. The present invention is particularly effective for wireless communication of wireless sensor networks, energy monitoring / control systems such as medical care, healthcare, smart grids, remote processing monitoring cameras, etc., button batteries, solar batteries, etc. of these systems Can be driven.

1, 2 terminals (communication terminals)
3 amplifier 4 mixer 5 filter 3 amplifier 8 comparator 10 wireless communication system 11 synchronization unit (symbol extraction means)
12 Timing controller (active period setting means)
13 Clock generator (clock generation means)
21a-21f switch (power supply / supply stop means)
22a-22f switch (power supply / supply stop means)
DESCRIPTION OF SYMBOLS 100 Receiver 101 Demodulator 102 Antenna 103 Demodulation processing part 111 Shift register 111a Shift register 111b Shift register 112 Counter 113 Edge detector (edge detection means)
121 counter 122 gating signal generator (power supply operation means)

Claims (8)

In a demodulator including a demodulation processing unit that demodulates a radio signal obtained by modulating an OOK (On / Off Keying) modulated packet including a synchronization word and data,
Clock generating means for generating a clock;
Symbol period extraction means for extracting a symbol period of the radio signal demodulated by the demodulation processing unit with reference to the clock;
Power supply / supply stop means for stopping power supply and power supply to the demodulation processing unit;
An active period for enabling power supply by the power supply / supply stop unit is set, and based on the active period, the power supply / supply stop unit is operated to supply power, and the power supply / supply stop unit is operated in a period other than the active period. Power supply control means for stopping the power supply operation in the power supply / supply stop means,
The power supply control means sets the entire period of the extracted symbol period as the active period in the demodulation of the synchronization word, and sets only the partial period of the extracted symbol period in the demodulation of the data as the active period. A demodulator that is set as a period.   The demodulator according to claim 1, wherein the power supply control unit sets the active period to the center of the extracted symbol period with reference to the clock. The power supply control means includes
A counter for counting the clock;
In the demodulation of the data, the power supply / supply stop means performs power supply operation during a period defined by the timing when the count value of the counter reaches the count value corresponding to the start time and end time of the active period. The demodulator according to claim 1, further comprising: a power supply operation unit that causes the power supply to operate. The symbol period extracting means includes
A counter for counting the clock;
Edge detection that detects the change point of the output signal of the demodulation processing unit as the boundary of the symbol period with reference to the clock, and stores the count value of the counter at the timing when the boundary is detected as the boundary of the symbol period The demodulator according to any one of claims 1 to 3, further comprising: means. The symbol period extracting means has a shift register composed of a two-stage register for shifting and storing with the clock,
The edge detecting means inputs an output signal of the demodulation processing unit to the register at the first stage, and detects a boundary between the symbol periods based on a difference between two systems of data stored in each register. The demodulator according to claim 4. The symbol period extracting means has a shift register composed of at least six stages of registers that shift and store the clock.
The edge detection means inputs the output signal of the demodulation processing unit to the register at the first stage, stores data in at least three registers at the front stage of the shift register, and at least at the rear stage of the shift register. 5. The demodulator according to claim 4, wherein a boundary between the symbol periods is detected based on a difference from data stored in each of the three registers.   A wireless communication system comprising a plurality of communication terminals including the demodulation device according to claim 1 and performing wireless communication between the communication terminals. A wireless communication system comprising a plurality of communication terminals including the demodulation device according to claim 3 or 6 and performing wireless communication between the communication terminals,
Based on the upper limit value of the frequency tolerance of the clock generation means on the transmission side and the clock generation means on the reception side, the difference in clock period per cycle between the communication terminal on the transmission side and the communication terminal on the reception side is a packet. The wireless communication system is characterized in that the packet length of the packet is determined in advance so that the accumulated error accumulated up to the last symbol is within a predetermined range.

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