JP2013089831A - Wiring structure and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure excellent in insulation property between wiring lines and having high reliability, and a method for manufacturing the same.SOLUTION: A method for manufacturing a wiring structure includes: applying varnish composed of a non-photosensitive resin including a polyimide resin as a base polymer by a spin coating method, and curing the polyimide resin by baking and curing to form a film as a first insulating film 12; then forming a plated seed layer 18, forming a photo-resist groove pattern 22, plating, removing the photo-resist groove pattern 22, and removing the plated seed layer 18 other than that under wiring, to form wiring 26 on the first insulating film; then dispersing silica particles 30 on a surface of the first insulating film, and dry-etching the first insulating film 12 with a mixed gas of CF4 and O2 by using the dispersed silica particles 30 as a mask, to form irregularity 32 having a level difference of 100 nm or more; and then similarly forming a polyimide resin film 34 as a second insulating film by using the spin coating method.

Description

The present invention relates to a wiring structure and a manufacturing method thereof.

  In recent years, along with demands for downsizing, high performance, and low prices for electronic devices, along with miniaturization of semiconductor chips and multi-terminals, miniaturization of circuit boards on which semiconductor chips are mounted, multilayering, and high electronic components Density mounting is in progress. In particular, with the increase in the number of terminals of a semiconductor chip and the narrowing of the pitch of terminals, the multilayer circuit board is also required to have fine wiring.

  In wiring structures such as multilayer printed circuit boards, LSI package boards, wafer level packages, and multi-chip packages, inexpensive organic resin films (polyimide, phenolic resin, epoxy resin, etc.) are used as insulating films that insulate between wiring layers. ing. Further, as the wiring, a copper wiring formed by a subtractive method, a semi-additive method, or the like, in particular, a semi-additive method that can be made finer than the subtractive method is used.

JP 2005-032841 A JP-A-2005-303186

  However, with the narrowing of the wiring pitch, problems such as withstand voltage, which have not existed before, are emerging. As a result of the study by the present inventors, it has been found that an insulation failure occurs in which the insulation resistance between the wirings is lowered in the HAST test (high temperature and high humidity insulation test).

  An object of the present invention is to provide a highly reliable wiring structure having excellent insulation between wirings and a method for manufacturing the same.

  According to one aspect of the embodiment, the first insulating film, the wiring formed on the first insulating film, the second insulating film formed on the first insulating film and on the wiring A wiring structure is provided in which the interface between the first insulating film and the second insulating film has an uneven shape with a step of 100 nm or more.

  Further, according to another aspect of the embodiment, a step is formed on the surface of the first insulating film in a region where the wiring is not formed and a step of forming the wiring on the first insulating film is 100 nm or more. Provided is a method for manufacturing a wiring structure, which includes a step of forming a concavo-convex shape and a step of forming a second insulating film on the wiring and on the surface of the first insulating film on which the concavo-convex shape is formed. Is done.

  According to the disclosed wiring structure and the manufacturing method thereof, the uneven shape formed at the insulating film interface between the wirings can effectively inhibit the movement of ions due to the electrostatic force between the wirings. As a result, it is possible to realize a highly reliable wiring structure with excellent insulation between the wirings.

FIG. 1 is a schematic cross-sectional view (part 1) illustrating the wiring structure according to the first embodiment. FIG. 2 is a schematic cross-sectional view (part 2) illustrating the wiring structure according to the first embodiment. FIG. 3 is a process cross-sectional view (part 1) illustrating the method for manufacturing the wiring structure according to the first embodiment. FIG. 4 is a process cross-sectional view (part 2) illustrating the method for manufacturing the wiring structure according to the first embodiment. FIG. 5 is a process cross-sectional view (part 3) illustrating the method for manufacturing the wiring structure according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing the wiring structure according to the second embodiment. FIG. 7 is a process cross-sectional view (part 1) illustrating the method for manufacturing the wiring structure according to the second embodiment. FIG. 8 is a process cross-sectional view (part 2) illustrating the method for manufacturing the wiring structure according to the second embodiment. FIG. 9 is a schematic sectional view showing a wiring structure according to the third embodiment. FIG. 10 is a process cross-sectional view (part 1) illustrating the method for manufacturing the wiring structure according to the third embodiment. FIG. 11 is a process cross-sectional view (part 2) illustrating the method for manufacturing the wiring structure according to the third embodiment. FIG. 12 is a process cross-sectional view (part 3) illustrating the method for manufacturing the wiring structure according to the third embodiment. FIG. 13 is a graph showing the relationship between the height difference of the interface shape, the failure occurrence time of the HAST test, and the ionized Cu movement distance ratio. FIG. 14 is a graph showing the relationship between the difference in height of the interface shape and the moving speed of ionized Cu. FIG. 15 is a graph showing the relationship between the particle size ratio of silica particles and the moving speed of ionized Cu. FIG. 16 is a graph showing the relationship between the dispersion rate of silica particles and the moving speed of ionized Cu.

[First Embodiment]
The wiring structure and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  1 and 2 are schematic cross-sectional views showing the wiring structure according to the present embodiment. 3 to 5 are process cross-sectional views illustrating the wiring structure manufacturing method according to the present embodiment.

  First, the wiring structure according to the present embodiment will be explained with reference to FIGS.

  An insulating film 12 is formed on the substrate 10. A wiring 26 is formed on the insulating film 12. The insulating film 12 is a film serving as a base for forming wiring, and may be the insulating substrate itself in addition to the insulating film 12 formed on the substrate 10. Although it does not specifically limit as the board | substrate 10, For example, a printed circuit board, a LSI package board | substrate, a semiconductor substrate etc. are mentioned. One or more wiring layers and functional elements may be formed on the substrate 10. The insulating film 12 is not particularly limited, and examples thereof include an inorganic insulating film such as a silicon oxide film and a silicon nitride film, and an organic insulating film such as a polyimide resin, a phenol resin, and an epoxy resin. The wiring 26 is not particularly limited, but is formed of a low-resistance metal material such as copper (Cu), for example.

  An insulating film 32 is formed on the insulating film 12 and the wiring 26. The insulating film 32 is an interlayer insulating film for insulating between the wiring 26 and a wiring (not shown) formed in an upper layer or a protective film for protecting the wiring 26. The insulating film 32 is not particularly limited, and examples thereof include an inorganic insulating film such as a silicon oxide film and a silicon nitride film, and an organic insulating film such as a polyimide resin, a phenol resin, and an epoxy resin.

  Concave and convex shapes 32 are formed on the surface of the insulating film 12. Thereby, the interface between the insulating film 12 and the insulating film 26 is roughened. For example, as shown in FIG. 2, the concavo-convex shape 32 is formed by a plurality of columnar structures 36 formed on the surface of the insulating film 12.

  Thus, in the wiring structure according to the present embodiment, the interface between the insulating film 12 and the insulating film 32 is roughened. The reason why the interface between the insulating film 12 and the insulating film 32 is roughened is to improve the withstand voltage between the adjacent wirings 26.

  The cause of lowering the withstand voltage between the wirings 26 is roughly divided into two insulation failure modes. One is a mode in which avalanche discharge occurs in a region where the electric field strength between wirings is strong, and dielectric breakdown explodes. The other is a mode in which the ionized wiring material (ionized Cu) behaves as a conduction path by diffusing the interface of the insulating film by the electrostatic force induced by the voltage applied between the wirings in the region where the electric field strength between the wirings is low. is there. Such an insulation failure mode is observed in a voltage application test (HAST test) or the like in a high temperature / humidified atmosphere performed as a reliability test. If moisture or an electrolyte is present in the environment, metal ions may be eluted from the wiring, leading to ion migration.

  The inventors of the present application conducted an extensive study on the relationship between the dielectric breakdown mode and the shape of the insulating film interface. By roughening the interface between the insulating film 12 and the insulating film 32 to a predetermined uneven shape 32, It has been found that the insulation failure between the wirings 26, particularly the latter insulation failure mode, can be reduced.

  As the concavo-convex shape 32 suitable for improving the withstand voltage between the wirings 26, first, it is desirable that the step (the difference in height between the concave portion and the convex portion) is 100 nm or more. This is because, in the uneven shape formed by a small step having a height difference of less than 100 nm, the inhibition of ion movement due to the electrostatic force in the distance direction between the wirings is small (see Example 1 and FIG. 13 described later). (See FIG. 14).

  The upper limit of the uneven height difference is not particularly limited. However, if the height difference is made too large, the aspect ratio of the columnar structure 36 becomes too large, and the structure is collapsed when the insulating film 34 is formed. It is assumed that a defect will occur. It is desirable that the upper limit of the uneven height difference is appropriately set according to the thickness of the columnar structure 36, the lower layer structure of the insulating film 12, and the like.

  Further, from the viewpoint of preventing ions from easily exceeding the height difference of the concavo-convex shape 32, it is desirable that the interface between the insulating film 12 and the insulating film 26 be directed in a direction intersecting the distance direction between the wirings. In particular, if the angle between the interface between the insulating film 12 and the insulating film 26 and the distance direction between the wirings is shallow, the inhibition of ion movement due to the electrostatic force in the distance direction between the wirings is reduced. It is desirable that the angle formed by the interface between the wiring line 26 and the distance direction between the wirings is 60 degrees or more.

  Such a concavo-convex shape 32 can be realized, for example, by forming a plurality of columnar structures 36 on the surface of the insulating film 12. In actual products and reliability tests, the voltage applied between electrically independent wirings is not necessarily directed in a certain direction due to the design of wiring patterns. In order to have an ion migration inhibiting effect against voltage application from multiple directions, it is desirable to provide a plurality of columnar structures that are point-symmetric structures in plan view.

  In this specification, the columnar structure 36 refers to not only a columnar structure having a uniform thickness but also a structure having a different thickness depending on the location, for example, a cone-shaped structure or a frustum-shaped structure. Is also included. The planar shape of the top of the columnar structure 36 is not particularly limited, and may be circular or polygonal. The columnar structure 36 corresponds to a cylinder, a cone, and a truncated cone when the planar shape is circular, and corresponds to a polygonal column, a polygonal pyramid, and a polygonal frustum when the planar shape is a polygon. The shape of the columnar structure 36 is not particularly limited as long as it is within a range in which the above effect can be realized, and may be appropriately changed.

  The thickness of the columnar structure 36 is preferably 0.3 or less, with the interval between adjacent wirings 26 being 1 (see Example 1 and FIG. 15 described later). This is because if the thickness of the columnar structures 36 exceeds 0.3, the number of columnar structures 36 formed between the wirings 26 is too small to effectively inhibit ion migration.

  The columnar structure 36 is preferably formed in a region of 15% to 85% of the surface of the insulating film 12 (see Example 1 described later and FIG. 16). This is because if the region where the columnar structure 36 is formed is too small, ion migration cannot be effectively inhibited, and if it is too large, there is no difference from the case where the columnar structure 36 is not formed.

  Moreover, it is desirable that the columnar structures 36 that form the concavo-convex shape 32 are irregularly arranged. This is because, in a concavo-convex shape formed in a certain regular arrangement, electrons or ions may pass through the insulating film between the structures by hopping, and may become a leak path between the wirings. The irregular arrangement of the columnar structures 36 is not particularly limited, but can be realized by, for example, a manufacturing method described later.

  Next, the method for manufacturing the wiring structure according to the present embodiment will be explained with reference to FIGS.

  First, a substrate 10 on which an insulating film 12 is formed as a base for forming wiring is prepared. The substrate 10 is not particularly limited, and for example, a printed substrate, an LSI package substrate, a semiconductor substrate, or the like can be applied. One or more wiring layers and functional elements may be formed on the substrate 10. The insulating film 12 is not particularly limited, and for example, an inorganic insulating film such as a silicon oxide film or a silicon nitride film, an organic insulating film such as a polyimide resin, a phenol resin, or an epoxy resin can be applied. . Instead of the substrate 10 on which the insulating film 12 is formed, an insulating substrate may be used. Here, as an example, a substrate 10 on which an insulating film 12 of polyimide resin is formed is used.

  Next, a conductive adhesion layer 16 of, for example, titanium (Ti) and a plating seed layer 18 of, for example, copper (Cu) are formed on the insulating film 12 by, for example, sputtering or vacuum deposition (FIG. 3A). ). The conductive adhesion layer 16 is not particularly limited. For example, a metal such as titanium, tungsten (W), or tantalum (Ta), or an alloy or metal compound containing at least one of these metals is applied. be able to. The plating seed layer 18 is not particularly limited, but a material having a low resistance value, for example, copper or silver (Ag) can be applied.

  Next, a photoresist 20 is formed on the plating seed layer 16 by, eg, spin coating or roll coating.

  Next, the photoresist is exposed and developed, and an opening 22 reaching the plating seed layer 16 is formed in the photoresist 20 in a region where wiring is to be formed.

  Next, a plating metal such as Cu is grown in the opening 22 using the plating seed layer 18 as a seed by electroplating, and the wiring conductor layer 24 embedded in the opening 22 and connected to the plating seed layer 18 is formed. It forms (FIG.3 (b)).

  Next, for example, cleaning is performed using a chemical solution such as acetone, isopropyl alcohol (IPA), N-methylpyrrolidone (NMP), and the photoresist 20 is removed. The photoresist 18 may be removed using a dry process such as ashing.

  Next, a portion of the plating seed layer 18 and the conductive adhesion layer 16 that are covered with the photoresist 20 are removed, and a wiring composed of a laminated structure of the conductive adhesion layer 16, the plating seed layer 18, and the wiring conductor layer 24. 26 is formed (FIG. 4A). For the removal of the plating seed layer 18, for example, wet etching using a chemical solution such as ammonium persulfate or potassium sulfate can be applied. Further, for example, wet etching using ammonium fluoride can be applied to the removal of the conductive adhesion layer 16. Note that the plating seed layer 18 and the conductive adhesion layer 16 may be removed by dry etching.

  Next, silica particles 30 having an average particle diameter of, for example, about 200 nm are dispersed on the surface of the insulating film 12 on which the wiring 26 is formed. The particles dispersed on the insulating film 12 are not particularly limited as long as the particles are made of a material having etching characteristics different from those of the insulating film 12.

  The particle size and dispersion density of the silica particles 30 are such that the interval between the wirings 26 is 1, the particle size rate of the silica particles is 0.3 or less, and the silica particle dispersion rate is in the range of 15% to 85%. As appropriate, the distance is appropriately set according to the interval between the wirings 26.

Next, dry etching is performed using the silica particles 30 as a mask to roughen the surface of the insulating film 12 to form a concavo-convex shape 34 (FIG. 5A). For example, using the silica particles 30 as a mask, anisotropic etching is performed with a mixed gas of CF ₄ and O ₂ , and the insulating film 12 in a region where the silica particles 30 are not formed is etched by about 100 nm. The particle size and dispersion density of the silica particles 30 correspond to the thickness and planar density of the columnar structure 36 to be formed.

  Next, a cleaning treatment is performed as necessary to remove the silica particles 30.

  Next, an insulating film 34 that covers the wiring 26 is formed on the insulating film 12 on which the wiring 26 and the uneven shape 32 are formed (FIG. 5B). For example, after the insulating film forming composition is applied by a spin coating method or the like, the insulating film 34 is formed by performing a pre-curing heat treatment and a curing process using a hot plate or an oven. In the heat treatment and the curing treatment, an atmosphere during the treatment can be appropriately selected as necessary. For example, an air atmosphere, a nitrogen atmosphere, a vacuum atmosphere, or the like can be applied. The thickness of the insulating film 34 can be appropriately set as necessary.

  The constituent material of the insulating film 34 may be an organic material or an inorganic material as long as it can maintain insulation between wirings. As a constituent material of the insulating film 34, for example, a polyimide resin, a phenol resin, an epoxy resin, or the like can be applied.

  The method for applying the composition for forming an insulating film is not particularly limited, and can be appropriately selected depending on the purpose. For example, a spin coating method, a dip coating method, a kneader coating method, a curtain coating method, a blade coating method, or the like can be applied.

  Thus, the wiring structure according to the present embodiment is formed.

  As described above, according to the present embodiment, by forming the uneven shape at the insulating film interface between the wirings, it is possible to effectively inhibit the movement of ions due to the electrostatic force between the wirings. Thereby, the withstand voltage between wiring can be improved.

[Second Embodiment]
A wiring structure and a manufacturing method thereof according to the second embodiment will be described with reference to FIGS. The same components as those in the wiring structure and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 6 is a schematic cross-sectional view showing the wiring structure according to the present embodiment. 7 and 8 are process cross-sectional views illustrating the wiring structure manufacturing method according to the present embodiment.

  First, the wiring structure according to the present embodiment will be explained with reference to FIG.

  As shown in FIG. 6, the wiring structure according to the present embodiment is the same as that of the first embodiment shown in FIG. 1 except that the upper end portion of the concavo-convex shape 32 is lower than the interface between the insulating film 12 and the wiring 26. It is the same as the wiring structure. By making the upper end of the concavo-convex shape 32 lower than the interface between the insulating film 12 and the wiring 26, the path between the wirings 26 passing through the interface between the insulating film 12 and the insulating film 34 can be lengthened. As a result, the phenomenon of leakage due to the influence of induced electrons or the like along the interface can be efficiently prevented, and the withstand voltage can be further improved.

  Next, the manufacturing method of the wiring structure according to the present embodiment will be explained with reference to FIGS.

  First, the wiring 26 is formed on the insulating film 12 in the same manner as the manufacturing method of the wiring structure according to the first embodiment shown in FIGS. 3A to 4A.

  Next, dry etching is performed using the wiring 26 as a mask to form a groove 28 having a depth of, for example, about 500 nm in the surface portion of the insulating film 12 (FIG. 7A).

  Next, silica particles 30 having an average particle diameter of, for example, about 200 nm are dispersed on the bottom surface of the groove 28 (FIG. 7B).

  Next, dry etching is performed using the silica particles 30 as a mask, and the surface of the insulating film 12 is roughened to form a concavo-convex shape 32 (FIG. 8A).

  Next, a cleaning treatment is performed as necessary to remove the silica particles 30.

  Next, an insulating film 34 covering the wiring 26 is formed on the insulating film 12 on which the wiring 26 and the uneven shape 32 are formed (FIG. 8B).

  Thus, the wiring structure according to the present embodiment is formed.

  As described above, according to the present embodiment, by forming the uneven shape at the insulating film interface between the wirings, it is possible to effectively inhibit the movement of ions due to the electrostatic force between the wirings. Thereby, the withstand voltage between wiring can be improved.

[Third Embodiment]
A wiring structure and a manufacturing method thereof according to the third embodiment will be described with reference to FIGS. The same components as those in the wiring structure and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 9 is a schematic cross-sectional view showing the wiring structure according to the present embodiment. 10 to 11 are process cross-sectional views illustrating the wiring structure manufacturing method according to the present embodiment.

  First, the wiring structure according to the present embodiment will be explained with reference to FIG.

  The wiring structure according to the present embodiment is the same as the wiring structure according to the first embodiment, except that the wiring 26 is a so-called damascene wiring embedded in the insulating film 12. The uneven shape 32 is formed on the surface of the insulating film 12 in which the wiring 26 is embedded.

  Next, the manufacturing method of the wiring structure according to the present embodiment will be explained with reference to FIGS.

  First, a substrate 10 on which an insulating film 12 is formed as a base for forming wiring is prepared.

  Next, a wiring trench 14 is formed in the insulating film 12 in a region where wiring is to be formed by photolithography and dry etching (FIG. 10A).

  Next, a conductive adhesion layer 16 of, for example, Ti and a plating seed layer 18 of, for example, Cu are formed on the insulating film 12 in which the wiring trenches 14 are formed by, for example, sputtering or vacuum deposition.

  Next, a plating metal such as Cu is grown by electroplating using the plating seed layer 18 as a seed to form the wiring conductor layer 24 (FIG. 10B).

  Next, the wiring conductor layer 24, the plating seed layer 18 and the conductive adhesion layer 16 on the insulating film 12 are removed by, for example, chemical mechanical polishing (CMP), and the conductive adhesion layer 16 and the plating seed in the groove 14 are removed. The layer 18 and the wiring conductor layer 24 are selectively left. As a result, a wiring 26 is formed which is embedded in the groove 14 and includes the conductive adhesion layer 16, the plating seed layer 18 and the wiring conductor layer 24 (FIG. 11A).

  Next, silica particles 30 having an average particle diameter of, for example, about 200 nm are dispersed on the surface of the insulating film 12 in which the wirings 26 are embedded (FIG. 11B).

  Next, dry etching is performed using the silica particles 30 as a mask to roughen the surface of the insulating film 12 to form a concavo-convex shape 32 (FIG. 12A).

  Next, a cleaning treatment is performed as necessary to remove the silica particles 30.

  Next, an insulating film 34 that covers the wiring 26 is formed on the insulating film 12 in which the wiring 26 is embedded and the uneven shape 32 is formed on the surface (FIG. 12B).

  Thus, the wiring structure according to the present embodiment is formed.

  As described above, according to the present embodiment, by forming the uneven shape at the insulating film interface between the wirings, it is possible to effectively inhibit the movement of ions due to the electrostatic force between the wirings. Thereby, the withstand voltage between wiring can be improved.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, although the wiring structure having one wiring layer is shown in the above embodiment, the number of wiring layers is not limited to one, and may be two or more.

  Moreover, although the example which forms the wiring 26 by what is called a semi-additive method was shown in the said 1st Embodiment, the formation method of the wiring 26 is not limited to this. The wiring 26 may be formed not only by the semi-additive method but also by other methods such as a subtractive method.

  In addition, the constituent materials, manufacturing conditions, and the like described in the above embodiments are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

[Example 1]
After applying a non-photosensitive resin varnish whose base polymer is a polyimide resin on a 6-inch Si wafer by spin coating, the polyimide resin was cured by pre-baking and curing at 300 ° C. for 1 hour. . Thereby, a polyimide resin film having a thickness of about 15 μm was formed as the first insulating film.

  Next, reverse sputtering was performed on the surface of the first insulating film, and then 0.1 μm thick Ti and 0.3 μm Cu were sputtered to form a conductive adhesion layer and a plating seed layer.

  Next, after forming a novolac-type photoresist film on the plating seed layer, exposure was performed with a contact aligner using a glass mask having a land pattern with a diameter of 80 μm and a trench wiring pattern with a width of 1 μm, and the photoresist film was developed. As a result, a photoresist film having a land pattern of φ80 μm and a trench wiring pattern of 1 μm in width was formed.

  Next, Cu electroplating was performed using the plating seed layer as a sheet, and a Cu wiring conductor layer was formed in the land pattern and the trench wiring pattern of the photoresist film. At this time, the electric Cu plating was made to have a height of about 1.5 μm to 2.0 μm.

  Next, after stripping the photoresist film using NMP, the plating seed layer and the conductive adhesion layer that were not plated by the coating of the photoresist film are sequentially etched with ammonium persulfate and ammonium fluoride to form a wiring conductor layer. Was separated to form a metal wiring.

  Next, silica particles having an average particle diameter of 200 nm were dispersed on the surface of the first insulating film. The dispersion ratio of the silica particles at this time was calculated as a ratio of the projected area of the portion where the silica particles adhered to the surface area of the exposed first insulating film, and was 41.57%.

Next, using the dispersed silica particles as a mask, the first insulating film was dry-etched using a gas in which CF ₄ and O ₂ were mixed. The height difference of the surface shape formed on the first insulating film was adjusted by varying the conditions such as output, pressure, and time during etching.

  Next, after applying a non-photosensitive resin varnish whose base polymer is a polyimide resin by spin coating, the polyimide resin was cured by pre-baking and curing at 300 ° C. for 1 hour. As a result, a polyimide resin film having a film thickness of about 5 μm was formed as the second insulating film.

  Next, in order to ensure conduction for the reliability test, the polyimide resin on the land pattern was removed by laser irradiation.

  With respect to the wiring structure thus formed, as a reliability test (HAST test), a voltage of 3.5 V can be applied to a maximum of 150 via a land pattern between two independent wires in an environment of 130 ° C. and 85% RH. The insulation was applied between the wirings for a time. The wiring interval between the two wirings is 1 μm. The test results are shown in FIGS.

  FIG. 13 is a graph showing the relationship between the height difference of the interface shape, the failure occurrence time of the HAST test, and the movement distance ratio of ionized Cu.

  The difference in height of the interface shape on the horizontal axis is the difference in height between the low and high portions of the concavo-convex shape formed on the surface of the first insulating film, and corresponds to the height of the columnar structure. The failure occurrence time of the HAST test on the left vertical axis is the time until dielectric breakdown occurs in the insulating film between two wirings. The movement distance ratio of ionized Cu on the right vertical axis is the ratio of the movement distance of Cu ions when the distance between two wires is 1. As the moving distance ratio of ionized Cu is closer to 1, the moving distance of Cu ions is larger and the insulating property is lower.

  As shown in FIG. 13, when the difference in height of the interface shape is 50 nm or less, the defect occurrence time is about a dozen hours. On the other hand, when the difference in height of the interface shape exceeds 50 nm, the difference in height of the interface shape increases rapidly. When the thickness became 100 nm or more, no defect occurred even after 150 hours. In addition, since the defect did not generate | occur | produce even if 150 hours passed when the height difference of an interface shape was 100 nm or more, on the graph, it plots temporarily at 150 hours.

  Further, when the height difference of the interface shape is less than 100 nm, the moving distance ratio of ionized Cu exceeds 0.5, whereas when the height difference of the interface shape becomes 100 nm or more, it rapidly decreases and becomes 0.15 or less. .

  FIG. 14 is a graph showing the relationship between the difference in height of the interface shape calculated from the test results of FIG. 13 and the moving speed of ionized Cu.

  As shown in FIG. 14, the moving speed of ionized Cu is greatly reduced by setting the difference in height of the interface shape to 100 nm or more. This indicates that when the height difference of the interface shape is 100 nm or more, the migration of ionized Cu is effectively inhibited, and the withstand voltage between the wirings can be improved.

  FIG. 15 is a graph showing the relationship between the particle size ratio of silica particles and the moving speed of ionized Cu. The particle size ratio of the silica particles is a ratio of the diameter of the silica particles when the distance between two wirings is 1.

  As shown in FIG. 15, by making the particle size ratio of silica particles 0.3 or less, the moving speed of ionized Cu is greatly reduced. This indicates that when the particle size ratio of the silica particles is 0.3 or less, the migration of ionized Cu is effectively inhibited and the withstand voltage between the wirings can be improved.

  FIG. 16 is a graph showing the relationship between the dispersion rate of silica particles and the moving speed of ionized Cu.

  As shown in FIG. 16, the moving speed of ionized Cu is greatly reduced by setting the dispersion rate of silica particles in the range of 15% to 85%. This indicates that when the dispersion ratio of the silica particles is in the range of 15% to 85%, the migration of ionized Cu is effectively inhibited, and the withstand voltage between the wirings can be improved.

  From the results of FIGS. 15 and 16, it was verified that the withstand voltage between the wirings can be improved by setting the particle size ratio of the silica particles to 0.3 or less and the dispersion ratio to a range of 15% to 85%.

[Example 2]
After applying a non-photosensitive resin varnish whose base polymer is a polyimide resin on a 6-inch Si wafer by spin coating, the polyimide resin was cured by pre-baking and curing at 300 ° C. for 1 hour. . Thereby, a polyimide resin film having a thickness of about 15 μm was formed as the first insulating film.

  Next, after forming a novolac-type photoresist film on the first insulating film, exposure was performed with a contact aligner using a glass mask having a land pattern with a diameter of 80 μm and a trench wiring pattern with a width of 1 μm, and the photoresist film was developed. . As a result, a photoresist film having a land pattern of φ80 μm and a trench wiring pattern of 1 μm in width was formed.

Next, using the photoresist film as a mask, the first insulating film was dry-etched using a mixed gas of CF ₄ and O ₂ to transfer the land pattern and the trench wiring pattern to the first insulating film.

Next, the photoresist film on the first insulating film was removed by ashing using O ₂ gas.

  Next, reverse sputtering was performed on the surface of the first insulating film, and then 0.1 μm thick Ti and 0.3 μm Cu were sputtered to form a conductive adhesion layer and a plating seed layer.

  Next, electric Cu plating was performed using the plating seed layer as a sheet, and a Cu wiring conductor layer was formed on the plating seed layer. At this time, the electric Cu plating was made to have a height of about 2.5 μm to 3.0 μm.

  Next, unnecessary wiring conductor layers, plating seed layers, and conductive adhesion layers deposited on the first insulating film were removed by CMP to form metal wiring. At this time, the height of the metal wiring was about 1.5 μm to 2.0 μm.

  Next, silica particles were dispersed on the surface of the first insulating film. At this time, the particle diameter and dispersion conditions of the silica particles were changed, and various samples having different silica particle diameter ratios and dispersion ratios were formed. The particle size ratio and the dispersion ratio of the silica particles are respectively calculated as a ratio of the particle diameter to the distance between the wirings and a ratio of the projected area of the portion where the silica particles are adhered to the exposed first insulating film surface area.

Next, using the dispersed silica particles as a mask, the first insulating film was dry-etched using a gas in which CF ₄ and O ₂ were mixed. Here, conditions such as output, pressure, time, etc. at the time of etching were set so that the difference in height of the surface shape formed on the first insulating film was 200 nm.

  Next, after applying a non-photosensitive resin varnish whose base polymer is a polyimide resin by spin coating, the polyimide resin was cured by pre-baking and curing at 300 ° C. for 1 hour. As a result, a polyimide resin film having a film thickness of about 5 μm was formed as the second insulating film.

  Next, in order to ensure conduction for the reliability test, the polyimide resin on the land pattern was removed by laser irradiation.

  With respect to the wiring structure thus formed, as a reliability test (HAST test), a voltage of 3.5 V can be applied to a maximum of 150 via a land pattern between two independent wires in an environment of 130 ° C. and 85% RH. The insulation was applied between the wirings for a time.

  As a result, the same measurement results as the wiring structure of Example 1 were obtained for the wiring structure of Example 2.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1) a first insulating film;
A wiring formed on the first insulating film;
A second insulating film formed on the first insulating film and on the wiring;
The wiring structure, wherein the interface between the first insulating film and the second insulating film has an uneven shape with a step of 100 nm or more.

(Appendix 2) In the wiring structure described in Appendix 1,
The uneven structure is formed of a plurality of columnar structures formed on a surface of the first insulating film.

(Appendix 3) In the wiring structure described in Appendix 2,
The plurality of columnar structures are formed in a region of 15% to 85% of the surface of the first insulating film.

(Appendix 4) In the wiring structure described in Appendix 2 or 3,
The wiring has a first wiring pattern and a second wiring pattern provided adjacent to each other,
The thickness of the columnar structure is 0.3 or less, where 1 is the interval between the first wiring pattern and the second wiring pattern.

(Appendix 5) In the wiring structure according to any one of appendices 2 to 4,
The wiring structure, wherein the plurality of columnar structures are irregularly arranged.

(Appendix 6) In the wiring structure according to any one of appendices 2 to 5,
An upper end portion of the columnar structure is lower than an interface between the first insulating film and the wiring.

(Appendix 7) In the wiring structure according to any one of appendices 1 to 6,
The wiring structure is characterized in that the wiring is embedded in the first insulating film.

(Appendix 8) In the wiring structure according to any one of appendices 1 to 7,
The wiring structure is characterized in that the wiring is formed of a wiring material mainly composed of Cu.

(Additional remark 9) The process of forming wiring on the 1st insulating film,
Forming a concavo-convex shape with a step of 100 nm or more on the surface of the first insulating film in a region where the wiring is not formed;
Forming a second insulating film on the wiring and on the surface of the first insulating film on which the uneven shape is formed. A method for manufacturing a wiring structure, comprising:

(Additional remark 10) In the manufacturing method of the wiring structure as described in additional remark 9,
Forming the concavo-convex shape on the surface of the first insulating film,
Dispersing particles of a material having etching characteristics different from those of the first insulating film on the surface of the first insulating film;
Etching the first insulating film using the particles as a mask, and forming the concavo-convex shape on the surface of the first insulating film.

(Additional remark 11) In the manufacturing method of the wiring structure of Additional remark 10,
In the step of dispersing the particles, the particles are dispersed so that the dispersion ratio of the particles is in the range of 15% to 85%.

(Additional remark 12) In the manufacturing method of the wiring structure of Additional remark 10 or 11,
The wiring has a first wiring pattern and a second wiring pattern provided adjacent to each other,
In the step of dispersing the particles, the interval between the first wiring pattern and the second wiring pattern is set to 1, and the particles having a particle size of 0.3 or less are dispersed. Manufacturing method.

(Appendix 13) In the method for manufacturing a wiring structure according to any one of appendices 9 to 12,
The method of manufacturing a wiring structure, further comprising a step of etching the first insulating film using the wiring as a mask before the step of forming the uneven shape on the surface of the insulating film.

DESCRIPTION OF SYMBOLS 10 ... Substrate 12, 34 ... Insulating film 14 ... Wiring groove 16 ... Conductive adhesion layer 18 ... Plating seed layer 20 ... Photoresist film 22 ... Opening 24 ... Wiring conductor layer 26 ... Wiring 28 ... Groove 30 ... Silica particle 32 ... Uneven shape 36 ... columnar structure

Claims (6)

A first insulating film;
A wiring formed on the first insulating film;
A second insulating film formed on the first insulating film and on the wiring;
The wiring structure, wherein the interface between the first insulating film and the second insulating film has an uneven shape with a step of 100 nm or more. The wiring structure according to claim 1,
The uneven structure is formed of a plurality of columnar structures formed on a surface of the first insulating film. The wiring structure according to claim 2,
The plurality of columnar structures are formed in a region of 15% to 85% of the surface of the first insulating film. In the wiring structure according to claim 2 or 3,
The wiring has a first wiring pattern and a second wiring pattern provided adjacent to each other,
The thickness of the columnar structure is 0.3 or less, where 1 is the interval between the first wiring pattern and the second wiring pattern. Forming a wiring on the first insulating film;
Forming a concavo-convex shape with a step of 100 nm or more on the surface of the first insulating film in a region where the wiring is not formed;
Forming a second insulating film on the wiring and on the surface of the first insulating film on which the uneven shape is formed. A method for manufacturing a wiring structure, comprising: In the manufacturing method of the wiring structure according to claim 5,
Forming the concavo-convex shape on the surface of the first insulating film,
Dispersing particles of a material having etching characteristics different from those of the first insulating film on the surface of the first insulating film;
Etching the first insulating film using the particles as a mask, and forming the concavo-convex shape on the surface of the first insulating film.

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