JP2013088916A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a non-volatile memory capable of switching a high-speed operation and a low-speed operation and reducing power consumption during the low-speed operation more than before.SOLUTION: In a semiconductor device 1, a clock generation circuit 40 generates a clock whose frequency during a high frequency mode is higher than the frequency during a low frequency mode. A central processing unit 20 obtains reading data read from a non-volatile memory 10 via a data bus 11. A clock delay section 50A includes a first path 51 via a plurality of stages of buffers 55 in a cascade connection and a second path 52 that bypasses the plurality of stages of buffers 55. The clock delay section 50A supplies a clock from the clock generation circuit 40 to the central processing unit 20 via the first path 51 during the high frequency mode and a clock from the clock generation circuit 40 to the central processing unit 20 via the second path 52 during the low frequency mode.

Description

  The present invention relates to a semiconductor device including a clock generation circuit and a clock distribution circuit.

  When distributing the clock generated by the clock generation circuit, it is necessary to prevent timing shift due to wiring capacity, delay time, etc., that is, malfunction due to clock skew. For example, the clock distribution circuit described in Japanese Patent Application Laid-Open No. 2000-122751 (Patent Document 1) includes a plurality of clock lines connected to a clock tree structure and a plurality of buffers inserted in each clock line. By connecting the output branches of the buffers that make up each clock line so that they differ, the delay time of the clock in each clock line can be changed slightly, resulting in variations in delay time due to other semiconductor elements and wiring lengths. This makes it possible to take a skew margin due to the operation.

  Although not directly related to clock distribution, techniques for controlling the delay amount of the clock are disclosed in the following documents.

  International Publication No. WO 00/45246 (Patent Document 2) discloses a clock generation circuit having a delay circuit, a selector, and a control circuit. Here, the delay circuit has a plurality of cascade-connected buffers for delaying the input clock signal and a plurality of output terminals for outputting clock signals delayed by different delay times. The selector selects one of the plurality of output terminals of the delay circuit based on the output from the control circuit.

  Japanese Patent Laid-Open No. 2007-241441 (Patent Document 3) discloses a data output device that outputs data with a delay amount suitable for a device on the data receiving side based on an input clock. Specifically, the data output device described in this document includes a plurality of delay units connected in multiple stages, a delay amount selection unit that selects one of the different clocks passing through the delay unit, and a selection Data output means for outputting data in accordance with the generated clock.

  A method of controlling the clock frequency is also known in order to prevent malfunction due to clock skew. For example, in the electronic device described in Japanese Patent Laid-Open No. 9-244770 (Patent Document 4), the access frequency of a CPU (Central Processing Unit) is set to prevent malfunction when the power supply voltage drops to a drop voltage. The CPU is reset when the determination is delayed and the voltage drops to a reset voltage lower than the drop voltage.

  In the microcontroller described in Japanese Patent Laid-Open No. 2004-86531 (Patent Document 5), the clock frequency is increased only when high performance is required, and the clock is operated at a high speed. Both performance and low power consumption are achieved. In particular, in the case of this document, in order to further reduce the power consumption, the driving capability of the buffer provided in the delay circuit is adjusted according to the clock frequency.

JP 2000-122751 A International Publication No. 00/45246 JP 2007-241441 A Japanese Patent Laid-Open No. 9-244770 JP 2004-86531 A

  By the way, a non-volatile memory such as a flash memory generally has a longer access time than a volatile memory such as a DRAM (Dynamic Random Access Memory). Therefore, when the CPU reads data from the non-volatile memory with no wait (waiting time 0) while the CPU is operating at a high clock frequency, the clock supplied to the CPU so as not to cause a timing shift. Need to be significantly delayed by a multi-stage buffer.

  On the other hand, when the CPU is operated at a low clock frequency or when a wait cycle is inserted when the CPU takes in read data, the above phase adjustment is not necessary. However, since a multi-stage buffer is provided in accordance with the case of high frequency and no wait, wasteful power consumption is generated by the multi-stage buffer during low-speed reading or wait cycle insertion.

  The present invention has been made in consideration of the above-described problems, and an object of the present invention is to enable switching between a high-speed operation and a low-speed operation in a semiconductor device provided with a nonvolatile memory. It is to reduce the power consumption during operation than before.

  A semiconductor device according to an embodiment of the present invention includes a clock generation circuit, a nonvolatile memory, a data bus, a central processing unit, and a clock delay unit. The clock generation circuit has a low frequency mode and a high frequency mode as operation modes, and generates a clock having a higher frequency in the high frequency mode than in the low frequency mode. The nonvolatile memory operates based on the clock generated by the clock generation circuit. The data bus is connected to the nonvolatile memory. The central processing unit operates based on the clock generated by the clock generation circuit, and acquires read data read from the nonvolatile memory via the data bus. The clock delay unit is provided in a clock supply path from the clock generation circuit to the central processing unit. The clock delay unit includes a first path through a plurality of cascade-connected buffers and a second path that bypasses the plurality of buffers. In the high frequency mode, the clock delay unit receives a clock from the clock generation circuit as a first path. Supply to the central processing unit via the route. In the low frequency mode, the clock delay unit supplies the clock from the clock generation circuit to the central processing unit via the second path.

  According to the above embodiment, when data is read from the nonvolatile memory in the high frequency mode, the clock is supplied to the central processing unit via the plurality of stages of buffers. On the other hand, when data is read from the nonvolatile memory in the low frequency mode, a clock is supplied bypassing a plurality of stages of buffers. Thereby, it is possible to switch between the case of the high speed operation and the case of the low speed operation, and the power consumption at the time of the low speed operation can be reduced as compared with the conventional case.

1 is a block diagram showing a configuration of a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a timing chart showing signal waveforms of respective parts of the semiconductor device 1 of FIG. 1 in a low frequency mode. FIG. 2 is a timing chart showing signal waveforms of respective parts of the semiconductor device 1 of FIG. 1 in a high frequency mode. It is a block diagram which shows the structure of the semiconductor device 2 by Embodiment 2 of this invention. FIG. 5 is a circuit diagram showing a configuration example of a D flip-flop circuit with a write enable terminal in FIG. 4. FIG. 5 is a timing chart showing signal waveforms of respective parts of the semiconductor device 2 of FIG. 4 in the case of a low-speed reading mode. FIG. 6 is a timing chart showing signal waveforms at various parts of the semiconductor device 2 in the case of a high-speed reading mode. It is a block diagram which shows the structure of the semiconductor device 3 by Embodiment 3 of this invention. It is a block diagram which shows the structure of the semiconductor device 4 by Embodiment 4 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of Semiconductor Device 1]
FIG. 1 is a block diagram showing a configuration of a semiconductor device 1 according to the first embodiment of the present invention. Referring to FIG. 1, a semiconductor device 1 is a microcomputer chip including a CPU 20, a flash memory 10, an SRAM (Static Random Access Memory), and a number of functional modules such as a communication interface (other than the CPU 20 and the flash memory 10). Many of the functional modules are not shown). These functional modules are connected via the bus 11. A logic circuit 22 in the CPU 20 is connected to the bus 11 via a bus interface (Bus I / F) 21. The bus 11 includes a control bus, an address bus, and a data bus.

  The semiconductor device 1 further includes a control register group 30, a clock generation circuit 40, and a plurality of phase adjustment units (also referred to as clock delay units) 50A and 50B for adjusting the phase of the clock.

  The control register group 30 includes a control register 31 for switching the frequency of the clock generated by the clock generation circuit 40 and a control register 32 for controlling the operation of the phase adjusting units 50A and 50B. The set values of the control registers 31 and 32 can be read from the CPU 20 or rewritten.

  The clock generation circuit 40 generates a clock that is an operation reference of the entire semiconductor device 1. The clock generation circuit 40 has a high frequency mode and a low frequency mode as operation modes. A clock having a higher frequency is generated in the high frequency mode than in the low frequency mode. In the first embodiment, when the control signal CS1 output from the control register 31 is at a high level (H level), the clock generation circuit 40 operates in a high frequency mode, and when the control signal CS1 is at a low level (L level), the clock is generated. The generation circuit 40 operates in the low frequency mode. The clock generated by the clock generation circuit 40 is distributed to each part of the semiconductor device 1.

  When a clock tree is used as the clock distribution method, in a normal method, the delay from the clock starting point to the clock input terminal of each flip-flop (FF) is adjusted to be uniform (zero skew). In order to realize zero skew, the length of the wiring to each flip-flop is made uniform, and the number of buffers to each flip-flop is made equal.

  On the other hand, a useful skew that gives a predetermined phase difference is used in a circuit that cannot satisfy the operating frequency specification with zero skew. Specifically, a buffer is added to the clock line connected to the flip-flop on the data receiver side. As a result, the phase of the clock on the data receiver side is delayed with respect to the phase of the clock on the flip-flop or memory on the data transmission side so that the operating frequency specification is satisfied.

  In the case of FIG. 1, a phase adjustment unit 50A is provided to delay the phase of the clock CLK4 supplied to the flip-flop 23 in the CPU 20 with respect to the clock CLK1 supplied to the flash memory 10. FIG. 1 shows a flip-flop 23 as a representative flip-flop provided in the CPU 20. Data DT 2 is input from the logic circuit 22 to the data terminal of the flip-flop 23.

  The phase adjustment unit 50 </ b> A includes a first clock path 51 including a delay circuit 56 including a multi-stage buffer 55 and a second clock path 52 bypassing the delay circuit 56. The delay amount of the first clock path 51 is larger than the delay amount of the second clock path 52.

  The first clock path 51 is used in the high frequency mode. As a result, data can be read from the flash memory 10 having a slow data access without waiting. On the other hand, the second clock path 52 is used in the low frequency mode. Since the second clock path 52 is not provided with a plurality of stages of buffers, power consumption can be reduced.

  The phase adjustment unit 50A includes a clock selector 58, gating cells 53 and 54, an inverter, and a configuration for switching the first and second clock paths 51 and 52 described above. 57. The clock selector 58 and the gating cells 53 and 54 are controlled by a control signal CS2 output from the control register 32 for switching the clock path.

  The clock CLK4 is supplied from the clock selector 58 to the flip-flop 23 in the CPU 20. The clock selector 58 selectively outputs one of the signal CLK2 from the clock path 51 with a large delay and the signal CLK3 from the clock path 52 with a small delay.

  The large delay clock path 51 is a path for supplying the clock CLK4 to the clock terminal of the flip-flop 23 in the high frequency mode. A clock gating cell 53 is provided in the first stage of the clock path 51, and a delay circuit 56 is provided in the subsequent stage of the clock gating cell 53. The delay circuit 56 delays the phase of the clock to ensure the setup time of the flip-flop 23 in the high frequency mode.

  The clock path 52 with a small delay is a path for supplying the clock CLK4 to the clock terminal of the flip-flop 23 in the low frequency mode. A clock gating cell 54 is provided at the first stage of the clock path 52. Since the clock path 52 has a smaller number of buffer stages than the clock path 51 having a large delay, the delay amount of the clock path 52 is smaller than that of the clock path 51.

  A clock path 51 with a large delay and a clock path 52 with a small delay are switched by a clock control signal CS2 corresponding to the set value of the control register 32 for clock path switching. In the high frequency mode, the clock path 51 with a large delay is selected by setting the clock control signal CS2 to H level, and in the low frequency mode, the clock path 52 with a small delay is selected by setting the clock control signal CS2 to L level. The

  The connection relationship among the clock generation circuit 40, the control register 32, and the gating cells 53 and 54 is as follows. A control signal CS2 from the control register 32 is input to the first input terminal of the gating cell 53, and a signal obtained by inverting the logic level of the control signal CS2 by the inverter 57 is input to the first input terminal of the gating cell 54. Is done. The clock generated by the clock generation circuit 40 is input to the second input terminals of the gating cells 53 and 54 through the buffers 41, 42A, and 44A. Each of the gating cells 53 and 54 outputs a logical product of signals input to the first and second input terminals.

  Therefore, by setting the control signal CS2 to the H level in the high frequency mode, the gating cell 53 passes the input clock, and the gating cell 54 outputs an L level signal. On the other hand, by setting the control signal CS2 to the L level in the low frequency mode, the gating cell 54 passes the input clock, and the gating cell 53 outputs the L level signal.

  In the high frequency mode, the phase of a clock supplied to a flip-flop provided in another functional module that reads data from the flash memory 10 also needs to be significantly delayed. For this reason, a phase adjustment unit having the same configuration as the phase adjustment unit 50A provided in the clock line for the CPU 20 is also provided in the clock supply path to other flip-flops. FIG. 1 shows, as an example, a phase adjustment unit 50B provided in a clock supply path to the flip-flops 12 and 13. The clock generated by the clock generation circuit 40 is input to the gating cells 53 and 54 provided in the phase adjustment unit 50B via the buffers 41, 42B, and 44B.

[Operation of Semiconductor Device 1]
FIG. 2 is a timing chart showing signal waveforms of respective parts of the semiconductor device 1 of FIG. 1 in the case of the low frequency mode. In the timing chart of FIG. 2, the clock control signal CS1 output from the clock frequency switching control register 31, the clock CLK1 for the flash memory 10, and the first clock path 51 with a large delay are sequentially transmitted from the top. The clock CLK2 input to the selector 58, the clock CLK3 input to the clock selector 58 through the second clock path 52 with a small delay, the clock CLK4 input to the clock terminal of the flip-flop 23, and the address bus Voltage waveforms of an address signal input to the flash memory, read data DT1 output from the flash memory 10 to the bus 11, and read data DT2 input to the data terminal of the flip-flop 23 in the CPU 20 are shown.

  1 and 2, the clock generation circuit 40 operates in the low frequency mode by setting the control signal CS1 to the L level. In FIG. 2, as an example, the clock frequency in the low frequency mode is 50 MHz (period: 20 ns), the access time Tac1 (from time t1 to time t5) of the flash memory 10 is about 9 ns, and from the flash memory 10 to the flip-flop 23. The path delay Td1 (from time t5 to time t7) is about 4 ns.

  In the low frequency mode, the read data Data1 from the flash memory 10 can be taken into the flip-flop 23 without waiting without using a clock whose phase is delayed by the clock path 51 having a large delay. Therefore, the clock path 52 with a small delay is selected by the control signal CS2 at the L level. At this time, the clock CLK4 input to the flip-flop 23 of the CPU 20 has substantially the same phase as the clock CLK1 input to the flash memory 10 (a slight path delay from the clock selector 58 to the flip-flop 23 is added). The clock path 51 with a large delay and the clock path 52 with a small delay are selected by the clock selector 58 exclusively. Since the clock path 51 which is not selected is gated by the first stage gating cell 53, the clock CLK2 does not toggle and shows the L level. As a result, the read data Data1 is taken into the flip-flop 23 at time t10 when about 20 ns have elapsed from time t1 when the address Addr1 was input to the flash memory 10.

  FIG. 3 is a timing chart showing signal waveforms of respective parts of the semiconductor device 1 of FIG. 1 in the case of the high frequency mode. FIG. 3 shows voltage waveforms at the same location as in FIG.

  1 and 3, the clock generation circuit 40 operates in the high frequency mode by setting the control signal CS1 to the H level. FIG. 3 shows a case of 100 MHz (period: 10 ns) as an example of the clock frequency in the high frequency mode. Times t1 to t6 and times t6 to t9 each correspond to one cycle. The access time Tac1 (from time t1 to time t5) of the flash memory 10 and the path delay Td1 (from time t5 to time t7) while data is transmitted from the flash memory 10 to the flip-flop 23 are the same as in the case of FIG. I have to.

  In the high frequency mode, the access time Tac1 of the flash memory 10 is close to 9 ns with respect to the clock cycle of 10 ns, and it takes 10 ns or more in total when including the path delay from the flash memory 10 to the flip-flop 23 in the CPU 20. For this reason, in order to read the read data Data1 from the flash memory 10 into the flip-flop 23 without waiting, the clock CLK4 input to the flip-flop 23 must be delayed by about 4 ns from the clock CLK1 input to the flash memory 10. I must.

  Therefore, in the high frequency mode, the clock path 51 with a large delay is selected by the control signal CS2 at the H level. The clock CLK2 that has passed through the large delay clock path 51 is delayed by a delay time Td2 (from time t1 to time t3) corresponding to the delay circuit 56 from the clock CLK1 input to the flash memory 10. The clock CLK4 input to the flip-flop 23 has substantially the same phase as the clock CLK2 that has passed through the clock path 51 with a large delay. Since the unselected clock path 52 is gated by the first stage gating cell 54, the clock CLK3 does not toggle and shows the L level. As a result, the read data Data1 is taken into the flip-flop 23 when about 13 ns have elapsed from time t1 when the address Addr1 was input to the flash memory 10 (time t8).

[effect]
As described above, the semiconductor device 1 according to the first embodiment is configured such that the clock path 51 with a large delay and the clock path 52 with a small delay can be selected. In the high frequency mode in which the semiconductor device 1 is operated at the upper limit of the operating frequency, by selecting the clock path 51 with a large delay, the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23 in the CPU 20 are selected. Add phase difference. As a result, the CPU 20 can read data from the flash memory 10 without waiting.

  On the other hand, when the semiconductor device 1 is operated in the low-frequency mode in which the clock frequency is lowered to reduce power consumption, the clock CLK1 supplied to the flash memory 10 and the clock supplied to the flip-flop 23 in the CPU 20 There is no need to add a phase difference to CLK4. In this case, the clock path 52 with a small delay is selected in order to reduce power consumption.

  When the clock path 51 with a large delay is selected, each buffer 55 constituting the delay circuit 56 repeats the toggle operation, so that the power consumption increases. By selecting the small delay clock path 52 by the gating cells 53 and 54 in the low frequency mode as described above, an L level signal is input to the delay circuit 56 provided in the large delay clock path 51, The output of each buffer 55 is fixed at H level or L level. As a result, since the delay circuit 56 does not perform a toggle operation, power consumption can be reduced.

  The switching between the high frequency mode and the low frequency mode and the selection of the clock paths 51 and 52 can be easily performed by setting the values of the control registers 31 and 32 from the CPU 20.

<Embodiment 2>
[Configuration of Semiconductor Device 2]
FIG. 4 is a block diagram showing a configuration of the semiconductor device 2 according to the second embodiment of the present invention.

  The semiconductor device 2 of FIG. 4 differs from the semiconductor device 1 of FIG. 1 in that it includes a control register 33 for controlling a wait cycle instead of the control register 31 for switching the clock frequency. In the case of FIG. 4, the clock generation circuit 40 is fixed to the high frequency mode.

  The semiconductor device 2 of FIG. 4 further includes a flip-flop 23A with a write enable (WE) terminal instead of the flip-flop 23 provided in the CPU 20 of FIG. Different from the semiconductor device 1.

  The control register 33 for controlling the wait cycle is connected to the flash memory 10 and the bus interface 21A in the CPU 20A. The control register 33 can be read and written by the CPU 20A. When reading data from the flash memory 10, a predetermined number of wait cycles corresponding to the set value of the control register 33 are inserted. More specifically, the timing at which the WE signal output from the bus interface 21A to the WE terminal of the flip-flop 23A is activated (becomes H level) changes according to the set value of the control register 33. The timing at which the flip-flop 23 captures data is controlled by the timing at which the WE signal is activated.

  Hereinafter, a case where the CPU 20A reads data from the flash memory 10 without waiting is referred to as a high-speed reading mode, and a case where the CPU 20A reads data from the flash memory 10 after a predetermined number of wait cycles has been referred to as a low-speed reading mode. In the second embodiment, CPU 20A is in the high-speed reading mode when control signal CS3 output from control register 33 is at the H level, and CPU 20A is in the low-speed reading mode when control signal CS3 is at the L level. .

  In the high-speed reading mode, it is necessary to give a phase difference between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20A, as in the high-frequency mode of the first embodiment. For this reason, the clock path 51 with a large delay is selected by setting the control register 32 to the H level.

  In the low-speed reading mode, as in the low-frequency mode of the first embodiment, it is not necessary to make a phase difference between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20A. . Therefore, in order to reduce power consumption, the clock path 52 with a small delay is selected by setting the control register 32 to the L level.

  Other configurations in FIG. 4 are the same as those in FIG. 1, and therefore the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 5 is a circuit diagram showing a configuration example of the D flip-flop circuit with the write enable terminal of FIG. In the circuit example of FIG. 5A, a flip-flop 23A with a WE terminal includes a normal flip-flop 60 without a WE terminal and a selector 61. The selector 61 receives the output signal of the flip-flop 60 and the read data DT2 from the flash memory 10, and inputs one signal selected according to the WE signal to the data terminal D of the flip-flop 60. In the case of FIG. 5, the selector 61 outputs the read data DT2 when the WE signal is at the H level (“1”), and outputs the output signal of the flip-flop 60 when the WE signal is at the L level (“0”). Re-input to terminal D. The clock CLK4 is input to the clock terminal CK of the flip-flop 60, and the output signal of the flip-flop 60 is given to the logic circuit 24 in the subsequent stage.

  In the circuit example of FIG. 5B, a flip-flop 23A with a WE terminal includes a normal flip-flop 60 and an AND gate 62 without a WE terminal. Read data DT <b> 2 is input from the flash memory 10 to the data terminal D of the flip-flop 60. The WE signal and the clock CLK4 are input to the first and second input terminals of the AND gate 62. The output signal of the AND gate 62 is input to the clock terminal CK of the flip-flop 60. The output signal of the flip-flop 60 is given to the logic circuit 24 in the subsequent stage.

[Operation of Semiconductor Device 2]
FIG. 6 is a timing chart showing signal waveforms of respective parts of the semiconductor device 2 of FIG. 4 in the low-speed reading mode. In the timing chart of FIG. 6, the control signal CS3 output from the control register 33 for wait cycle control, the clock CLK1 for the flash memory 10, and the delay delay clock path 51 are input to the clock selector 58 in order from the top. Clock CLK2, the clock CLK3 input to the clock selector 58 through the clock path 52 with a small delay, the clock CLK4 input to the clock terminal CK of the flip-flop 23A, and input to the flash memory via the address bus. The voltage waveforms of the address signal, read data DT1 output from the flash memory 10 to the bus 11, write enable (WE) signal, and read data DT2 input to the data terminal D of the flip-flop 23A in the CPU 20 are shown.

  As an example, the clock frequency in the case of FIG. 6 is 100 MHz (period: 10 ns), which is the same as that in the high frequency mode of the first embodiment. In FIG. 6, time t1 to t6 and time t6 to t9 each correspond to one cycle. The flash memory access time Tac2 (from time t1 to time t21) in the low-speed read mode (control signal CS3 is at L level) is slightly longer than in the high-speed read mode (control signal CS3 is at H level). Specifically, in the case of FIG. 6, the access time Tac2 is about 12 ns. The path delay Td1 (from time t21 to time t22) when data is transferred from the flash memory 10 to the flip-flop 23 is set to about 4 ns as in the first embodiment.

  In the low-speed read mode in which a wait cycle is inserted when the CPU 20A reads data from the flash memory 10 (when the control signal CS3 is at L level), the clock CLK2 delayed in phase by the clock path 51 having a large delay is used. Even without this, the read data Data1 from the flash memory 10 can be taken into the flip-flop 23A. Therefore, the clock path 52 with a small delay is selected by the control signal CS2 at the L level. At this time, the clock CLK4 input to the flip-flop 23A of the CPU 20A has substantially the same phase as the clock CLK1 input to the flash memory 10 (a slight path delay from the clock selector 58 to the flip-flop 23A is added). The clock path 51 that is not selected is gated by the first stage gating cell 53, so that the clock CLK2 does not toggle and shows a certain logic level (ie, L level).

  The WE signal in the low-speed reading mode changes to the H level in response to the falling edge (time t23) of the clock CLK4 in the second cycle after the read address is input from the CPU 20A to the flash memory 10 (time t24). ). Thereafter, the WE signal changes to the L level in response to the falling edge (time t25) of the third period of the clock CLK4 (time t26). The flip-flop 23A takes in the read data Data1 from the flash memory 10 at time t10 when the clock CLK4 rises to H level during the active state in which the WE signal is at H level. As a result, the read data Data1 is taken into the flip-flop 23A at time t10 when about 20 ns have elapsed from time t1 when the address Addr1 was input to the flash memory 10.

  FIG. 7 is a timing chart showing signal waveforms of respective parts of the semiconductor device 2 in the case of the high-speed reading mode. FIG. 7 shows voltage waveforms at the same location as in FIG.

  The clock frequency in the case of FIG. 7 is 100 MHz (period 10 ns) as in the case of FIG. 6, and the period from time t1 to t6 and the period from time t6 to t9 correspond to one period. The flash memory access time Tac1 (from time t1 to time t5) in the high-speed read mode (the control signal CS3 is at H level) is about 9 ns, which is the same as in the first embodiment. The path delay Td1 (from time t5 to time t7) during the transmission of data from the flash memory 10 to the flip-flop 23 is about 4 ns as in the first embodiment.

  In the high-speed read mode in which data is read from the flash memory 10 to the CPU 20A without waiting (when the control signal CS3 is at the H level), it is necessary to use the clock CLK2 whose phase is delayed by the delay delay clock path 51. . The clock CLK2 is delayed from the clock CLK1 input to the flash memory 10 by a delay time Td2 (about 4 ns from time t1 to time t3) corresponding to the delay circuit 56. The clock CLK4 input to the flip-flop 23 has substantially the same phase as the clock CLK2 that has passed through the clock path 51 with a large delay. Since the unselected clock path 52 is gated by the first stage gating cell 54, the clock CLK3 does not toggle and shows the L level.

  In the high-speed reading mode, the WE signal changes to the H level in response to the falling edge (time t31) of the clock CLK4 in the first cycle after the reading address is input from the CPU 20A to the flash memory 10. Time t32). Thereafter, the WE signal changes to the L level in response to the falling edge (time t33) of the second period of the clock CLK4 (time t34). The flip-flop 23A takes in the read data Data1 from the flash memory 10 at time t8 when the clock CLK4 rises to H level during the active state in which the WE signal is at H level. As a result, the read data Data1 is taken into the flip-flop 23A when about 14 ns elapses from the time t1 when the address Addr1 is input to the flash memory 10.

[effect]
As described above, the semiconductor device 2 according to the second embodiment is configured such that the clock path 51 with a large delay and the clock path 52 with a small delay can be selected as in the case of the first embodiment. In the high-speed read mode in which the CPU 20A reads data from the flash memory 10 without waiting, the clock path 51 with a large delay is selected. The timing of data reading is adjusted by adding a phase difference between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20.

  On the other hand, when a wait cycle is inserted when the CPU 20A reads data from the flash memory 10, a phase difference is set between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20. There is no need. In this case, the power consumption is reduced by selecting the clock path 52 with a small delay so that the buffers 55 constituting the delay circuit 56 do not perform the toggle operation.

<Embodiment 3>
[Configuration of Semiconductor Device 3]
FIG. 8 is a block diagram showing a configuration of the semiconductor device 3 according to the third embodiment of the present invention.

  The semiconductor device 3 of FIG. 8 is a combination of the semiconductor device 1 of FIG. 1 and the semiconductor device 2 of FIG. That is, the control register group 30B of the semiconductor device 3 of FIG. 8 further includes a control register 31 for switching the operation mode of the clock generation circuit 40 to the low frequency mode or the high frequency mode. Different from the control register group 30A. As described in FIG. 1, the clock generation circuit 40 generates a clock having a higher frequency in the high frequency mode than in the low frequency mode. When the control signal CS1 output from the control register 31 is at the H level, the clock generation circuit 40 operates in the high frequency mode, and when the control signal CS1 is at the L level, the clock generation circuit 40 operates in the low frequency mode.

  Since the other points of FIG. 8 are the same as those of FIGS. 1 and 4, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Operation of Semiconductor Device 3]
The following four operation states can be considered according to the set values of the control registers 31 and 33.

(I) In the case of the high frequency mode and the high speed reading mode When the control register 31 is set to the H level and the control register 33 is set to the H level, the clock generation circuit 40 operates in the high frequency mode, and the CPU 20A operates in the high speed reading mode. Works with. In this case, since the CPU 20A takes in the read data from the flash memory 10 without waiting, it is necessary to make a phase difference between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20A. For this reason, the clock path 51 with a large delay is selected by setting the control register 32 to the H level. The voltage waveform of each part of the semiconductor device 3 is the same as that described with reference to FIG.

(Ii) In the case of the high frequency mode and the low speed reading mode When the control register 31 is set to the H level and the control register 33 is set to the L level, the clock generation circuit 40 operates in the high frequency mode, and the CPU 20A operates in the low speed reading mode. Works with. In this case, since the CPU 20A takes in the read data from the flash memory 10 after a predetermined wait cycle, a phase difference is set between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20A. There is no need. Therefore, in order to reduce power consumption, the clock path 52 with a small delay is selected by setting the control register 32 to the L level. The voltage waveform of each part of the semiconductor device 3 is the same as that described in FIG. 6, for example.

(Iii) Low-frequency mode and high-speed reading mode When the control register 31 is set to L level and the control register 33 is set to H level, the clock generation circuit 40 operates in the low-frequency mode, and the CPU 20A operates at high speed. Operates in read mode. In this case, the CPU 20A fetches the read data from the flash memory 10 with no wait but the operating frequency is slow, so that the phase difference between the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20A is made. There is no need to turn it on. Therefore, in order to reduce power consumption, the clock path 52 with a small delay is selected by setting the control register 32 to the L level. The voltage waveform of each part of the semiconductor device 3 is the same as that described with reference to FIG.

(Iv) Low frequency mode and low speed reading mode When the control register 31 is set to L level and the control register 33 is set to L level, the clock generation circuit 40 operates in the low frequency mode, and the CPU 20A operates at low speed. Operates in read mode. In this case, the CPU 20A takes in the read data from the flash memory 10 after the elapse of a predetermined wait cycle, and the operating frequency is also slow. Therefore, the clock CLK1 supplied to the flash memory 10 and the clock CLK4 supplied to the flip-flop 23A in the CPU 20A. There is no need to add a phase difference between the two. Therefore, in order to reduce power consumption, the clock path 52 with a small delay is selected by setting the control register 32 to the L level.

<Embodiment 4>
[Configuration and Operation of Semiconductor Device 4]
FIG. 9 is a block diagram showing a configuration of the semiconductor device 4 according to the fourth embodiment of the present invention.

  The semiconductor device 4 of FIG. 9 is different from the semiconductor device 3 of FIG. 8 in that it includes power switches 70A and 70B corresponding to the phase adjusters 50A and 50B, respectively. Each of power switches 70A and 70B is provided in a power supply voltage supply path from power supply node VDD to gating cell 53 and each buffer 55. The power switches 70A and 70B are turned on / off by a control signal CS2 output from the control register 32. When the control signal CS2 is at the H level, the power switches 70A and 70B are turned on, and when the control signal CS2 is at the L level, the power switches 70A and 70B are turned off.

  Note that power switches 70A and 70B having the same configuration as in FIG. 9 can also be provided in the semiconductor device 1 of the first embodiment described in FIG. 1 and the semiconductor device 2 of the second embodiment described in FIG. The other points in FIG. 9 are the same as those in FIGS. 1, 4 and 8, and the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[effect]
According to the above configuration, when the low delay clock path 52 is selected by the control signal CS2, the power to the gating cell 53 and the delay circuit 56 provided in the unselected large delay clock path 52 is Blocked. Therefore, in addition to the effects described in the first to third embodiments, the power consumption can be further reduced.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 2, 3, 4 Semiconductor device, 10 flash memory, 11 bus, 12, 13, 23, 23A flip-flop, 21A bus interface, 30, 30A, 30B control register group, 31, 32, 33 control register, 40 clocks Generation circuit, 50A, 50B phase adjustment unit, 51 first clock path, 52 second clock path, 53, 54 clock gating cell, 55 buffer, 56 delay circuit, 58 clock selector, 70A, 70B power switch, CLK1 , CLK2, CLK3, CLK4 clock, CS1-CS3 control signal.

Claims (6)

A clock generation circuit having a low frequency mode and a high frequency mode as operation modes, and generating a clock having a higher frequency than in the low frequency mode in the high frequency mode;
A non-volatile memory that operates based on a clock generated by the clock generation circuit;
A data bus connected to the non-volatile memory;
A central processing unit that operates based on a clock generated by the clock generation circuit and acquires read data read from the nonvolatile memory via the data bus;
A clock delay unit provided in a clock supply path from the clock generation circuit to the central processing unit,
The clock delay unit includes a first path through cascaded multiple stages of buffers and a second path that bypasses the multiple stages of buffers, and in the high frequency mode, a clock from the clock generation circuit To the central processing unit via the first path,
The clock delay unit supplies a clock from the clock generation circuit to the central processing unit via the second path in the low frequency mode. The clock delay unit is
A first logic gate provided in the first stage of the first path;
A second logic gate provided at the first stage of the second path,
In the high-frequency mode, the first logic gate passes a clock from the clock generation circuit, and the second logic gate outputs a signal of a certain logic level,
2. The semiconductor device according to claim 1, wherein in the low frequency mode, the second logic gate passes a clock from the clock generation circuit, and the first logic gate outputs a signal of a constant logic level. The semiconductor device further includes a power switch provided in a power supply voltage supply path to the plurality of stages of buffers and the first logic gate,
3. The semiconductor device according to claim 2, wherein the power switch is turned off in the low frequency mode. The semiconductor device further includes first and second registers rewritable from the central processing unit,
The clock generation circuit is switched to the low frequency mode or the high frequency mode according to the logic level of the first control signal output from the first register,
The first and second logic gates pass the clock from the clock generation circuit or have a certain logic level according to the logic level of the second control signal output from the second register. The semiconductor device according to claim 2, wherein whether to output a signal is switched. A semiconductor device,
A clock generation circuit;
A non-volatile memory that operates based on a clock generated by the clock generation circuit;
A data bus connected to the non-volatile memory;
A central processing unit that operates based on a clock generated by the clock generation circuit and acquires read data read from the nonvolatile memory via the data bus;
The central processing unit has a low-speed read mode for acquiring the read data after elapse of a predetermined wait cycle, and a high-speed read mode for acquiring the read data with no wait,
The semiconductor device further includes a clock delay unit provided in a clock supply path from the clock generation circuit to the central processing unit,
The clock delay unit includes a first path through a plurality of cascaded buffers and a second path that bypasses the plurality of buffers, and from the clock generation circuit in the high-speed read mode Supplying a clock to the central processing unit via the first path;
The clock delay unit supplies a clock from the clock generation circuit to the central processing unit via the second path in the low-speed reading mode. A semiconductor device,
A clock generation circuit having a low frequency mode and a high frequency mode as operation modes, and generating a clock having a higher frequency than in the low frequency mode in the high frequency mode;
A non-volatile memory that operates based on a clock generated by the clock generation circuit;
A data bus connected to the non-volatile memory;
A central processing unit that operates based on a clock generated by the clock generation circuit and acquires read data read from the nonvolatile memory via the data bus;
The central processing unit has a low-speed read mode for acquiring the read data after elapse of a predetermined wait cycle, and a high-speed read mode for acquiring the read data with no wait,
The semiconductor device further includes a clock delay unit provided in a clock supply path from the clock generation circuit to the central processing unit,
The clock delay unit includes a first path through a plurality of cascaded buffers and a second path that bypasses the plurality of buffers, and in the high-frequency mode and the high-speed read mode, Supplying a clock from a clock generation circuit to the central processing unit via the first path;
The clock delay unit supplies a clock from the clock generation circuit to the central processing unit via the second path in the low-frequency mode or the low-speed reading mode.

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