JP2013080386A - Information processing device and address management method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device capable of reducing reinspection when a program is changed.SOLUTION: An information processing device 100 comprises: program storage means 103 which stores a program before a change and a program after the change; changed part extraction means 141 which extracts a changed part of the programs before and after the change; address determination means 142 which determines virtual addresses of the changed part from the beginning of instructions, determines physical addresses of the changed part when the program before the change and the changed part are allocated in the storage means, while holding addresses of the program before the change, and generates an intermediate table in which the physical addresses are associated with the virtual addresses; and address translation table generation means 143 which compares each instruction of the program after the change with each instruction of the program before the change for each address from the beginning, and generates an address translation table in which the physical addresses and the virtual addresses obtained from the intermediate table are registered, when different instructions are described.

Description

  The present invention relates to an information processing apparatus that creates an executable file.

  A high-level language such as C language requires a translation process for converting a source code coded by a developer into an object code that can be processed by the computer in order for the computer to execute the program.

  FIG. 1 shows an example of a general translation processing procedure. The compiler performs processing such as lexical analysis (keyword and variable extraction), syntax analysis (analysis according to grammar), semantic analysis (executable analysis), and code generation (object code generation) on the source code. The linker identifies and combines other files and libraries referenced by the object code. As a result, an executable file executable by the computer is generated. In the case of embedded software, the executable file is stored in the ROM and is generally called a program.

  By the way, in software development, it is often performed to correct or add processing contents to a program that has been once developed and stored in a ROM. When the developer changes the source code, it is necessary to perform all of the above translation processing on the entire source code even if the change is partly (for example, even with one instruction).

  FIG. 2 is an example of a diagram for explaining the influence of the change of the source code on the execution file. The program before the change has three functions A to C and is stored at the address shown in the ROM. When the developer makes a change to add three instructions to the function A, the change in the function A is reflected in the executable file generated by the translation process, so a part of the ROM address where the function A is stored Not only the address of all instructions after the changed part is changed. In the figure, the addresses of the instructions of functions B and C that do not change the source code, including three POP instructions, are all changed.

  When the relationship between the instruction and the address is changed, the timing of accessing the memory when the CPU executes the instruction A may change even when the same instruction A is executed. If the memory access timing changes, there is no denying the possibility of problems that did not occur until then. For this reason, in software development, the entire program is re-inspected even with some changes to the source code. In-vehicle software is said to account for 30 to 70% of the cost of development of the program, and the cost of the re-inspection accompanying the program change is greatly increased.

  A technique for suppressing the rearrangement of instructions accompanying the change of the source code has also been proposed (see, for example, Patent Document 1). Patent Document 1 discloses a language processing device in which functions that are not changed are arranged at original addresses.

FIG. 3 is an example of a diagram illustrating the rearrangement of the program of Patent Document 1. It is assumed that, for example, the following code is added to the executable file by changing the source code.
POP edi
POP exi
As a result, the addresses of these and subsequent instructions are changed. However, the language processing apparatus of Patent Document 1 does not change the address of the instructions of functions B and C that are not changed. For this reason, the instruction whose address is changed can be limited to the last instruction of the function A from “POP edi” of the function A. Since the size of the function A is increased due to the change, an instruction that is difficult to be arranged up to the address immediately before the function B is arranged at an address after the function C. As described above, in the cited document 1, the address change can be minimized by storing the program in units of functions.

JP 2002-108625 A

  However, in Patent Document 1, since there are address changes for some instructions of the changed function A, there is a problem that an instruction whose address has changed needs to be rechecked. That is, since the re-inspection is necessary from “POP edi” of the function A in FIG. 3 to the last instruction of the function A, the cost reduction effect is not sufficient.

  In view of the above problems, an object of the present invention is to provide an information processing apparatus that can further reduce re-examination when changing a program.

  The present invention includes a program storage means for storing a program before change and a program after change, a change part extraction means for extracting a change part of the program before change and the program after change, and the changed part including the change part. The virtual address when each instruction of the program is arranged in the external storage means is determined, and the change when the program before change and the change unit are arranged in the storage means while fixing the address of the program before change Address determining means for determining the physical address of each part and creating an intermediate table in which the physical address and the relative address are associated with each other, each instruction of the changed program, and each instruction of the changed program from the head Compared every time, if the same instruction is described, register and associate those addresses, and if different instructions are described, Serial to provide an intermediate table of the physical address and the relative address and the address conversion table creating means for creating an address conversion table registering taken out, the information processing apparatus having a.

  It is possible to provide an information processing apparatus that can further reduce re-examination at the time of program change.

It is a figure which shows an example of the procedure of a general translation process. It is an example of the figure explaining the influence which the change of a source code has on an executable file. FIG. 11 is an example of a diagram for explaining rearrangement of a program in Patent Literature 1; It is an example of the figure explaining arrangement | positioning of the program before and behind a change. It is an example of the figure which shows typically the information processing apparatus for development, and the program delivery system which has the vehicle which runs the developed program. FIG. 2 is an example of a hardware configuration diagram of a development information processing apparatus and a microcomputer. It is an example of a functional block diagram of a development program. It is an example of the flowchart figure which shows the procedure in which a linker produces | generates an address conversion table. It is an example of the figure explaining the comparison of the program before a change, and a program after a change. It is an example of the figure explaining preparation of an address translation table. It is a figure which shows an example of the functional block of a microcomputer. It is an example of the flowchart figure which shows the procedure in which a microcomputer converts an address and reads a program. (Example 2) which is an example of the flowchart figure which shows the procedure in which a linker produces | generates an address conversion table. It is an example of the figure explaining the comparison of the program before a change, and a program after a change (Example 2). FIG. 10 is an example of a diagram illustrating creation of an address conversion table (second embodiment). FIG. 10 is an example of a diagram illustrating comparison between a pre-change program and a post-change program (Example 3); FIG. 10 is an example of a diagram illustrating creation of an address conversion table (Example 3);

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

FIG. 4 is an example of a diagram for explaining the arrangement of programs before and after the change. Suppose that only the function A has a change that causes the following code to be added.
POP edi
POP esi
POP ebx
(i) Even if any change occurs in the execution file, the linker of the present embodiment does not change the relationship between the instruction and the address in the execution file before the change. As shown in the figure, not only the functions B and C that do not change, but also the function A that has been changed is arranged at the same address in the same ROM as before the change.

Instructions that do not exist in the original executable file are arranged (stored) in a different area from the functions A to C in the same ROM.
(ii) On the other hand, as it is, it becomes unclear which instruction of the function A should execute the above three instructions. For this reason, the linker generates an address conversion table that associates the addresses of the instructions in the execution file before the change with the addresses of the instructions in the execution file after the change.

  When the linker generates object code, it combines additional instructions into one executable file without distinguishing them from other instructions. Therefore, the relative address of the additional instruction is known based on the start address of the executable file (hereinafter, the arrangement of the modified executable file generated by the linker is assumed to be written in the ROM. This is called memory allocation, and the address of virtual memory allocation is called virtual allocation address). The changed program is executed in the order of virtual memory allocation. Therefore, the virtual memory allocation instruction and the instruction stored at the same address before the change are compared, and the instruction that does not match is converted by associating the virtual memory allocation instruction with the physical address of the instruction outside the area. A table can be generated.

  (iii) When the CPU executes an execution file after change stored in the ROM (execution file without change + additional instructions outside the area), the program counter displays the next in the ROM address order. The addresses of instructions to be read are sequentially stored. However, even if the CPU simply executes the instructions in order, the added three instructions cannot be executed. Therefore, the program counter outputs the address of the next instruction to be read to the address conversion unit.

  The address conversion unit refers to the address conversion table and outputs the physical address associated with the virtual memory allocation address to the address controller using the address of the instruction to be read as the address of the virtual memory allocation (to the physical address of the address of the instruction to be read) Convert). Therefore, when the CPU executes the added instruction, it accesses the area outside the functions A to C as necessary.

  As described above, even if only the additional instruction is stored outside the area without changing the addresses of the functions A to C, the CPU can execute the changed execution file without any inconvenience. In the software inspection process, since the address of the functions A to C is not changed, the developer only needs to execute a test for accessing an instruction outside the area. Therefore, the re-inspection process when changing the program can be greatly reduced, and the software development cost can be greatly reduced.

[Configuration example]
FIG. 5 is an example of a diagram schematically illustrating a development information processing apparatus according to the present embodiment and a program distribution system 500 having a vehicle on which a microcomputer 200 that executes the developed program is mounted. The development information processing apparatus 100 is a computer such as a PC (Personal Computer) or a workstation that executes each process of general software development. The program for which the inspection process has been completed is stored in the ROM of the microcomputer 200 when the vehicle 300 is shipped. When the program is changed after the vehicle 300 is shipped, a service engineer such as a dealer writes the changed program in the ROM of the microcomputer 200 of the vehicle 300 using a tool. Further, when the program is changed after the vehicle 300 is shipped, if a developer or the like stores the program in the server 400, a communication device (DCM: Data Communication Module) can be downloaded from the server 400. The microcomputer 200 mounted on the vehicle writes the downloaded program into the ROM of the vehicle 300. The program developed by the development information processing apparatus 100 may be stored in the ROM in any manner, and the execution method after being stored is the same.

  FIG. 6A shows an example of a hardware configuration diagram of the development information processing apparatus 100. The development information processing apparatus 100 includes a CPU 101, ROM 102, RAM 103, HDD 104, network I / F 105, graphic board 106, keyboard 107, mouse 108, media drive 109, and DVD-ROM drive 110. The CPU 101 executes the development program 130 stored in the HDD 104 to control the overall operation of the development information processing apparatus 100. The ROM 102 stores IPL (Initial Program Loader) and static data, and is different from the in-vehicle ROM. The RAM 103 is used as a work area when the CPU 101 executes the development program 130.

  The HDD 104 stores a development program 130 and an OS executed by the CPU 101. The network I / F 105 is, for example, an Ethernet (registered trademark) card for connecting to a network, and mainly provides layer 1 and 2 processing. Layer 3 and higher processing is provided by a TCP / IP protocol stack and a communication program (not shown) included in the OS.

  The graphic board 106 interprets a drawing command written in the video RAM by the CPU 101 and displays various information such as a window, a menu, a cursor, a character, or an image on the display 120. The keyboard 107 includes a plurality of keys for characters, numerical values, various instructions, etc., and accepts user operations and notifies the CPU 101 of them. Similarly, the mouse 108 accepts user operations such as movement of a cursor, selection of a processing target such as a menu, and processing content. The media drive 109 controls reading or writing (storage) of data with respect to a recording medium 111 such as a flash memory. The DVD-ROM drive 110 controls reading or writing of various data with respect to an optical medium 112 such as a CD-RW or DVD-RW as an example of a removable recording medium. In addition, a bus line 113 such as an address bus or a data bus for electrically connecting the above-described components is provided.

  The development program 130 is a file in an installable or executable format, and is recorded and distributed on a computer-readable recording medium 111 or optical medium 112. Further, the development program 130 may be distributed to the development information processing apparatus 100 in a file that can be installed or executed from a server (not shown).

  FIG. 6B is an example of a hardware configuration diagram of the microcomputer 200 mounted on the vehicle 300. The microcomputer 200 is assumed to be mounted on an ECU (Electronic Control Unit), but its application is not limited to a vehicle. There are various types of ECUs mounted on the vehicle, such as an engine ECU, a brake ECU, a body ECU, a navigation ECU (AV / information processing ECU), and a gateway ECU, depending on main functions. The microcomputer 200 of the present embodiment can be mounted without being affected by the difference in ECU functions. Further, the microcomputer 200 may be mounted on an ECU in which a plurality of functions are integrated into one.

  The microcomputer 200 includes a CPU 11, a ROM 12, an INTC 13, a RAM 14, a DMAC 15, and an I / O bridge 16 connected to a bus, and an ADC 17 and a CAN controller 18 are connected to the I / O bridge 16.

  The CPU 11 has a general configuration (for example, an arithmetic unit such as an ALU, an instruction buffer, an instruction decoder, a register set, etc.) including one or more cores and including a program counter 201 and an address conversion unit 202. . The address conversion unit 202 may be disposed outside the CPU 11.

  The ROM 12 is a non-volatile memory such as a flash memory, and stores a program 210 executed by the CPU 11 and static parameters. An address controller 203 is disposed in the ROM 12. The address controller 203 interprets the address of the instruction output from the address conversion unit 202 and outputs it to the ROM 12. The instruction at the designated address is read from the ROM 12 and stored in the instruction buffer of the CPU 11.

  The INTC 13 arbitrates based on the priority of the peripheral device and notifies the CPU 11 of the interrupt request input from the peripheral device via the IRQ or other interrupt terminal. As a result, the CPU 11 reads an instruction at an address determined according to the interrupted peripheral device from the ROM 12 and executes the process.

  The RAM 14 is a work area for the CPU 11 to execute the program 210. The CPU 11 reads the program 210 from the ROM 12, and reads the data from the RAM 14 via the data bus if necessary and executes the program 210. The DMAC 15 transmits data from the RAM 14 to the peripheral device via the I / O bridge 16 according to an instruction from the CPU 11. In response to an instruction from the CPU 11 interrupted by the peripheral device, data is received from the peripheral device via the I / O bridge 16 and written to the RAM 14.

  The I / O bridge 16 is a multiplexer or a bridge circuit, and is connected to an ADC and a CAN controller for each channel, and transmits / receives data to / from these peripheral devices. An ADC (analog to digital converter) 17 converts an analog signal detected by the sensor into a digital signal. The ADC 17 also notifies the CPU 11 of the end of conversion via the INTC 13. The CAN controller 18 is a communication device for communicating with other ECUs connected via an in-vehicle network. When receiving a communication data transmission request from the CPU 11, the CAN controller 18 stores the ID and data in each field of the frame and outputs them to the CAN bus. Further, when the CAN controller 18 detects the communication data of the ID to be received, it captures it and interrupts it to notify the CPU 11.

<Functional blocks of information processing device for development>
FIG. 7 shows an example of a functional block diagram of the development program 130. In the present embodiment, the linker 140 of the development program 130 has some new functions, but these functions may be implemented in the development program 130 as functions different from the linker 140.

The linker 140 includes a changing unit specifying unit 141, a changing unit address determining unit 142, and an address conversion table creating unit 143. In order to cause the linker 140 to activate these functions, the developer specifies linker options at the time of linking. For example, by specifying the linker option as follows and setting XXX in accordance with the specifications of the linker 140, various options such as creation of debug information and creation of a program database file can be designated.
LINK / XXX
The linker 140 generates an execution file (program 210) by combining the object code generated from the source code changed by the developer. In the figure, this is the changed program. The HDD 104 of the development information processing apparatus 100 stores a post-change program and a pre-change program.

  In the linker 140 according to the present embodiment, when a changer specific linker option is designated, the changer specifying unit 141 specifies the change part of the pre-change program and the post-change program. The linker 140 is designated with the start address in the ROM 12 of the program 210 along with the linker option specific to the change section. Therefore, the address of each instruction of the program 210 in the ROM 12 is known to the linker 140.

  The change part specifying part 141 specifies the change part of the pre-change program and the post-change program. The changing unit address determining unit 142 determines a physical address in the ROM 12 of the changing unit. The address conversion table creation unit 143 generates an address conversion table. These processes will be described in detail later.

[Create address translation table]
FIG. 8 is an example of a flowchart illustrating a procedure for the linker 140 to generate an address conversion table. Hereinafter, S10 to S30 will be described in order.
<Extraction of S10 change part>
FIG. 9A is an example of a diagram illustrating a comparison between the pre-change program and the post-change program. In FIG. 9A, three instructions “POP edi”, “POP esi”, and “POP ebx” are added.
a1. First, the changing unit specifying unit 141 obtains a virtual placement address when the top of the changed program is placed at the top address in the ROM 12. The same applies to the pre-change program.
a2. Next, the change part specifying part 141 reads the instructions of the program before change in the order of addresses, and determines whether or not the same instruction is registered in the program after change. That is, the changing unit specifying unit 141 compares all instructions of the post-change program in the order of addresses for one instruction of the pre-change program.
a3. The changing unit specifying unit 141 extracts the remainder obtained by removing the instructions in both the pre-change program and the post-change program from the post-change program as the changing unit. The change unit specifying unit 141 takes out all changed instructions, with the virtual placement address of the added instruction and the instruction of the changed program as one set.

<S20 Determination of Physical Address of Change Unit>
FIG. 9B is an example of a diagram illustrating the determination of the physical address of the execution file changing unit.
b1. The non-change portion of the post-change program is stored at the same address of the ROM 12 as that of the pre-change program. For this reason, the address of the non-change part in the ROM 12 is fixed and known. The changing unit address determining unit 142 determines a physical address when the changing unit is arranged with the address next to the final address of the non-changed unit or an address slightly apart from the final address as the head. In FIG. 9B, the instruction of the changing unit is arranged from 0xFF00.
b2. The changing unit address determining unit 142 stores the virtual arrangement address of the instruction of the changing unit and the physical address in association with each other.

<S30 Address conversion table creation>
FIG. 10 is an example for explaining the creation of the address conversion table.
The address translation table creation unit 143 creates an address translation table using the virtual placement address and physical address of the changed instruction identified by the modification unit identification unit 141.
c1. The ROM 12 stores the pre-change program (non-change part of the post-change program) and the added part. For this reason, the address conversion table creating unit 143 sequentially compares the instruction at the address of the virtual memory arrangement and the instruction at the physical address of the program before change, and changes the address when there are different instructions at the same address. In the figure, there are different instructions at the same address in the addresses from 0xF0A3 to 0xF0BF (the end of the function A) of the virtual arrangement addresses. Further, since the instructions are added to the post-change program, instructions from 0xF0BF to 0xF0C2 of the virtual allocation address are also converted.
c2. When there is the same instruction at the same physical address as the virtual placement address, the address translation table creation unit 143 creates an address translation table by associating the virtual placement address of the pre-change program with the physical address of the post-change program. That is, the same addresses are associated with each other.
c3. Of the instructions having the same physical address as the virtual arrangement address, the instruction arranged outside the area associates the physical address outside the area. Therefore, the address conversion table creating unit 143 takes out the virtual arrangement address and physical address extracted in b.2 and writes them in the address conversion table.
c4. Of the instructions with the same physical address as the virtual allocation address, the remaining instructions should be in the area of functions A to C. Therefore, the instructions of the program before the change are searched one by one at the virtual allocation address. The address of the instruction of the program before change is associated with the virtual arrangement address. The address conversion table is created as described above.

<Functional block of vehicle microcomputer>
FIG. 11 is a diagram illustrating an example of functional blocks of the microcomputer 200. The non-change part of the program 210 is stored in the same physical address of the ROM 12 as the pre-change program, and the change part is stored in the physical address of the ROM 12 determined by the change part address determination part 142.

  In principle, the program counter 201 designates the address of an instruction in order from the top address of the ROM 12, and the CPU 11 reads the instruction from the ROM 12. However, since the execution file before the change is stored in the ROM 12, the CPU 11 must read the instruction from an address outside the area where the instruction after the change is stored when the CPU 11 accesses the change unit.

  Therefore, the address conversion unit 202 reads the physical address associated with the virtual arrangement address using the address determined by the program counter 201 as the virtual arrangement address of the address conversion table. For example, when the address determined by the program counter 201 is 0xF000, 0xF000 is read from the address conversion table. Even when the addresses determined by the program counter 201 are 0xF0A0 to 0xF0A2, 0xF0A0 to 0xF0A2 are read from the address conversion table.

  On the other hand, when the address determined by the program counter 201 is 0xF0A3, 0xFF00 is read from the address conversion table. Similarly, 0xFF01 is read from the address conversion table for 0xF0A4, and address conversion is performed for 0xF0A5. 0xFF02 is read from the table. The address of the instruction read by the CPU 11 can be changed by the address conversion table.

  The address conversion table may be stored in the address conversion unit 202, or may be stored in the ROM 12, and the program 210 may be read from the ROM 12 and read into the register of the address conversion unit 202 when the microcomputer 200 is activated. .

The address controller 203 outputs the Row address among the physical addresses output by the address conversion unit 202 to the address line (Address) of the instruction bus to the Row controller. The Row controller decodes the Row address and activates the Row line.
Further, the address controller 203 outputs the Column address to the Column controller among the physical addresses output by the address conversion unit 202 to the address line (Address) of the instruction bus. The Column controller decodes the Column address and activates the Column line. Data in the area of the ROM 12 in which both the Row line / Column line are active is output to the data line and taken into the CPU 11.

[Test process]
The ROM 12 stores an instruction for the non-change unit and an additional instruction shown in FIG. The developer creates a test pattern in which the CPU 11 accesses the 0xFF00 to 0xFF02 in which the instruction of the change unit is stored, or performs a test, or creates a model in which the CPU 11 accesses the 0xFF00 to 0xFF02 using, for example, SMV code An inspection process such as an inspection is performed. Therefore, in this embodiment, the inspection process can be greatly reduced as compared with the case where the entire program 210 is tested.

[Operation procedure of microcomputer]
FIG. 12 is an example of a flowchart illustrating a procedure in which the microcomputer 200 converts the address and reads the program 210. The flowchart of FIG. 12 is repeatedly executed while the microcomputer 200 is activated.

  The address conversion unit 202 acquires the address of the instruction to be read from the program counter 201 (S110).

  The address conversion unit 202 reads the physical address associated with the address acquired from the program counter 201 with reference to the address conversion table (S120).

  The address conversion unit 202 compares the address acquired from the program counter 201 with the physical address read from the address conversion table (S130).

  If the two do not match (S130 No), the address conversion unit 202 outputs the physical address read from the address conversion table to the address controller (S170).

  If the two match (S130 Yes), the address conversion unit 202 outputs the address acquired from the program counter 201 to the address controller (S140).

  The address controller 203 supplies the instruction at the designated address to the CPU 11 (S150).

  When the CPU 11 executes the instruction, the program counter 201 increments the address by one (S160). By repeating such processing, the changed program 210 including the changing unit is executed.

  According to the development information processing apparatus 100 or the on-board microcomputer 200 according to the present embodiment, even if the program is changed, the re-inspection process when the program is changed can be greatly reduced by storing the program at the same address as before the change. Software development costs can be greatly reduced.

  In the first embodiment, the case where an instruction is added by a change has been described. However, a part of the instruction may be deleted by the change. In the present embodiment, the development information processing apparatus 100 when an instruction is deleted due to a change will be described.

  FIG. 13 is an example of a flowchart illustrating a procedure for the linker 140 to generate an address conversion table. In FIG. 13, S20 is unnecessary compared with the first embodiment.

<Extract S10 change part>
FIG. 14 is an example of a diagram illustrating a comparison between a pre-change program and a post-change program. In FIG. 14, “xor esp eax” is deleted from the pre-change program.
a1. First, the changing unit specifying unit 141 obtains a virtual placement address when the top of the changed program is placed at the top address in the ROM 12. The same applies to the pre-change program.
a2. Next, the change part specifying part 141 reads the instructions of the program before change in the order of addresses, and determines whether or not the same instruction is registered in the program after change. That is, the changing unit specifying unit 141 compares all instructions of the post-change program in the order of addresses for one instruction of the pre-change program.
a3. In the first embodiment, instructions in the post-change program but not in the pre-change program are extracted, but in this embodiment, instructions that are in the pre-change program but not in the post-change program are extracted. The changing unit specifying unit 141 takes out all changed instructions with a set of the virtual arrangement address of the changed (deleted) instruction and the information “no instruction” indicating that there is no instruction.

  In the present embodiment, there is no instruction change part due to the addition. Therefore, the changing unit address determining unit 142 does not need to determine a physical address.

<S30 Address conversion table creation>
Next, the address conversion table creation unit 143 generates an address conversion table.
FIG. 15 is an example of a diagram illustrating creation of an address conversion table.

If there are no added instructions, the program 210 stored in the ROM 12 will not change at all before and after the change. However, in order to reflect the change of the source code, it is necessary to avoid that the CPU 11 executes the instruction deleted by the change.
c1. The address conversion table creation unit 143 compares the instruction at the address in the virtual memory arrangement with the instruction at the physical address in the program before change, and changes the address when there are different instructions at the same address. In the figure, there are different instructions at the same address from 0xF0A2 to 0xF0BE (end of function A) of the virtual arrangement addresses.
c2. When there is the same instruction at the same physical address as the virtual placement address, the address conversion table creation unit 143 creates an address conversion table by associating the address of the program before change with the address of the program after change.
c3. Of the instructions having the same physical address as the virtual arrangement address, the instruction “no instruction” does not need to be associated with the virtual arrangement address. However, it is necessary to associate another address in the ROM 12 with the virtual arrangement address. Therefore, the address conversion table creating unit 143 searches the pre-change program for the same instruction as the “no instruction” instruction, and associates the instruction of the pre-change program with the virtual arrangement address of the “no instruction” instruction.
c4. Of the instructions with the same physical address as the virtual allocation address, the remaining instructions should be in the area of functions A to C. Therefore, the instructions of the program before the change are searched one by one at the virtual allocation address. The address of the instruction of the program before change is associated with the virtual arrangement address. The address conversion table is created as described above.

  When some instructions are erased due to the change, the addresses of the instructions after erasure are blocked one by one, and the relationship between the instructions and the addresses is deviated. For this reason, it is necessary to redo the inspection process in most of the program 210. On the other hand, in this embodiment, since the execution file stored in the ROM 12 is not changed at all, the inspection process can be greatly reduced.

In the present embodiment, a development information processing apparatus 100 combining the first embodiment and the second embodiment will be described. What is necessary is just to extract a change part by the two aspects of Example 1 and 2, and produce | generate an address conversion table.
Since the procedure of this embodiment is the same as that of the first embodiment, the flowchart is omitted.

<Extraction of S10 change part>
FIG. 16 is an example of a diagram illustrating a comparison between a pre-change program and a post-change program. In FIG. 16, three instructions “POP edi”, “POP esi”, and “POP ebx” are added, and “xor esp eax” is deleted from the pre-change program.
a1. First, the changing unit specifying unit 141 obtains a virtual placement address when the top of the changed program is placed at the top address in the ROM 12. The same applies to the pre-change program.
a2. Next, the change part specifying part 141 reads the instructions of the program before change in the order of addresses, and determines whether or not the same instruction is registered in the program after change. That is, the changing unit specifying unit 141 compares all instructions of the post-change program in the order of addresses for one instruction of the pre-change program.

  a3-1. As shown in FIG. 16A, the change unit identification unit 141 extracts instructions in the post-change program rather than the pre-change program. The changing unit specifying unit 141 takes out all changed instructions with the virtual placement address of the instruction of the changing unit and the instruction of the changed program as one set.

  a3-2. As shown in FIG. 16A, the change unit identification unit 141 extracts instructions that are in the pre-change program but not in the post-change program. The changing unit specifying unit 141 takes out all changed instructions with the virtual arrangement address of the instruction of the changing unit and the information “no instruction” indicating that there is no instruction as one set.

<S20 Determination of physical address>
As shown in FIG. 16B, the changing unit address determining unit 142 determines a physical address only for the changing unit obtained by the process of S3-1. The processing procedure is the same as in the first embodiment.
b1. The changing unit address determining unit 142 determines a physical address when the changing unit is arranged with the address next to the final address of the non-changed unit or an address slightly apart from the final address as the head. In FIG. 16, the instruction of the changing unit is arranged from 0xFF00.
b2. The changing unit address determining unit 142 stores the virtual arrangement address of the instruction of the changing unit and the physical address in association with each other.

<S30 Address conversion table creation>
FIG. 17 is an example of a diagram illustrating the creation of an address conversion table.
The address conversion table creating unit 143 generates an address conversion table using the changing unit, the virtual arrangement address, and the physical address specified by the changing unit specifying unit 141.
c1. The address conversion table creation unit 143 compares the instruction at the address in the virtual memory arrangement with the instruction at the physical address in the program before change, and changes the address when there are different instructions at the same address. In the figure, there are different instructions at the same address from 0xF0A2 to 0xF0BF (the end of the function A) of the virtual arrangement addresses. In addition, since the instructions are added to the post-change program, the virtual addresses 0xF0BF to 0xF0C are also targeted.
c2. When there is the same instruction at the same physical address as the virtual placement address, the address conversion table creation unit 143 creates an address conversion table by associating the address of the program before change with the address of the program after change.
c3. Of the instructions having the same physical address as the virtual arrangement address, the instruction arranged outside the area associates the physical address outside the area. Therefore, the address conversion table creating unit 143 takes out the virtual arrangement address and physical address extracted in b.2 and writes them in the address conversion table.

For the “no instruction” instruction, the same instruction as the instruction at the virtual placement address may be searched as in the second embodiment. However, in the illustrated example, the added instruction is described in the address of the instruction “no instruction”, and therefore, the correspondence between the virtual placement address and the physical address of the added instruction is prioritized.
c4. Of the instructions that differ between the virtual address and the same physical address, the remaining instructions should have the same instruction in the area. Therefore, the instruction before the change is searched for each instruction of the virtual address, and the instruction before the change. Is associated with the virtual arrangement address.

  As described above, the development information processing apparatus 100 according to the present embodiment creates the address conversion table regardless of whether an instruction is added or deleted, so that the program 210 before and after the change stored in the ROM 12 can be stored. There is no need to change the address. Therefore, the inspection process can be greatly reduced.

11 CPU
12 ROM
DESCRIPTION OF SYMBOLS 100 Information processing apparatus 130 Development program 140 Linker 141 Change part specific | specification part 142 Change part Address determination part 143 Address conversion table preparation part 200 Microcomputer 201 Program counter 202 Address conversion part 203 Address controller 210 Program 300 Vehicle 400 Server

Claims (5)

Program storage means for storing the program before the change and the program after the change;
Change part extraction means for extracting the change part of the program before the change and the program after the change,
While determining the virtual address when each instruction of the changed program including the changing unit is arranged in an external storage means,
While fixing the physical address of the program before the change, the physical address of the change unit when the program before the change and the change unit are arranged in the external storage unit is determined, and the virtual address of the change unit and the virtual address Address determining means for creating an intermediate table in which physical addresses are associated with each other;
Compare each instruction of the program after the change with each instruction of the program before the change for each address from the beginning, and if the same instruction is described, register those addresses in association with each other and describe a different instruction. An address translation table creating means for creating an address translation table in which the virtual address and the physical address of the intermediate table are registered in association with each other;
An information processing apparatus. When the change unit extraction means extracts an instruction that is in the program before the change and is not in the program after the change as the change unit,
The address conversion table creating means searches the program before the change for the instruction of the virtual address that is not in the program after the change, and registers the virtual address and the physical address of the searched instruction in association with each other in the address conversion table To
The information processing apparatus according to claim 1. The address conversion table creating means includes a program in which different instructions are described in the same address of the virtual address and the physical address, but the instruction of the virtual address is not changed for the virtual address that is not registered in the intermediate table. And register the virtual address and the physical address of the searched instruction in the address conversion table in association with each other.
The information processing apparatus according to claim 1 or 2. An address conversion table generated by the information processing apparatus according to claim 1;
The external storage means storing the program before the change and the change unit;
An address generation means for generating an address of an instruction read by the instruction execution means;
If the address generated by the address generation unit is different from the physical address associated with the virtual address of the same address conversion table as the address, the address conversion unit converts the address to the physical address;
An instruction reading unit that reads the instruction of the physical address converted by the address conversion unit from the storage unit and supplies the instruction to the instruction execution unit;
An information processing apparatus. An address management method for managing an address of a program created by an information processing apparatus,
From the program storage means for storing the program before the change and the program after the change, the change part extraction means reads the program before the change and the program after the change, and extracts both of the change parts;
An address determining unit determining a virtual address when each instruction of the changed program including the changing unit is arranged in an external storage unit;
Determining the physical address of the change unit when the program and the change unit before the change are arranged in an external storage unit while fixing the physical address of the program before the change;
Creating an intermediate table associating the virtual address and the physical address of the changing unit;
The address conversion table creating means compares each instruction of the program after the change and each instruction of the program before the change for each address from the head,
When the same instruction is described, the addresses are registered in association with each other. When different instructions are described, the address conversion is performed by associating and registering the virtual address and the physical address in the intermediate table. Creating a table;
Address management method.

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