JP2013078163A - Semiconductor device and electronic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily prevent occurrence of such a situation that a load circuit draws the power supply current excessively when the value of power supply current being supplied is smaller than expected and thereby the voltage of the power supply current drops undesirably.SOLUTION: A power supply control unit (21) using an internal power supply voltage (VCC), generated based on a power supply current supplied to a power supply input terminal (VBUS), as an operation power supply is provided with a current limit circuit (30) which provides a current to a power supply output terminal while limiting inflow of the current so that the current flowing into the power supply input terminal does not exceed a target current value. Furthermore, a current limit value switching circuit (31) is employed for controlling the inflow current from the current limit circuit to be smaller than the target current value, when the current flowing into the transmission path of the power supply current does not reach the target current value.

Description

  The present invention relates to a semiconductor device having a power control function for limiting an input current so as not to exceed a target current, and further relates to an electronic circuit device having such a power control function, for example, a USB (Universal Serial Bus (registered trademark)). The present invention relates to a technology that is effective when applied to a power supply control IC of a USB terminal device that satisfies the battery charging standard (Battery Charging Specification, Rev 1.1), which is an additional specification of)).

  In the original USB specifications, for the purpose of supplying power only to small peripheral devices, 500 mA at 5 V and 100 mA at 5 V were specified for supplying power to the connected devices. Recently, a battery charging standard (Battery Charging Specification, Rev 1.1, 4/15/2009), which is an additional USB specification, was formulated and a power supply capable of supplying 1500 mA was specified. This standard is a specification for battery charging, and deals with a method of acquiring power for charging from a USB port.

  In this battery charging standard, the following three types of power sources are defined as power sources for charging.

  The first is a standard downstream port (hereinafter also referred to as SDP). This is a port similar to that defined in the USB 2.0 specification, and is a port normally provided in a USB host or USB hub. The device can recognize the SDP in hardware by detecting individual connections to the ground via 15 kΩ of the USB data terminals (D +, D−). Electronic circuit devices (hereinafter also simply referred to as portable devices) such as PDAs (Personal Digital Assistants) and digital still cameras connected to the SDP can draw a power supply current of up to 500 mA from the SDP.

  The second is a charging downstream port (hereinafter also referred to as CDP). This defines a USB port having a larger current than SDP in a USB host or USB hub, and defines a port that can maintain a USB communication function and can be charged. CDP can supply 1500 mA. A device connected to the CDP can be recognized using a hardware handshake for the USB data terminals (D +, D-).

  The third is a dedicated charging port (hereinafter also referred to as DCP). This is a port that does not have a USB communication function and is dedicated to charging, and is defined as a power source that does not perform enumeration such as an AC adapter or a car adapter. The DCP can supply 1500 mA and is identified by a short circuit between the USB terminals D + and D− on the USB host or USB hub. This makes it possible to make an AC adapter with a USB socket.

  A portable device that conforms to the battery charging standard can determine how much current is appropriate to use the power received from the USB socket of a USB host or USB hub for its own operation or battery charging. You must judge. An attempt to acquire 1000 mA from a USB host or USB hub with a power supply capability of only 500 mA will overload the USB port. For example, a portable device compliant with the battery charging standard performs input current limitation as illustrated in FIG. 9 on the input power supply current according to the detected type of the USB port.

  Patent Document 1 focuses on the problem that when a USB-compatible electronic device is charged using an AC adapter with a USB connector, the standard current cannot be known because USB communication cannot be performed. That is, when the connection with the other electronic device is detected by the detection means, the control means monitors the measurement value of the measurement means while increasing the charging current value instructed to the charging means from the initial current value, and the measurement value The charging current value is determined based on the monitoring result. And a control means instruct | indicates the determined charging current value to a charging means, and makes a secondary battery charge. As a result, even if the information necessary for charging such as the standard current cannot be obtained from other electronic devices of the connection source, the secondary battery can be charged by charging with the charging current value determined based on the monitoring result. It can be performed stably.

JP 2010-154692 A

Battery Charging Specification, Rev 1.1, 4/15/2009

  The present inventor uses the USB data terminals D + and D− to determine whether the type of the USB port conforming to the battery charging standard is SDP, CDP, or DCP, so that the operation or We studied the control to obtain the appropriate current to use for charging the battery. According to this, whether the type of the USB port is SDP, CDP, or DCP may be determined by the power IC on the portable device side in accordance with the battery charging standard. However, when the determined port is DCP Further, as illustrated in FIG. 10, it has been clarified by the present inventor that there may be a port whose power supply capacity is 500 mA, which is less than 1500 mA. This is because the higher standard of the battery charging standard is the USB 2.0 standard, and there may be a view that even a DCP can satisfy the minimum current supply capability of 500 mA.

  However, when the power supply control IC determines the type of the connected USB port, and the control for obtaining the optimum target power supply value is performed, if the power supply current from the power supply side falls below the target current value, the portable device The power supply current is largely drawn by the load on the side, the internal operating voltage obtained by the power supply current is lowered, the operation of the power supply control IC itself is not guaranteed, and the portable device may cause a malfunction. It was found by. Originally, the power supply control IC has a circuit that limits the current so that the power supply current does not exceed the target current value, but determines the current limit value of the circuit that performs the current limit according to the determination result for the type of the connected USB port. For this reason, when the power supply current to be fed is smaller than the target current, this cannot be further restricted, and the necessity has not been found.

  The technique of Patent Document 1 measures the charging current value instructed to the charging means while increasing it from the initial current value, determines the charging current value of the charging means based on the monitoring result of the measured value, and supplies the charging current. It is essential to control the group and cannot contribute to the solution of the above-mentioned problems.

  The object of the present invention is to easily prevent the occurrence of a situation in which the power supply current is excessively drawn by the load circuit and the voltage of the power supply current drops negatively when the current value of the supplied power supply current is smaller than expected. An object of the present invention is to provide a semiconductor device that can be used.

  Another object of the present invention is that when the current value of the supplied power source current is smaller than expected, the power source current is excessively drawn by the load circuit and the voltage of the power source current drops negatively and malfunctions. An object of the present invention is to provide an electronic circuit device that can easily prevent generation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, the power supply control unit using the internal power supply voltage generated based on the power supply current supplied to the power supply input terminal as the operation power supply is controlled so that the current flowing into the power supply input terminal does not exceed the target current value. A current limiting circuit is provided that limits inflow and is applied to a power output terminal, and when the current flowing into the power supply current transmission path does not reach the target current value, the inflow current by the current limiting circuit is set to the target current value. Control to make it smaller.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, when the current value of the supplied power supply current is smaller than expected, it is possible to easily prevent the occurrence of a situation where the power supply current is excessively drawn by the load circuit and the voltage of the power supply current drops negatively. .

FIG. 1 is a block diagram illustrating an electronic circuit device to which a power supply control IC according to an embodiment of the invention is applied. FIG. 2 is a characteristic diagram illustrating the voltage waveform of the power supply current depending on the relationship between the current limit value set in the current limit circuit and the power supply capability from the power supply port. FIG. 3 is a characteristic diagram illustrating an operation waveform when the current limit value set in the current limit circuit according to the type of the power supply port is changed according to the actual power supply capability of the power supply port. FIG. 4 is a circuit diagram showing a specific example of a current limiting circuit and a current limiting value switching circuit. FIG. 5 is a circuit diagram showing another specific example of a current limiting circuit and a current limiting value switching circuit. FIG. 6 is a flowchart illustrating the determination processing procedure of the power supply current input mode by the determination circuit. FIG. 7 is an explanatory diagram illustrating a discrimination method between SDP and DCP / CDP in the discrimination processing procedure of FIG. FIG. 8 is an explanatory diagram illustrating a method for discriminating between DCP and CDP. FIG. 9 is an explanatory diagram showing the input current limitation performed on the input power supply current according to the type of the USB port determined by the portable device compliant with the battery charging standard. FIG. 10 is an explanatory diagram showing that when the determined port is DCP, there may be a port whose power supply capacity is 500 mA, which is less than 1500 mA.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Increase inflow current limit when inflow of external power supply current does not reach default>
A semiconductor device (10) according to a representative embodiment of the present invention includes a power supply input terminal (VBUS) for inputting a power supply current, a power supply output terminal (PSYS) for outputting a power supply current, and the power supply input terminal. A voltage generation circuit (20) that generates an internal power supply voltage based on the supplied power supply current, and a power supply control unit (21) that uses the internal power supply voltage as an operation power supply. The power supply control unit is disposed in a power supply current transmission path (22) between the power supply input terminal and the power supply output terminal, and restricts inflow of current so that the inflowing current does not exceed a target current value. A current limiting circuit (30) and detecting that the current flowing into the transmission path of the power supply current does not reach the target current value based on a voltage drop due to an increase in the current flowing through the transmission path, A current limit value switching circuit (31) for performing control to make the limit value of the inflow current by the current limit circuit smaller than the target current value.

  As a result, when a power supply current that does not reach the target current value is supplied from the power supply input terminal, the current limit value of the current limit circuit is reduced, and excessive current draw by the load circuit is prevented. Occurrence of a situation where the voltage drops undesirably can be prevented. Therefore, even when a small power supply current that does not reach the target current value is supplied, the power supply voltage of the semiconductor device can be maintained, and this semiconductor device can be used as a power supply control IC or the like due to a malfunction of the semiconductor device due to a drop in the power supply voltage. This can contribute to the prevention of malfunction or inoperability of the electronic circuit device to be used.

[2] <The current limit value determined by the power supply current input mode is further limited according to the actual inflow current>
In item 1, the power supply control unit further includes a determination circuit (32) for determining an input mode of the power supply current. The current limiting circuit can select the target current value according to the determination result of the determination circuit.

  Thereby, it is possible to easily cope with the power supply side that supplies different power supply currents even in the same input mode. For example, when the DCP mode is determined and the portable device having the above semiconductor device sets a current limit of 1500 mA in accordance with the battery charging standard, the actually connected host device has only a power supply capability of 100 mA. However, it can contribute to suppression of malfunction and inoperability of the portable device.

[3] <Determination of power supply current input mode by D + and D- terminals>
Item 2 further includes a pair of input terminals D + and D-. The determination circuit determines an input mode according to a state of an external path connected to the input terminals D + and D−.

  Thereby, it is possible to determine the power supply current input mode in conformity with the battery charging standard.

[4] <Inflow current limit value according to input mode by current limit value switching circuit>
In any one of Items 2 to 3, the target current value in the first mode (DCP) determined by the determination circuit is a first current value, and the target current value in the second mode (SDP) determined by the determination circuit The target current value is a second current value that is smaller than the first current value. In the first mode, the current limit value switching circuit controls the inflow current value controlled to be smaller than the first current value to the second current value.

  Thus, when the first mode is DCP in the battery charging standard and the first current value which is the target current is 1500 mA, and the second mode is SDP in the battery charging standard and the second current value which is the target current is 500 mA. In addition, the operation of the semiconductor device and the operation of the load circuit for the power supply current can be guaranteed even for the power supply from the host device which has only a power supply capability of 500 mA in the first mode.

[5] <Constant current constant voltage control>
Any one of 1 to 4 further includes a battery terminal (PBAT) to which the battery (12) is connected. The power supply control unit further includes a charge control unit (33) that performs constant-current / constant-voltage control on a power supply current supplied from a power supply current transmission path in a subsequent stage of the current limiting circuit and supplies the current to the battery terminal. .

  As a result, in the semiconductor device having a battery charging function, the operation of the semiconductor device is guaranteed even when the supply of the power supply current smaller than the target is received. In this case, the charging function for the battery can be guaranteed.

[6] <Current limiting circuit for switching the current limiting value by biasing the output of the input current limiting amplifier>
In any one of Items 1 to 5, the current limiting circuit includes an input current control transistor (M1) used for limiting an input current flowing into a power supply input terminal, and the input at a predetermined ratio with respect to the input control transistor. A current detection transistor (M2) that attempts to flow a current, and a gate voltage of the input current control transistor is controlled based on a current flowing through the current detection transistor, and is larger than the target current value flowing through the input current control transistor A negative feedback amplifier circuit (OP2, M4) for limiting the current to the target current value. The current limit value switching circuit includes a current limit switching amplifier that reduces a limit current value of the input current control transistor by the negative feedback amplifier circuit when a voltage drop due to an increase in current flowing in the current detection transistor reaches a predetermined value. It consists of a circuit (OP3, M10).

  According to this, since the degree of the voltage drop due to the increase in the current flowing through the current detection transistor is determined based on the predetermined value, the power supply current value switching reference is hardly influenced by the magnitude of the power supply current.

[7] <Switching the current limit value by switching the reference potential of the input current limit amplifier>
6. The current limiting circuit according to claim 1, wherein the current limiting circuit includes an input current control transistor (M1) used for limiting an input current flowing into a power supply input terminal, and the input control transistor at a predetermined ratio. A current detection transistor (M2) that attempts to flow an input current; and a negative feedback amplifier circuit (OP4) that controls the gate voltage of the input current control transistor based on the current flowing through the current detection transistor. The negative feedback amplifier circuit also serves as a switching circuit for the current limit value. In the negative feedback amplifier circuit, the detection voltage (N1) formed based on the current flowing in the current detection transistor is a first reference voltage (VBG) that is a constant voltage or the voltage of the power input terminal is divided. By exceeding the second reference voltage (VN3), the current flowing through the input current control transistor is limited. When the current flowing through the input current control transistor is equal to or greater than the target current value, the first voltage is made lower than the second voltage, and when the current flowing through the input current control transistor is smaller than the target current value, the first voltage is reduced. The voltage of 2 is made lower than the first voltage.

  According to this, since the negative feedback amplifier circuit also serves as the current limit value switching circuit, the configuration is simpler than that of the sixth aspect. However, since the second reference voltage is a voltage obtained by dividing the voltage of the power input terminal, the current limit switching reference is affected by the magnitude of the power supply current, and the current limit width may be narrowed. .

[8] <Increase inflow current limit when inflow of external power supply current does not reach the default>
An electronic circuit device (1) according to another embodiment of the present invention is based on a power supply input terminal for inputting a power supply current, a power supply output terminal for outputting a power supply current, and a power supply current supplied to the power supply input terminal. A voltage generation circuit for generating an internal power supply voltage, a power supply control unit using the internal power supply voltage as an operating power supply, and a load circuit connected to the power supply output terminal. The power supply control unit is disposed in a power supply current transmission path between the power supply input terminal and the power supply output terminal, and restricts the inflow of current so that the inflowing current does not exceed a target current value. And an inflow current by the current limiting circuit by detecting that the current flowing into the transmission path of the power supply current does not reach the target current value based on a voltage drop due to an increase in the current flowing through the transmission path. And a current limit value switching circuit for performing control for making the limit value smaller than the target current value.

  As a result, when a power supply current that does not reach the target current value is supplied from the power supply input terminal, the current limit value of the current limit circuit is reduced, and excessive current draw by the load circuit is prevented. Occurrence of a situation where the voltage drops undesirably can be prevented. Therefore, even when a small power supply current that does not reach the target current value is supplied, the power supply voltage of the semiconductor device can be maintained, and the malfunction of the electronic circuit device or the inoperable state due to the malfunction of the semiconductor device due to the decrease of the power supply voltage. Can contribute to the suppression of the occurrence of

[9] <Current limit value determined by power supply current input mode is further limited according to actual inflow current>
In Item 8, the power supply control unit further includes a determination circuit that determines an input mode of the power supply current. The current limiting circuit can select the target current value according to the determination result of the determination circuit.

  Thereby, it is possible to easily cope with the power supply side that supplies different power supply currents even in the same input mode. For example, when the DCP mode is determined and the portable device having the above semiconductor device sets a current limit of 1500 mA in accordance with the battery charging standard, the actually connected host device has only a power supply capability of 100 mA. However, it can contribute to suppression of malfunction and inoperability of the portable device.

[10] <Determination of power supply current input mode by D + and D- terminals>
Item 9 further includes a pair of input terminals D + and D-. The determination circuit determines an input mode according to a state of an external path connected to the input terminals D + and D−.

  Thereby, it is possible to determine the power supply current input mode in conformity with the battery charging standard.

[11] <Inflow current limit value according to input mode by current limit value switching circuit>
10. The target current value in the first mode determined by the determination circuit according to claim 9 is a first current value, and the target current value in the second mode determined by the determination circuit is greater than the first current value. Is also a small second current value. In the first mode, the current limit value switching circuit controls the inflow current value controlled to be smaller than the first current value to the second current value.

  Thus, when the first mode is DCP in the battery charging standard and the first current value which is the target current is 1500 mA, and the second mode is SDP in the battery charging standard and the second current value which is the target current is 500 mA. In addition, the power supply current load circuit operation and the electronic circuit device operation can be guaranteed even for power supply from a host device having only 500 mA power supply capability in the first mode.

[12] <Constant current constant voltage control>
The battery according to claim 8, further comprising a battery and a battery terminal to which the battery is connected. The power supply control unit further includes a charge control unit that performs constant-current / constant-voltage control on a power supply current supplied from a power supply current transmission path in a subsequent stage of the current limiting circuit and supplies the current to the battery terminal.

  As a result, in the power supply control unit having the battery charging function, the operation of the power supply control unit is ensured even when the supply of the power supply current smaller than the target is received. .

[13] <Current limiter circuit for switching the current limit value by biasing the output of the input current limit amplifier>
12. The current limiting circuit according to any one of Items 8 to 12, wherein the current limiting circuit is configured to flow an input current control transistor used for limiting an input current flowing into a power supply input terminal and a predetermined ratio with respect to the input control transistor. A current detection transistor to be controlled, and a gate voltage of the input current control transistor is controlled based on a current flowing through the current detection transistor, and a current larger than the target current value flowing through the input current control transistor is set as the target current value. A negative feedback amplifier circuit. The current limit value switching circuit includes a current limit switching amplifier that reduces a limit current value of the input current control transistor by the negative feedback amplifier circuit when a voltage drop due to an increase in current flowing in the current detection transistor reaches a predetermined value. Consists of a circuit.

  According to this, since the degree of the voltage drop due to the increase in the current flowing through the current detection transistor is determined based on the predetermined value, the power supply current value switching reference is hardly influenced by the magnitude of the power supply current.

[14] <Switching the current limit value by switching the reference potential of the input current limit amplifier>
12. The current limiting circuit according to any one of Items 8 to 12, wherein the current limiting circuit is configured to flow an input current control transistor used for limiting an input current flowing into a power supply input terminal and a predetermined ratio with respect to the input control transistor. And a negative feedback amplifier circuit that controls a gate voltage of the input current control transistor based on a current flowing through the current detection transistor. The negative feedback amplifier circuit also serves as a switching circuit for the current limit value. In the negative feedback amplifier circuit, a detection voltage formed based on a current flowing through the current detection transistor is a constant voltage, and a first reference voltage or a second reference voltage obtained by dividing the voltage of the power input terminal is obtained. By exceeding, the current flowing through the input current control transistor is limited. When the current flowing through the input current control transistor is equal to or greater than the target current value, the first voltage is made lower than the second voltage, and when the current flowing through the input current control transistor is smaller than the target current value, the first voltage is reduced. The voltage of 2 is made lower than the first voltage.

  According to this, since the negative feedback amplifier circuit also serves as the current limit value switching circuit, the configuration is simpler than that of the sixth aspect. However, since the second reference voltage is a voltage obtained by dividing the voltage of the power input terminal, the current limit switching reference is affected by the magnitude of the power supply current, and the current limit width may be narrowed. .

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 illustrates an electronic circuit device according to the present invention. The electronic circuit device 1 shown in the figure is a portable device such as a PDA or a digital still camera having a USB interface function that satisfies the battery charging standard. This portable device 1 is connected to a USB host 2 via a USB cable 3. The portable device 1 has a power input terminal VBUS, a ground terminal GND, and differential data terminals D + and D− as interface terminals with the USB cable 3.

  Here, the USB interface included in the portable device 1 corresponds to any of the SDP, CDP, and DCP ports in the battery charging standard as described with reference to FIG. Here, the control function for the power supplied from the port is mainly described regardless of whether the USB host 2 is SDP, CDP, or DCP, and the data interface is not the gist of the present invention, so that description is omitted. To do.

  The electronic circuit device 1 includes a power supply control IC 10 as a semiconductor device, and further includes a system circuit 11 as a load circuit that operates by receiving a power supply controlled by the power supply IC 10, and a battery 12 that is charged via the power supply IC 10. Have. The power supply control IC 10 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a CMOS or BI-CMOS integrated circuit manufacturing technique.

  The power supply IC 10 includes, in addition to the power supply input terminal VBUS for inputting a power supply current, the differential data terminals D + and D−, and the ground terminal GND, the power supply output terminal PSYS for outputting the power supply current, which is representatively shown, A voltage generation circuit (RGL) 20 that generates an internal power supply voltage VCC and the like based on a power supply current supplied to an input terminal VBUS, and a power supply control unit (VCNT) 21 that uses the internal power supply voltage VCC as an operation power supply.

  The power supply control unit 21 includes a current limit circuit 30, a current limit value switching circuit 31, a determination circuit 32, and a charge control unit 33. Since the power supply control unit 21 uses the internal power supply voltage VCC as an operating power supply, if the power supply current supplied from the power supply input terminal VBUS exceeds the power supply capability and is excessively drawn into the system circuit 11, the power supply current voltage Drops, and the voltage required for the internal power supply voltage VCC cannot be obtained. The current limiting circuit 30 suppresses excessive current draw exceeding the power supply capability.

  The current limiting circuit 30 is disposed in the power supply current transmission path 22 between the power supply input terminal VBUS and the power supply output terminal PSYS, and restricts the inflow of current so that the inflowing current does not exceed the target current value. .

  The determination circuit 32 determines the input mode of the power supply current, for example, whether the port of the USB host 2 is SDP, CDP or DCP, based on the state of the differential data terminals D + and D−. This determination result 34 is given to the current limiting circuit 30. The current limit circuit 30 selects the target current value, that is, the limit value of the inflow current according to the determination result 34 of the determination circuit 32, so that the power supply suitable for the power supply capability of the USB port according to SDP, CDP or DCP. The current can be drawn into the load circuit 11.

  The current limit value switching circuit 31 detects that the current flowing into the transmission path 22 of the power supply current has not reached the target current value based on a voltage drop due to an increase in the current flowing through the transmission path 22. Thus, control is performed to make the limit value of the inflow current by the current limit circuit 21 smaller than the target current value. In particular, here, when it is determined that the port of the USB host 2 is DCP, when the power supply capacity of the port is not 1500 mA according to the battery charging standard but 500 mA which is the same as the SDP, it matches the power supply capacity of 1500 mA. In the current limit value, a power supply current having a power supply capacity of 500 mA is excessively drawn into the load circuit 11. In this case, even when the determination result by the determination circuit 32 is DCP, the current limit value is the current when the power supply capacity is 500 mA. The limit value can be automatically changed.

  As a result, when a power supply current that does not reach the target current value is supplied from the power supply input terminal VBUS, the current limit value of the current limit circuit 30 is reduced, and excessive current drawing by the load circuit is prevented. It is possible to prevent the occurrence of a situation where the power supply voltage is undesirably dropped. Therefore, even when a small power supply current that does not reach the target current value is supplied, the power supply voltage VCC of the power supply control IC 10 can be maintained, and the power supply control IC 10 is caused to malfunction by a malfunction of the power supply control IC 10 due to a decrease in the power supply voltage VCC. This can contribute to preventing the malfunction or inoperability of the electronic circuit device 1 to be used.

  FIG. 2 illustrates a voltage waveform of the power supply current depending on the relationship between the current limit value set in the current limit circuit and the power supply capability from the power supply port. When the power supply capability (current capability) of the power supply is higher than the current limit value by the current limiting circuit 30 of the power supply control IC 10, no voltage drop occurs in the power supply current as in L1. On the other hand, when the power supply capability (current capability) of the power supply is lower than the current limit value by the current limit circuit 30 of the power supply control IC 10, a voltage drop occurs in the power supply current as in L2.

  FIG. 3 illustrates an operation waveform when the current limit value set in the current limit circuit according to the type of the power supply port is changed according to the actual power supply capability of the power supply port. By reducing the current limit value (input current limit value) by the current limit circuit 30 of the power supply control IC 10 based on the voltage drop of the power supply current supplied from the power supply port, the power supply current drop is prevented. .

  FIG. 4 shows specific examples of the current limiting circuit 30 and the current limiting value switching circuit 31.

  Based on the reference voltage VBG generated by the band gap reference circuit (BGR), the voltage generation circuit 20 feeds back the divided voltage of the resistance voltage dividing circuit to the operational amplifier, and the drain of the pMOS transistor that receives the output of the operational amplifier at the gate, A predetermined power supply voltage VCC is formed at a connection node with the resistance voltage dividing circuit.

  The charge control unit 33 has a transfer pMOS transistor disposed between a transmission path of the power supply current that has passed through the current limiting circuit 30 and the PBAT of the battery terminal, and the gate of the transfer pMOS transistor is used as a constant current constant voltage control circuit. The charging current supplied to the battery terminal PBAT under the control of (CCCV) is made constant or the voltage of the battery terminal PBAT is made constant. Battery current can be supplied from the battery 12 to the load circuit 11 via a diode. As a result of the power supply control IC 10 having a battery charging function, the operation of the power supply control IC 10 is guaranteed as described above even when a supply of a power supply current smaller than the target is received. be able to.

  The current limiting circuit 30 includes a p-channel MOS transistor (hereinafter simply referred to as a pMOS transistor) M1 as an input current control transistor used for limiting an input current flowing into the power input terminal VBUS, and a pMOS transistor M1. PMOS transistor M2 as a current detection transistor that attempts to flow the input current at a predetermined ratio, and the gates of pMOS transistor M1 and pMOS transistor M2 are the ratio of the on-resistance of resistance element R1 and pMOS transistor M4. A divided voltage determined by is applied. The gate size of the pMOS transistor M1 and the pMOS transistor M2 is, for example, 1000: 1. An n-channel type MOS transistor (hereinafter simply referred to as an nMOS transistor) M3 whose conductance is controlled by the operational amplifier OP1 is arranged in the current path of the pMOS transistor M2, and the drain voltage of the pMOS transistor M2 matches the drain voltage of the pMOS transistor M1. It has become so. This takes into account the channel length modulation effect of the pMOS transistors M1 and M2. As a result, a current corresponding to the transistor size ratio of the drain current of the pMOS transistor M1 flows through the drain of the pMOS transistor M2. Between the source of the nMOS transistor M3 and the ground GND, a plurality of series circuits of resistor elements R2, R3 and nMOS transistors M5, M6, which are representatively shown, are arranged in parallel, and one current path is provided according to the determination signal 34. It comes to choose. For example, in the case of CDP and DCP having a large power supply current supplied to VBUS, the path of the resistance element R2 having a small resistance value is selected. In the case of SDP having a small power supply current, the path of the resistance element R3 having a large resistance value is selected. Is done. The gate of the pMOS transistor M4 is connected to the non-inverting input terminal (+) of the source of the MOS transistor M3, and the inverting input terminal (−) is coupled to the output of the operational amplifier OP2 to which the reference voltage VBG is supplied. When the current flowing through the pMOS transistor M1 increases, the voltage at the node N1 rises and approaches the reference voltage at the inverting input terminal (−). When the voltage at the node N1 and the reference voltage at the inverting input terminal (−) become equal, the pMOS The current flowing through the transistor M1 is limited.

  The output terminal of the operational amplifier OP2 is connected to the power supply voltage VCC via the nMOS transistor M10. The operational amplifier OP3 that controls the gate of the nMOS transistor M10 receives the reference voltage VBG at the non-inverting input terminal (+) and the voltage at the voltage dividing node N2 by the series resistance elements R10 and R11 that receives the power supply current at the inverting input terminal (−). Receive. When the voltage of the power supply current drops due to excessive drawing of the power supply current by the load circuit 11, the voltage of the voltage dividing node N2 also drops accordingly, and the voltage of the node N2 becomes equal to or lower than the reference voltage VBG, thereby causing the conductance of the nMOS transistor M10. Increases to act to reduce the on-resistance of the pMOS transistor M4, thereby limiting the current flowing through the pMOS transistor M1.

  An operation when the current supply capability of the power supply is larger than the current limit value of the power supply control IC when the current capability of the USB port is 1500 mA or more in the circuit configuration of FIG. 4 will be described. That is, the DCP mode is determined by the determination circuit 32 and the path of the resistance element R2 having a small resistance value is selected. In this case, the load current does not exceed the power supply capacity, and the level of the node N2 does not fall below the reference. On the other hand, when the power supply current increases, the current flowing through the nMOS transistor M3 increases as the current flowing through the pMOS transistor M1 increases. Accordingly, the voltage at the node N1 increases, and the non-half-transfer input terminal (+) of the operational amplifier OP2 increases. Becomes equal to the reference voltage VBG of the inverting input terminal (−) of the operational amplifier OP2, the negative feedback control of the operational amplifier OP2 makes it impossible to flow a current greater than a certain current value to the pMOS transistor M1.

  On the other hand, when the current capability of the USB host is less than 1500 mA despite the DCP mode being determined in the circuit configuration of FIG. 4, that is, when the current supply capability of the power supply is smaller than the current limit value of the power supply control IC, the node The voltage of N1 never becomes higher than the reference value. When the power supply current is drawn by the load circuit 11 beyond its power supply capability, the input voltage is attenuated. As a result, when the voltage at the node N2 decreases and the voltage at the inverting input terminal (−) of the operational amplifier OP3 becomes equal to the voltage at the non-inverting input terminal (+), current limitation by the pMOS transistor M1 is performed by negative feedback control of the operational amplifier OP3. And the voltage due to the power supply current is controlled to a constant value. In this way, the current limit of the power supply current by the pMOS transistor M1 is automatically adjusted according to the current supply capability of the USB host circuit.

  As described above, in FIG. 4, the negative feedback amplifier circuit (OP2, M4) controls the gate voltage of the pMOS transistor M1 based on the current flowing through the pMOS transistor M2, and exceeds the target current value flowing through the pMOS transistor M1. A large current is limited to the target current value. The current limit switching amplifier circuit (OP3, M10) is configured to cause the negative feedback amplifier circuit (OP2, M4) to supply a current through the input current control transistor M1 when a voltage drop due to an increase in the current flowing through the pMOS transistor M1 reaches a predetermined value. Reduce the limit value.

  According to this, since the degree of the voltage drop due to the increase in the current flowing through the current detection transistor is determined using the operational amplifier OP3 based on the reference voltage which is a predetermined value, the switching reference of the power supply current value is the magnitude of the power supply current. It is hard to be influenced by such.

  FIG. 5 shows another specific example such as a current limiting circuit 30 and a current limiting value switching circuit 31. In FIG. 5, the current limiting circuit 30 has the same basic configuration as that of FIG. 4, and an operational amplifier OP4 having two inverting input terminals (−) is employed instead of the operational amplifier OP3. One inverting input terminal (−) is supplied with a reference voltage VBG. The other inverting input terminal (−) is supplied with a divided voltage VN3 obtained by dividing the power supply current applied to the power supply input terminal VBUS by the series resistors R20 and R21. The configuration related to the other inverting input terminal (−) is a configuration for realizing the current limit value switching circuit 31. In short, the negative feedback amplifier circuit composed of the operational amplifier OP4 and the MOS transistor M4 also serves as the current limit value switching circuit 31. The other configurations are the same as those in FIG. 4, and circuit elements having the same functions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The negative feedback amplifier circuit (OP4, M4) divides the first reference voltage VBG or the voltage of the power supply input terminal VBUS, the detection voltage formed based on the current flowing through the current detection transistor M1 being a constant voltage. By exceeding the second reference voltage VN3 of the compressed node N3, the current flowing through the input current control transistor M1 is limited. When the current flowing through the input current control transistor M1 is greater than or equal to the target current value, the first voltage VBG is made lower than the second voltage VN3, and the current flowing through the input current control transistor M1 is lower than the target current value. When the voltage is small, the second voltage VN3 is made lower than the first voltage VBG. Since the operational amplifier PO4 expects the output to be inverted when the voltage at the non-inverting input terminal (+) becomes high and matches the voltage at the inverting input terminal (−), the two inverting input terminals (− ), The lower voltage is preferentially referred to.

  In the circuit configuration of FIG. 5, when the current capability of the USB host is 1500 mA or more and the current supply capability of the power supply is larger than the current limit value of the power supply control IC, that is, the DCP mode is determined by the determination circuit 32 and the resistance value When the path of the small resistance element R2 is selected, the same operation as in FIG. 4 is performed, and thus detailed description thereof is omitted.

  On the other hand, when the current capability of the USB host is less than 1500 mA even when the DCP mode is determined in the circuit configuration of FIG. 5, that is, when the current supply capability of the power supply is smaller than the current limit value of the power supply control IC 10. Initially, the reference voltage VBG is lower than the voltage VN3 of the voltage dividing node, but when the power supply current is drawn by the load circuit 11 beyond its power supply capability, the input voltage is attenuated. As a result, the voltage at the node N1 is lowered together with the voltage at the power input terminal VBUS. As a result, when the divided voltage VN3 becomes lower than the reference voltage VBG and the voltage at the node N1 becomes equal to the divided voltage VN3, the voltage at the non-inverting input terminal (+) of the operational amplifier OP4 becomes the voltage at the inverting input terminal (−). By the negative feedback control of the operational amplifier OP4, the current limitation by the pMOS transistor M1 is further increased, and the supply of the power source current by the load circuit 11 is further limited. In this way, the current limit of the power supply current by the pMOS transistor M1 is automatically adjusted according to the current supply capability of the USB host circuit.

  According to this, since the negative feedback amplifier circuit (OP4, M4) also serves as a current limit value switching circuit, the configuration can be simplified compared to FIG. However, since the divided voltage VN3, which is the second reference voltage, is a voltage obtained by dividing the voltage of the power input terminal VBUS, the switching criterion of the current limit is influenced by the magnitude of the power supply current, etc. The width may be narrowed.

  FIG. 6 illustrates the determination process procedure of the input mode of the power supply current by the determination circuit 32, FIG. 7 illustrates the determination method of SDP and DCP / CDP in the determination process procedure of FIG. 6, and FIG. A CDP discrimination method is exemplified. The method shown in each figure is the method shown by the battery charging standard. It is possible to determine whether the power supply current input mode is SDP, DCP, or CDP by performing the determination processing of steps S1 to S4 shown in FIG. Basically, it is performed by determining the state of the differential data terminals D + and D− on the USB host side. For example, in the case of DCP, the differential data terminals D + and D− are short-circuited on the USB host side, and when the current is supplied to the D + side as illustrated in FIG. As shown in FIG. 8, the DCP can be discriminated by making a determination of whether the input from the D + side is high or low when a current is supplied to the D− side.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the present invention is not limited to the case where the present invention is applied to a power supply control IC conforming to the USB battery charging standard, and can be applied to various power supply current control techniques. The configurations of the current limit circuit 30 and the current limit value switching circuit 31 are not limited to those shown in FIGS. 4 and 5, and other circuit configurations may be adopted.

DESCRIPTION OF SYMBOLS 1 Portable device 2 USB host 3 USB cable VBUS Power supply input terminal GND Ground terminal D +, D- Differential data terminal 10 Power supply control IC as a semiconductor device
11 System Circuit as Load Circuit 12 Battery PSYS Power Supply Output Terminal VCC Internal Power Supply Voltage 21 Power Supply Control Unit (VCNT)
DESCRIPTION OF SYMBOLS 30 Current limit circuit 31 Current limit value switching circuit 32 Judgment circuit 33 Charge control part M1 pMOS transistor as input current control transistor M2 pMOS transistor as current detection transistor OP3 Negative feedback amplifier circuit OP2 Current limit amplifier circuit OP4, R20, R21 Negative feedback amplifier circuit also serving as the current limiting amplifier circuit

Claims (14)

A power input terminal for inputting power supply current;
A power supply output terminal for outputting power supply current;
A voltage generation circuit that generates an internal power supply voltage based on a power supply current supplied to the power supply input terminal;
A power supply control unit using the internal power supply voltage as an operating power supply,
The power supply control unit is disposed in a power supply current transmission path between the power supply input terminal and the power supply output terminal, and restricts the inflow of current so that the inflowing current does not exceed a target current value. When,
By detecting that the current flowing into the transmission path of the power supply current does not reach the target current value based on the voltage drop due to the increase in the current flowing through the transmission path, the current limiting circuit limits the inflow current And a current limit value switching circuit for performing control to make the value smaller than the target current value. The power supply control unit according to claim 1, further comprising a determination circuit that determines an input mode of the power supply current,
The semiconductor device in which the current limiting circuit is configured to select the target current value according to a determination result of the determination circuit. In Claim 2, it further has a pair of input terminals D + and D-,
The semiconductor device, wherein the determination circuit determines an input mode according to a state of an external path connected to the input terminals D + and D−. 3. The target current value in the first mode determined by the determination circuit according to claim 2 is a first current value, and the target current value in the second mode determined by the determination circuit is greater than the first current value. Is also a small second current value,
In the first mode, the current limit value switching circuit controls the inflow current value controlled to be smaller than the first current value to a second current value. The battery terminal according to claim 1, further comprising a battery terminal to which a battery is connected,
The power supply control unit further includes a charge control unit that performs constant current and constant voltage control on a power supply current supplied from a power supply current transmission path in a subsequent stage of the current limiting circuit and supplies the power to the battery terminal. . The current limiting circuit according to claim 1, wherein the current limiting circuit includes an input current control transistor used for limiting an input current flowing into a power input terminal;
A current detection transistor that attempts to flow the input current at a predetermined ratio with respect to the input control transistor;
A negative feedback amplifier for controlling a gate voltage of the input current control transistor based on a current flowing through the current detection transistor to limit a current larger than the target current value flowing through the input current control transistor to the target current value A circuit,
The current limit value switching circuit includes a current limit switching amplifier that reduces a limit current value of the input current control transistor by the negative feedback amplifier circuit when a voltage drop due to an increase in current flowing in the current detection transistor reaches a predetermined value. A semiconductor device consisting of a circuit. The current limiting circuit according to claim 1, wherein the current limiting circuit includes an input current control transistor used for limiting an input current flowing into a power input terminal;
A current detection transistor that attempts to flow the input current at a predetermined ratio with respect to the input control transistor;
A negative feedback amplifier circuit that controls a gate voltage of the input current control transistor based on a current flowing through the current detection transistor;
The negative feedback amplifier circuit also serves as the current limit value switching circuit,
In the negative feedback amplifier circuit, a detection voltage formed based on a current flowing through the current detection transistor is a first reference voltage which is a constant voltage or a second reference voltage obtained by dividing the voltage of the power input terminal. By limiting the current flowing through the input current control transistor,
When the current flowing through the input current control transistor is equal to or greater than the target current value, the first voltage is made lower than the second voltage, and when the current flowing through the input current control transistor is smaller than the target current value, the first voltage is reduced. The semiconductor device in which the voltage of 2 is made lower than the first voltage. A power input terminal for inputting power supply current;
A power supply output terminal for outputting power supply current;
A voltage generation circuit that generates an internal power supply voltage based on a power supply current supplied to the power supply input terminal;
A power supply controller using the internal power supply voltage as an operating power supply;
A load circuit connected to the power output terminal,
The power supply control unit is disposed in a power supply current transmission path between the power supply input terminal and the power supply output terminal, and restricts the inflow of current so that the inflowing current does not exceed a target current value. When,
By detecting that the current flowing into the transmission path of the power supply current does not reach the target current value based on the voltage drop due to the increase in the current flowing through the transmission path, the current limiting circuit limits the inflow current An electronic circuit device comprising: a current limit value switching circuit that performs control to make a value smaller than the target current value. The power supply control unit according to claim 8, further comprising a determination circuit that determines an input mode of the power supply current,
The electronic circuit device, wherein the current limit circuit is capable of selecting the target current value according to a determination result of the determination circuit. In Claim 9, it further has a pair of input terminals D + and D-,
The determination circuit determines an input mode according to a state of an external path connected to the input terminals D + and D−. 10. The target current value in the first mode determined by the determination circuit is the first current value according to claim 9, and the target current value in the second mode determined by the determination circuit is greater than the first current value. Is also a small second current value,
In the first mode, the switching circuit of the current limit value controls an inflow current value controlled to be smaller than the first current value to a second current value. The battery according to claim 8, further comprising a battery and a battery terminal to which the battery is connected.
The electronic circuit further includes a charge control unit that performs constant current and constant voltage control on a power source current supplied from a power source current transmission path in a subsequent stage of the current limiting circuit and supplies the power source to the battery terminal. apparatus. The current limiting circuit according to claim 8, wherein the current limiting circuit includes an input current control transistor used for limiting an input current flowing into a power input terminal;
A current detection transistor that attempts to flow the input current at a predetermined ratio with respect to the input control transistor;
A negative feedback amplifier for controlling a gate voltage of the input current control transistor based on a current flowing through the current detection transistor to limit a current larger than the target current value flowing through the input current control transistor to the target current value A circuit,
The current limit value switching circuit includes a current limit switching amplifier that reduces a limit current value of the input current control transistor by the negative feedback amplifier circuit when a voltage drop due to an increase in current flowing in the current detection transistor reaches a predetermined value. An electronic circuit device consisting of a circuit. The current limiting circuit according to claim 8, wherein the current limiting circuit includes an input current control transistor used for limiting an input current flowing into a power input terminal;
A current detection transistor that attempts to flow the input current at a predetermined ratio with respect to the input control transistor;
A negative feedback amplifier circuit that controls a gate voltage of the input current control transistor based on a current flowing through the current detection transistor;
The negative feedback amplifier circuit also serves as the current limit value switching circuit,
In the negative feedback amplifier circuit, a detection voltage formed based on a current flowing through the current detection transistor is a constant voltage, and a first reference voltage or a second reference voltage obtained by dividing the voltage of the power input terminal is obtained. By limiting the current flowing through the input current control transistor,
When the current flowing through the input current control transistor is equal to or greater than the target current value, the first voltage is made lower than the second voltage, and when the current flowing through the input current control transistor is smaller than the target current value, the first voltage is reduced. An electronic circuit device, wherein the voltage of 2 is made lower than the first voltage.

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