JP2013077980A - Electronic circuit and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To directly compensate for the drift of a drain idle current.SOLUTION: A control method of an electronic circuit comprising an FET including a gate to which an input signal is inputted and a drain from which an output signal is outputted is provided. The control method of the electronic circuit includes a step S10 of calculating a variation ΔIdq(t) of a drain idle current corresponding to an input signal x(t) after the lapse of a time (t) from input of the input signal to the gate of the FET, a step S12 of calculating a gate bias voltage Vg for compensating for the variation ΔIdq(t), and a step S14 of applying the gate bias voltage to the gate of the FET.

Description

  The present invention relates to an electronic circuit and a control method thereof, for example, an electronic circuit that compensates for drift of a drain idle current and a control method thereof.

  In recent mobile phone base stations and the like, a high output and high efficiency high frequency amplifier circuit is required. Instead of an amplifier circuit using silicon or GaAs, a high-frequency amplifier circuit using a nitride semiconductor such as GaN has begun to be used. An amplifier circuit using a nitride semiconductor is capable of high voltage operation and high current density operation, and can select a substrate with high thermal conductivity. Thus, an amplifier circuit using a nitride semiconductor is excellent as a high-output high-frequency amplifier circuit.

  For example, in an amplifier circuit using a nitride semiconductor, it is known that a drain idle current drifts when a large input power is input. In Patent Document 1, in order to compensate for the gain fluctuation caused by the drift of the drain idle current, the attenuation amount of the signal caused by the drain idle current is calculated based on the voltage difference of the drain bias component of the resistor connected in series to the drain. Gain compensation is described.

JP 2010-268393 A

  According to Patent Document 1, gain fluctuation due to drift of the drain idle current is compensated as a result, but the drift of the drain idle current is not compensated. High-frequency high-frequency amplifier circuits are known to perform distortion compensation. However, when the drain idle current drifts, the distortion compensation cannot follow. According to Patent Document 1, compensation for distortion caused by the drift of the drain idle current is not performed. In Patent Document 1, since gain compensation is performed based on the drain bias and drain current value, gain compensation is difficult when a large signal is input. As described above, it is required to directly compensate for the drift of the drain idle current.

  The present invention has been made in view of the above problems, and an object thereof is to directly compensate for the drift of the drain idle current.

  The present invention relates to a method for controlling an electronic circuit including a FET having a gate to which an input signal is input and a drain to which an output signal is output, and a time t has elapsed since the input signal was input to the gate of the FET. Calculating a change amount ΔIdq (t) of the drain idle current corresponding to the input signal x (t) later; calculating a gate bias voltage Vg for compensating the change amount ΔIdq (t); Applying the gate bias voltage to the gate of the FET. According to the present invention, the drain idle current drift can be directly compensated.

  In the above configuration, ΔIdq (t) is calculated using a response function h (τ) = ΔIdq (τ) with respect to time τ after an impulse signal in an analog signal or a unit pulse signal in a digital signal is input to the gate. The drain idle current change amount ΔIdq (t) corresponding to the input signal x (t) after the elapse of time t can be obtained.

を用い、前記変化量ΔＩｄｑ（ｔ）を算出する構成とすることができる。 In the above configuration, the step of calculating the change amount ΔIdq is a response function h (τ) = ΔIdq (τ) of the drain idle current change amount ΔIdq with respect to time τ from when the unit pulse signal in the digital signal is input, sampling When the period corresponds to T, the number of samples corresponds to N, the sample number corresponds to n, and nT corresponds to t,

The change amount ΔIdq (t) can be calculated using.

  The said structure WHEREIN: It can be set as the structure including the step which averages the said input signal for every said sampling period.

を用い、前記変化量ΔＩｄｑ（ｔ）を算出する構成とすることができる。 In the above configuration, the step of calculating the change amount ΔIdq (t) is a response function h (τ) = ΔIdq (τ) of the change amount ΔIdq of the drain idle current with respect to time τ from when the impulse signal in the analog signal is input. When finite time is τ0,

The change amount ΔIdq (t) can be calculated using.

  In the above configuration, the step of calculating the gate bias voltage Vg may be configured using an analog linear amplifier.

  In the above configuration, the FET may be a FET using a nitride semiconductor.

  The present invention relates to an FET having a gate to which an input signal is input and a drain to which an output signal is output, and to the input signal x (t) after time t has elapsed since the input signal was input to the gate of the FET. A first calculation unit for calculating a corresponding change amount ΔIdq (t) of the drain idle current; a second calculation unit for calculating a gate bias voltage Vg for compensating the change amount ΔIdq (t); and the gate bias voltage. And an application unit that applies Vg to the gate of the FET. According to the present invention, the drain idle current drift can be directly compensated.

  In the above configuration, ΔIdq (t) is calculated using a response function h (τ) = ΔIdq (τ) with respect to time τ after an impulse signal in an analog signal or a unit pulse signal in a digital signal is input to the gate. The drain idle current change amount ΔIdq (t) corresponding to the input signal x (t) after the elapse of time t can be obtained.

を用い、前記変化量ΔＩｄｑ（ｔ）を算出する構成とすることができる。 In the above configuration, the first calculation unit has a response function h (τ) = ΔIdq (τ) of a change amount ΔIdq of the drain idle current with respect to a time τ from when the unit pulse signal in the digital signal is input, and a sampling period T When the number of samples is N, the sample number is n, and nT corresponds to t,

The change amount ΔIdq (t) can be calculated using.

  The said structure WHEREIN: It can be set as the structure containing the averaging part which averages the said input signal for every said sampling period.

を用い、前記変化量ΔＩｄｑ（ｔ）を算出する構成とすることができる。 In the above-described configuration, the first calculation unit has a response function h (τ) = ΔIdq (τ) of the change amount ΔIdq of the drain idle current with respect to the time τ from when the impulse signal in the analog signal is input, and sets the finite time to τ0. When

The change amount ΔIdq (t) can be calculated using.

  In the above configuration, the second calculation unit may include an analog linear amplifier.

  In the above configuration, the FET may be a FET using a nitride semiconductor.

  According to the present invention, the drain idle current drift can be directly compensated.

FIG. 1 is a cross-sectional view of an FET used in an amplifier circuit. FIG. 2 is a diagram showing the input signal power Pin and the drain idle current Idq with respect to time. FIG. 3 is a diagram showing the time dependence of the drain idle current Idq with respect to the impulse input. FIG. 4 is a diagram showing the drain idle current Idq with respect to the gate voltage Vg. FIG. 5 is a block diagram of the electronic circuit according to the first embodiment. FIG. 6 is a flowchart illustrating the electronic circuit control method according to the first embodiment. FIG. 7 is a block diagram of an electronic circuit according to the second embodiment. FIG. 8 is a flowchart illustrating the control method of the electronic circuit according to the second embodiment. FIG. 9 is a circuit diagram of an integration circuit that realizes Equation 9. FIG. 10 is a block diagram of an electronic circuit according to the third embodiment. FIG. 11 is a block diagram of an electronic circuit according to the fourth embodiment. FIG. 12 is a block diagram of an electronic circuit according to the fifth embodiment. FIG. 13 is a circuit diagram of an electronic circuit including a Vg converter. FIG. 14 is a schematic diagram of a transmission circuit. FIGS. 15A to 15E are diagrams showing input signals (for example, transmission signals) at the respective locations in FIG.

  First, an FET using a nitride semiconductor will be described as an example of an FET (Field Effect Transistor) used in an electronic circuit. FIG. 1 is a cross-sectional view of an FET used in an amplifier circuit. As shown in FIG. 1, a buffer layer 42, an electron transit layer 44, an electron supply layer 46, and a cap layer 48 are sequentially formed on a substrate 40 to form a nitride semiconductor layer 50. The substrate 40 is a substrate made of, for example, SiC, sapphire, or Si. The buffer layer 42 is an AlN layer having a film thickness of 300 nm, for example. The electron transit layer 44 is a GaN layer having a film thickness of 1000 nm, for example. The electron supply layer 46 is, for example, an n-type AlGaN layer having a thickness of 20 nm. The cap layer 48 is, for example, an n-type GaN layer having a thickness of 5 nm. A gate electrode 54, a source electrode 52 and a drain electrode 56 are formed on the nitride semiconductor layer 50. The gate electrode 54 is disposed between the source electrode 52 and the drain electrode 56 on the upper surface of the nitride semiconductor layer 50. The source electrode 52 and the drain electrode 56 are formed of, for example, a Ta layer and an Al layer from the nitride semiconductor layer 50 side. The gate electrode 54 is formed of, for example, a Ni layer and an Au layer from the nitride semiconductor layer 50 side. An insulating film 58 made of, for example, a silicon nitride film is formed on the nitride semiconductor layer 50 so as to cover the gate electrode 54. The nitride semiconductor layer 50 is not limited to the above layers. For example, InGaN, AlInGaN, InAlN, or the like can be used as the nitride semiconductor layer 50.

  For example, in the FET using the nitride semiconductor layer 50 shown in FIG. 1, different materials of the substrate 40 and the nitride semiconductor layer 50 are bonded. For this reason, for example, a deep electron trap is formed in the nitride semiconductor layer 50 near the bonding surface or the bonding surface. When the electron trap captures or emits electrons, a drain idle current Idq drift occurs.

  Next, the drain idle current Idq drift will be described. FIG. 2 is a diagram showing the input signal power Pin and the drain idle current Idq with respect to time. A nitride semiconductor FET is used for the amplifier circuit. A high frequency input signal Pin is input to the gate, and an amplified signal is output from the drain. The drain current when the input signal is 0 or the power is very small is the drain idle current Idq. In FIG. 2, the drain idle current Idq when the input signal Pin is 0 is Idqo. Idqo corresponds to the drain idle current Idq at the bias point (operating point). A high power signal is input between times t1 and t2. During this time, electrons are trapped in traps in the nitride semiconductor FET. Thereby, the drain idle current Idq becomes small. However, since the high power input signal is input between the times t1 and t2, the drain idle current Idq cannot be measured. When the input signal becomes 0 at time t2, the drain idle current Idq is smaller than Idgo. Thereafter, electrons are emitted from the trap, so that it gradually approaches Idqo. The change in the drain idle current Idq is the drain idle current Idq drift.

  The drift of the drain idle current Idq is caused by the electric field distribution in the FET, in other words, the potential difference. Note that the drift of the drain idle current Idq changes close to an exponential function when it is caused by a single type of trap. On the other hand, in the case of a plurality of types of traps, the drift of the drain idle current Idq is a change in which exponential functions having different time constants are superimposed.

  Next, a method for compensating for the drift of the drain idle current Idq will be described. Here, it is assumed that a change amount ΔIdq of the drain idle current Idq, which is an output from the drain, linearly responds to the input of the electronic circuit of the gate voltage control system. The input of the electronic circuit of the voltage control system may be not only the input signal but also the input signal, the output signal, or other factors as a factor for changing the drain idle current Idq. Further, the amount of change ΔIdq of the drain idle current Idq with respect to the input is not completely linear, and there is also a nonlinear component, but if it is limited to use in a range where a sufficient effect can be obtained even if the nonlinearity is ignored, Non-linear components are negligible. Even if it is limited in this way, the probability that the vicinity of the saturated output where the nonlinearity becomes remarkable in the modulation signal is small as a practical problem is small, so that it is sufficiently practical.

FIG. 3 is a diagram showing the time dependence of the drain idle current Idq with respect to the impulse input. A unit pulse having a sufficiently short width is input as the input signal Pin at time t = 0. The amount of change ΔIdqo from the initial value of the drain idle current Idq is as follows.
ΔIdq (t) = 0 when t <0
ΔIdq (t) = h (t) when t> 0
As described above, the function of the change amount ΔIdq of the drain idle current with respect to the time τ from when the impulse signal in the analog signal is input is defined as a response function h (τ) = ΔIdq (τ).

数式１において、ｈ（ｔ）が既知であれば、入力信号ｘ（ｔ）からΔＩｄｑ（ｔ）が算出できる。ｈ（ｔ）は図３のように、Ｉｄｑのインパルス応答を測定することで得ることができる。ｈ（ｔ）を測定する際は、ドレインアイドル電流Ｉｄｑドリフトの時定数と比べて、入力するパルス幅を十分小さくすれば、近似的にインパルスと考えられる。よって、パルス幅の小さい信号を入力し、近似的にｈ（ｔ）を測定する。パルス振幅幅は、ΔＩｄｑが十分測定できる程度に大きくてもよい。 ΔIdq (t) as an output with respect to the input signal x (t) that changes with time is given by the following Equation 1.

In Formula 1, if h (t) is known, ΔIdq (t) can be calculated from the input signal x (t). h (t) can be obtained by measuring the impulse response of Idq as shown in FIG. When measuring h (t), if the input pulse width is made sufficiently smaller than the time constant of the drain idle current Idq drift, it is considered that the impulse is approximately. Therefore, a signal having a small pulse width is input and h (t) is approximately measured. The pulse amplitude width may be large so that ΔIdq can be measured sufficiently.

入力ｘ（ｔ）およびｈ（ｔ）の時間変化より十分早い周期でサンプリングすることにより、数式３のようにデジタル処理を用い、ΔＩｄｑ（ｔ）を算出できる。

ここで、Ｔはサンプリング周期であり、Ｎはサンプリング数である。すなわちＮ×Ｔはτ０より大きいことが好ましい。 Referring to FIG. 3, if Idq is substantially equal to Idqo at a finite time t = τ 0, as shown in Equation 1, even if time integration is not performed from −infinity to infinity, t = A finite interval may be performed from 0 to τ0.

By sampling at a period sufficiently faster than the time change of the inputs x (t) and h (t), ΔIdq (t) can be calculated using digital processing as in Equation 3.

Here, T is a sampling period, and N is the number of samplings. That is, N × T is preferably larger than τ0.

ΔＩｄｑを補正するためのΔＶｇは数式５となる。

さらに、ΔＩｄｑを補正するためのゲート電圧Ｖｇは数式６となる。

以上のように、用いるＦＥＴに対し、予めｈ（ｔ）およびｆ（ΔＶｇ）を測定しておけば、ドレインアイドル電流Ｉｄｑドリフトの補正が可能となる。 Next, the drain idle current Idq with respect to the gate voltage Vg in the FET will be described. FIG. 4 is a diagram showing the drain idle current Idq with respect to the gate voltage Vg. Vgo indicates the gate voltage at the bias point. The drain idle current Idq at the bias point is Idqo. In order to compensate for the change amount ΔIdq of the drain idle current Idq from Idqo, a gate voltage Vg obtained by changing the change amount ΔVg from Vgo may be applied to the gate. As shown in FIG. 4, the relationship between ΔIdq and ΔVg has a one-to-one correspondence, and can be expressed as Equation 4 using a monotone function f.

ΔVg for correcting ΔIdq is given by Equation 5.

Further, the gate voltage Vg for correcting ΔIdq is expressed by Equation 6.

As described above, if h (t) and f (ΔVg) are measured in advance for the FET to be used, the drain idle current Idq drift can be corrected.

  The first embodiment is an example in which the drain idle current Idq drift is corrected using a baseband digital signal. FIG. 5 is a block diagram of the electronic circuit according to the first embodiment. As shown in FIG. 5, the electronic circuit 100 includes an amplifier 12, a delay circuit 14, a D / A converter 16, a mixer 18, a local oscillator 20, a shift register 22, a weighted integrator 24, a Vg converter 26, a D / A. A converter 28 and an application unit 30 are provided. The amplifier 12 includes an FET 10 having a gate for receiving an input signal and a drain for outputting an output signal.

  A baseband digital input signal is input from the input terminal Tin. The input signal is branched to the delay circuit 14 and the shift register 22. The delay circuit 14 delays the input signal. The D / A converter 16 converts the digital signal into an analog signal. The mixer 18 mixes the input signal with the carrier wave oscillated by the local oscillator 20 and up-converts the input signal into a high-frequency signal. The application unit 30 applies a high-frequency signal and a gate bias voltage Vg (DC component voltage) superimposed on the gate of the FET 10.

  The shift register 22 sequentially stores past digital input signals. For example, N input signals are stored. The weighted integrator 24 calculates ΔIdq from N pieces of data acquired at the sampling period T. Here, the sampling period T is the same as the sampling period of the baseband signal, for example. The shift register 22 and the weighted integrator 24 function as the first calculation unit 23. The Vg converter 26 calculates the gate voltage Vg for correcting ΔIdq using Equation 6. The D / A converter 28 converts the gate voltage Vg into an analog value. The Vg converter 26 and the D / A converter 28 function as the second calculator 27. The delay circuit 14 has a delay time in order to match the timing at which the gate bias voltage Vg and the input signal are applied to the gate.

ここで、Ｔはサンプリング周期、Ｎはサンプリング数、ｎはサンプル番号である。ｎ＝０はｔ＝０に相当する。デジタル信号における単位パルス信号が入力してからの時間τに対するドレインアイドル電流の変化量ΔＩｄｑの関数がｈ（τ）＝ΔＩｄｑ（τ）である。単位パルス信号は、パルス幅がサンプリング周期Ｔ、大きさが１のパルス信号である。サンプリング周期ＴがＩｄｑドリフトの時定数より十分に小さい場合は、数式７を適用できる。 FIG. 6 is a flowchart illustrating the electronic circuit control method according to the first embodiment. As shown in FIG. 6, first, the weighted integrator 24 has a drain idle current change amount ΔIdq (t corresponding to the input signal x (t) after a lapse of time t after the input signal is input to the gate of the FET. ) Is calculated (step S10). For example, the weighted integrator 24 uses the response function h (τ) = ΔIdq (τ) (see FIG. 3), and calculates the change amount ΔIdq (t) of the drain idle current corresponding to the input signal x (t) at time t. calculate. For example, ΔIdq (t) is calculated using Equation 7. For example, when the input signal is a baseband digital signal and is a discrete signal x (n), Equation 3 is expressed as Equation 7.

Here, T is a sampling period, N is the number of samplings, and n is a sample number. n = 0 corresponds to t = 0. A function of the change amount ΔIdq of the drain idle current with respect to time τ after the unit pulse signal in the digital signal is input is h (τ) = ΔIdq (τ). The unit pulse signal is a pulse signal whose pulse width is the sampling period T and whose size is 1. When the sampling period T is sufficiently smaller than the time constant of Idq drift, Equation 7 can be applied.

  Next, the Vg converter 26 calculates a gate bias voltage Vg for compensating for the change amount ΔIdq (t) (step S12). For example, the gate bias voltage Vg is calculated using Equation 6. Next, the application unit 30 applies a gate bias voltage to the gate of the FET 10 (step S14). Then exit. The above is repeated every sampling time T.

  If h (τ) is too small for the unit pulse signal to measure h (τ) in advance, the unit pulse size is multiplied by K in the linear range, the response waveform is 1 / K, and h (τ) can be measured.

  According to the first embodiment, the response function h (τ) and the function f (ΔVg) are measured in advance. As in step S10, ΔIdq (t) corresponding to the input signal x (t) is calculated. For example, ΔIdq (t) is calculated using the response function h (τ). As in step S12, Vg is calculated using f (ΔVg). Vg is applied to the gate of the FET 10 as in step S14. Thereby, the drift of the drain idle current Idq can be directly corrected.

  Thus, in step S10, when h (τ) = ΔIdq (τ), the sampling period is T, the number of samples is N, the sample number is n, and nT corresponds to t, the amount of change ΔIdq is calculated using Equation 7. (T) can be calculated.

  For example, in an amplifier circuit that performs distortion compensation, if the drain idle current Idq drifts, the distortion compensation does not function. Therefore, the drain idle current Idqo at the bias point is set large. Thereby, even if the drain idle current Idq drifts, the influence on the distortion compensation can be reduced. However, since Idqo is increased, power consumption is increased. According to the first embodiment, since the drift of the drain idle current Idq can be directly corrected, the influence on the distortion compensation is small. For this reason, since Idqo can be reduced, power consumption can be reduced.

  In the first embodiment, the sampling period of the weighted integrator 24 is the baseband sampling period. The second embodiment is an example in which the sampling period of the weighted integrator 24 is different from the baseband sampling period. In general, the optimum sampling period for digital processing for compensating for Idq drift is considered to be different from the sampling period of the baseband signal. FIG. 7 is a block diagram of an electronic circuit according to the second embodiment. As shown in FIG. 7, the electronic circuit 102 includes an averaging unit 32. The averaging unit 32 averages the baseband signal for the sampling period used by the weighted integrator 24. For example, the sampling signal of the baseband signal is about 10 nsec. On the other hand, the time constant of the drain idle current Idq drift is, for example, several tens of milliseconds to several tens of seconds. In this case, it is sufficient that the sampling period T of the weighted integrator 24 is about sub m seconds. Therefore, the averaging unit 32 averages the baseband input signal every sampling period T of the weighted integrator 24. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 8 is a flowchart illustrating the control method of the electronic circuit according to the second embodiment. As shown in FIG. 8, the averaging unit 32 averages the baseband input signal for each sampling period T of the weighted integrator 24 (step S16). The subsequent processing is the same as that in FIG.

  According to the second embodiment, the averaging unit 32 averages the baseband input signal for each sampling period T of the weighted integrator 24. Thereby, the sampling period T of the weighted integrator 24 can be lengthened. Thus, the burden on the weighted integrator 24 can be reduced.

ここで、τはトラップの時定数である。よって、数式１は数式９のように表される。

図９は、数式９を実現する積分回路の回路図である。図９に示すように。積分回路３８は、入力端と出力端との間に抵抗Ｒが直列に接続され、キャパシタＣが出力端とグラウンドとの間に接続されている。入力端の電圧Ｖｉｎ（ｔ）、出力端の電圧Ｖｃ（ｔ）とすると、Ｖｃ（ｔ）は数式１０のように表される。

ここで、Ｒは抵抗Ｒの抵抗値、ＣはキャパシタＣのキャパシタンスである。 The third embodiment is an example in which the drain idle current Idq drift is corrected using a baseband analog signal. In this example, the function of the weighted integrator 24 is realized using an analog integration circuit. When there is one kind of trap that contributes to the drain idle current Idq drift, ΔIdq changes almost exponentially. In this case, h (t) can be assumed as in Expression 8.

Here, τ is a time constant of the trap. Therefore, Formula 1 is expressed as Formula 9.

FIG. 9 is a circuit diagram of an integration circuit that realizes Equation 9. As shown in FIG. In the integrating circuit 38, a resistor R is connected in series between the input end and the output end, and a capacitor C is connected between the output end and the ground. Assuming that the voltage Vin (t) at the input terminal and the voltage Vc (t) at the output terminal, Vc (t) is expressed as Equation 10.

Here, R is the resistance value of the resistor R, and C is the capacitance of the capacitor C.

ここで、Ａは係数である。 By setting the resistance value R and the capacitance C so that RC = τ, the integration circuit 38 can be used as a circuit for calculating Formula 9. From Equation 9 and Equation 10, ΔIdq (t) is expressed as Equation 11 using Vc (t).

Here, A is a coefficient.

  FIG. 10 is a block diagram of an electronic circuit according to the third embodiment. As shown in FIG. 10, the electronic circuit 104 includes an integration circuit 38 and an A / D converter 66 instead of the shift register 22 and the weighted integrator 24 of FIG. 5 of the first embodiment. The integration circuit 38 functions as the first calculation unit 23. In the third embodiment, a baseband analog input signal is input to the input terminal Tin. The coupler 60 branches the input signal. One of the branches is up-converted to a carrier frequency by the mixer 18 and is input to the applying unit 30 via the delay circuit 62. The other branched part is input to the integrating circuit 38 via the delay circuit 64. The integrating circuit 38 calculates ΔIdq (t) in an analog manner as shown in Equation 11. The A / D converter 66 converts an analog signal into a digital signal. The A / D converter 66, the Vg converter 26, and the D / A converter 28 function as the second calculator 27. The delay time of the delay circuit 62 and the delay circuit 64 is set so that the timing of the input signal and the gate bias voltage Vg matches. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  The fourth embodiment is an example in which the drain idle current Idq drift is corrected using an analog signal after up-conversion. FIG. 11 is a block diagram of an electronic circuit according to the fourth embodiment. As illustrated in FIG. 11, in the electronic circuit 106 according to the fourth embodiment, the coupler 60 is disposed at the subsequent stage of the mixer 18. That is, the coupler 60 branches the high-frequency signal after up-converting the baseband signal. A detector 68 is provided between the delay circuit 64 and the integration circuit 38. The detector 68 includes a diode D and a resistor R2. The detector 68 detects the envelope of the high frequency signal. The integration circuit 38 calculates ΔIdq (t) based on the envelope. Other configurations are the same as those of the third embodiment, and the description thereof is omitted.

  The fifth embodiment is an example in which the drain idle current Idq drift is corrected using a high-frequency analog signal amplified by an amplifier. FIG. 12 is a block diagram of an electronic circuit according to the fifth embodiment. As illustrated in FIG. 12, in the electronic circuit 108 according to the fifth embodiment, the coupler 60 is disposed at the subsequent stage of the amplifier 12. That is, the coupler 60 branches the high frequency signal amplified by the amplifier 12. The detector 68 detects the envelope of the high frequency signal. The integration circuit 38 calculates ΔIdq (t) based on the envelope. Other configurations are the same as those of the fourth embodiment shown in FIG.

  According to the third to fifth embodiments, when the response function h (τ) = ΔIdq (τ) and the finite time is τ0, the change amount ΔIdq (t) can be calculated using Equation 2. As the first calculation unit 23, for example, the change amount ΔIdq (t) can be calculated using the analog integration circuit 38.

  The sixth embodiment is an example in which the second calculation unit 27 in the first to fifth embodiments is realized using an analog circuit. Here, it is assumed that the relationship between ΔIdq and ΔVg can be approximated linearly. In this case, Equation 6 is expressed as Vg = Vgo + (1 / k) × (−ΔIdq).

  FIG. 13 is a circuit diagram of an electronic circuit including a Vg converter. As shown in FIG. 13, the circuit 70 includes operational amplifiers 72, 74 and 76. The operational amplifier 72 is a voltage follower circuit, and outputs the same voltage Vc as the voltage Vc (corresponding to ΔIdq) input to the terminal T1. The operational amplifier 74 outputs − (A / k) × Vc. Here, the resistance values of the resistors R11 and R12 are set so that R12 / R11 = A / k. The operational amplifier 76 outputs Vg = Vg + (A / k) × Vc to the terminal T2. Here, the resistance values of the resistors R21 and R22 are made equal. A voltage of Vgo / 2 is input to the positive input. Here, when ΔIdq = −AVc, Vg = Vgo + (1 / k) (− ΔIdq). Therefore, the gate bias voltage Vg for correcting ΔIdq can be output to the application unit 30. Other configurations are the same as those of the third to fifth embodiments, and the description thereof is omitted.

  According to the sixth embodiment, an analog linear amplifier can be used as the second calculation unit 27 in the first to fifth embodiments.

  FIG. 14 is a schematic diagram of the transmission circuit, and each example shows which signal of the transmission circuit is used to compensate for the drift of the drain idle current. FIG. 15A to FIG. 15E are diagrams showing input signals (for example, transmission signals) at the respective locations in FIG. As shown in FIG. 14, the transmission circuit includes a D / A converter 80, a low-pass filter 82, a mixer 18, a local oscillator 20, and an amplifier 12. The signal input to the input terminal Tin is a baseband digital signal x (n). The signal x (n) is a signal obtained by digitizing the wave height for each sampling period T. It is a signal in which numerical values (wave heights) from n = 0 to N−1 are arranged as a number sequence with respect to time t. In FIG. 15A, a waveform corresponding to a baseband analog signal is indicated by a broken line. Each wave height in the sampling period is indicated by an up arrow.

  As shown in FIG. 15B, the output signal x1 (t) of the D / A converter 80 is a signal obtained by converting x (n) into a stepped signal. As shown in FIG. 15C, the output signal x (t) of the low-pass filter 82 is a continuous function of time and corresponds to a baseband analog signal.

  The output signal of the mixer 18 is up-converted to a carrier wave. FIG. 15D shows an envelope x2 (t) of the output signal of the mixer 18. FIG. 15E shows an envelope x3 (t) of the output signal of the amplifier 12.

  As illustrated in FIG. 14, the first and second embodiments are examples in which the drain idle current Idq drift is corrected using the baseband digital signal illustrated in FIG. The third embodiment is an example in which the drain idle current Idq drift is corrected using the baseband analog signal shown in FIG. The fourth embodiment is an example in which the drain idle current Idq drift is corrected using the envelope of the high-frequency analog signal output from the mixer 18 shown in FIG. The fifth embodiment is an example in which the drain idle current Idq drift is corrected using the envelope of the high-frequency analog signal output from the amplifier 12 shown in FIG.

  In this way, the first calculation unit 23 calculates ΔIdq (t) corresponding to the input signal x (t) at time t using h (τ) from the signal at any location of the transmission circuit of FIG. Also good.

  It is important that the control in the first to sixth embodiments is adjusted so that the average output of the amplifier 12 is most effective in the output power region where the average output is approximately greater than the saturated power −20 dBm. This is because the drain idle current Idq drift becomes a problem in such output power.

  In the first to sixth embodiments, the nitride semiconductor FET has been described as an example of the FET that is likely to cause the drain idle current Idq drift. Examples 1 to 5 can also be used for GaAs FETs and SiFETs. The nitride semiconductor FET is an FET including, for example, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and / or InAlN. The GaAs-based FET is an FET including, for example, GaAs, InAs, AlAs, InGaAs, AlGaAs, and / or InAlGaAs. The SiFET is, for example, a MOS (Metal Oxide Semiconductor) FET using Si.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 FET
DESCRIPTION OF SYMBOLS 12 Amplifier 23 1st calculation part 27 2nd calculation part 38 Integration circuit 70 Circuit

Claims (14)

A method for controlling an electronic circuit including a FET having a gate for inputting an input signal and a drain for outputting an output signal,
Calculating a drain idle current change amount ΔIdq (t) corresponding to the input signal x (t) after a lapse of time t after the input signal is input to the gate of the FET;
Calculating a gate bias voltage Vg for compensating for the variation ΔIdq (t);
Applying the gate bias voltage to the gate of the FET;
A method for controlling an electronic circuit, comprising:   The ΔIdq (t) is calculated using a response function h (τ) = ΔIdq (τ) with respect to a time τ after an impulse signal in an analog signal or a unit pulse signal in a digital signal is input to the gate, and the time t has elapsed. 2. The method of controlling an electronic circuit according to claim 1, wherein the electronic circuit control method is performed by obtaining a change amount ΔIdq (t) of a drain idle current corresponding to the input signal x (t) later. The step of calculating the change amount ΔIdq includes a response function h (τ) = ΔIdq (τ) of a change amount ΔIdq of the drain idle current with respect to a time τ after the unit pulse signal in the digital signal is input, When the number of samples is N, the sample number is n, and nT is t,

The method of controlling an electronic circuit according to claim 1, wherein the change amount ΔIdq (t) is calculated using   4. The method of controlling an electronic circuit according to claim 3, further comprising the step of averaging the input signal for each sampling period. The step of calculating the change amount ΔIdq (t) includes a response function h (τ) = ΔIdq (τ) of a drain idle current change amount ΔIdq with respect to time τ from when the impulse signal in the analog signal is input, and a finite time. Is τ0,

The method of controlling an electronic circuit according to claim 1, wherein the change amount ΔIdq (t) is calculated using   6. The electronic circuit control circuit according to claim 1, wherein the step of calculating the gate bias voltage Vg uses an analog linear amplifier.   The method of controlling an electronic circuit according to claim 1, wherein the FET is an FET using a nitride semiconductor. An FET having a gate for receiving an input signal and a drain for outputting an output signal;
A first calculator that calculates a change amount ΔIdq (t) of a drain idle current corresponding to the input signal x (t) after a lapse of time t since the input signal is input to the gate of the FET;
A second calculator for calculating a gate bias voltage Vg for compensating for the change amount ΔIdq (t);
An application unit for applying the gate bias voltage Vg to the gate of the FET;
An electronic circuit comprising:   The ΔIdq (t) is calculated using a response function h (τ) = ΔIdq (τ) with respect to a time τ after an impulse signal in an analog signal or a unit pulse signal in a digital signal is input to the gate, and the time t has elapsed. 9. The electronic circuit according to claim 8, wherein the electronic circuit is obtained by calculating a change amount ΔIdq (t) of a drain idle current corresponding to the input signal x (t) later. The first calculation unit includes a response function h (τ) = ΔIdq (τ) of the change amount ΔIdq of the drain idle current with respect to time τ from when the unit pulse signal in the digital signal is input, T is the sampling period, and the number of samples N, sample number n, and nT correspond to t,

The electronic circuit according to claim 8, wherein the change amount ΔIdq (t) is calculated by using.   9. The electronic circuit according to claim 8, further comprising an averaging unit that averages the input signal for each sampling period. When the first calculation unit has a response function h (τ) = ΔIdq (τ) of the change amount ΔIdq of the drain idle current with respect to time τ from when the impulse signal in the analog signal is input, and finite time is τ0,

The electronic circuit according to claim 8, wherein the change amount ΔIdq (t) is calculated by using.   The electronic circuit according to claim 8, wherein the second calculation unit includes an analog linear amplifier.   The method of controlling an electronic circuit according to claim 8, wherein the FET is an FET using a nitride semiconductor.

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