JP2013069862A - Magnetoresistance effect element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit malfunction of a magnetic memory.SOLUTION: A magnetoresistance effect element of an element comprises: a storage layer having perpendicular magnetic anisotropy and a variable magnetization direction; a reference layer having perpendicular magnetic anisotropy and an invariable magnetization direction; a non-magnetic layer 11 between the storage layer and the reference layer; and a shift adjustment layer having an invariable magnetization direction. The reference layer includes a first temperature dependence LM1 of magnetization and the shift adjustment layer includes a second temperature dependence LM2 of magnetization different from that of the reference layer. A leak field of the reference layer and a leak field of the shift adjustment layer are cancelled with each other under a memory operation temperature. A shift magnetic field caused by one of a leak field of the reference layer and a leak field of the shift adjustment layer is applied to magnetization of the storage layer under a mounting temperature.

Description

  Embodiments described herein relate generally to a magnetoresistive element.

  In order to realize a magnetic memory using a TMR (Tunnel Magneto Resistive) element, various techniques have been proposed.

  As one of them, “1” or “0” data is recorded in the MTJ element so as to correspond to the magnetization arrangement state of the MTJ (Magnetic Tunnel Junction) element, and based on the difference in the resistance value of the element due to the TMR effect, There is a method for reading data.

  As a method of reversing the magnetization of the magnetic layer of the MTJ element, that is, the method of reversing the magnetization of the MTJ element caused by passing a spin-polarized current through the MTJ element from the viewpoint of miniaturization and low current (Hereinafter referred to as the spin injection magnetization reversal method) has attracted attention.

  For reading out data from a magnetic memory, there is a method of forming a resistance value (potential or current) as a determination standard using a reference cell or replica cell and comparing the determination standard with the resistance value of the MTJ element of the memory cell. Used.

  In the magnetic memory, the problem of thermal disturbance of the magnetic material becomes obvious as the element is miniaturized. Due to this thermal disturbance, if the magnetization of the magnetic layer of the MTJ element in the reference cell and the replica cell is unintentionally reversed, a malfunction may occur in data determination (data reading). is there.

Z. Li, and S. Zhang, “Thermally assisted magnetization reversal in the presence of spin-transfer torque”, Physical Review B, Vol. 69, 134416 (2004)

  We propose a technique to suppress the malfunction of magnetic memory.

  The magnetoresistive effect element according to the present embodiment includes a storage layer having perpendicular magnetic anisotropy and a variable magnetization direction, a reference layer having perpendicular magnetic anisotropy and a magnetization direction invariable, and the memory A non-magnetic layer between the reference layer and the reference layer, and a side of the reference layer opposite to the side on which the non-magnetic layer is provided, and has perpendicular magnetic anisotropy and the magnetization direction is unchanged. The reference adjustment layer has a first magnetization temperature dependency, and the shift adjustment layer has a second magnetization temperature dependency different from the first magnetization temperature dependency. The leakage magnetic field of the reference layer and the leakage magnetic field of the shift adjustment layer are canceled from each other at the memory operating temperature, and the shift magnetic field caused by one of the reference layer and the shift adjustment layer at the mounting temperature is stored in the memory. Applied to the magnetization of the layer.

The figure for demonstrating the structure of the magnetic memory containing the magnetoresistive effect element of embodiment. The figure for demonstrating the structure of the magnetic memory containing the magnetoresistive effect element of embodiment. The figure for demonstrating the structure of the magnetic memory containing the magnetoresistive effect element of embodiment. The figure for demonstrating the structure of the magnetic memory containing the magnetoresistive effect element of embodiment. The figure for demonstrating the magnetoresistive effect element of 1st Embodiment. The figure for demonstrating the magnetoresistive effect element of 1st Embodiment. The figure which shows the specific example of the magnetoresistive effect element of 1st Embodiment. The figure which shows the specific example of the magnetoresistive effect element of 1st Embodiment. The figure which shows the specific example of the magnetoresistive effect element of 1st Embodiment. The figure for demonstrating the magnetoresistive effect element of 2nd Embodiment. The figure for demonstrating the magnetoresistive effect element of 2nd Embodiment. The figure for demonstrating the magnetoresistive effect element of 2nd Embodiment. The figure for demonstrating the magnetoresistive effect element of 2nd Embodiment.

[Embodiment]
Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

(1) First embodiment
The magnetoresistive effect element according to the first embodiment will be described with reference to FIGS.

(A) Configuration
The configuration of the magnetoresistive effect element according to the first embodiment will be described with reference to FIGS. For example, the magnetoresistive effect element of the first embodiment is used as a memory element of a magnetic memory.

<Overall configuration>
A configuration of a magnetic memory including the magnetoresistive effect element according to the present embodiment will be described with reference to FIGS.

  FIG. 1 schematically shows a configuration of a package device 200 including a magnetic memory 100.

  The chip of the magnetic memory 100 including the magnetoresistive effect element of this embodiment is mounted in the package device 200. The magnetic memory 100 is sealed in an insulator (package) 210. In the package device 200, the chip of the magnetic memory 100 is connected to the external connection terminal 290 of the package device 200 via a bonding wire, a lead frame, or a metal bump (for example, a copper bump). For example, a solder ball (or solder bump) 290 is used for the external connection terminal 290.

  The package device 200 including the magnetic memory 100 is mounted on the mounting substrate 300. The package device 200 is connected to connection terminals (or wirings) 390 on the mounting substrate 300 by solder balls 290 as external connection terminals. Thus, the magnetic memory is connected to another chip or element (not shown) on the mounting substrate 300, and a memory system (for example, a memory card or SSD) or a system LSI including the magnetic memory is formed.

FIG. 2 schematically shows a layout example of the chip of the magnetic memory 100.
In the present embodiment, the magnetic memory 100 is, for example, an MRAM (Magnetoresistive Random Access Memory). However, the ROM may be formed using the magnetoresistive effect element of this embodiment.

  As shown in FIG. 2, in the magnetic memory 100, the memory cell array 30 is provided in a chip (semiconductor substrate) 70.

  A plurality of cells 20 are provided in the memory cell array 30. Each cell 20 includes at least one magnetoresistance effect element 1A and at least one selection element 2.

  FIG. 3 is an equivalent circuit diagram showing an example of the internal configuration of the memory cell array 30.

  As shown in FIG. 3, the memory cell array 30 includes a plurality of cells 20.

  The plurality of cells 20 are arranged in an array in the memory cell array 30. In the memory cell array 30, a plurality of bit lines BL, bBL and a plurality of word lines WL are provided. The bit lines BL and bBL extend in the column direction, and the word line WL extends in the row direction. The two bit lines BL and bBL form one bit line pair.

  The cell 20 is connected to the bit lines BL and bBL and the word line WL.

  The plurality of cells 20 arranged in the column direction are connected to a common bit line pair BL, bBL. The plurality of cells 20 arranged in the row direction are connected to a common word line WL.

  The cell 20 includes, for example, one magnetoresistive effect element 1A and one selection element 2. The magnetoresistive effect element 1A is, for example, an MTJ (Magnetic Tunnel Junction) element.

  The selection switch 2 is, for example, a field effect transistor. Hereinafter, the field effect transistor as the selection switch 2 is referred to as a selection transistor 2. In the present embodiment, the cell 20 that stores data from the outside is referred to as a memory cell MC.

  One end of the MTJ element 1A is connected to the bit line BL, and the other end of the MTJ element 1A is connected to one end (source / drain) of the current path of the selection transistor 2. The other end (drain / source) of the current path of the selection transistor 2 is connected to the bit line bBL. A control terminal (gate) of the selection transistor 2 is connected to the word line WL.

  FIG. 4 is a schematic diagram for explaining a cross-sectional structure of the cell 20 including the MTJ element 1A of the present embodiment.

  As shown in FIG. 4, the cell 20 is formed in the active area AA of the semiconductor substrate 70. The active area AA is partitioned by an insulating film 71 embedded in the element isolation region of the semiconductor substrate 70.

  The selection transistor 2 is provided on the active area AA.

  The two source / drain diffusion layers 63 and 64 of the selection transistor 2 are provided in the active area AA (semiconductor substrate 70). A gate insulating film 61 is provided on the surface of the active area AA between the two source / drain diffusion layers 63 and 64. The gate electrode 62 is provided on the gate insulating film 61. As shown in FIG. 3, the gate electrode 62 extends in the row direction and is used as the word line WL.

  The source / drain diffusion layer 63 of the select transistor 2 is connected to the bit line 75 (bBL) via a contact plug 72A embedded in the interlayer insulating film 79A. The source / drain diffusion layer 64 of the select transistor 2 is connected to the MTJ element 1A via a contact plug 72B embedded in the interlayer insulating films 79A and 79B.

  The MTJ element 1A has a laminated structure including at least two magnetic layers and a nonmagnetic layer (tunnel barrier layer) between two magnetic layers. Of the two magnetic layers included in at least the MTJ element 1A, one magnetic layer is called a storage layer (also called a magnetization free layer, a free layer, or a recording layer), and the other magnetic layer is a reference layer (a magnetization invariant layer, a fixed layer). It is also called a layer). The storage layer has reversible (variable) magnetization. The reference layer has a fixed (invariant) magnetization. Details of the structure of the MTJ element 1A of the present embodiment will be described later.

  The upper end of the MTJ element 1A is connected to the bit line 76 (BL) through the upper electrode 52. The lower end of the MTJ element 1A is connected to the source / drain diffusion layer 64 of the selection transistor 2 through the lower electrode 51 and the contact plug 72B.

  The MTJ element 1A is provided immediately above the plug 72B. However, the MTJ element 1A may be disposed at a position shifted from immediately above the contact plug (for example, above the gate electrode of the selection transistor) using the intermediate wiring layer. The MTJ element 1A is provided in the interlayer insulating film 79C.

  FIG. 4 shows an example in which one cell 20 is provided in one active area AA. However, two cells may be provided in one active area AA so that the two cells share one contact plug 72A and the source / drain diffusion layer 63. As a result, the size of the cell 20 is reduced. In FIG. 4, a planar structure field effect transistor is shown as the selection transistor 2, but the structure of the field effect transistor is not limited to this. For example, a three-dimensional field effect transistor such as RCAT (Recess Channel Array Transistor) or FinFET may be used as the selection transistor.

The row control circuit 32 is provided in the chip 70 so as to be adjacent to the memory cell array 30 in the row direction. The column control circuit 33 is provided in the chip 70 so as to be adjacent to the memory cell array 30 in the column direction.
The row control circuit 32 controls the rows of the memory cell array 30. The row control circuit 32 is connected to one end of the word line WL. The row control circuit 32 controls activation / inactivation of the word line based on an external address signal.

  The column control circuit 33 controls the columns of the memory cell array 30. The column control circuit 33 is connected to one end and the other end of the bit line. The column control circuit 33 controls activation / deactivation of the bit line based on an external address signal.

  The memory cell MC (20) activated by the row control circuit 32 and the column control circuit 33 is accessed from the outside (memory controller or host) as a selected cell.

  In the vicinity of the memory cell array 30, a write circuit 35 and a read circuit 36 are provided in the chip 70.

  The write circuit 35 is connected to one end and the other end of the bit line via the column control circuit 33. The write circuit 35 includes a source circuit such as a current source or a voltage source for generating the write current Iw, and a sink circuit for absorbing the write current Iw.

  The read circuit 36 is connected to one end of the bit line via the column control circuit 33. The read circuit 36 includes a current source or voltage source for generating a read current Ir, a sense amplifier 37 that detects and amplifies a read signal, a latch circuit that temporarily holds data, and the like.

  For example, a circuit (hereinafter referred to as a peripheral circuit 39) other than the row / column control circuits 32 and 33, the write circuit 35, and the read circuit 36 is provided in the same chip 70 as the memory cell array 30. For example, a buffer circuit, a state machine (control circuit), an ECC (Error Checking and Correcting) circuit, or the like is provided in the chip 70 as the peripheral circuit 39.

<Operation>
(Write operation)
A data write operation in the MTJ element 1A of the present embodiment and the magnetic memory including the MTJ element 1A will be described.

  For example, the spin-transfer magnetization reversal method (Spin-Torque-Transfer) is used to write data in the MTJ element 1A of the present embodiment and a magnetic memory (eg, MRAM) including the MTJ element 1A.

  In the spin-injection magnetization switching MRAM, the write circuit 35 supplies a write current Iw to a cell selected as a write target (hereinafter referred to as a selected cell) when writing data.

  The write circuit 35 causes the write current Iw to flow bidirectionally through the MTJ element 1A in the memory cell MC according to the data written to the selected cell. That is, the write current Iw from the bit line BL to the bit line bBL or the write current Iw from the bit line bBL to the bit line BL is output from the write circuit 35 according to the data to be written.

  In the MTJ element 1A of the present embodiment, the relative magnetization directions of the storage layer and the reference layer are reversed by, for example, the spin injection magnetization reversal method. The direction of magnetization of the storage layer of the MTJ element 1A is changed by the spin torque caused by the write current Iw passed through the MTJ element 1A. In other words, the magnetization direction of the storage layer changes when spin-polarized electrons included in the write current Iw act on the magnetization (spin) of the storage layer.

  Here, “the magnetization direction of the reference layer is in a fixed state” or “the magnetization direction of the reference layer is invariable” means that the magnetization reversal threshold value for reversing the magnetization direction of the storage layer is not less than This means that when a current (magnetization reversal current) flows through the reference layer, the magnetization direction of the reference layer does not change.

Therefore, in the MTJ element 1A, a magnetic layer having a large magnetization reversal threshold is used as a reference layer, and a magnetic layer having a reversal threshold smaller than that of the reference layer is used as a storage layer. As a result, the MTJ element 1A including the storage layer whose magnetization direction is variable and the reference layer whose magnetization direction is fixed is formed.
Further, the write current Iw has a current value equal to or higher than the inversion threshold value of the storage layer and a current value smaller than the inversion threshold value of the reference layer.

When the magnetization direction of the storage layer is made parallel (P: Parallel) to the magnetization direction of the reference layer, that is, when the magnetization direction of the storage layer is made the same as the magnetization direction of the reference layer, the storage layer A current Iw flowing from the first to the reference layer is supplied to the MTJ element 1A.
In this case, electrons move from the reference layer toward the storage layer via the tunnel barrier layer. Of the electrons that have passed through the reference layer and the tunnel barrier layer and moved to the storage layer, majority electrons (spin-polarized electrons) have the same direction as the magnetization (spin) of the reference layer. The spin angular momentum (spin torque) of the spin-polarized electrons is applied to the magnetization of the storage layer, and the magnetization of the storage layer is reversed in the same direction as the magnetization direction of the reference layer. When the magnetization arrangement of the MTJ element 1A is a parallel arrangement (parallel state), the resistance value of the MTJ element 1A is the smallest.

When the magnetization direction of the storage layer is antiparallel (AP) with the magnetization direction of the reference layer, that is, when the magnetization direction of the storage layer is opposite to the magnetization direction of the reference layer The current Iw flowing from the reference layer toward the storage layer is supplied to the MTJ element 1A.
In this case, electrons move from the storage layer toward the reference layer. Electrons having spins antiparallel to the magnetization direction of the reference layer are reflected by the reference layer. The reflected electrons are injected into the storage layer as spin-polarized electrons. The spin torque of the spin-polarized electrons (reflected electrons) is applied to the magnetization of the storage layer, and the magnetization of the storage layer is reversed in the direction opposite to the magnetization direction of the reference layer. When the magnetization arrangement of the MTJ element 1A is an antiparallel arrangement (antiparallel state), the resistance value of the MTJ element 1A is the largest.

  For example, the MTJ element 1A having a small resistance value (magnetization array is in a parallel state) is associated with the “0” data holding state (first stable state) and has a high resistance value (the magnetization array is in an antiparallel state). The MTJ element 1A is associated with the “1” data holding state (second stable state).

(Read operation)
A data read operation in the MTJ element 1A of the present embodiment and the magnetic memory including the MTJ element 1A will be described.

  In reading data from the MTJ element 1A and the magnetic memory (MRAM) including the MTJ element 1A according to the present embodiment, for example, the sense amplifier 37 of the read circuit 36 receives a signal (potential) and a reference signal from the selected cell to be read. By comparing the magnitude relationship with (reference potential), the MTJ element 1A in the selected cell is in the “0” data holding state (magnetization parallel state, low resistance state) or the “1” data holding state (magnetization counter-current). Whether it is a parallel state or a high resistance state).

  At the time of data reading, a signal (read signal) from the selected cell is generated by flowing a read current Ir in the MTJ element 1A in the selected cell. The magnitude of the signal based on the read current Ir flowing through the MTJ element 1A varies according to the resistance value of the MTJ element 1A. A signal (potential or current) based on the read current Ir flowing through the MTJ element 1A is input to the sense amplifier 37.

  The current value of the read current Ir is set to a value smaller than the current value (reversal threshold value) of the write current Iw so that the magnetization of the storage layer is not reversed by the read current.

  A reference signal (standard signal) at the time of data reading is generated using a cell called a reference cell or a replica cell. When data is read from the MRAM, a combined resistance for comparison with the resistance value of the MTJ element is formed using the reference cell and the replica cell, or an applied potential is generated for the bit line to which the reference cell is connected.

  As described above, reading of data from the MRAM may be executed using the reference cell and the replica cell. Therefore, as shown in FIGS. 2 and 3, in the memory cell array 30, a memory cell MC for storing data from the outside and a reference cell / replica cell RC for generating a reference potential are provided. Hereinafter, when the reference cell and the replica cell are not distinguished, the reference cell and the replica cell are referred to as a reference potential generation cell.

  In the memory cell array 30, the region 31A in which the memory cell MC is provided is called a memory cell region 31A, and the region 31B in which the reference potential generation cell RC is provided is called a reference potential generation cell region 31B.

  The memory cell MC and the reference potential generation cell RC are formed by substantially the same process and have substantially the same structure. That is, the reference potential generation cell RC includes the MTJ element 1A of this embodiment and the selection transistor 2, and has the same structure as the cell (memory cell) 20 shown in FIG.

  The reference potential generating cell RC such as the reference cell and the replica cell is not a target for data writing from the outside. However, in order to form a reference potential generating cell RC having a predetermined resistance value for reading data, is the reference potential generating cell RC in a “0” data holding state (parallel state) before shipping the chip? Whether the data is in the “1” data holding state (magnetization antiparallel state) is defined.

  The memory area (number of memory cells) accessed using one reference potential generating cell RC is, for example, several tens to several hundreds bits or more. Therefore, when one reference potential generation cell RC becomes defective, the data in the memory area corresponding to the defective reference potential generation cell RC cannot be normally read. Thus, if the magnetization reversal of the MTJ element 1A which is not intended even in 1 bit occurs in the reference potential generation cell, there is a possibility that the whole chip becomes defective.

  Therefore, in consideration of the manufacturing cost of the memory and the reliability of the memory, it is preferable that the reference cell and the replica cell maintain the prescribed data holding state after the chip is shipped and when the memory is used.

  For example, in the MTJ element of the reference potential generation cell RC, the magnetization of the memory layer is reversed by thermal disturbance due to heat of heat treatment (for example, solder reflow process) when the magnetic memory chip is mounted on the mounting substrate. there's a possibility that.

  If the reference potential generation cell RC and the memory cell MC are formed in the same chip in the same process, the reference potential generation cell region 31B may be provided outside the memory cell array 30. The reference potential generation cell region 31B may include one column (one bit line pair) of reference potential generation cells RC, or may include two or more columns of reference potential generation cells RC.

  2 and 3, a reference potential generation cell region 31B provided so as to extend in the column direction is shown, and a plurality of reference potential generation cells arranged in the column direction are common bit lines (reference bit lines). Connected to. The reference potential generation cell region 31B is adjacent to the memory cell region 31A in the row direction. However, the reference potential generation cell region 31B may be provided at one end (termination) in the column direction of the memory cell array 30 according to the specifications of the magnetic memory. In this case, the reference potential generation cell region 31B is provided in the memory cell array 1 so as to extend in the row direction, and the reference potential generation cells RC arranged in the row direction are connected to a common word line (reference word line). The

(B) Magnetoresistive effect element
The magnetoresistive effect element 1A of the present embodiment will be described with reference to FIGS.
FIG. 5 is a cross-sectional view showing the structure of the magnetoresistive effect element (MTJ element) 1A of this embodiment.

As shown in FIG. 5, the MTJ element 1 </ b> A of the present embodiment includes a storage layer 10, a reference layer 12, and a nonmagnetic layer 11. The nonmagnetic layer 11 is provided between the storage layer 10 and the reference layer 12. An MTJ element 1A shown in FIG. 5 is, for example, a top pin type MTJ element, in which a nonmagnetic layer 11 is stacked on a storage layer 10, and a reference layer 12 is stacked on the nonmagnetic layer 11. As described above, the magnetization direction of the storage layer 10 can be reversed. The reference layer 12 has a magnetization reversal threshold value larger than that of the storage layer 10, and the magnetization direction of the reference layer 12 is substantially fixed. In consideration of data writing using the spin injection magnetization reversal method, the storage layer 10 is preferably formed using a material having a small damping constant.

The MTJ element 1A of the present embodiment is a perpendicular magnetization type MTJ element.
The storage layer 10 and the reference layer 12 have magnetic anisotropy in the direction perpendicular to the film surfaces of the magnetic layers 10 and 12. The magnetization of the storage layer 10 and the magnetization of the reference layer 12 are in the direction perpendicular to the film surface. A magnetic material (magnetization layer, magnetic film) whose magnetization is perpendicular to the film surface is also called a perpendicular magnetization film.

  The perpendicular magnetic anisotropy of the magnetic layers (storage layer and reference layer) 10 and 12 included in the MTJ element 1A is formed, for example, using the magnetocrystalline anisotropy of the magnetic body (magnetic layer).

  In the perpendicular magnetization type MTJ element 1A utilizing the magnetocrystalline anisotropy, since the c-axis of the crystal corresponds to the direction perpendicular to the film surface, even if each crystal grain rotates in the in-plane direction of the film, The c-axis does not disperse while maintaining the direction perpendicular to the film surface. Therefore, the perpendicular magnetization film can suppress the dispersion of crystal axes.

  For example, a Co—Cr alloy is given as a material having a large magnetocrystalline anisotropy energy density. The crystal structure of the Co—Cr alloy material is a hexagonal crystal structure and has a uniaxial magnetocrystalline anisotropy with the c-axis as the easy axis of magnetization. Therefore, in the crystal orientation of the magnetic layer using the Co—Cr alloy, the crystal growth direction of the Co—Cr alloy is controlled so that the c-axis of the crystal is parallel to the perpendicular direction of the film surface. Thereby, dispersion of crystal axes in the magnetic layer utilizing magnetocrystalline anisotropy is suppressed.

Similarly, even when a tetragonal magnetic layer is used for the MTJ element 1A, it is possible to realize a perpendicular magnetization type MTJ configuration by controlling the c-axis in the direction perpendicular to the film surface. become. Magnetic material tetragonal structure, for example, a material having an L1 ₀ type crystal structure is used. For example, Fe—Pt ordered alloy, Fe—Pd ordered alloy, Co—Pt ordered alloy, Fe—Co—Pt ordered alloy, Fe—Ni—Pt ordered alloy, Fe—Ni—Pd ordered alloy and the like can be mentioned. L1 ₀ type of the material of the crystal structure, the use as a perpendicular magnetization film, the crystal orientation is (001) it is preferable to preferentially oriented surface.

  The perpendicular magnetic anisotropy of the magnetic layers 10 and 12 of the MTJ element 1A may be expressed by utilizing the interfacial magnetic anisotropy of the magnetic layer resulting from the strain at the interface of the laminated film or the electronic state of the interface. Similarly to the case where the magnetocrystalline anisotropy is utilized, even when the perpendicular magnetic anisotropy of the magnetic layers 10 and 12 is formed by the interfacial magnetic anisotropy, the dispersion of the crystal axes can be suppressed. By suppressing the dispersion of the crystal axes, an increase in the inversion threshold current is suppressed.

  For example, an artificial lattice is used as the perpendicular magnetization film using the interface magnetic anisotropy. An example of an artificial lattice is a structure in which magnetic Co and nonmagnetic Pt (or Pd) are alternately stacked. Each magnetic body (each layer) in the artificial lattice preferably has a thickness of about 0.3 to 1.0 nm in order to improve the magnetic anisotropic energy density. However, when the thickness of each layer in the artificial lattice is reduced, the spin pumping effect becomes more prominent and the damping constant of the artificial lattice increases. Therefore, when an artificial lattice is used for the storage layer 10, it is preferable to consider the film thickness of each layer of the artificial lattice.

  The perpendicular magnetization type MTJ element 1A can suppress the dispersion of crystal axes as compared with the in-plane magnetization type MTJ element. In order to increase the magnetic anisotropy energy density, the perpendicular magnetization type MTJ element 1A increases the film thickness of the magnetic layer or increases the aspect ratio of the MTJ element like the in-plane magnetization type MTJ element. You do n’t have to. For example, the aspect ratio of the perpendicular magnetization type MTJ element 1A can be 1. Therefore, the perpendicular magnetization type MTJ element 1A can reduce the aspect ratio and is suitable for miniaturization. The MTJ element 1A in the memory cell 20 may be a top pin type or a bottom pin type.

  The nonmagnetic layer 11 is, for example, a magnesium oxide (MgO) film. The nonmagnetic layer 11 using an insulating film such as a MgO film is called a tunnel barrier layer. Hereinafter, the nonmagnetic layer is referred to as a tunnel barrier layer 11.

For example, calcium oxide (CaO), strontium oxide (SrO), titanium oxide (TiO), vanadium oxide (VO), niobium oxide (NbO), and aluminum oxide (Al ₂ O ₃ ) may be used for the nonmagnetic layer. Good. Mg nitride or Al nitride may be used for the nonmagnetic layer. Further, not only a single layer film of these oxides and nitrides, but also a laminated film of these insulators may be used for the nonmagnetic layer 11.

  MgO has a crystal structure of a sodium chloride (NaCl) structure. When a material having a NaCl structure such as MgO is used as the nonmagnetic layer (tunnel barrier layer) 11, the MgO film as the nonmagnetic layer 11 has a crystal orientation, for example, a bcc (001) plane (or orientation) ) And its equivalent plane (or orientation).

  An interface layer (not shown) may be provided between the storage layer 10 and the tunnel barrier layer 11 and between the reference layer 12 and the tunnel barrier layer 11. The interface layer is a magnetic layer that contacts the tunnel barrier layer 11. In addition, the memory layer 10 and the reference layer 12 may be referred to as not only a magnetic layer provided separately, but also a portion (region) of the memory layer 10 or the reference layer 12 in contact with the tunnel barrier layer 11 as an interface layer. The interface layer relaxes the lattice mismatch between the tunnel barrier layer 11 and the magnetic layers 10 and 12 and improves the crystallinity of the tunnel barrier layer 11 and the magnetic layers 10 and 12. As a result, the characteristics (for example, MR ratio) of the MTJ element are improved. The interface layer is formed using a magnetic layer containing at least two elements from the group containing Co (cobalt), Fe (iron), and B (boron). However, the material of the interface layer is not limited to the magnetic layer containing Co, Fe, or B.

  The MTJ element 1A of the present embodiment includes a shift adjustment layer (also called a bias layer or a shift magnetic field adjustment layer) 13. The shift adjustment layer 13 is provided on the side (surface) opposite to the side (surface) on which the tunnel barrier layer 11 is provided in the reference layer 12. That is, the shift adjustment layer 13 is stacked on the reference layer 12, and the reference layer is sandwiched between the tunnel barrier layer 11 and the shift adjustment layer 13.

  The shift adjustment layer 13 is a magnetic layer. The shift adjustment layer 13 is a perpendicular magnetization film like the storage layer 10 and the reference layer 12. The direction of magnetization of the shift adjustment layer 13 is fixed, and the shift adjustment layer 13 is formed so that the direction of magnetization does not reverse (is unchanged) even when the write current Iw is supplied.

  For example, the magnetization direction of the shift adjustment layer 13 and the magnetization direction of the reference layer 12 are opposite to each other (the magnetization arrangement is in an antiparallel state). Thereby, during the operation of the memory, the shift adjustment layer 13 substantially eliminates the leakage magnetic field from the reference layer 12, and the shift magnetic field generated in the storage layer 10 due to the leakage magnetic field from the reference layer 12 is To reduce.

  For example, the magnetization direction of the reference layer 12 is controlled by controlling the magnitude of the coercive force of the reference layer 12 and the coercive force of the shift adjustment layer 13 or by antiferromagnetic coupling between the reference layer 12 and the shift adjustment layer 13. The magnetization directions of the shift adjustment layer 13 are set to be opposite to each other.

  In the perpendicular magnetization type MTJ element that does not include the shift adjustment layer, the shift magnetic field of the storage layer 10 may not become zero due to the leakage magnetic field from the reference layer 12 in some cases. When the shift magnetic field of the storage layer 10 does not become zero, the magnetization arrangement of the storage layer 10 and the reference layer 12 may be fixed in a relatively stable parallel state (“0” data holding state, low resistance state). There is sex. When a large shift magnetic field is generated due to the leakage magnetic field from the reference layer 12, the information of the memory cell (data holding state of the MTJ element) rewritten to “1” data by the spin torque is immediately “ There is a possibility of returning to 0 "data.

  Therefore, as in the MTJ element 1A of the present embodiment, the shift adjustment layer 13 is provided in the MTJ element 1A for a reliable memory operation, so that the reference layer 12 in the MTJ element 1A during the memory operation is provided. And the shift magnetic field applied to the storage layer 10 is substantially zero. As a result, the MTJ element 1A of the present embodiment has both a “1” data holding state (high resistance state and antiparallel state) and a “0” data holding state (low resistance state and parallel state) during memory operation. Can take.

  An intermediate layer (also called a spacer layer or an insertion film) may be provided between the reference layer 12 and the shift adjustment layer 13. The intermediate layer suppresses the diffusion of atoms between the reference layer 12 and the shift adjustment layer 13. Accordingly, it is possible to suppress the diffused atoms from becoming impurities with respect to each of the reference layer 12 and the shift adjustment layer 13 and deteriorating the characteristics of the reference layer 12 and the shift adjustment layer 13. For the intermediate layer, for example, a metal such as tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), or ruthenium (Ru) is used. For example, when the reference layer 12 and the shift adjustment layer 13 form an antiferromagnetic junction, the reference layer 12 and the shift adjustment layer 13 may depend on the material of the intermediate layer.

  An underlayer may be provided for the MTJ element 1A. For example, the underlayer is provided on the side of the storage layer 10 opposite to the side where the tunnel barrier layer 11 is provided. When the MTJ element has a top pin type structure, the memory layer 10 is stacked on the base layer. The memory layer 10 is provided between the base layer and the tunnel barrier layer. In order to improve the magnetization characteristics of the storage layer 10, a material having an atomic dense surface may be used for the underlayer depending on the material of the storage layer 10. For example, for the underlayer, platinum (Pt), Pd (palladium), iridium (Ir), tungsten (W), tantalum (Ta), hafnium (Hf), metal nitride, and the like have an atomic dense surface. It is used as a material for For example, the lower electrode 51 of the MTJ element 1A shown in FIG. 3 may have a function as an underlayer for improving the crystallinity of the magnetic layer included in the MTJ element 1A. In this case, the lower electrode 51 is preferably made of a material having a small lattice mismatch with respect to the magnetic layer in contact with the lower electrode 51. The upper electrode 52 of the MTJ element 1A shown in FIG. 3 may be used as a hard mask for processing the MTJ element 1A into a predetermined shape.

  For example, in the MTJ element 1A of the present embodiment, the storage layer 10, the reference layer 12, and the shift adjustment layer 13 include a magnetic layer (alloy layer or artificial lattice) containing Co and Pt as a perpendicular magnetization film.

  For example, the operation guarantee temperature of the magnetic memory (hereinafter also referred to as the memory operation temperature) is in the range from about −30 ° C. to about + 85 ° C. In addition, in the manufacturing process of the magnetic memory, for example, in the mounting process when the chip of the magnetic memory is mounted on the mounting substrate, a temperature region higher than 120 ° C. (for example, 160 ° C. to 320 ° C.) as in the solder reflow process. Degree) of heat treatment. Therefore, it is preferable to consider the possibility that a temperature of about −30 ° C. to 320 ° C. is applied in the manufacturing process and use of the memory (memory operation) with respect to the specifications of the magnetic memory.

Hereinafter, the temperature T _j of a high region given during the mounting process, such as the temperature of the heat treatment during the solder reflow process, is referred to as the mounting temperature T _j . For example, the mounting temperature T _j includes not only the temperature emitted from the heating source but also the surface temperature of the chip or the package device and the temperature of the junction of the terminals.

  FIG. 6 schematically shows the temperature dependence of the magnetization of the reference layer 12 and the magnetization of the shift adjustment layer 13 in the MTJ element 1A of the present embodiment (hereinafter referred to as magnetization temperature dependence or magnetization temperature characteristic).

  The horizontal axis of FIG. 6 represents temperature (unit: ° C.), and the vertical axis of FIG. 6 represents the magnitude (arbitrary unit) of the magnetization (magnetic field) Ms of the reference layer 12 and the shift adjustment layer 13. In FIG. 6, the characteristic line LM1 indicates the magnetization temperature dependency of the reference layer 12, and the characteristic line LM2 indicates the magnetization temperature dependency of the shift adjustment layer 13.

  As shown in FIG. 6, in the present embodiment, the reference layer 12 and the shift adjustment layer 13 have different magnetization temperature dependencies LM1 and LM2.

  In the MTJ element 1A of the present embodiment, the composition ratio of Co and Pt included in the reference layer 12 and the composition ratio of Co and Pt included in the shift adjustment layer 13 are different from each other. The shift adjustment layer 13 is formed.

  As shown in the magnetization temperature dependence LM1 and LM2 of each magnetic layer in FIG. 6, the magnetization of the reference layer 12 attenuates more than the magnetization of the shift adjustment layer 13 as the temperature increases.

  In FIG. 6, the magnitude of the magnetization of the reference layer 12 is substantially the same as the magnitude of the magnetization of the shift adjustment layer 13 in a temperature region of 120 ° C. or less.

  Here, the magnetic characteristics of the MTJ element under a certain temperature condition will be described with reference to FIGS.

  A case where the MTJ element 1A of the present embodiment exists under a temperature condition of 100 ° C. or lower will be described with reference to FIG.

FIG. 7A shows an RH loop under a temperature condition of 100 ° C. or lower. The vertical axis of FIG. 7A represents the ratio (R1) of the resistance value R1 in the anti-parallel state (“1” data holding state) and the resistance value R0 in the parallel state (“0 data holding state”) in the MTJ element 1A. / R0). The horizontal axis of (a) of FIG. 7 has shown the external magnetic field _Hext (unit: kOe).

  In FIG. 7A, a characteristic line A1 indicated by an alternate long and short dash line indicates reversal hysteresis (hereinafter referred to as a minor loop) of the storage layer due to an external magnetic field. In FIG. 7A, a characteristic line B1 indicated by a dotted line indicates inversion hysteresis (hereinafter referred to as a major loop) of the reference layer due to an external magnetic field. In FIG. 7A, a characteristic line C1 indicated by a solid line indicates a shifted magnetic field. Here, the coercive force Hc of the storage layer is set to 500 Oe, and the MR ratio of the MTJ element = (R1−R0) / R0 is set to 200%. Further, under a temperature condition of 100 ° C. or less, the shift magnetic field Hshift due to the leakage magnetic field is set to 0 Oe.

  In FIG. 7B, the state of the magnetizations 80, 81, 82 of each of the magnetic layers 10, 12, 13 included in the MTJ element 1A and the leakage magnetic field when the MTJ element 1A of the present embodiment is at a temperature of 100 ° C. or less. The states of 88 and 89 are schematically shown.

  As shown in FIGS. 6 and 7B, the leakage magnetic field 88 of the reference layer 12 has substantially the same magnitude as the leakage magnetic field 89 of the shift adjustment layer 13 at 100 ° C. or lower. The direction of the magnetization 81 of the reference layer 12 is opposite to the direction of the magnetization 82 of the shift adjustment layer 13. The directions of the leakage magnetic field 88 of the reference layer 12 and the leakage magnetic field 89 of the shift adjustment layer 89 are also opposite to each other. Therefore, the leakage magnetic fields 88 and 89 applied to the storage layer 10 are canceled out. Thus, the shift magnetic field applied to the storage layer 10 is canceled in the temperature state during operation of the magnetic memory of 100 ° C. or lower.

  In the present embodiment, a state in which the leakage magnetic field 88 of the reference layer 12 is canceled by the leakage magnetic field 89 of the shift adjustment layer 13 and the shift magnetic field applied to the storage layer 10 is substantially canceled is referred to as a shift cancellation state. Call it. In the shift cancel state, the shift magnetic field is almost zero, and the magnitude of the shift magnetic field in the shift cancel state is less than 100 Oe (absolute value).

  As shown in the minor loop A1 in FIG. 7A, when the MTJ element 1A is in the shift cancel state, the magnetization direction of the storage layer 10 is hardly affected by the leakage magnetic field from the reference layer 12. Furthermore, it can be reversed by the spin torque.

  A case where the MTJ element 1A of the present embodiment exists under a temperature condition higher than 100 ° C. will be described with reference to FIG.

FIG. 8A shows an RH loop under a temperature condition of 230 ° C. or higher. The vertical axis of FIG. 8A represents the ratio (R1) between the resistance value R1 of the MTJ element in the magnetization antiparallel state (“1” data holding state) and the resistance value R0 of the parallel state (“0 data holding state”). / R0). The horizontal axis of (a) of FIG. 8 has shown the external magnetic field _Hext (unit: kOe).

  In FIG. 8A, a characteristic line A2 indicated by a one-dot chain line indicates a minor loop due to an external magnetic field, and a characteristic line B2 indicated by a dotted line indicates a major loop due to an external magnetic field. In FIG. 8A, a characteristic line C2 indicated by a solid line indicates a shifted magnetic field. The coercive force Hc of the storage layer is set to 500 Oe, and the MR ratio of the MTJ element = (R1−R0) / R0 is set to 200%. Under a temperature condition of 230 ° C. or higher, the shift magnetic field Hshift is set to −1000 Oe.

  In FIG. 8B, the MTJ element 1A of the present embodiment is in the state of the magnetizations 80X, 81X, and 82X of each of the magnetic layers 10, 12, and 13 included in the MTJ element 1A under a temperature condition of about 230 ° C. and leakage. The states of the magnetic fields 88X and 89X are schematically shown.

  As shown in FIGS. 6 and 8B, the magnitude of the magnetization 81X of the reference layer 12 is smaller than the magnitude of the magnetization 82X of the shift adjustment layer 13 in a temperature region higher than the memory operating temperature. Along with this, the magnitude of the leakage magnetic field 88X of the reference layer 12 becomes smaller than the magnitude of the leakage magnetic field 89X of the shift adjustment layer 13. As a result, the leakage magnetic fields 88X and 89X of the reference layer 12 and the shift adjustment layer 13 are not canceled under a temperature condition of 230 ° C. or higher.

  Therefore, under a temperature condition of 230 ° C. or higher, the leakage magnetic field 89X of the shift adjustment layer 13 affects the storage layer 10, and a shift magnetic field is generated in the storage layer 10 due to the leakage magnetic field 89X. A shift magnetic field is applied to the magnetization of the storage layer 10. At this time, due to the shift magnetic field caused by the leakage magnetic field of the shift adjustment layer 13, the magnetization 80X of the storage layer 10 is in the same direction as the direction of the leakage magnetic field 89X of the shift adjustment layer 13, that is, the direction of the magnetization 80 of the reference layer 12. It is fixed in the opposite direction.

  Therefore, as shown in the minor loop A2 of FIG. 8A, the MTJ element 1A under the temperature condition of about 230 ° C. is when the magnetization arrangement of the storage layer 10 and the reference layer 12 is in an antiparallel state. In other words, data can be stably held when the MTJ element 1A is in the “1” data holding state.

  Note that the magnetization of the storage layer 10 may also have temperature dependence, as with the reference layer 12 and the shift adjustment layer 13.

  In this embodiment, the leakage magnetic field of the reference layer and the leakage magnetic field of the shift adjustment layer are not canceled out, and the shift magnetic field caused by the leakage magnetic field of the shift adjustment layer is applied to the storage layer (generated in the storage layer). This state is called an excessive cancel state. On the contrary, the state in which the shift magnetic field caused by the reference magnetic field leakage magnetic field is not canceled, but the reference layer leakage magnetic field and the shift adjustment magnetic layer leakage magnetic field are not canceled. Called. For example, in the excessive cancellation state and the insufficient cancellation state, the magnitude of the shift magnetic field is, for example, 100 Oe (absolute value) or more.

  In the magnetoresistive effect element (MTJ element) 1A of the present embodiment, different magnetization temperature dependencies are given to the magnetic layers (here, the reference layer and the shift adjustment layer) of the MTJ element 1A. As a result, the MTJ element 1A of the present embodiment can reverse the magnetization of the storage layer 10 under the memory operating temperature condition, and the storage layer 10 due to the leakage magnetic field that affects the storage layer 10 under the temperature condition during the mounting process. The magnetization of the storage layer 10 can be suppressed.

  Therefore, during the mounting process for the magnetic memory including the magnetoresistive effect element 1A of the present embodiment, the data retention state of the reference cell, the replica cell, etc. is not intended due to the thermal disturbance caused by the heat applied during the mounting process. Transition to can be reduced.

  Therefore, according to the magnetoresistive effect element 1A of the present embodiment, it is possible to reduce the defect of the memory chip due to the heat during the manufacturing process.

(C) Specific example
A specific example of the magnetic layer included in the magnetoresistive effect element (MTJ element) of the present embodiment will be described with reference to FIG.

  As described above, by designing the parameters of the magnetic layers 12 and 13 such that the difference in magnetic temperature dependency between the reference layer 12 and the shift adjustment layer 13 of the MTJ element increases as the temperature rises, It is possible to form the MTJ element 1A that can stably maintain the “1” data holding state (or “0” data holding state) under the temperature condition during the mounting process.

In order to suppress the magnetization reversal of the storage layer 10 due to heat (thermal disturbance) under the condition of the mounting temperature T _j using the leakage magnetic field, the thermal stability index ΔE / (k _B T of the storage layer 10 ) is, at mounting temperature T _j, (so as to satisfy the equation 1), it is preferable that the magnetic parameters of the storage layer is set at the MTJ device 1A of the present embodiment.

In (Equation 1), “ΔE / (k _B T _j )” represents a thermal stability index of the memory layer at the mounting temperature T _j . “ΔE” indicates the size of the magnetization reversal energy barrier of the storage layer, and “k _B ” indicates the Boltzmann constant. “H _ext ” indicates a leakage magnetic field (shift magnetic field), and “H _k ^eff ” indicates an effective anisotropic magnetic field.

(Formula 1) assumes the following conditions.
In a magnetic memory (for example, MRAM) having a storage capacity of 1 Gbit, the total number of reference potential generation cells (for example, reference cells) including parity bits is assumed to be 72 kbit. If magnetization reversal occurs in the MTJ element in the reference potential generation cell even in 1 bit in one chip in the mounting process (for example, solder reflow process), the chip is regarded as a defective chip. The initial defect of 100 ppm in the market, that is, the probability of a defective chip is 1 chip or less in 10,000 chips. In this case, the magnetization reversal of the reference potential generating cell is suppressed to 1 bit / (72 kbit × 10000 chip) or less, and the magnetization reversal probability of the reference potential generating cell is 1.36 × 10 ⁻⁹ .
Assuming that the variation of the magnetization reversal energy barrier ΔE of the memory layer in the chip is 7.2%, there is a leakage magnetic field, and ΔE / (k in (Equation 1) under the condition of the mounting temperature T _j. It is preferable to satisfy the relationship of _B T _j ) in order to stabilize the operation.

The size of the thermal stability index of the storage layer depends on the number of reference cells and the variation of the magnetization reversal energy barrier ΔE. For example, when the variation of the magnetization reversal energy barrier ΔE of the storage layer can be reduced to 6% and the number of reference cells can be reduced to 18 kb, the left side of (Formula 1) in the presence of a leakage magnetic field and under mounting temperature conditions It is preferable that the value obtained from each parameter is greater than 49.5. In the general MRAM, the range of the magnetization reversal energy barrier ΔE / (k _B T) of the storage layer is about 48 to 56.

Here, as the mounting temperature T _j, using a solder reflow temperature. The parameters of the magnetic layer of the MTJ element 1A of this embodiment will be described with the solder reflow temperature set at 260 ° C. However, the solder reflow temperature as the mounting temperature T _j may be any value as long as it is within the range of 160 ° C. to 320 ° C.

  With reference to FIG. 9, in the MTJ element 1A of the present embodiment, when a magnetic layer containing Co and Pt is used as the reference layer 12 and the shift adjustment layer 13, the reference layer 12 using the magnetic layer and The parameters of the shift adjustment layer 13 will be described.

  FIG. 9 shows the magnetization temperature dependence of magnetic layers (hereinafter referred to as CoPt layers) having different composition ratios of Co and Pt. The horizontal axis in FIG. 9 indicates temperature (unit: ° C.), and the vertical axis in FIG. 9 indicates saturation magnetization Ms normalized at 85 ° C.

  FIG. 9 shows the magnetization temperature dependence of three CoPt layers (artificial lattices or alloys) having different composition ratios. In FIG. 9, the white circle plots show the magnetization temperature dependence in the CoPt layer (Co: Pt = 1: 2) in which the Co composition ratio is “1” and the Pt composition ratio is “2”. The square plot shows the magnetization temperature dependence of a CoPt layer (Co: Pt = 1.5: 1) having a Co composition ratio of “1, 5” and a Pt composition ratio of “1”. The crossed-out plot shows the magnetization temperature dependence of the CoPt layer (Co: Pt = 2: 1) having a Co composition ratio of “2” and a Pt composition ratio of “1”. In FIG. 9, the mounting temperature is assumed to be 260 ° C.

As shown in FIG. 9, when the Co composition ratio (concentration) in the CoPt layer is larger than the Pt composition ratio (concentration), the temperature dependence of magnetization decreases. When the Co composition ratio (concentration) in the CoPt layer becomes larger than the Pt composition ratio (concentration), the saturation magnetization Ms of the magnetic layer at the mounting temperature T _j (= 260 ° C.) increases.

  By utilizing the characteristics of the CoPt layer containing Co and Pt, the reference layer 12 is so attenuated that the magnetization of the reference layer 12 is larger than the magnetization of the shift adjustment layer 13 under a temperature condition higher than 100 ° C. The parameters of the shift adjustment layer 13 are designed.

That is, in the MTJ element 1A of the present embodiment, the shift adjustment layer 13 having a small magnetization temperature dependency and the magnetization temperature dependency of the shift adjustment layer 13 at a mounting temperature T _j (for example, 160 ° C. to 320 ° C.). In comparison, the MTJ element is formed using the reference layer 12 having a higher magnetization temperature dependency.

Thus, by adjusting the composition ratio of two or more elements (here, Co and Pt) in the magnetic layer, as shown in FIGS. 7 and 8, the leakage magnetic field is reduced under the memory operating temperature. The leakage magnetic field that has been canceled and remains (not canceled) under the mounting temperature T _j is applied to the storage layer 10. When the leakage magnetic field of the shift adjustment layer 13 is larger than the leakage magnetic field of the reference layer 12 under the mounting temperature condition, the direction of the leakage magnetic field (shift magnetic field) applied to the storage layer 10 is the magnetization direction of the reference layer 12. The reverse direction.

  Based on the magnetic characteristics of the reference layer 12 and the shift adjustment layer 13 as described above, the magnitude of the leakage magnetic field of the magnetic layer at the mounting temperature is considered.

For example, the diameter of the MTJ element is set to 30 nm. The film thickness of the storage layer is set to 2 nm. The film thickness of the tunnel barrier layer 11 is set to 1 nm. The thermal stability index ΔE / (k _B T) of the memory layer at 85 ° C. is set to 100, and the magnitude of the anisotropic magnetic field H _k ^eff at 85 ° C. is set to 6996 Oe.

At 260 ° C., when the thermal stability index ΔE / (k _B T) of the storage layer becomes about 45 and the effective anisotropic magnetic field H _k ^eff attenuates to 4686 Oe, the MTJ element is in the “1” data holding state. Based on (Equation 1), the shift magnetic field (leakage magnetic field) H _ext for stably maintaining is about −447 Oe.

In this case, the composition ratio of the CoPt layer as the reference layer is set to Co: Pt = 1: 2, and the film thickness is set to about 7 nm. The saturation magnetization Ms of the reference layer having this composition ratio is 600 emu / cc at 85 ° C.
The composition ratio of the CoPt layer as the shift adjustment layer is set to Co: Pt = 2: 1, and the film thickness is set to about 18 nm. The saturation magnetization of the shift adjustment layer having this composition ratio is about 950 emu / cc at 85 ° C.

When a reference layer and a shift adjustment layer made of an artificial lattice having such a composition ratio are used, the magnitude of the leakage magnetic field H _ext applied to the storage layer 10 at 85 ° C. is about 16 Oe. Therefore, the leakage magnetic field of the reference layer 12 and the leakage magnetic field of the shift adjustment layer 13 are canceled out, and the shift magnetic field applied to the storage layer 10 is substantially canceled.

  On the other hand, as shown in FIG. 9, by using different CoPt layers with different composition ratios, different magnetic temperature dependences are generated between the reference layer 12 and the shift adjustment layer 13, under a temperature condition of 260 ° C. The saturation magnetization of the CoPt layer (here, the reference layer) having a composition ratio of Co: Pt = 1: 2 is approximately 0.47 times under the temperature condition of 85 ° C., and the composition ratio is Co: Pt = 2: The saturation magnetization of one CoPt layer (here, the shift adjustment layer) is approximately 0.85 times as high as 85 ° C. Therefore, the saturation magnetization of the reference layer 12 at 260 ° C. is about 282 emu / cc, and the saturation magnetization of the shift adjustment layer 13 at 260 ° C. is about 808 emu / cc. Thus, as the temperature rises, the magnetization of the reference layer 12 is greatly attenuated as compared to the magnetization of the shift adjustment layer 13.

  In this case, at 260 ° C., the leakage magnetic field applied to the storage layer 10 is −550 Oe. The magnitude of the leakage magnetic field (shift magnetic field) applied to the storage layer 10 of the MTJ element based on the above parameters satisfies (Equation 1).

  For example, in an MTJ element that can maintain a “1” data retention state under mounting temperature conditions, the Co composition ratio in the CoPt layer as the shift adjustment layer 13 is larger than the Pt composition ratio, and the CoPt layer as the reference layer 12 The composition ratio of Co is smaller than the composition ratio of Pt. For example, the Co composition ratio of the CoPt layer as the shift adjustment layer 13 is larger than the Co composition ratio of the CoPt layer as the reference layer 12. The composition ratio of Pt included in the CoPt layer as the shift adjustment layer 13 is smaller than the composition ratio of Pt included in the CoPt layer as the reference layer 12.

  Therefore, the reference potential generating cell (reference cell and replica cell) in the “1” data holding state under the mounting temperature condition has a magnetization direction of the storage layer 10 due to a leakage magnetic field (shift magnetic field) applied to the storage layer 10. Is maintained antiparallel to the magnetization direction of the reference layer 12. The memory cell to which data from the outside is written includes an MTJ element designed with the same parameters as the reference potential generation cell. As described above, since the leakage magnetic fields of the reference layer and the shift adjustment layer are canceled under the memory operating temperature, the magnetization of the storage layer can be reversed and predetermined data can be written into the memory cell.

The parameter of the magnetic layer (for example, CoPt layer) is adjusted so that the leakage magnetic field of the reference layer 12 is larger than the leakage magnetic field of the shift adjustment layer 13 under the mounting temperature condition, and the magnetization temperature dependence and shift of the reference layer 12 are adjusted. By making the magnetization temperature dependence of the adjustment layer 13 different, an MTJ element that can stably maintain the “0” data holding state and a reference potential generation cell including the MTJ element can be formed. That is, the parameters of the reference layer 12 and the shift adjustment layer 13 of the MTJ element are designed so that an insufficient cancel state occurs under the mounting temperature condition.
In the MTJ element that maintains the “0” data retention state at the mounting temperature, a CoPt layer having a Co composition ratio larger than the Pt composition ratio is used as a reference layer, and a CoPt layer having a Co composition ratio smaller than the Pt composition ratio is used. Used as a shift adjustment layer. As a result, the leakage magnetic field of the remaining reference layer 12 acts on the storage layer 10 at the mounting temperature, and the magnetization of the storage layer is fixed in the same direction as the magnetization direction of the reference layer.

  The parameters of the magnetic layers 11, 12, and 13 are designed so that the magnetization of the storage layer 10 that should maintain a predetermined data retention state is not reversed by the leakage magnetic field of the reference layer 12 or the shift adjustment layer 13 under the mounting temperature condition. can do.

  As described above, in the magnetoresistive effect element (MTJ element) 1A of the present embodiment, the reference layer 12 and the shift adjustment layer 13 have different magnetization temperature dependencies, and the magnetization of one magnetic layer increases as the temperature increases. Is attenuated more than the magnetization of the other magnetic layer. As a result, at the mounting temperature, an excess canceling state (or insufficient canceling state) of the leakage magnetic field (shifted magnetic field) appears in the magnetoresistive effect element 1A, and a leakage magnetic field (a magnetization arrangement state) that can maintain a predetermined data holding state (magnetization array state). Shift magnetic field) can be applied to the storage layer 10.

  As described above, in the magnetoresistive effect element according to the present embodiment, the magnetization of the storage layer is fixed by the leakage magnetic field from the shift adjustment layer (or the reference layer) under the mounting temperature condition, and the storage layer is caused by the application of heat. Magnetization reversal is reduced.

  For example, after a chip (package device) including a magnetic memory is shipped, if the chip is mounted by a mounting manufacturer or user, the MTJ of the reference cell or replica cell may be caused by thermal disturbance caused by the heating temperature at the time of mounting the chip. There is a possibility that magnetization reversal occurs in the element.

  In order to prevent chip failure due to thermal disturbance in the mounting stage, a writing circuit or a resistance state determination circuit for the reference cell and the replica cell may be incorporated in the chip. In this case, the chip cost increases. Further, when the magnetization reversal (data transition) of the MTJ element occurs due to heating during the mounting process, the mounting manufacturer or user must rewrite the data in the reference cell and the replica cell.

  There is a concern that the product competitiveness of the chip including the magnetic memory is reduced due to such a problem in the mounting process.

  Like the magnetoresistive effect element of this embodiment, a predetermined data retention state can be stably maintained under mounting temperature conditions, so that a mounting manufacturer and a user can perform reference potential generation cells (reference cells and replica cells) after the mounting process. ) For checking the data holding state and for writing data to the reference potential generation cell.

  In addition, the magnetoresistive effect element according to the present embodiment can reduce the data read failure due to the magnetization reversal of the MTJ element of the reference potential generating cell at the mounting temperature.

  In the magnetoresistive effect element of this embodiment, it is not necessary to make a reference potential generation cell and a memory cell separately in order to make the resistance of the reference potential generation cell more resistant to thermal disturbance than that of the memory cell. In addition, a circuit for checking the data holding state (resistance state) of the reference potential generation cell and a circuit for writing data to the reference potential generation cell may not be provided in the chip after the mounting process. Therefore, the magnetoresistive effect element of this embodiment can prevent an increase in manufacturing cost of the magnetic memory.

  As described above, according to the magnetoresistive effect element and the magnetic memory of the present embodiment, it is possible to suppress the memory malfunction caused by heat.

(D) Manufacturing method
Hereinafter, a method for manufacturing a magnetoresistive element (for example, MRAM) including the magnetoresistive element (for example, MTJ element) 1A of the present embodiment and the magnetoresistive element of the present embodiment will be described. Here, the manufacturing method of the MTJ element and the magnetic memory will be described using FIGS. 1 to 5 as appropriate.

  For example, an element isolation insulating film 71 having an STI (Shallow Trench Isolation) structure is embedded in the semiconductor substrate 70 to form an element isolation region. By forming this element isolation region, the active area AA is partitioned in the semiconductor substrate 70.

  The selection transistor 2 in the memory cell MC, the reference cell, and the replica cell RC is formed on the active area AA of the semiconductor substrate 70 by, for example, CVD (Chemical Vapor Deposition) method, photolithography, RIE (Reactive Ion Etching) method, or the like. Is done. Further, elements of a row / column control circuit, a write circuit, a read circuit, and a peripheral circuit are formed on the semiconductor substrate 70.

  An interlayer insulating film 79A is deposited on the semiconductor substrate 70 by a multilayer wiring technique, and a contact plug 72A is formed in the interlayer insulating film. A metal film as a wiring (for example, a lower bit line) or an intermediate layer is formed on the interlayer insulating film 79A and the contact plug 72.

  Then, as shown in FIG. 4, the magnetoresistive effect element (MTJ element) of the present embodiment is formed within a predetermined wiring level. For example, when the MTJ element is a top pin type element, a storage layer (magnetic layer) 10, a tunnel barrier layer (nonmagnetic layer) 11, a reference layer (magnetic layer) 12, and a shift adjustment layer are formed on the electrode material 51. A (magnetic layer) 13 and a hard mask (upper electrode) 52 are sequentially deposited. Using the hard mask 52 patterned into a predetermined shape (for example, a circular shape) as a mask, the stacked body including the magnetic layer is processed, and the MTJ element 1A of this embodiment is formed.

  The material of the memory layer 10 is appropriately designed in terms of magnetic properties, film thickness, material composition, and the like so as to satisfy the above (Formula 1). For example, a CoPt layer (CoPt artificial lattice or CoPt alloy) is used as the material of the reference layer 12 and the shift adjustment layer 13. The reference layer 12 and the shift adjustment layer 13 have different Co and Pt composition ratios in the magnetic layers 12 and 13 so that the magnetization temperature dependency of the reference layer 12 differs from the magnetization temperature dependency of the shift adjustment layer 13. Adjusted. Further, the film thickness and the magnetic characteristics of each layer are designed so that the magnetic characteristics of the reference layer 12 and the shift adjustment layer 13 satisfy the above-described (Equation 1).

  For example, under the mounting temperature of the chip mounting process, the reference layer 12 and the shift adjustment layer 13 have a leakage magnetic field that affects the magnetization of the storage layer 10 rather than the leakage magnetic field of the reference layer 12. When the magnetization temperature characteristic is designed, the Co composition in the CoPt layer as the shift adjustment layer 13 is made higher than the Pt composition ratio, and the Co composition ratio in the CoPt layer as the reference layer 12 is made lower than the Pt composition ratio. . For example, the Co composition ratio of the shift adjustment layer 13 is higher than the Co composition ratio of the reference layer 12, and the Pt composition ratio of the shift adjustment layer 13 is lower than the Pt composition ratio of the reference layer 12. As a result, the leakage magnetic fields of the reference layer 12 and the shift adjustment layer 13 are in an excessively canceled state under the mounting temperature condition, and the mounting temperature (for example, the solder reflow temperature) becomes the MTJ element 1A of the present embodiment during the mounting process. When applied to, the magnetization direction of the storage layer 10 is fixed by the leakage magnetic field of the shift adjustment layer 13.

  For example, under the mounting temperature (160 ° C. to 320 ° C.) in the chip mounting process, the reference layer 12 is such that the leakage magnetic field of the reference layer 12 affects the magnetization of the storage layer 10 rather than the leakage magnetic field of the shift adjustment layer 13. When the magnetization temperature characteristics of the shift adjustment layer 13 are designed, the Pt composition in the CoPt layer as the shift adjustment layer 13 is made higher than the Co composition ratio, and the Pt composition ratio in the CoPt layer as the reference layer 12 is Co. The composition ratio is lower. For example, the Pt composition ratio of the m shift adjustment layer 13 is made higher than the Pt composition ratio of the reference layer 12, and the Co composition ratio of the shift adjustment layer 13 is made lower than the Co composition ratio of the reference layer 12. As a result, the leakage magnetic fields of the reference layer 12 and the shift adjustment layer 13 are in an insufficiently canceled state under the mounting temperature condition, and the reference is made when the mounting temperature is applied to the MTJ element 1A of the present embodiment in the mounting process. The direction of magnetization of the storage layer 10 is fixed by the leakage magnetic field of the layer 12.

  After the MTJ element 1A is formed, an interlayer insulating film and wiring (for example, an upper bit line) are formed by a multilayer wiring technique. Thus, a magnetic memory chip including the MTJ element 1A of the present embodiment is formed.

  As shown in FIG. 1, a chip 100 of a magnetic memory is sealed in a package device (insulating resin) 200 so as to be electrically connected to solder balls (or solder bumps) as external terminals. Before or after sealing in the package device, the data holding state (magnetization arrangement state, resistance state) of the MTJ element 1A in the reference potential generation cell as the reference cell and the replica cell is the same as that of the magnetic memory. Depending on the reading method, it is appropriately set to the “1” data holding state or the “0” data holding state.

  Thereafter, the magnetic memory including the MTJ element 1A of the present embodiment is shipped to a mounting manufacturer or a user.

  As shown in FIG. 1, a magnetic memory package device 200 including the MTJ element 1A of this embodiment is mounted on a mounting substrate 300 by a mounting manufacturer or a user. In this mounting process, for example, heat corresponding to the melting temperature of the solder is given to the surface of the package device 200 and the solder joint as the mounting temperature. For example, at the time of mounting, the package device is exposed to a temperature condition of about 160 ° C. to 320 ° C.

  As described above, the MTJ element 1A of the present embodiment is formed so that the reference layer 12 and the shift adjustment layer 13 have different magnetization temperature dependencies. In the MTJ element 1A of the present embodiment, the magnetic characteristics of the storage layer 10 of the MTJ element 1A are designed so as to satisfy the above-described (Equation 1).

  Under the mounting temperature in the mounting process, the leakage magnetic field of the reference layer 12 and the leakage magnetic field of the shift adjustment layer 13 are not canceled, and the magnetic field in the same direction as the leakage magnetic field of the shift adjustment layer 13 or the leakage magnetic field of the reference layer 12 (shift magnetic field). ) Is applied to the magnetization of the storage layer 10. The magnitude of the leakage magnetic field is such that the MTJ element 1A in the reference potential generating cell 20 has a data holding state (magnetization array) that should be held at “1” or “0” even if it is affected by heat at the mounting temperature. ) Can be maintained so that the magnetization of the storage layer 10 can be fixed.

  Thus, the magnetic memory including the MTJ element 1A of the present embodiment formed by the above-described manufacturing method is used in the reference potential generation cell RC that is defined to hold “1” data or “0” data during the memory operation. Even when the mounting temperature (160 ° C. to 320 ° C.) is given to the chip (package device), the “1” or “0” data holding state is stably maintained. Therefore, after the mounting process, the mounting manufacturer or the user does not need to execute the process of checking the data holding state of the reference potential generation cell RC and the process of writing data to the reference potential generation cell. Further, a circuit for checking the data holding state of the reference potential generation cell and a circuit for writing data to the reference potential generation cell 20 may not be formed in the chip of the magnetic memory.

  Furthermore, in the MTJ element 1A of this embodiment and the magnetic memory including the MTJ element 1A, the magnitude of the magnetization of the reference layer 12 and the magnitude of the magnetization of the shift adjustment layer 13 are under the memory operating temperature when the memory is used after the mounting process. Since the magnetization directions are substantially the same and opposite to each other, the leakage magnetic field of the reference layer 12 and the leakage magnetic field of the shift adjustment layer 13 are canceled. Therefore, the magnetic memory including the MTJ element 1A of the present embodiment formed by the above-described manufacturing method stores predetermined data in the memory layer 10 with almost no influence of the shift magnetic field at the memory operating temperature. You can write to a cell.

  As described above, according to the magnetoresistive effect element and the method for manufacturing a magnetic memory of the present embodiment, it is possible to provide a memory that suppresses malfunction due to heat during the manufacturing process. Further, the manufacturing of the magnetoresistive effect element and the magnetic memory according to the present embodiment can be made efficient, and an increase in manufacturing cost of the magnetic memory can be suppressed.

(E) Summary
As described with reference to FIGS. 1 to 9, in the magnetoresistive effect element (MTJ element) of this embodiment, the temperature dependency of the magnetization of the reference layer and the temperature dependency of the magnetization of the shift adjustment layer are different from each other. Yes.

In the mounting process, a process temperature (hereinafter referred to as a mounting temperature) T _j used when the chip 100 including the MTJ element 1A of the present embodiment is connected to the mounting substrate 300, for example, a temperature used in the solder reflow process ( Hereinafter, the magnetic memory including the MTJ element 1A of the present embodiment may be exposed under the condition of the solder reflow temperature.

  For example, in the process of mounting a magnetic memory, heat at 230 ° C. is applied for about 10 seconds at the solder joint between the magnetic memory (package device) and the substrate, and heat at 260 ° C. is applied for about 50 seconds on the package surface. It is assumed that

  Memory cells used in a memory (for example, ROM) to which a program is written before the magnetic memory is mounted, and reference potential generation cells such as reference cells and replica cells for data discrimination are stored at a mounting temperature. It is preferable that the magnetization of the layer and the reference layer is not reversed due to thermal disturbance.

  The magnitude of the magnetization reversal energy barrier of the magnetic layer is related to the magnetization reversal due to thermal disturbance. In order to reduce the defect rate due to magnetization reversal within the allowable range of the product specification at the mounting temperature, the magnetization reversal energy barrier of the storage layer is set to a certain value or more. When the solder reflow process temperature (for example, 260 ° C.) is assumed as the mounting temperature and each parameter of the memory layer is designed to satisfy the product specifications, the memory operation guarantee temperature (for example, 85 ° C. or less) The magnetization reversal energy barrier of the storage layer has a very large value. On the other hand, in the magnetic memory using the spin injection magnetization reversal method for data writing, the magnetization reversal energy barrier of the storage layer has a correlation with the magnitude of the magnetization reversal current. In order to reduce the power consumption of the spin transfer magnetization reversal, the magnetization reversal energy barrier of the storage layer is preferably a small value. In a magnetic memory using a general magnetoresistive effect element, it may be difficult to achieve both reduction of the magnetization reversal current at the guaranteed operating temperature and prevention of magnetization reversal of the storage layer at the mounting temperature.

  The reference cell and the replica cell do not need to write external data during the memory operation. Therefore, the parameters of the storage layer of the MTJ element of the reference cell and the replica cell are designed without considering the magnetization reversal current (inversion threshold) of the MTJ element of the reference cell and the replica cell during the memory operation. In some cases, resistance to thermal disturbance in the replica cell is ensured. However, in this case, the memory layer of the MTJ element of the reference cell and the replica cell is designed independently of the memory layer of the MTJ element of the memory cell, so that the manufacturing cost of the chip increases.

  In the MTJ element 1A of the present embodiment, the reference layer 12 and the shift adjustment layer 13 have different magnetization temperature dependencies.

  In the MTJ element 1A of the present embodiment, the leakage magnetic field of the reference layer 12 and the leakage magnetic field of the shift adjustment layer 13 cancel each other under the memory operating temperature. Therefore, the leakage magnetic field (shift magnetic field) caused by the reference layer 12 or the shift adjustment layer 13 is not applied to the storage layer 10 under the operating temperature condition of the memory.

In the MTJ element of this embodiment, under the mounting temperature condition, the magnetization temperature dependence of one of the reference layer 12 and the shift adjustment layer 13 is compared with the magnetization temperature dependence of the other magnetic layer. Attenuates greatly.
Under the mounting temperature condition, the leakage magnetic field caused by the magnetic layer having a small magnetization temperature dependency with small attenuation remains, and the remaining leakage magnetic field is applied to the storage layer 10 as a shift magnetic field. In the MTJ element 1A in which the direction of the leakage magnetic field is the same as the magnetization direction of the storage layer 10 before the mounting process, the magnetization direction of the storage layer 10 is stably maintained by the shift magnetic field applied to the storage layer 10. Is done.

  As described above, under the mounting temperature condition, the leakage magnetic field of the reference layer 12 or the leakage magnetic field of the shift adjustment layer 13 affects the magnetization of the storage layer 10, so that the heat resistance (thermal stability) of the storage layer 10 with respect to the mounting temperature. ) Is ensured, and magnetization reversal of the storage layer 10 is suppressed.

  In the MTJ element 1A in which the direction of the leakage magnetic field under the mounting temperature condition and the magnetization direction of the storage layer before the mounting process are opposite to each other, the magnetization direction of the storage layer is hardly reversed by the leakage magnetic field. Thus, the magnetic layer can be designed.

  As described above, the magnetoresistive effect element (MTJ element) and the magnetic memory including the magnetoresistive effect element according to the present embodiment have the magnetization reversal of the MTJ element that should retain predetermined data due to the application of heat in the high-temperature process of the mounting process. Can be suppressed. Therefore, malfunction of the MTJ element of this embodiment and the magnetic memory including the same can be suppressed. In addition, according to the MTJ element and the magnetic memory of this embodiment, it is possible to reduce the occurrence of malfunctions and defective chips due to the defective data holding state of the reference potential generation cell.

  The MTJ element of this embodiment and the magnetic memory including the MTJ element do not have to increase the magnetization reversal energy barrier of the storage layer in order to suppress the magnetization reversal of the MTJ element due to heat in the mounting process. The magnetization reversal current supplied to the storage layer need not be increased. Therefore, according to the MTJ element and the magnetic memory of this embodiment, a memory with low power consumption and high storage density can be formed.

  In the MTJ element and the magnetic memory including the MTJ element according to the present embodiment, the MTJ element used for the reference potential generation cell and the MTJ element used for the memory cell may not be separately formed in different manufacturing processes. The MTJ element and magnetic memory of this embodiment can reduce the burden of mounting manufacturers and users on checking and correcting the data holding state of the reference potential generation cell. In the MTJ element and magnetic memory of this embodiment, the circuit for checking the data holding state of the reference potential generation cell after mounting the chip and the circuit for rewriting the data holding state do not have to be formed on the chip. In the MTJ element and the magnetic memory of this embodiment, the memory cell and the reference potential generation cell can be formed using the same material. Therefore, according to the MTJ element of this embodiment and the magnetic memory using the MTJ element, it is possible to increase the efficiency of manufacturing the magnetic memory and suppress an increase in process cost.

(2) Second embodiment
The magnetoresistive effect element (for example, MTJ element) of the second embodiment will be described with reference to FIGS. In the second embodiment, substantially the same configuration and function as those in the first embodiment will be described as necessary.

  FIG. 10 shows a cross-sectional structure of the MTJ element 1B of the second embodiment.

  In the MTJ element 1B of the second embodiment, the reference layer 12 includes a ferrimagnetic film 17.

  The ferrimagnetic film 17 includes a rare earth metal sublattice and a transition metal sublattice. For example, the ferrimagnetic film 17 includes at least one element selected from a group including rare earth metal elements such as terbium (Tb), dysprosium (Dy), and samarium (Sm), cobalt (Co), iron (Fe), and the like. And at least one element selected from the group containing transition metal elements.

  In this embodiment, the ferrimagnetic film 17 is formed using, for example, terbium (Tb) as a rare earth metal sublattice and cobalt (Co) as a transition metal sublattice. Hereinafter, the rare earth metal sublattice is referred to as a Tb sublattice, and the transition metal sublattice is referred to as a Co sublattice. In the ferrimagnetic film 17, the magnetization direction of the Tb sublattice is opposite to the magnetization direction of the Co sublattice.

  In the MTJ element 1 </ b> B of the present embodiment, an interface layer 16 is provided between the ferrimagnetic film 17 and the tunnel barrier layer 11. The interface layer 16 is, for example, a magnetic layer. An intermediate layer (metal layer) such as Ta, W, or Mo may be provided between the ferrimagnetic film 17 and the interface layer 16.

As described above, in the region near the tunnel barrier layer in the memory layer 10, the interface layer may be provided also on the memory layer side in order to improve the element characteristics (for example, MR ratio) of the MTJ element. Hereinafter, for clarity of explanation, the interface layer 16 between the ferrimagnetic film 17 and the tunnel barrier layer 17 is referred to as a reference layer side interface layer 16. In the present embodiment, the ferrimagnetic film 17 and the reference layer side interface layer 16 are regarded as one reference layer 12.
However, the ferrimagnetic film 17 and the reference layer side interface layer 16 may be regarded as separate magnetic layers. In this case, the ferrimagnetic film 17 is particularly called a reference layer.

  The reference layer side interface layer 16 functions as a spin injection source for the storage layer 10.

  The magnetization of the reference layer side interface layer 16 is strongly coupled to the magnetization of the Co sublattice of the ferrimagnetic film 17. Therefore, the magnetization direction of the reference layer side interface layer 16 is the same as the magnetization direction of the Co sublattice in the ferrimagnetic film 17 and is opposite to the magnetization direction of the Tb sublattice. The reference layer side interface layer 16 is a magnetic layer made of, for example, a CoFeB layer. The reference layer side interface layer 16 may be a magnetic layer containing at least two elements selected from the group containing Co, Fe, and B, and may be a CoB layer, a CoFe layer, or the like.

  For example, when the magnetization direction of the reference layer side interface layer 16 is the same as the magnetization direction of the memory layer 10, the magnetization arrangement of the MTJ element 1B is in a parallel state (low resistance state), and the MTJ element 1B stores data. The corresponding data corresponds to “0” data. When the magnetization direction of the reference layer side interface layer 16 is opposite to the magnetization direction of the storage layer 10, the magnetization arrangement of the MTJ element 1B is in an antiparallel state (high resistance state), and the MTJ element 1B stores data. Data corresponds to “1” data.

  In the MTJ element 1B of this embodiment, the magnetization of each sublattice of the ferrimagnetic film 17 and the magnetization of the reference layer side interface layer 16 reduce the net leakage magnetic field at the memory operating temperature to 0 without using the shift adjustment layer. Is done. As a result, the MTJ element 1B of the present embodiment cancels the leakage magnetic field (shift magnetic field) applied to the storage layer 10 at the memory operating temperature.

In the MTJ element 1B of the present embodiment, the two sublattices (here, the Tb sublattice and the Co sublattice) of the ferrimagnetic film 17 have different magnetization temperature dependencies. As a result, a shift cancel state is formed at the memory operating temperature, and the leakage magnetic field of the remaining sublattice is applied to the magnetization of the storage layer 10 at the mounting temperature _Tj . Hence, the MTJ element 1B of this embodiment can suppress the MTJ element 1B to the magnetization reversal of the reference potential generating cell due to the heat caused by the mounting temperature T _j is generated.

  The magnetic characteristics of the MTJ element 1B of this embodiment will be described with reference to FIGS.

  FIG. 11 shows the magnetization temperature dependence of two sublattices (here, a Tb sublattice and a Co sublattice) included in the ferrimagnetic film. The horizontal axis in FIG. 11 represents temperature (unit: ° C.), and the vertical axis in FIG. 11 represents saturation magnetization Ms (arbitrary unit). In FIG. 11, the characteristic line LM3 corresponds to the magnetization temperature dependence of the Tb sublattice in the ferrimagnetic film, and the characteristic line LM4 corresponds to the magnetization temperature dependence of the Co sublattice in the ferrimagnetic film.

  FIG. 12 schematically shows the magnetic field caused by the magnetic layer of the MTJ element under each temperature condition. 12A schematically shows the magnetization state and leakage magnetic field state of each magnetic layer included in the MTJ element 1B under the memory operating temperature, and FIG. 12B shows each of the MTJ element 1B included in the MTJ element 1B. The state of magnetization of a magnetic layer and the state of a leakage magnetic field are shown typically.

  As shown by the characteristic lines LM3 and LM4 in FIG. 11 and (a) in FIG. 12, below the memory operating temperature (for example, 100 ° C.), the magnetization 93 of the Tb sublattice in the ferrimagnetic film 17 and the Co sublattice The combined magnetization with the magnetization 94 has substantially the same magnitude as that of the reference layer side interface layer 16. For example, at the memory operating temperature, the magnitude of the magnetization of the Tb sublattice is substantially the same as the magnitude of the magnetization of the Co sublattice.

  Therefore, at a memory operating temperature of 100 ° C. or less, the leakage magnetic fields caused by the ferrimagnetic film 17 and the interface layer 16 cancel each other, and the shift magnetic field generated in the storage layer 10 is cancelled. Therefore, under the memory operating temperature, the MTJ element 1B of the present embodiment can reverse the magnetization of the storage layer 10.

  Therefore, the memory cell including the MTJ element 1B of the second embodiment can take both the “1” data holding state and the “0” data holding state at the memory operating temperature (for example, 100 ° C. or lower).

As shown in (b) of the characteristic line LM3, LM4 and 12 in FIG. 11, the mounting temperature T _j above temperature range, while a low Neel temperature of the two sub-gratings in the ferrimagnetic film 17 sub The magnetization 94X of the lattice (here, the Tb sublattice) is greatly attenuated compared to the magnetization 93X of the other sublattice (here, the Co sublattice). On the other hand, in mounting temperature _{T j} above temperature range, the magnetization 93X of the other sublattice (Co sublattice) is residual.

Therefore, in mounting the temperature T _j above temperature range, the leakage magnetic field in the same direction as the magnetization direction of orientation and reference layer side interface layer 16 of the magnetization 93X of Co sublattice in ferrimagnetic film 17, acts in the storage layer 10 A shift magnetic field caused by the leakage magnetic field of the Co sublattice and the leakage magnetic field of the interface layer 16 is applied to the magnetization of the storage layer 10. Therefore, under the mounting temperature T _j , the direction of the magnetization 90X of the storage layer 10 is the same as the direction of the leakage magnetic field of the Co sublattice in the ferrimagnetic film 17 and the reference layer side interface layer 16 due to the applied shift magnetic field. Fixed in direction.

  Therefore, the magnetization reversal of the storage layer 10 is suppressed by the residual magnetic field 93X of the sublattice of the ferrimagnetic film 17 and the leakage magnetic field caused by the reference layer side interface layer 16 at the mounting temperature. Therefore, the reference potential generating cell (reference cell or replica cell) that holds “0” data can stably maintain the data holding state.

  FIG. 13 shows the magnetization temperature dependence of the ferrimagnetic film when the composition ratio of Tb and Co in the ferrimagnetic film is changed. The horizontal axis in FIG. 13 indicates temperature (unit: ° C.), and the vertical axis in FIG. 13 indicates saturation magnetization Ms (arbitrary unit). A characteristic line SS1 in FIG. 13 shows the magnetization temperature dependence of the ferrimagnetic film in which the composition ratio of the Tb sublattice is larger than the composition ratio of the Co sublattice. A characteristic line SS2 in FIG. 13 shows the magnetization temperature dependence of the ferrimagnetic film in which the composition ratio of the Co sublattice is larger than the composition ratio of the Tb sublattice.

  In FIG. 13, whether the saturation magnetization of the ferrimagnetic film containing Tb and Co is positive or negative indicates the direction of magnetization of the ferrimagnetic film. For example, when the magnetization of the ferrimagnetic film has a positive value, the MTJ element shows a “0” data holding state (first stable state). For example, the magnetization of the ferrimagnetic film is negative. In the case of having the value of “1”, the MTJ element indicates the “1” data holding state (second stable state).

  As shown in FIG. 13, when the composition ratio of the Tb sublattice increases more than the composition ratio of the Co sublattice in the ferrimagnetic film containing Co and Tb, the temperature at which the magnetization of the Tb sublattice in the ferrimagnetic film disappears. Becomes lower.

  Considering the composition ratio of Co and Tb in the ferrimagnetic film as shown in FIG. 13 and the magnetization characteristics of each sublattice, the leakage magnetic field of the Co sublattice at the mounting temperature (for example, 160 ° C. to 300 ° C.). Is designed to be sufficiently larger than the leakage magnetic field of the Tb sublattice so that the magnetic properties of the ferrimagnetic film of the MTJ element are designed.

  Here, a case where the MTJ element 1B including the ferrimagnetic film and the reference layer side interface layer in the present embodiment maintains a “0” data retention state (low resistance state, magnetization arrangement in a parallel state) at the mounting temperature. , Verify.

The configuration of the MTJ element used for verifying the parameters of the magnetic layer will be described. The diameter of the MTJ element is set to 30 nm. The thickness of the storage layer of the MTJ element is set to 2 nm, and the thickness of the tunnel barrier layer is set to 1 nm. At 85 ° C., the magnetization reversal energy barrier (thermal stability index) ΔE / k _B T of the storage layer is set to 60, and the anisotropic magnetic field Hk of the storage layer is set to 6996 Oe.

In the present embodiment, the mounting temperature T _j is 160 ° C.

In the MTJ element of this embodiment, the magnetization reversal energy barrier ΔE / k _B T of the storage layer at 160 ° C. attenuates to 45, and the anisotropic magnetic field Hk attenuates to 3650 Oe. In this case, the magnitude of the leakage magnetic field (shift magnetic field) H _ext for stably maintaining the storage layer in the “0” data holding state is 880 Oe based on the above (Equation 1).

  In view of this, the total thickness of the ferrimagnetic film 17 and the reference layer side interface layer 16 (the thickness of the entire reference layer 12) is set to 11 nm. Then, the composition ratio (Tb: Co) of Tb and Co in the ferrimagnetic film 17 is set to 4: 1.

In the reference layer 12 including the ferrimagnetic film 17, the total net magnetization NetMs of the ferrimagnetic film 17 and the reference layer side interface layer 16 is approximately 0 (zero) emu / cc. The shift magnetic field (leakage magnetic field) H _ext applied to the memory layer at 85 ° C. is 0 (zero) Oe.

At 160 ° C., the magnetization of the Tb sublattice in the ferrimagnetic film 17 disappears, and the magnetization of the Co sublattice in the ferrimagnetic film 17 and the magnetization of the reference layer side interface layer 16 remain. In the MTJ element 1B including the reference layer 12 in which the film thickness and the composition ratio of the ferrimagnetic film are set, the magnitude of the leakage magnetic field H _ext applied to the storage layer 10 at 160 ° C. is 880 Oe.

  The composition ratio of each element of the CoFeB layer as the reference layer side interface layer 16 is appropriately set so that the relationship shown here is satisfied.

  As described above, according to the parameters of the reference layer (the ferrimagnetic film and the interface layer) and the storage layer of the MTJ element 1B exemplified here, the reference layer 12 and the storage are stored under the mounting temperature (160 ° C. here) condition. The magnetic field with the layer 10 can secure a shift magnetic field that maintains the “0” data retention state.

  As described above, in the MTJ element 1B of this embodiment, the film thicknesses of the ferrimagnetic film 17 and the reference layer side interface layer 16 and the composition ratio of the sublattice included in the ferrimagnetic film 17 are controlled, respectively. A shift magnetic field applied to the storage layer 10 due to the leakage magnetic field from the reference layer 12 under the mounting temperature can be obtained so as to satisfy (Equation 1).

  The magnetoresistive effect element 1B of this embodiment includes a reference layer having a ferrimagnetic film and an interface layer, and two sublattices (rare earth metal sublattice and transition metal sublattice) in the ferrimagnetic film have different magnetization temperatures. Has dependency.

  Thereby, in the magnetoresistive effect element 1B of the present embodiment, the shift magnetic field is canceled at the memory operating temperature, so that the magnetization of the storage layer is reversed according to the data to be written. In the magnetoresistive effect element 1B according to the present embodiment, the shift magnetic field remains due to the temperature dependence of the sublattice in the ferrimagnetic film at the mounting temperature, and the magnetization reversal of the storage layer is caused by the shift magnetic field. It is suppressed and a predetermined data holding state is maintained.

  Therefore, the magnetic memory including the magnetoresistive effect element of this embodiment can write data to the memory cell during the memory operation, and magnetization reversal occurs in the MTJ element due to heat during the mounting process. It is possible to suppress a change in data to be held in the reference potential generation cell. Therefore, similarly to the first embodiment, the magnetoresistive effect element of this embodiment and the magnetic memory including the same can suppress the occurrence of malfunction in the magnetic memory due to heat in the mounting process.

  The magnetic memory including the magnetoresistive effect element according to the present embodiment can reduce the check process and the data write process for the reference potential generation cell after the mounting process, and the circuit for these processes is not provided in the chip of the magnetic memory. Both get better. Also, the magnetic memory including the magnetoresistive effect element of this embodiment can be formed in the same chip by using the same material and the same process as the MTJ element of the memory cell and the MTJ element of the reference potential generating cell. Therefore, the magnetic memory including the magnetoresistive effect element according to the present embodiment can increase the efficiency of manufacturing the magnetic memory, and can suppress an increase in the manufacturing cost of the magnetic memory.

  By appropriately setting the materials used for the ferrimagnetic film and the reference layer side interface layer, the magnetization reversal in the shift cancel state can be executed under the memory operating temperature, and the “1” data retention state is stable under the mounting temperature condition. An MTJ element that can be maintained at a high level can be formed.

  As described above, according to the magnetoresistive effect element of the second embodiment, it is possible to suppress the memory malfunction caused by the heat during the manufacturing process as in the first embodiment.

[Others]
In the present embodiment, the magnetoresistive effect element (MTJ element) of the reference cell and the replica cell suppresses the magnetization reversal caused by heat during the mounting process by utilizing the difference in the magnetization temperature dependence of the plurality of magnetic layers. The configuration was described. However, the magnetic memory including the MTJ element 1A of each embodiment may be a ROM. In the MTJ element as a ROM memory element, the magnetization reversal of the MTJ element due to heat during the mounting process may be suppressed by the difference in the magnetization temperature dependence of the plurality of magnetic layers. As a result, unintentional magnetization reversal of the MTJ element in the ROM due to heat can be suppressed, and data to be stored in the ROM can be suppressed from being rewritten with incorrect data.

Data reading from a magnetic memory using reference potential generation cells (reference cells and replica cells) will be described. For example, there are the following three methods for generating a reference signal (potential or current) input to a sense amplifier for reading data from a magnetic memory.
As a first method, a combined resistance is formed by a reference cell in a high resistance state (anti-parallel state, “1” data holding state) and a reference cell in a low resistance state (parallel state, “0” data holding state). . As a result, an intermediate resistance value between the resistance value in the “1” data holding state and the resistance value in the “0” data holding state (hereinafter referred to as an intermediate resistance) is formed. A current (or voltage) is applied to the two reference cells forming the intermediate resistor, and a reference signal for data reading is generated. In this reference signal generation method, a reference cell of several tens of kbits is provided in a chip.

  As a second method, when data is read using a read current (current flowing from the storage layer to the reference layer) that flows in the direction of magnetization reversal from the antiparallel state to the parallel state, the reference cell in the “0” data holding state is 1 is used. The potential of the bit line to which the reference cell is connected is generated using one replica cell in the “0” data holding state and one replica cell in the “1” data holding state. In this reference signal generation method, a reference cell in a “0” data holding state of several tens of kbits is provided in a chip. In addition, a replica cell of “0” data holding state and “1” data holding state of several tens of bits is provided in the chip.

  As a third method, when data is read using a read current (current flowing from the reference layer to the storage layer) that flows in the direction of magnetization reversal from the parallel state to the antiparallel state, the reference cell in the “1” data holding state is 1 is used. The potential of the bit line to which the reference cell is connected is generated using one replica cell in the “0” data holding state and one replica cell in the “1” data holding state. In this reference signal generation method, a reference cell in a “0” data holding state of several tens of kbits is provided in a chip. In addition, a replica cell of “0” data holding state and “1” data holding state of several tens of bits is provided in the chip.

  The reason why the reference signal for data reading is generated using the replica cell as in the second and third methods is to suppress the read disturb (reversal of magnetization of the reference cell) of the reference cell due to the read current. It is.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1A, 1B: magnetoresistive effect element, MC: memory cell, RC: reference potential generation cell, 10: storage layer, 11: nonmagnetic layer, 12: reference layer, 13: shift adjustment layer, 16: interface layer, 17: Ferrimagnetic film.

Claims (5)

A storage layer having perpendicular magnetic anisotropy and a variable magnetization direction;
A reference layer having perpendicular magnetic anisotropy and an invariable magnetization direction;
A nonmagnetic layer between the storage layer and the reference layer;
A shift adjustment layer provided on the opposite side of the reference layer to the side on which the nonmagnetic layer is provided, having a perpendicular magnetic anisotropy, and having a magnetization orientation unchanged;
Comprising
The reference layer has a first magnetization temperature dependency; the shift adjustment layer has a second magnetization temperature dependency different from the first magnetization temperature dependency;
At the memory operating temperature, the leakage magnetic field of the reference layer and the leakage magnetic field of the shift adjustment layer are canceled each other,
At the mounting temperature, a shift magnetic field caused by one of the reference layer and the shift adjustment layer is applied to the magnetization of the storage layer.
A magnetoresistive effect element. A storage layer having perpendicular magnetic anisotropy and a variable magnetization direction, a ferrimagnetic layer having perpendicular magnetic anisotropy, in which the magnetization direction is invariant, and including a first sublattice and a second sublattice. A reference layer including a magnetic film;
A nonmagnetic layer between the reference layer and the storage layer;
An interface layer provided between the ferrimagnetic film and the nonmagnetic layer and having perpendicular magnetic anisotropy;
Comprising
The first sublattice has a first magnetization temperature dependency, and the second sublattice has a second magnetization temperature dependency different from the first magnetization temperature dependency,
At the memory operating temperature, the leakage magnetic field between the ferrimagnetic film and the interface layer is canceled each other,
At the mounting temperature, the magnitude of the magnetization of the first sub-lattice is smaller than the magnitude of the magnetization of the second sub-lattice, and the shift magnetic field caused by the second sub-lattice and the interface layer is Applied to the magnetization of
A magnetoresistive effect element.   3. The magnetoresistive effect element according to claim 1, wherein the direction of magnetization of the storage layer is parallel to the direction of the shift magnetic field at the mounting temperature. 4.   The first sublattice is at least one element selected from the group including Tb, Dy, and Sm, and the second sublattice is at least one element selected from the group including Co and Fe. The magnetoresistive element according to claim 2, wherein the magnetoresistive element is provided.   5. The magnetoresistive effect element according to claim 1, wherein the memory operating temperature is 100 ° C. or lower, and the mounting temperature is 160 ° C. or higher.

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