JP2013069357A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having advantage in reducing power consumption.SOLUTION: A semiconductor memory device comprises: a memory cell array provided with a plurality of memory cells; sense amplifiers S/A0 through S/A7 for sensing input data or output data of the plurality of memory cells; latch circuits 22 disposed among even-side amplifiers and odd-side sense amplifiers so as to electrically isolate them; cache memories 23 electrically connected to either the even-side amplifiers or the odd-side sense amplifiers; and a controlling circuit for controlling them. When performing input operation of the input data, the controlling circuit transfers the input data of the memory cells to either the even-side amplifiers or the odd-side sense amplifiers while transferring input data of the latch circuits 22 to either the even-side amplifiers or the odd-side sense amplifiers.

Description

  The present invention relates to a semiconductor memory device.

  As an example of the semiconductor memory device, there is a NAND flash memory, for example.

  In the data transfer operation of the NAND flash memory, a BUS pre-charge method in which data transfer is performed depending on whether the data bus is discharged or whether the state of charge is maintained may be applied according to the value of the cache memory. This method is often used from the viewpoint of area reduction.

  However, in the BUS pre-charge method, when “0” is transferred to the bus (BUS), charging and discharging are repeated, which is inefficient from the viewpoint of current consumption. In addition, since all the buses (BUS) are charged even when data is transferred between relatively close latches, current is wasted correspondingly. Therefore, there is a tendency that it is disadvantageous for low power consumption.

JP-A-9-274527

  Provided is a semiconductor memory device advantageous for low power consumption.

  According to the embodiment, a semiconductor memory device according to an aspect includes a memory cell array including a plurality of memory cells, an even-numbered side that senses input data or output data of the memory cell, an odd-numbered sense amplifier, and the even-numbered side. A latch circuit arranged so as to be electrically separated between the odd-numbered sense amplifiers, a memory electrically connected to either the even-numbered side or odd-numbered side sense amplifiers, and these are controlled. A control circuit, and during the input operation of the input data, the control circuit transfers the input data of the latch circuit to either the even-numbered side or odd-numbered side sense amplifier, and the input data of the memory Are transferred to either the odd-numbered side or even-numbered side sense amplifier.

1 is a block diagram showing an example of the overall configuration of a semiconductor memory device according to a first embodiment. FIG. 2 is an equivalent circuit diagram illustrating a configuration example of a block in FIG. 1. The block diagram which shows the S / A & latch area | region and buffer area | region in FIG. FIG. 4 is a block diagram showing a relationship between a bit line and a data bus in FIG. 3. The block diagram which shows the structural example of the S / A & latch area | region in FIG. 1 in FIG. FIG. 6 is an equivalent circuit diagram illustrating a configuration example of a latch circuit (temporary latch) in FIG. 5. FIG. 3 is a flowchart showing a data input operation of the semiconductor memory device according to the first embodiment. The timing chart figure which shows data input operation (Data in). FIG. 3 is a flowchart showing a data output operation of the semiconductor memory device according to the first embodiment. The timing chart figure which shows data output operation | movement (Data out). The block diagram which shows the S / A & latch area | region and buffer area | region which concern on a reference example. FIG. 12 is a block diagram illustrating a configuration example of an S / A & latch area in FIG. 11. The block diagram which shows the circuit structure of the data bus unit of the S / A & latch area | region in FIG. FIG. 14 is an equivalent circuit diagram showing a circuit configuration in S / A units in FIG. 13. The flowchart which shows the data input operation | movement of the semiconductor memory device which concerns on a reference example. The timing chart figure which shows data input operation (Data in). The flowchart which shows the data output operation | movement of the semiconductor memory device which concerns on a reference example. The timing chart figure which shows data output operation | movement (Data out).

  Embodiments and reference examples will be specifically described below with reference to the drawings. In this description, a NAND flash memory is taken as an example of the semiconductor memory device, but the present invention is not limited to this. For example, the same applies to other semiconductor memory devices such as BiCS in which NAND flash memories are stacked in three dimensions, ReRAM (Resistance Random Access Memory), PRAM (Phase change Random Access Memory), and MRAM (Magnetic Random Access Memory). It is possible to apply to. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor memory device according to the first embodiment will be described.
<1. Configuration example>
1-1. Overall configuration example
First, an example of the overall configuration of the semiconductor memory device according to the first embodiment will be described with reference to FIG. As illustrated, the semiconductor memory device according to the first embodiment includes a memory cell array 11, a sense amplifier / latch region 12, buffer regions 13 and 14, a control circuit 15, and a pad 16.

  The memory cell array 11 is composed of a plurality of blocks (BLOCK0 to BLOCKn). Each of the blocks (BLOCK0 to BLOCKn) includes a plurality of memory cells arranged in a matrix, as will be described in detail later.

  The sense amplifier / latch (S / A & latch) region 12 includes a plurality of sense amplifier / latch (S / A & latch) circuits 21 connected in common to an internal I / O bus (n: 0). Is placed. The plurality of sense amplifier / latch (S / A & latch) circuits 21 are driven by control signals generated by the control circuit 15 and buffered by the buffer regions 13 and 14. Details will be described later.

  The buffer regions 13 and 14 are arranged at both ends so as to sandwich the memory cell array 11 and the sense amplifier / latch region 12. The buffer areas 13 and 14 are configured to buffer the control signal generated by the control circuit 15.

  For example, the control circuit 15 generates the control signal and controls the overall operation of the semiconductor memory device.

  Input / output data (I / O <n: 0>), address (address), command (command), and the like are given from the host device or the like outside the semiconductor memory device via the pad 16.

  The overall circuit configuration is as shown in FIG. A. The control signal generated by the control circuit is buffered in the buffer area and drives the switch of the S / A & Data latch.

1-2. Block (BLOCK) configuration example
Next, a configuration example of a block (BLOCK) according to the first embodiment will be described with reference to FIG. Here, one block (BLOCK 1) will be described as an example. Here, since the memory cells in the block BLOCK 1 are erased collectively, the block is a data erasing unit.

  As shown in the drawing, the block BLOCK1 is composed of a plurality of memory cell units MU arranged in the word line direction (WL direction). The memory cell unit MU is arranged in a bit line direction (BL direction) intersecting the WL direction, and a NAND string (memory cell string) including eight memory cells MC0 to MC7 whose current paths are connected in series, and a NAND string The source-side selection transistor S1 connected to one end of the current path of the current and the drain-side selection transistor S2 connected to the other end of the current path of the NAND string.

  In this example, the memory cell unit MU is composed of eight memory cells MC0 to MC7, but may be composed of two or more memory cells, for example, 56, 32, etc. It is not limited to individuals.

  The other end of the current path of the source side select transistor S1 is connected to the source line SL. The other end of the current path of the drain-side selection transistor S2 is provided above the memory cell unit MU corresponding to each memory cell unit MU, and is connected to the bit line BLm-1 extending in the BL direction.

  Word lines WL0 to WL7 extend in the WL direction and are commonly connected to control gate electrodes CG of a plurality of memory cells in the WL direction. The selection gate line SGS extends in the WL direction and is commonly connected to a plurality of selection transistors S1 in the WL direction. The selection gate line SGD also extends in the WL direction and is commonly connected to a plurality of selection transistors S2 in the WL direction. Each of the memory cells MC0 to MC7 has a stacked structure including a tunnel insulating film, a floating gate FG, an inter-gate insulating film (IPD), and a control gate CG which are sequentially provided on a semiconductor substrate (not shown).

  A page (PAGE) exists for each of the word lines WL0 to WL7. For example, as indicated by being surrounded by a broken line in the figure, the page 7 (PAGE 7) exists in the word line WL7. Since a data read operation and a data write operation which will be described later are performed for each page (PAGE), the page (PAGE) is a data read unit and a data write unit.

1-3. Configuration example of S / A & latch area and buffer area
Next, a configuration example of the sense amplifier / latch (S / A & latch) region 12 and the buffer region 14 according to the first embodiment will be described with reference to FIG.
As shown in the figure, a plurality of sense amplifier / latch circuits 21 are arranged in the S / A & latch region 12. The plurality of sense amplifier / latch circuits 21 include a sense amplifier circuit, a latch circuit 21, and a cache memory 23, respectively.

  The sense amplifier circuit includes a plurality of sense amplifiers (S / A0 to S / A7) on an even side (Even side) and an odd side (Odd side). The even side (even side) and odd side (odd side) regions of the sense amplifier circuit are divided and arranged so as to correspond to the even and odd addresses of the cache memory 23.

  The latch circuit (temporary latch) 21 includes an even side sense amplifier (S / A0, S / A2, S / A4, S / A6) and an odd side sense amplifier (S / A1, S / A1, S). S / A3, S / A5, S / A7) are arranged so as to be divided.

  The cache memory (Cache memory <7: 0>) 23 caches even addresses and odd addresses.

  Details of the sense amplifier circuit, the latch circuit 21, and the cache memory 23 will be described later.

  In the buffer area 14, a plurality of buffer circuits BF0 to BF7, BF22, and BF23 are arranged.

  The buffer circuits BF0 to BF7 are commonly connected to the sense amplifiers S / A0 to S / A7, buffer the S / A control signals 0 to 3 generated from the control circuit 15, and sense amplifiers S / A0 to S / A7. Give to each.

  The buffer circuit BF22 is connected to the latch circuit 22 in common, and buffers the tmp latch control signal 3 generated from the control circuit 15 and applies the buffer to the latch circuit 22.

  The buffer circuit BF23 is connected in common to the cache memory 23, and buffers the cache memory control signal <7: 0> generated from the control circuit 15 and applies the cache memory control signal <7: 0> to the cache memory 23.

  The buffer area 13 has the same configuration as the buffer circuit area 14. Which of the buffer regions 13 and 14 is used can be applied depending on the distance from the sense amplifier / latch circuit 21 to be selected.

  As described above, in the buffer areas 13 and 14 according to this example, the S / A control signals 0 to 3 given to the sense amplifier / latch area 12 can be shared between the even-numbered side and the odd-numbered side. For this reason, as shown by being surrounded by a broken line 17 in the figure, the control wiring can be shared and the wiring area can be reduced. For example, compared to a reference example shown in FIG. 17 described later, the wiring area and the buffer element can be reduced to half. Further, there is a merit in that the area of the circuit that generates the S / A control signal in the control circuit 15 can be reduced.

1-4. Relationship between bit line and data bus
Next, the electrical connection relationship between the bit line and the data bus according to the first embodiment will be described with reference to FIG.
As shown in the figure, bit lines BL0 to BL7 from the memory cell array 11 are electrically connected to sense amplifiers SA0 to SA7, respectively.

  The data bus 20 is electrically connected to the sense amplifiers SA0 to SA7, the latch circuit 22, and the cache memory 23 in common.

  Here, the arrangement of the sense amplifiers SA0 to SA7, the latch circuit 22, and the cache memory 23 is shown in order to explain the electrical connection relationship between the bit line and the data bus, but these arrangements in the embodiment are as follows. FIG. 3 shows the above.

1-5. Sense amplifier / latch circuit 21
Next, the sense amplifier / latch circuit 21 will be described more specifically with reference to FIG.
As shown in the figure, the sense amplifier / latch circuit 21 includes a cache memory (Cache memory 0-7) 23 and odd-side S / A circuits (S / A1, S / A3, S / A5, S / A7). "Data bus_e (20_e)" connected to the "S bus" and "Data bus_e (20_e)" connected to the S / A circuit (S / A0, S / A2, S / A4, S / A6) on the even side Is done.

  Data bus pre-charge transistors P10 and P11 are connected to Data bus_e (20_e) and Data bus_o (20_o), respectively. The internal power supply voltage Vcc is applied to one end of the current path of the precharge transistors P10 and P11, the other end of the current path is connected to Data bus_e (20_e) and Data bus_o (20_o), respectively, and the gate is connected to the control circuit 15 Execution command is given. For this reason, when an execution command is input to the precharge transistors P10 and P11, the current path is turned on, and the data bus_e (20_e) and the data bus_o (20_o) are precharged (pre-charge).

  The cache memory 23 is connected to the Data bus_o (20_o), and temporarily holds data input from the outside of the chip by the host device or the like.

  The latch circuit (tmp latch) 22 includes an S / A circuit (S / A0, S / A2, S / A4, S / A6) on the Even side and an S / A circuit (S / A1, S / A3, S / A5 and S / A7) are arranged so as to be electrically separated from each other.

  In this example, the configuration includes eight S / A circuits and eight cache memories, but this is not restrictive. Although the odd address of the S / A circuit is arranged on the cache memory side, this is not the case. The data latch, the cache memory 23, and the temporary latch 22 may be circuits that have a function of temporarily holding data. Therefore, for example, a static latch or a dynamic latch may be used.

1-6. Circuit configuration example of latch circuit
Next, a circuit configuration example of the latch circuit (temporary latch) 22 will be described more specifically with reference to FIG.
As illustrated, the latch circuit 22 according to this example includes a latch unit 30, a charging transistor P23, and switches SWA and SWB.

The latch unit 30 includes inverters 31 and 32 that are latch-connected to each other.
The inverter 31 includes a P-type transistor P21 having one end of a current path connected to the internal power supply voltage Vcc and a gate connected to the node A, and one end of the current path connected to the ground power supply voltage GND and a gate connected to the node A. The other end of the path is configured by an N-type transistor N21 connected to the other end of the transistor P21. The inverter 32 includes a P-type transistor P22 having one end of a current path connected to the internal power supply voltage Vcc and a gate connected to the inverter 32, and one end of the current path connected to the ground power supply voltage GND and a gate connected to the inverter 32. The other end of the path is configured by an N-type transistor N22 connected to the other end of the transistor P22 and the node A.

  Charging transistor P23 has one end of the current path connected to internal power supply voltage Vcc, the gate supplied with a control signal from control circuit 15, and one end of the current path connected to node A.

  The switch SWA has one end of a current path connected to the internal power supply voltage Vcc, a gate supplied with a control signal from the control circuit 15, and one end of the current path connected to the node A.

  The switch SWB has one end of a current path connected to the ground power supply voltage GND, a gate supplied with a control signal from the control circuit 15, and one end of the current path connected to a node A.

<Regarding Transfer Operation of Latch Circuit 22>
Here, the transfer operation of the latch circuit 22 configured as described above will be described by taking as an example a case where data is transferred from Data bus_e (20_e) to Data bus_o (20_o).

  First, the Data bus_e / o (20_e / o) is charged, and the node A is charged by the charging transistor P23.

  Subsequently, the value of Data bus_e (20_e) is transferred to the node A by turning on the switch SWA.

  Subsequently, Data bus_e / o (20_e / o) is charged. At this time, the current paths of the switches SWA and SWB are made non-conductive.

  Subsequently, the value of the node A is transferred to the Data bus_o (20_o) by conducting the current path of the switch SWB.

<2. Data input / data output operation>
2-1. Data input operation
Next, a data input operation flow of the sense amplifier / latch (S / A & latch) circuit 21 according to the first embodiment will be described with reference to FIG. Here, the data input operation refers to an operation of transferring input data (write data) input from an external host device or the like and cached in the cache memory 23 to each desired sense amplifier. In this operation flow, control of each step is performed by the control circuit 15.
First, in step S11, the current paths of the precharge transistors (Data bus pre-charge transistors) P10 and P11 are made conductive by the BUS pre-charge method, and Data bus_e (20_e) and Data bus_o (20_o) are charged, respectively. .

  Subsequently, when the cache memory control signal 0 and the temporary latch control signal are turned on at steps S12 and S13, the cache data of the Cache memory0 is held in the latch circuit (temporary latch) through the Data bus_o (20_o). At this time, the Data bus_e side (20_e) does not operate.

  Subsequently, at the time of step S14, Data bus_o is again charged in the same manner.

Subsequently, in steps S15 and S16, when the cache memory control signal 1, the temporary latch control signal, and the S / A control signal 0 are turned ON, the latch data of the latch circuit (temporary latch) 22 passes through the Data bus_e. While being transferred to the sense amplifier S / A0, the cache data in the Cache memory 1 is transferred to the S / A1 through the Data bus_o.
As described above, in this example, the latch circuit 22 is arranged so as to divide the even side / odd side sense amplifiers, and the S / A signal control signal 0 is the first stage sense amplifier S / s of the even side / odd side. Shared by A0 and S / A1. For this reason, when the S / A signal control signal 0 is input, the switches of the sense amplifiers S / A0 and S / A1 are simultaneously opened, and the data can be set simultaneously in the sense amplifiers S / A0 and S / A1. it can.

  Subsequently, in step S17, it is determined whether or not all data transfer has been completed (n = max ?: n = 4 in this example). If all data transfer has not been completed (NO), the value of n is incremented (n = n + 1), and the same operation is repeated until all data is transferred. On the other hand, if all the data transfer has been completed (YES), this operation ends (end).

Data input operation timing chart
A timing chart of the data input operation is shown in FIG.
As shown in the drawing, in the first embodiment, the S / A signal control signals 0 to 3 can be shared by the sense amplifiers S / A0 to S / A7 between the Even side / Odd side.

  Therefore, for example, at time t2, if the S / A signal control signal 0 is input while the temporary latch control signal and the cache memory control signal 1 are at the “H” level, the first stage of the Even side / Odd side Data can be simultaneously transferred to the sense amplifiers S / A0 and S / A1.

  Similarly, for example, at time t4, data can be simultaneously transferred to the second-stage sense amplifiers S / A2 and S / A3 on the Even side / Odd side.

  Here, compared with the Data In waveform of the reference example shown in FIG. 16, it seems that the operation of temporarily transferring to the temporary latch is increased. However, in the first embodiment, Data bus_e and Data bus_o are operated in parallel. As a result, the number of clocks required for all data transfer in the end can be made the same.

  Furthermore, since the capacity of one bus (BUS) 20 is reduced by dividing the data bus_e and the data bus_o, the driving force can be increased. Thus, the data transfer time can be shortened by improving the driving force.

  Data transfer between the Odd side sense amplifiers (S / A1, S / A3, S / A5, S / A7) connected to the Data bus_o and the Cache memory 23 does not use the Data bus_e. The current consumption can be reduced by that amount.

2-2. Data output operation
Next, a data output operation flow of the sense amplifier / latch (S / A & latch) circuit 21 according to the first embodiment will be described with reference to FIG. Here, the data output operation refers to an operation for transferring output data (read data) set in the sense amplifier to the cache memory 23 to the cache, and an operation in the opposite flow to the data input operation. In this operation flow, control of each step is performed by the control circuit 15.
First, at the time of step S21, similarly, the current paths of the precharge transistors (Data bus pre-charge transistors) P10 and P11 are made conductive by the BUS pre-charge method, and Data bus_e (20_e) and Data bus_o (20_o) are set. Charge each one.

Subsequently, in steps S22 and S23, when the S / A control signal 0, the temporary latch control signal, and the cache memory control signal 1 are turned on, the data of the sense amplifier S / A0 is latched through the Data_bus_e. The data of the sense amplifier S / A1 is latched in the Cache memory 1 through the Data bus_o.
Thus, also in the data output operation, in the first embodiment, the latch circuit 22 is arranged so as to divide the Even side / Odd side sense amplifier, and the S / A signal control signal 0 is the Even side / Odd side. Shared by the first sense amplifiers S / A0 and S / A1 on the side. Therefore, when the S / A signal control signal 0 is input, the switches of the sense amplifiers S / A0 and S / A1 are opened at the same time, and the data held in the sense amplifiers S / A0 and S / A1 are transferred simultaneously. be able to.

  Subsequently, at the time of step S24, Data bus_e and Data bus_o are similarly charged.

  Subsequently, in steps S25 and S26, when the temporary latch control signal and the cache memory control signal 0 are turned on, the data of the latch circuit (temporary latch) 22 is held in the cache memory 0 through the data bus_o. At this time, the Data bus_e side does not operate.

  Subsequently, at step S27, it is determined whether or not all data transfer has been completed (n = max ?: n = 4 in this example). If all data transfer has not been completed (NO), the value of n is incremented (n = n + 1), and the same operation is repeated until all data is transferred. On the other hand, if all the data transfer has been completed (YES), this operation ends (end).

Data output operation timing chart
A timing chart of the data output operation is shown in FIG.
As shown in the drawing, in the first embodiment, the S / A signal control signals 0 to 3 can be shared by the sense amplifiers S / A0 to S / A7 between the Even side / Odd side.

  Therefore, for example, at time t1, if the S / A signal control signal 0 is input while the temporary latch control signal and the cache memory control signal 1 are at the “H” level, the first stage of the Even side / Odd side Data can be simultaneously transferred from the sense amplifiers S / A0 and S / A1.

  Similarly, for example, at time t3, data can be simultaneously transferred from the second-stage sense amplifiers S / A2 and S / A3 on the Even side / Odd side.

  Here, compared with the Data Out waveform according to the reference example shown in FIG. 18, in the first embodiment, it seems that the operation of temporarily transferring to the temporary latch is increased, but the Data bus_e and Data bus_o are operated in parallel. Thus, similarly, the number of clocks finally required for all data transfer can be made the same. The effect of reducing current consumption is the same as that of Data In.

<3. Effect>
According to the semiconductor memory device and the control operation thereof according to the first embodiment, at least the following effects (1) to (3) can be obtained.

(1) Power consumption can be reduced.
As described above, the semiconductor memory device according to this example includes the latch circuit 22 arranged between the even-numbered and odd-numbered sense amplifiers S / A0 to S / A7 so as to electrically isolate them. Therefore, in this example, when the input data is input, the control circuit 15 transfers the input data of the latch circuit 23 to the even-numbered sense amplifiers (S / A0, S / A2, S / A4, S / A6). At the same time, the input data of the cache memory 23 is transferred to the odd-numbered sense amplifiers (S / A1, S / A3, S / A5, S / A7).

  Thus, in this example, the even-numbered and odd-numbered sense amplifiers are electrically divided by the latch circuit 22, and the data transfer operations of the even-numbered and odd-numbered sense amplifiers can be performed simultaneously and in parallel.

  Therefore, the data transfer between the Odd side sense amplifier (S / A1, S / A3, S / A5, S / A7) connected to the Data bus_o (odd side) and the Cache memory 23 is performed by Data bus_e (even side). ) Is not used, and current consumption can be reduced by the amount of Data bus_e (even side) that is not used.

  Here, for example, as shown in FIG. 13, the S / A circuit according to the reference example includes one Sense Amp and three Data latches 1 to 3, and the sizes of the Sense Amp, Data latches 1 to 3, and Cache memory. Consider estimating the amount of power consumption reduction as in the first embodiment.

  When the capacity of the data bus 200 of the reference example is “1”, Data bus_e = “2/5” and Data bus_o = “3/5”. In the example of the first embodiment, since eight cache memories 23 are connected, it takes eight times in total to transfer all data. Therefore, using the first embodiment, the current consumed to transfer all data is 4 * 1 (Data bus_e * 4) + 4 * 3/5 (Data bus_o * 4) = “6.4”. On the other hand, the current consumption of the reference example is 8 * 1 = “8”.

  As a result, it can be seen that the power consumption can be reduced by about 20%.

  Furthermore, if the data size that can be input at one time is 16 Kbytes, the number of data buses in the example of the first embodiment is 16000, so it is clear that the overall power consumption reduction effect has a very large impact. . In addition, the power consumption reduction effect has the same merit in the data output operation.

  Thus, according to the semiconductor memory device and the control operation thereof according to the first embodiment, the power consumption can be reduced, which is advantageous for reducing the power consumption.

(2) The occupied area can be reduced, which is advantageous for miniaturization.
As described above, in the configuration according to this example, the S / A control signals 0 to 3 given to the sense amplifier / latch region 12 can be shared between the even-numbered side and the odd-numbered side.

  Therefore, as shown by being surrounded by a broken line 17 in FIG. 3, the control wiring can be shared, and the wiring area can be reduced. For example, the number of wires, the wiring area, and the buffer element can be reduced to about half as compared with a reference example surrounded by a broken line 170 in FIG.

Further, there is a merit in that the area of the circuit that generates the S / A control signal in the corresponding control circuit 15 can be reduced.
As described above, since a plurality of latch circuits (Data latch) 22 and cache memory (Cache memory) 23 are electrically connected to one Data bus 20, the total wiring length of the BUS 20 is increased, and the wiring capacity is increased. It tends to grow. Furthermore, as the NAND flash memory is miniaturized and increased in capacity, the number of Data buses 20 that can be accommodated in the chip increases, and the current consumed by the Data bus tends to increase.

  However, in the first embodiment, the current consumption consumed by data transfer can be reduced, and the control signal of the Sense Amp circuit can also be reduced. As described above, according to the structure of this example, the Sense Amp circuit area is divided into two on the even side and the odd side, and only one latch circuit (Temporary latch) 22 is arranged between the divided areas. , The effect of area increase can be minimized.

(3) The driving force can be improved and the transfer speed can be improved.
Furthermore, the capacity of the data bus connected to a specific data latch 22 can be reduced by dividing the data bus 20 into the even-numbered data bus 20_e and the odd-numbered data bus 20_o. Therefore, there is an advantage in that the driving force can be improved and the transfer speed can be improved.

[Reference example]
Next, for comparison and reference with the first embodiment, a semiconductor memory device according to a reference example will be described. In this description, a detailed description of the same parts as those in the first embodiment is omitted.

<Configuration>
First, the sense amplifier & latch area 120 and the buffer area 140 according to the reference example are shown as shown in FIG. In the comparative example shown in the figure, for example, no latch circuit is arranged, and therefore, S / A control signals 0-7 are respectively required corresponding to the sense amplifiers S / A0 to S / A7. This is different from the first embodiment. Therefore, it is disadvantageous for reducing power consumption. In addition, as indicated by a broken line 170 in the figure, the wiring area increases, which tends to be disadvantageous for miniaturization.

  The sense amplifier & latch region 120 according to the reference example is shown as in FIG. As shown in the figure, the sense amplifiers S / A0 to S / A7 and the cache memory 0-7 are electrically connected to one data bus 200.

  The circuit configuration of the sense amplifier in data bus units according to the reference example is shown in FIG. As shown in the figure, the sense amplifiers S / A0 and S / A1 are each configured by one sense amplifier circuit connected to the local bus local bus0 and local bus1 and three data latch circuits. As described above, in FIG. 12, the sense amplifiers S / A0 to S / A7 and the cache memories Cache memory 0-7 are shown to have the same size. However, in practice, the sense amplifiers S / A0 to S / A7 are each composed of one sense amplifier circuit and three data latch circuits. Therefore, the sense amplifiers S / A0 to S / A7 occupy about four times or more the size of the cache memory Cache memory0-7.

  The circuit configuration of the sense amplifiers S / A0 to S / A7 according to the reference example is as shown in FIG. As illustrated, the sense amplifier S / A0 includes a local switch switch 0-3, a data bus switch data bus switch, and two bus pre-charge transistors (data bus pre-charge transistors).

<Data input / data output operation>
Data input operation
Next, the data input operation flow of the semiconductor memory device according to the reference example is shown in FIG. Here, the input data input from the outside of the semiconductor memory device chip is temporarily held in the Cache memory 0-7.

  First, in step S110, when an execution command is input, the Data bus pre-charge transistor is turned on and the Data bus 200 is pre-charged (charged).

  Subsequently, at step S120, the control signal 150 is transferred from the control circuit 150 to the cache memory 0 and the S / A0 circuit through the buffer areas 130 and 140, and the cache memory 0 and the S / A0 circuit Switch are opened.

  Subsequently, in step S130, data transfer is performed depending on whether the data bus is discharged or the charged state is maintained according to the value of Cache memory0. When the control signal 0 is turned off, the cache memory 0 and the switch of the S / A0 circuit are closed, and the transfer of the cache memory 0 is finished.

  Subsequently, in step S140, it is determined whether or not all data transfer has been performed. Depending on the determination result, this operation is repeated 8 times to transfer all data.

  A timing chart of the data input operation along the flow is shown in FIG.

  Such a transfer method is called a BUS pre-charge method, and this transfer method is often used from the viewpoint of area reduction. Since there are many Cache memory0-7 and Data latch1-3 of sense amplifier, a small size transistor is used for area reduction. For this reason, it is difficult to drive the BUS 200 having a large capacity with a small PMOS transistor. In the BUS pre-charge method, the data transfer is performed by charging the BUS line 200 using a large-sized PMOS transistor before data transfer and discharging through the NMOS transistor on the latch side or holding the charged state through the PMOS transistor. Is realized. Although the BUS pre-charge method is effective in reducing the area, charging and discharging are repeated when “0” is transferred to the BUS 200, which is inefficient from the viewpoint of current consumption. Further, since all the buses 200 are charged even by data transfer between relatively close latches, the current is consumed wastefully by that amount.

Data output operation
Next, the data output operation flow and the timing chart of the semiconductor memory device according to the reference example are shown in FIGS.

  As shown in the figure, the data output operation is the reverse of the operation between the sense amplifier S / A0-7 and the Cache memory 0-7 in the data input operation.

  For this reason, the data output operation also tends to be disadvantageous for low power consumption, as in the data input operation.

  Although the embodiments and reference examples of the present invention have been described, these embodiments and reference examples are presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Sense amplifier * latch area | region, 13, 14 ... Buffer area | region, 15 ... Control circuit, 16 ... Pad.

Claims (5)

A memory cell array comprising a plurality of memory cells;
An even-numbered side and an odd-numbered side sense amplifier for sensing input data or output data of the memory cell;
A latch circuit disposed between the even-numbered side and odd-numbered side sense amplifiers to electrically separate them;
A memory electrically connected to either the even-numbered side or the odd-numbered side sense amplifier;
A control circuit for controlling these, and during the input operation of the input data, the control circuit,
A semiconductor memory device that transfers input data of the latch circuit to either the even-numbered side or odd-numbered side sense amplifier and transfers input data of the memory to either the odd-numbered side or even-numbered side sense amplifier. During the output operation of the output data, the control circuit
The semiconductor according to claim 1, wherein output data of either the even-numbered side or odd-numbered side sense amplifier is transferred to the latch circuit, and output data of either the odd-numbered side or even-numbered side sense amplifier is transferred to the memory. Storage device. The semiconductor memory device according to claim 1, wherein the control circuit generates a control signal for data transfer in common between the even-numbered and odd-numbered sense amplifiers. An even-side data bus electrically connected to the even-side sense amplifier;
An odd-numbered data bus electrically connected to the odd-numbered sense amplifier;
The even side and odd side data buses are electrically separated by the latch circuit,
The semiconductor memory device according to claim 2, wherein the control circuit operates the even-numbered and odd-numbered data buses in parallel during the input operation or the output operation. The latch circuit is
A latch unit for latching the input data or output data;
A charging transistor for charging the output node of the latch unit;
A first switching element having one end of a current path electrically connected to the even-numbered data bus and the other end of the current path connected to the output node;
The semiconductor memory device according to claim 4, further comprising: a second switching element in which one end of a current path is electrically connected to the odd-numbered data bus and the other end of the current path is connected to the output node.

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