JP2013069056A - Information processor and memory management method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which allows efficient processing of image data transferred from a transfer equipment and a memory management method.SOLUTION: An information processor comprises: a memory; a table; change means; and notification means. The memory has multiple buffer areas holding multiple pieces of image data. The table assigns the multiple buffer areas to reception buffers where image data is written and buffers for holding image data are held. When image data written in a reception buffer is held, the change means switches between the reception buffer where the image data to be held is written and a holding buffer. The notification means notifies an image transfer destination of information showing the reception buffer after the change when the change means switches between the reception buffer and the holding buffer.

Description

  Embodiments described herein relate generally to an information processing apparatus and a memory management method.

  Some information processing apparatuses perform image processing on image data sequentially transferred from a transfer apparatus. Further, the DMA transfer device has a function of directly writing image data into a reception buffer provided in a memory in the information processing device without using the control unit of the information processing device. When performing image processing on the image data written in the reception buffer by the DMA transfer device, the information processing device transfers the image data from the reception buffer to the holding buffer so that the image data on the buffer is not overwritten by the DMA transfer device. Processing to physically copy is required.

Japanese Patent Laid-Open No. 10-248003

  An object of the present invention is to provide an information processing apparatus and a memory management method capable of efficiently processing image data transferred from a transfer apparatus.

  According to the embodiment, the information processing apparatus includes a memory, a table, a changing unit, and a notification unit. The memory has a plurality of buffer areas for holding a plurality of image data. The table allocates a plurality of buffer areas to a reception buffer in which image data is written and a holding buffer that holds the image data. When holding the image data written in the reception buffer, the changing unit exchanges the reception buffer and the holding buffer in which the image data to be held is written. The notifying unit notifies the image transfer source of information indicating the changed reception buffer when the changing unit switches the reception buffer and the holding buffer.

FIG. 1 is a diagram schematically illustrating a configuration example of an image transfer system. FIG. 2 is a diagram illustrating an example of a buffer reference table. FIG. 3 is a flowchart for explaining the overall processing flow in the image processing system. FIG. 4 is a diagram illustrating an example of state transition in the buffer reference table. FIG. 5 is a flowchart for explaining the flow of memory management processing in the information processing apparatus.

Hereinafter, embodiments will be described with reference to the drawings.
FIG. 1 is a diagram schematically illustrating a hardware configuration example of an image processing system according to an embodiment.
The image processing system includes a camera 1, a DMA (Direct Memory Access) transfer device 2, and an information processing device 3. The camera 1 functions as an image generation unit that generates image data. For example, the camera 1 is configured by a digital camera that outputs captured images as digital image data. The camera 1 transmits image data of the captured image to the DMA transfer device 2.

  The DMA transfer device 2 is a data transfer device that can directly write data to an external memory. The DMA transfer device 2 includes a control unit 11 and a buffer memory 12. The control unit 11 controls the operation of the DMA transfer apparatus 2 and controls data transfer. The buffer memory 12 temporarily holds data. The buffer memory 12 is, for example, a FIFO memory and functions as a reception buffer memory that receives image data from the camera 1.

  The control unit 11 has a transfer address table 11a for designating a data transfer destination. The control unit 11 receives a notification indicating the address of the transfer buffer (reception buffer) from the information processing device 3, and updates the transfer address table 11a as needed. The control unit 11 refers to the transfer address table 11a to determine an address (transfer address) in the external memory in the information processing apparatus 3 that is a data transfer destination (write destination).

  That is, in the image processing system having the configuration shown in FIG. 1, the DMA transfer device 2 that transfers to the external memory of the information processing device 3 temporarily holds the image data output from the camera 1 in the buffer memory 12. The control unit 11 of the DMA transfer device 2 refers to the transfer address table 11a to determine the address (transfer address) of the reception buffer provided in the external memory in the information processing device 3. When the transfer address is determined, the control unit 11 directly transfers (writes) the image data stored in the buffer memory 12 to the reception buffer in the external memory in the information processing apparatus 3.

Next, the configuration of the information processing apparatus 3 will be described.
In the configuration example illustrated in FIG. 1, the information processing device 3 includes a control unit 21, an external memory 22, and an image processing unit 23. The control unit 21 governs the overall operation of the information processing apparatus 3. The control unit 21 includes a processor (CPU), a RAM, a ROM, and the like, and implements various processes when the processor executes programs stored in the ROM. For example, the control unit 21 has a memory management function for managing a buffer area (buffer memory) provided in the external memory 22 in order to store image data transferred from the DMA transfer device 2.

  The external memory 22 has a plurality of buffer areas R1, R2, and R3. A reception buffer or a holding buffer is allocated to the plurality of buffer areas R1, R2, and R3 of the external memory 22. The reception buffer of the external memory 22 is a buffer memory to which data is directly transferred from the DMA transfer device 2. In other words, in the present image processing system, the DMA transfer device 2 can write data to the reception buffer of the external memory 22 without going through the control unit 21 of the information processing device 3.

  In the configuration example shown in FIG. 1, the external memory 22 having a plurality of buffer areas and the control unit 21 that controls the operation of the plurality of buffer areas by the memory management function function as a memory management unit 25.

  The image processing unit 23 performs image processing on the image data transferred from the DMA transfer device 2 (image taken by the camera 1). The image processing unit 23 is controlled to perform image processing on the image data stored in the holding buffer in the external memory 22 so that the image data is not updated (overwritten) during the image processing.

  The control unit 21 has a buffer reference table 24 indicating allocation of reception buffers and holding buffers. In the configuration example illustrated in FIG. 1, an example in which three buffer areas RA, RB, and RC are provided in the external memory 22 is illustrated. In this case, the buffer reference table 24 holds information assigned to the three buffer areas in the two reception buffers (double buffers) and the holding buffer.

FIG. 2 is a diagram illustrating a configuration example of the buffer reference table 24.
In the example illustrated in FIG. 2, the buffer reference table 24 sets two reception buffers and one holding buffer. For example, buffer areas RA, RB, and RC designated by the head address in the external memory 22 are allocated to each buffer. In the example shown in FIG. 2, a buffer area RA having a head address “a” is allocated to the first reception buffer, and a buffer area RB having a head address “b” is allocated to the second reception buffer. A buffer area RC having a head address “c” is allocated to the buffer. In the configuration example shown in FIG. 2, information indicating the area (usage status) selected as the transfer destination of the image data is also added.

  The two reception buffers are used as buffers in which image data is directly written from the DMA transfer device 2 in order (alternately). The holding buffer is a buffer memory that holds image data so as not to be overwritten from the DMA transfer apparatus 2. For example, when there is an image acquisition request from the image processing unit 23, the reception buffer storing the image data to be processed is replaced with a holding buffer. The replacement of the holding buffer and the receiving buffer can be realized by exchanging the address information of the holding buffer and the address information of the receiving buffer in the buffer reference table 24 (rewriting the head addresses of each other).

  In the present embodiment, the description will be made assuming an example in which two reception buffers and one holding buffer are defined by a buffer reference table, but the present invention is not limited to this. For example, the reception buffer may be a plurality of three or more. In this case, the reception buffer may be rotated in order.

Next, the flow of processing in the entire image processing system will be described.
FIG. 3 is an operation sequence diagram in the image processing system.
First, the control unit 21 of the information processing device 3 as the memory management unit 25 refers to the buffer reference table 24 to determine a reception buffer to which image data is to be transferred next from the DMA transfer device 2 (step S11, S15, S19). The control unit 21 determines a reception buffer to which image data is to be transferred next from the DMA transfer device 2 so that the image data is sequentially written to the plurality of reception buffers.

For example, when two reception buffers are set as shown in FIG. 2, the control unit 21 next transfers the image data from the DMA transfer device 2 so that the image data is alternately written into the two reception buffers. Determines the receive buffer to be transferred.
When the reception buffer for receiving the image data is determined, the control unit 21 notifies the DMA transfer apparatus 2 of the start address (transfer address) in the external memory 22 as information indicating the determined reception buffer (steps S12, S16, and S20). .

  The DMA transfer device 2 stores information indicating the reception buffer notified from the information processing device 3 in the transfer address table 11 a of the control unit 11. In this state, image data captured by the camera 1 is written in the buffer memory 12 of the DMA transfer apparatus 2 (steps S13, S17, and S21). When the image data from the camera 1 is written into the buffer memory 12, the control unit 11 of the DMA transfer device 2 stores the transfer address in the external memory 22 in the information processing device 3 specified by the transfer address table 11a in the buffer memory 12. An image transfer process for directly writing the written image data is performed (steps S14, S18, S22).

  The DMA transfer device 2 and the information processing device 3 (its memory management unit 25) repeatedly execute the processes of steps S11 to S14. Thereby, the image data photographed by the camera 1 is sequentially written in the plurality of reception buffers of the information processing device 3.

  In the information processing apparatus 3, the image processing unit 23 requests image data to be processed from the control unit 21 at an arbitrary timing (step S23). When an image request is received from the image processing unit 23, the control unit 21 determines a reception buffer that stores image data to be processed. When the reception buffer storing the image data to be processed is determined, the control unit 21 switches the reception buffer that holds the image data to be processed and the current holding buffer (steps S24 and S25). That is, the control unit 21 exchanges the address of the reception buffer that holds the image data to be processed and the address of the holding buffer in the buffer reference table 24. When the reception buffer holding the processing target image data and the holding buffer are switched, the control unit 21 notifies the image processing unit 23 of the image data stored in the area changed to the holding buffer as the processing target image data. (S26).

  For example, in the example shown in FIG. 2, when the image data stored in the area RA of the head address “a” set in the first reception buffer is the processing target of the image processing, the control unit 21 The start address of the holding buffer is rewritten to “a”, and the start address of the first reception buffer is rewritten to “c”. By this. The first reception buffer and the holding buffer can be logically switched without physically copying the image data, and the image data received by the reception buffer can be provided to the image processing unit 23 at high speed.

  Further, after updating the buffer reference table 24 by exchanging the first reception buffer and the holding buffer, the control unit 21 determines the area of the reception buffer with reference to the table 24 in the same manner as the processing in steps S11 to S14. Then, the start address (transfer address) of the determined reception buffer is notified to the DMA transfer apparatus 2 (S28, S32). The DMA transfer device 2 sets the notified transfer address, receives the image data from the camera 1 by the buffer memory 12 (S29, S33), and transfers the image data stored in the buffer memory 12 to the set transfer address. (S30, S34).

Next, the flow of processing shown in FIG. 3 will be described with a specific example.
FIG. 4 is a diagram illustrating an example of the transition state of the buffer reference table 24 by the processing illustrated in FIG.
For example, in the example illustrated in FIG. 3, the control unit 21 of the information processing device 3 first determines the reception buffer as the area RA with reference to the buffer reference table 24 (step S11). Then, the control unit 21 notifies the DMA transfer apparatus 2 of the leading address “a” of the area RA as a transfer address (step S12). The DMA transfer device 2 sets the notified transfer address “a”, receives the first image data from the camera 1 by the buffer memory 12 (step S13), and stores the first image data stored in the buffer memory 12 Is transferred to the transfer address “a” (step S14).

  Next, the control unit 21 of the information processing device 3 refers to the buffer reference table 24 to determine the reception buffer that receives the image data next to the area RA as the area RB (step S15), and uses the area RB as a transfer address. The start address “b” is notified to the DMA transfer apparatus 2 (step S16). The DMA transfer device 2 sets the transfer address “b” notified from the information processing device 3, receives the second image data from the camera 1 by the buffer memory 12 (step S 17), and stores it in the buffer memory 12. The second image data is transferred to the transfer address “b” (step S18).

  Next, the control unit 21 of the information processing device 3 refers to the buffer reference table 24 to determine a reception buffer for receiving image data next to the region RB as the region RA (step S19), and uses the region RA as a transfer address. Is notified to the DMA transfer apparatus 2 (step S20). The DMA transfer device 2 sets the transfer address “a” notified from the information processing device 3, receives the third image data from the camera 1 by the buffer memory 12 (step S 21), and stores it in the buffer memory 12. The third image data is transferred to the transfer address “b” (step S22).

  According to the processing in steps S11 to S22, the state of the buffer reference table 24 changes as shown in (1) of FIG. That is, when two reception buffers are set, the control unit 21 of the information processing device 3 manages the memory so that image data is alternately written from the DMA transfer device 2 to the two reception buffers.

  Further, when receiving an image acquisition request from the image processing unit 23 (step S23), the control unit 21 of the information processing device 3 refers to the buffer reference table 24 and stores image data to be processed. The buffer is determined as the area RA. When it is determined that the reception buffer storing the image data to be processed is the area RA having the head address “a”, the control unit 21 holds the image data to be processed in the buffer reference table 24. The start address “a” of the reception buffer and the start address “c” of the holding buffer are exchanged (steps S24 and S25). When the reception buffer and the holding buffer are switched, the control unit 21 notifies the image processing unit 23 of the image data stored in the area RA changed to the holding buffer as the image data to be processed (step S26).

  That is, in response to an image request from the image processing unit 23, the control unit 21 changes the setting of the area RA of the head address “a” that holds the image data to be processed in the holding buffer (step S 24). The setting of the area RC of “c” is changed to the reception buffer (step S25). According to the processing in steps S24 to S25, the state of the buffer reference table 24 changes as shown in (2) of FIG. That is, the memory is managed so that the area RA that has been a reception buffer is changed to a holding buffer, and the area RC that has been a holding buffer is changed (replaced) to a reception buffer.

  In addition, after updating the buffer reference table 24 (after switching the reception buffer and the holding buffer), the control unit 21 of the information processing device 3 refers to the buffer reference table 24 and receives the next image data. The buffer is determined as the area RB having the head address “b” (step S27), and the head address “b” of the area RB is notified to the DMA transfer apparatus 2 as the transfer address (step S28). The DMA transfer device 2 sets the transfer address “b” notified from the information processing device 3, receives the fourth image data from the camera 1 by the buffer memory 12 (step S 29), and stores it in the buffer memory 12. The fourth image data is transferred to the transfer address “b” (step S30).

  Next, the control unit 21 of the information processing device 3 refers to the buffer reference table 24 to determine the reception buffer that receives the image data next to the region RB as the region RC (step S31), and uses the region RC as a transfer address. Is notified to the DMA transfer apparatus 2 (step S32). The DMA transfer device 2 sets the transfer address “c” notified from the information processing device 3, receives the fifth image data from the camera 1 by the buffer memory 12 (step S33), and stores it in the buffer memory 12 The fifth image data is transferred to the transfer address “c” (step S34).

  According to the processing in steps S27 to S34, the state of the buffer reference table 24 after the reception buffer and the holding buffer are exchanged changes as shown in (3) of FIG. That is, the control unit 21 of the information processing device 3 manages the memory so that the image data is alternately written from the DMA transfer device 2 to the two reception buffers even after the reception buffer and the holding buffer are switched.

  According to the above processing, in the image processing system in which the DMA transfer device continuously writes images to the memory in the information processing device, when the image processing unit of the information processing device accesses the image data, it is a processing target. Image data is held by virtually exchanging addresses between the reception (transfer) buffer and the holding buffer without performing physical copy processing of the image data. Thereby, the information processing apparatus can hold the image data without performing physical copy processing of the image data to be processed by the image processing unit, and as a result, the processing speed can be increased.

Next, a memory management process in the information processing apparatus 3 will be described.
When the image transfer from the DMA transfer device 2 is permitted, the control unit 21 of the information processing device 3 as the memory management unit 25 refers to the buffer reference table 24 and determines a reception buffer to which image data is to be transferred next. The transfer address is notified to the DMA transfer apparatus 2 as information indicating the address of the reception buffer. (Step S51). The DMA transfer device 2 writes the image data acquired from the camera 1 to the transfer address notified from the information processing device. If there is no transfer (writing) of image data from the DMA transfer device 2 (step S52, NO), the process returns to step S52.

  When an image acquisition request is received from the image processing unit 23 (step S53, YES), the control unit 21 determines a reception buffer that stores image data to be subjected to image processing, and the address of the reception buffer. Is updated to the address of the holding buffer (step S54). At the same time, the control unit 21 updates the address of the holding buffer before changing the receiving buffer to the holding buffer with the address of the receiving buffer (step S55).

  That is, when the control unit 21 receives an image acquisition request from the image processing unit 23 (step S53, YES), in the buffer reference table 24, the address of the reception buffer storing the image data to be processed and the holding buffer Swap addresses. After switching the reception buffer and the holding buffer, the control unit 21 returns to step S51 and accepts transfer (writing) of image data from the DMA transfer apparatus 2 using the newly set reception buffer in order. .

  According to the memory management process as described above, the reception buffer storing the image data to be subjected to image processing can be logically changed to a holding buffer to perform a physical image copy process. Can be logically changed to a receive buffer. As a result, the information processing apparatus 3 can speed up processing such as image processing.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  RA ... buffer area, RB ... buffer area, RC ... buffer area, 1 ... camera, 2 ... DMA transfer device, 3 ... information processing device, 11 ... control unit, 11a ... transfer address table, 12 ... buffer memory, 21 ... control , 22 ... external memory, 23 ... image processing unit, 24 ... buffer reference table, 25 ... memory management unit.

Claims (5)

A memory having a plurality of buffer areas for holding a plurality of image data;
A table for allocating a plurality of buffer areas to a reception buffer to which image data is written and a holding buffer to hold image data;
When holding the image data written in the reception buffer, changing means for replacing the reception buffer and the holding buffer in which the image data to be held is written;
A notification means for notifying the image transfer source of information indicating the changed reception buffer when the reception buffer and the holding buffer are switched by the changing means;
An information processing apparatus comprising: An image processing unit that performs image processing on the image data held in the holding buffer;
When the image processing unit sets the image data written in the reception buffer as a processing target, the changing unit switches the reception buffer and the holding buffer in which the image data to be processed is written,
The information processing apparatus according to claim 1, wherein: The table holds the address of the reception buffer and the address of the holding buffer,
The changing means replaces the address of the reception buffer that stores the image data to be processed and the address of the holding buffer in the table.
The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus. The reception buffer is a buffer area in which image data is written by a DMA transfer device as the image transfer source.
The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus. A memory management method used for a memory having a plurality of buffer areas,
A plurality of buffer areas are allocated to a reception buffer to which image data is written and a holding buffer to hold image data.
When holding the image data written in the reception buffer, replace the reception buffer and the holding buffer in which the image data to be held is written,
When the reception buffer and the holding buffer are switched, information indicating the changed reception buffer is notified to the image transfer source.
And a memory management method.

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