JP2013065374A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of performing efficient data retrieval.SOLUTION: A semiconductor memory device comprises a plurality of unit structures. Each of the unit structures comprises: a sense amplifier (SA) that is connected with each of memory cells; a first line (LBUS) that is connected with the sense amplifier; a first latch (XDL) that is connected with the first line; a second latch (LDL) that is connected with the first line; and an arithmetic circuit (Y) that is connected with the first line and performs a logical operation for data in the first and second latches. A plurality of first detection circuits (31 and 32), each of which is connected with a respective plurality of unit structure groups that include part of a plurality of different unit structures, detect the L level of the potential of at least one of the first lines in the respective unit structure groups. A second detection circuit (43) detects the fact that detection has been performed by at least one of the first detection circuits.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  In many cases, data held in the storage device is specified by an address. On the other hand, data may be specified by a search term like CAM (content addressable memory). That is, a search term is specified, and data including the search term is found in the memory. The designation of data through search terms is usually performed by software. For example, a device including a semiconductor memory device and a processor is prepared, and a search is performed by operating the processor based on software. The processor reads data to be searched into the temporary storage device and finds data including the search word. As the capacity of a storage device increases, it takes a long time to complete such a search.

JP 2011-044200 A JP 2005-353171 A

  An object of the present invention is to provide a semiconductor memory device capable of efficient data retrieval.

  In the semiconductor memory device according to one embodiment, the semiconductor memory device includes a plurality of unit structures. The unit structure includes a sense amplifier connected to each of the memory cells, a first line connected to the sense amplifier, a first latch connected to the first line, a second latch connected to the first line, An arithmetic circuit connected to the first line and performing a logical operation on the data in the first and second latches. The plurality of first detection circuits are connected to a plurality of unit structure groups each including a different part of the plurality of unit structures, and the potential of at least one first line in the corresponding unit structure group is L level. Detect something. The second detection circuit detects that detection has been made by at least one first detection circuit.

1 is a block diagram schematically showing a semiconductor memory device according to a first embodiment. FIG. 1 is a circuit diagram of a part of a memory cell array. FIG. 3 is a cross-sectional view of a part of a memory cell array. FIG. 3 is a circuit diagram showing a part of the bit line control circuit of the first embodiment. 4 is a flowchart of data search by the semiconductor memory device according to the first embodiment. The figure which shows one state of the data in the data latch of 1st Embodiment. A block diagram showing some bit line control circuits of a 2nd embodiment. 10 is a flowchart of data search by the semiconductor memory device according to the second embodiment. The figure which shows one state of the data in the data latch of 2nd Embodiment. The figure which shows the state of the data in the data latch following FIG. The figure which shows the state of the data in the data latch following FIG. The figure which shows the state of the data in the data latch following FIG. The figure which shows the state of the data in the data latch following FIG.

  Embodiments will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary. However, it should be noted that the drawings are schematic.

  In addition, each embodiment shown below exemplifies an apparatus and a method for embodying the technical idea of this embodiment, and the technical idea of the embodiment is the material, shape, and structure of component parts. The arrangement is not specified as follows. Various changes can be added to the technical idea of the embodiments within the scope of the claims.

  Each functional block in the following description can be realized as either hardware, computer software, or a combination of both. For this reason, in order to make it clear that each block is any of these, it is generally described below in terms of their function. Whether such functionality is implemented as hardware or software depends upon the specific implementation or design constraints imposed on the overall system. Those skilled in the art can implement these functions in various ways for each specific embodiment, and any implementation technique is included in the scope of the embodiments. Moreover, it is not essential that each functional block is distinguished as in the following specific example. For example, some functions may be executed by a functional block different from the functional blocks exemplified in the following description. Furthermore, the illustrated functional block may be divided into smaller functional sub-blocks. The embodiment is not limited by which functional block is specified.

(First embodiment)
FIG. 1 is a block diagram schematically showing the semiconductor memory device according to the first embodiment. As shown in FIG. 1, a semiconductor memory device (flash memory) 1 includes a memory cell array 2. The memory cell array 2 includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a common source line, and the like. The memory cell is composed of, for example, an EEPROM cell, and is configured such that the stored data can be electrically rewritten.

  The bit line control circuit 3 reads data in the memory cell, detects the state of the memory cell, and applies a write (program) voltage to the memory cell via the bit line to write the data in the memory cell. The bit line control circuit 3 is controlled by the control circuit 4. The bit line control circuit 3 includes a sense amplifier 3a, a data latch 3b, a search circuit 3c, a register 3d, a determination module 3e, and the like.

  The data latch 3b and the search circuit 3c are connected to a data input / output terminal via a data circuit (data buffer) 6 and an I / O interface 7. The data input / output terminal receives various commands CMD, address AA, and data DT from the outside. Of these, the command CMD and the address AA are supplied to the control circuit 4, and the address AA and the data DT are supplied to the bit line control circuit 3. On the other hand, data read from the memory cell is output from the input / output terminal via the bit line control circuit 3.

  The word line control circuit 11 receives a voltage necessary for reading, writing, or erasing data from the voltage generation circuit 12. The word line control circuit 11 applies the voltage from the voltage generation circuit 12 to the word line selected according to the control of the control circuit 4. The voltage generation circuit 12 supplies a voltage necessary for data reading, writing, erasing and the like to the word line control circuit 11 and the like under the control of the control circuit 4.

  The control circuit 4 is connected to a control signal input terminal via the input interface 13. The control circuit 4 receives control signals ALE (address latch enable), / CLE (command latch enable), / WE (write enable), and / RE (read enable) via a control signal input terminal. The control circuit 4 controls the bit line control circuit 3, the word line control circuit 11, and the voltage generation circuit 12 according to these control signals, command CMD, and address AA. The control circuit 4 also outputs a ready / busy signal R / B via the ready / busy interface 14.

  The memory cell array 2 includes a plurality of blocks. FIG. 2 is a circuit diagram of a part (one block) of the memory cell array. FIG. 3 is a sectional view of a part (one block) of the memory cell array. As shown in FIGS. 2 and 3, the block Block includes a plurality of memory cell columns (memory cell units) MU arranged along the word line direction (WL direction). The memory cell column MU includes a NAND string and select transistors S1 and S2. The NAND string includes a plurality (for example, 64) of memory cell transistors MT in which current paths (source / drain SD) are connected in series with each other. The selection transistors S1 and S2 are connected to both ends of the NAND string, respectively. The other end of the current path of the selection transistor S2 is connected to the bit line BL, and the other end of the current path of the selection transistor S1 is connected to the source line SL. The memory cell transistors MT in the block block are erased collectively. That is, a block is an erase unit. The word lines WL0 to WL63 extend in the WL direction and are connected to all the memory cell transistors MT belonging to the same row. The select gate line SGD extends in the WL direction and is connected to all the select transistors S2 in the block. The select gate line SGS extends in the WL direction and is connected to all the select transistors S1 in the block.

  A storage space formed by a plurality of memory cell transistors MT connected to the same word line WL constitutes a unit called a page. Data is read and written for each page. The semiconductor memory device 1 may be configured such that one memory cell can hold a plurality of bits of data. In such a memory cell, a plurality of pages are allocated to one word line.

  The memory cell MT is provided at each intersection of the bit line BL and the word line WL. Memory cell MT is provided on a well formed in a semiconductor substrate. The well receives a predetermined voltage from the voltage generation circuit 12. The memory cell MT includes a tunnel insulating film stacked on a well, a floating gate electrode FG as a charge storage layer, an inter-gate insulating film (not shown), a control gate electrode CG (word line WL), and a source / drain region SD. have. A source / drain which is a current path of a certain memory cell MT is connected in series to a source / drain of an adjacent memory cell MT. Each of the select transistors S1 and S2 includes a gate insulating film (not shown), gate electrodes SGS and SGD, and source / drain regions SD stacked on a semiconductor substrate.

  Next, the bit line control circuit 3 will be described. FIG. 4 is a circuit diagram showing a part of the bit line control circuit 3. As shown in FIG. 4, the bit line control circuit 3 includes eight unit structures US. One unit structure US operates for any of I / O0-7. Each unit structure US has the same configuration. In the figure, the unit structures US for I / O2 to I / O6 are omitted for the sake of clarity. Each unit structure US forms part of the sense amplifier circuit 3a and the data latch 3b. The reason why the eight unit structures US are set as one set is that the data bus YIO connecting the bit line control circuit 3 and the data circuit 6 has eight data lines YIO0 to YIO7. Data lines YIO0 to YIO7 correspond to I / O0 to I / O7, respectively. Different unit structures US are connected to different data lines YIO0 to YIO7 and bit lines. Eight continuous unit structures US shown in FIG. 4 constitute one set of unit structures US, and one set cooperates to process and hold data (8-byte data) corresponding to 8 columns (COL). Such a set of unit structures US is referred to as a unit structure group. A plurality of such unit structure groups are included in the bit line control circuit 3. The number of unit structure groups is, for example, a number that can process and hold data having a size equal to one page by all groups. For example, if the size of one page is 8 kB, the bit line control circuit 3 includes 1 k unit structure groups. The bit line control circuit 3 has one search circuit 3c for each unit structure group.

  Each unit structure US includes sense amplifiers SA0 to SA7 at the lower end (most position in the memory cell array 2). Each of sense amplifiers SA0-SA7 is connected to one bit line BL. The sense amplifiers SA0 to SA7 are commonly connected to one data bus SBUS via each switch circuit 21. The data bus SBUS is common to one unit structure US and has a width of 1 bit. The switch circuit 21 is controlled by the control circuit 4.

  In each unit structure, the data bus SBUS is connected to one end of the arithmetic circuit Y. One of the main uses of the arithmetic circuit Y is to perform a process for enabling a plurality of bits of data to be written in one memory cell. In order to achieve this, the arithmetic circuit Y is configured to perform various logical operations. Specifically, the arithmetic circuit Y performs, for example, a specific logical operation on data in a data latch (for example, the data latch LDL) described later and data in another data latch (for example, the data latch UDL), The result can be transferred to and held in any of the previous data latches or further data latches. The logical operation includes at least a negative operation (NOT), a logical sum (OR), a logical product (AND), an exclusive logical sum (XOR), or a combination thereof. The arithmetic circuit Y is controlled by the control circuit 4. The sense amplifiers SA0 to SA7 and the arithmetic circuit Y correspond to the sense amplifier circuit 3a in FIG.

  In each unit structure US, the other end of the arithmetic circuit Y is connected to the data bus LBUS. The data bus LBUS is connected to the data latches XDL0 to XDL7 via the respective switch circuits 22. The data bus LBUS is also connected to data latches UDL0 to UDL7 via respective switch circuits 23. The data bus LBUS is further connected to data latches LDL0 to LDL7 via respective switch circuits 24. In the figure, data latches UDL0 to UDL7 are depicted as a set of data latches UDL. Data latches LDL0 to LDL7 are also depicted as a set of data latches LDL. In each unit structure US, the data bus LBUS is further connected to a corresponding one of the data lines YIO0 to YIO7 via the switch 26. The switches 22 to 24 and 26 are controlled by the control circuit 4. Data latches XDL0 to XDL7, UDL0 to UDL7, and LDL0 to LDL7 correspond to the data latch of FIG.

  Each data bus LBUS is connected to the gate of a corresponding one n-type metal oxide semiconductor (MOS) FET (field effect transistor) 31. One end of each transistor 31 is grounded, and the other end is connected to one end of one n-type MOSFET 32. The other ends of all the transistors 32 in the unit structure group are commonly connected to the local detection line LDL. The gates of all the transistors 32 in the unit structure group receive the signal DETECT from the control circuit 4. The transistors 31, 32, and 33 constitute a first detection circuit for searching for one column of data in one unit structure group.

  The local detection line LD is connected to the power supply potential end via the p-type MOSFET 33. The gate of the transistor 33 receives the control signal CHR 1 from the control circuit 4. The local detection line LDL is also connected to the input of the tag latch 34. The output of the tag latch 34 is connected to the gate of the n-type MOSFET 41. The transistor 41 is grounded at one end and connected to one end of the n-type MOSFET 42 at the other end. The other end of the transistor 42 is connected to the detection line DL. Each unit structure group is commonly connected to the detection line DL. The detection line DL is connected to the power supply potential end via the p-type MOSFET 43. The tag latch 34 and the transistors 41, 42, and 43 constitute a second detection circuit for detecting whether there is a search hit among the plurality of unit structure groups. The transistors 31, 32, 33, 34, 41, 42, 43, and the tag latch 34 correspond to the detection circuit 3c in FIG.

  One unit structure group functions to process and transfer data for eight consecutive columns (for example, COL (column) 0 to COL7). Similarly, another unit structure group is for eight columns (for example, COL8 to COL15) different from the first set. Hereinafter, similarly, a plurality of unit structure groups function for any of a plurality of sets of eight consecutive columns.

  Next, data reading will be described. Hereinafter, the unit structure group for COL0 to COL7 will be described as a representative. However, it should be noted that in practice, all unit structure groups independently perform the same operation in parallel. That is, the operations described below for COL0 are performed in parallel for COL8, COL16, COL23. Similarly, the operations described below for COL1 are performed in parallel for COL9, COL17, COL24. The same description applies to the remaining COLs.

  First, data is read for any one of the eight columns. Which column is selected is arbitrary, but in the following description, it is assumed that the minimum number COL0 is selected.

  Eight 1-bit data respectively corresponding to I / O0 to I / O7 of COL0 are input from the bit line BL corresponding to the sense amplifier SA0 for I / O0 to I / O7. Subsequently, the data amplified by the sense amplifier SA0 for I / O0 to I / O7 is data latched for I / O0 to I / O7 via the arithmetic circuit Y for I / O to I / O7, respectively. Held in XDL0. The data held in the data latch XDL0 for I / O0 to I / O7 is supplied to the data lines YIO0 to YIO7, respectively. Thus, the data of COL0 is transferred to the data bus YIO all at once.

  Next, similarly, data is read for another column (for example, COL1). That is, the data of I / O0 to I / O7 of COL1 is input to each sense amplifier SA1 for I / O0 to I / O7. Subsequently, the data amplified by the sense amplifiers SA1 for I / O0 to I / O7 are respectively latched in the data latches for I / O to I / O7 via the arithmetic circuit Y for I / O to I / O7. Held in XDL1. The data held in the data latch XDL1 for I / O to I / O7 is supplied to the data lines YIO0 to YIO7, respectively. Thus, the data of COL1 is transferred to the data bus YIO at once. Thereafter, similarly, for all of COL2 to COL7, 8-bit data is sequentially transferred to the data bus YIO. Therefore, XDL0 to XDL7 are for COL0 to COL7. The same applies to the other unit structure groups. For example, in the unit structure group responsible for COL8 to COL15, XDL0 to XDL7 are for COL8 to COL15. The order in which the COLs are processed is arbitrary, but the order from the smallest number to the largest number is typical.

  Such a transfer is a measure for the sense amplifiers SA0 to SA7 to share one arithmetic circuit Y for each I / O. The purpose is to reduce the area of the semiconductor memory device by reducing the number of arithmetic circuits Y. Therefore, if such area reduction is not necessary, a method of sharing the arithmetic circuit Y is not essential. In the non-shared example, each unit structure US is simply provided with one arithmetic circuit Y for one column, one data bus SBUS, and one LBUS. That is, one sense amplifier SA is connected to one corresponding latch XDL, one corresponding latch UDL, one corresponding latch LDL via a dedicated data bus SBUS, a dedicated arithmetic circuit Y, and a dedicated data bus LBUS. Connected to.

  For data writing, the data passes through the data bus YIO, the data bus LBUS, the data latch XDL, the arithmetic circuit Y, and the sense amplifier SA in this order to reach the bit line BL.

  Next, data search will be described with reference to FIGS. FIG. 5 is a flowchart of data retrieval by the semiconductor memory device according to the first embodiment.

  First, the semiconductor memory device 1 receives a read command for reading search target data (step S1). In the following example, for simplification of description, it is assumed that the search target data is the same size as one page. The case where the search target data exceeds one page will be described later.

  When receiving the read command, the control circuit 4 reads data to be read from the memory cell through the control of the word line control circuit 11 and the like, and holds it in the data latch LDL (step S2). Details of the reading are as described above. The state in which the read data is held in the data latch LDL is schematically shown in FIG. Each box (box) in FIG. 6 indicates 1-byte data corresponding to one column. Actually, for example, 1-byte data of COL0 is a set of 1-bit data held in each of the eight data latches LDL0 for COL0. In the following description, a set of eight data latches that hold 1-byte data for the same column is referred to as a data latch group. Similarly, in the data latch groups XDL and UDL, one data latch group XDL or UDL holds 8-bit data of the corresponding column.

  As shown in FIG. 6, each data latch group LDL for COL0 to COL7 holds data D0 to D7, respectively. Although omitted in FIG. 6 for simplification, the same applies to COL8 and later. As described above, the columns are provided in a number that can hold one page of data as a whole. Therefore, as a result of data reading, data of one page size is held by the data latch group LDL having a capacity of one page.

  Returning to FIG. The semiconductor memory device 1 receives search data from the outside and holds it in a register (not shown) in the data circuit 6, for example (step S3). The search data has the same number of bits (8 in this example) as the set of unit structures US. The search data is also referred to as a key or the like, and typically includes a bit string for representing an arbitrary character. Next, the search data is output from the register and held in all the data latch groups XDL via the data bus YIO (step S4). In the example of FIG. 6, the search data is D2. Since there is one search data D2, all the data latch groups XDL hold the search data D2. For this reason, it is possible to supply the search data D2 to the data latch group XDL simultaneously by turning on the switches 26 and 22 in the entire unit structure US. This leads to efficiently holding the search data D2.

  Returning to FIG. The arithmetic circuit Y calculates the XOR of the data in the data latch group XDL and the data in the data latch group LDL for one column in the unit structure group to be written, and repeats this calculation for all eight columns (step S5). The order of the eight columns is arbitrary, but the order from the smallest number to the largest number is typical. The result of the logical operation is held in the corresponding data latch group UDL. Specifically, it is as follows. First, in each unit structure group, logical operations on any one column (for example, COL0, COL8, COL16, COL24...) Are performed in parallel. In the following description, the description will be given focusing on the unit structure groups for COL0 to COL7, and the description will be applied independently to all the unit structure groups. XOR between 1-bit data in each data latch XDL0 for COL0 and I / O0-I / O7 for COL0 being processed and 1-bit data in each data latch LDL0 for I / O0 to I / O7 for COL0 Are calculated by the arithmetic circuits Y for I / O0 to I / O7. The result of the logical operation appears on the data bus LBUS for each bit, and is then held in each data latch UDL0 for COL0. H level data appears on at least one of the eight data buses LBUS. This is because the data latch groups XDL and LDL for COL0 hold different data D2 and D0.

  Next, the same processing as described for COL0 is sequentially repeated for all remaining columns in the unit structure group in each unit structure. As a result, in each unit structure group, the result of the logical operation is held in the data latch group UDL for all the columns.

  Next, one column in each unit structure group is held in the wired OR tag latch 34 of 8-bit data in the data latch group, and this is repeated for all columns. Specifically, it is as follows. First, the control circuit 4 precharges the local detection line LDL by activating the signal CHR1, and then activates the signal DETECT. First, the data in the data latch group UDL for any one column (for example, COL0) in each unit structure group is read to the corresponding data bus LBUS. If the potential of any one of the eight data buses LBUS is H level, the corresponding transistor 31 is turned on, so that the local detection line LDL transitions to L level. For COL0, the local detection line LDL transits to the L level. The signal on the local detection line LDL is held in the tag latch 34 (step S6). The L level output of the tag latch 34 does not turn on the transistor 41.

  Next, the wired OR of the data in each tag latch 34 in the plurality of unit structure groups is calculated (step S7). Specifically, it is as follows. First, the control circuit 4 precharges the detection line DL to high level by activating the signal CHR2, and activates the signal DETECT2. As a result, a discharge path for the detection line DL is formed in the unit structure group including the transistor 41 that is turned on. On the other hand, the discharge path for the detection line DL is not formed in the unit structure group including the transistor 41 that is turned off. In the unit structure group of FIG. 6, since the output of the tag latch 34 is low level for the current search target COL0, the discharge path from the detection line DL is not formed. When the tag latch in any unit structure group holds the H level, the potential of the detection line DL transits to the L level by the unit structure group. The register 3d holds the potential of the detection line DL for the lowest-numbered column in each unit structure group thus obtained.

  Next, in the same manner, the set of steps S6 and S7 is repeated until the determination for all the columns in each unit structure group is completed (step S8). The order of the eight columns is arbitrary, but the order from the smallest number to the largest number is typical. In the unit structure group of FIG. 6, there is a hit determination for the data of COL2. For this reason, in step S7 for COL2, the local detection lines LDL in the unit structure group for COL0 to COL7 maintain the H level. The H level data on the local detection line LDL turns on the transistor 41, and as a result, the potential on the detection line DL transitions to the L level. When the repetition of the set of steps S6 and S7 is completed, a total of 8 bits indicating the comparison results for the 8 sets of columns are accumulated in the register 3d. Among these, if there is even one hit determination, it means that the search target page includes the search data. Based on this, the determination module 3e determines the inspection result (step S9). In step S8, when the hit determination is made before the search for the eight sets of columns is completed, step S8 may be completed as the hit determination for the search target page. The determination module 3e transmits the determination result to the control circuit 4 (step S10). This transmission can be performed by, for example, a status used for transmission of a pass / fail judgment result at the time of data program (writing). The control circuit 4 further outputs the received determination result to the outside of the semiconductor memory device 1.

  When the search target data exceeds one page, the process is repeated until the search for the portion in which the set of steps S1 to S10 exceeds one page is completed. However, in each iteration, steps S3 and S4 for holding search data are skipped. This is because the search data does not change in each iteration.

  As described above, the semiconductor memory device according to the first embodiment includes the search circuit 3c in addition to the data latches XDL, UDL, LDL, and the arithmetic circuit Y. By using these elements, that is, by hardware elements, it can be determined whether or not specified data is included in a specific storage space. Therefore, data can be specified by search data (search key) instead of an address as in CAM. The search by hardware can be completed at a higher speed than the search by conventional software. The search circuit 3c is an extremely simple logic circuit, and the data latches XDL, UDL, LDL, and the arithmetic circuit Y are originally provided irrespective of the technology of the present application. There is almost no.

(Second Embodiment)
In addition to the operation of the first embodiment, the second embodiment relates to updating search data therein after data including the search data is found.

  FIG. 7 is a block diagram showing a part of the bit line control circuit of the semiconductor memory device according to the second embodiment. The search circuit 3c of the second embodiment includes a transistor 51 and a plurality of sets of transistors 52 and 53 in addition to those of the first embodiment. In each unit structure group, all data buses LBUS are commonly connected to one end of the p-type MOSFET 51. The transistor 51 receives the power supply potential at the other end, and receives the signal CHR3 from the control circuit 4 at the gate. Each data bus LBUS is connected to one end of n-type MOSFETs 52 and 53 connected in series. The transistor 53 is also grounded. In each unit structure group, the gates of all the transistors 52 are commonly connected to the output of the tag latch 34, and the gates of all the transistors 53 are commonly connected to the signal TAG2DL from the control circuit 4. The transistors 51, 52 and 53 contribute to writing a value based on the search result into the data latch. All configurations other than those described so far are the same as those in the first embodiment.

  Next, the data update will be described with reference to FIG. FIG. 8 is a flowchart of data update by the semiconductor memory device according to the second embodiment. First, steps S1 to S7 are performed. However, step S7 is arbitrarily executed and is performed only when, for example, a search result is required to be output.

  As described in the first embodiment, as a result of step S6, the tag latch 34 holds the H level data in the case of a search hit and holds the L level data in the case of a search miss as a result of step S6. doing. As in the first embodiment, the data of all columns is read for each of the eight columns (for example, COL0). Therefore, the current cycle is the first round, and therefore, COL0 is a search target as a typical example.

  Next, a value based on the data in the tag latch 34 is written into the data latch group UDL for the search target column (step S21). Specifically, it is as follows. First, the control circuit 4 precharges all the data buses LBUS in each unit structure group to a high level by activating the signal CHR3. Next, the control circuit 4 activates the signal TAG2DL. With this activation, in each unit structure group, if L level data is held in the tag latch 34 (that is, at the time of a search error), all the transistors 52 are turned off, so the data bus LBUS maintains the H level. To do. The potentials of the data buses LBUS for I / O0 to I / O7 at this time are respectively written in the data latches UDL0 to UDL7 for the current search target column. Therefore, as shown in FIG. 9, the data latch group UDL0 for COL0 holds all the data of H level, that is, all the data of “1”. In the figure, it is displayed in hexadecimal.

  Returning to FIG. Similarly, the set of step S6, step S7 and step 21 as necessary is repeated (step S23) until the result holding in the data latch group UDL for all the columns in each unit structure group is completed. In the example of FIG. 9, there is a hit determination for the data of COL2. For this reason, in S21 for COL2, all the data buses LBUS in the unit structure group for COL0 to COL7 transition to the L (0) level by the activation of the signal TAG2DL. Therefore, as shown in FIG. 9, the data latch group UDL2 for COL2 holds all L level data, that is, all “0” data. On the other hand, the remaining COL1, 3-7 data latch groups UDL1, 3-7 all hold data of "1".

  Subsequent steps S9 and S10 are also optionally executed, for example, only when it is desired to output a search result.

  Next, the arithmetic circuit Y calculates the AND of the data in the data latch group LDL and the data in the data latch group UDL for one column in each unit structure group, and repeats this calculation for all eight columns (step S24). The order of the eight columns is arbitrary, but the order from the smallest number to the largest number is typical. The result of the operation is held in the data latch group LDL for the column being processed. Specifically, it is as follows. First, in each unit structure group, for any one column (eg, COL0, COL8, COL16, COL24...), The correspondence between 1-bit data in each data latch UDL (eg, UDL0) and each data latch LDL (eg, LDL0). AND with 1-bit data to be calculated is calculated by the arithmetic circuit Y for I / O0 to I / O7. The result of the operation is held in each data latch LDL0 in the corresponding (same) column. As a result, data (for example, data D0) is written again in the data latch group LDL (for example, data latch group LDL0) of the column being processed (for example, COL0). Similarly, in each unit structure group, the AND operation and the result holding are repeated for the remaining columns. During this repetition, in the unit structure group of FIG. 10, the AND for COL2 is “0” for all bits. The logical sum of the other COLs 1 to 3 is “1” for all bits.

  Next, the semiconductor memory device 1 receives data (N2) to be overwritten on the search data (step S25). The update data has the same size as the search data, that is, 1 byte. The received data is held in, for example, a register (not shown) in the search circuit 3c. Next, the update data is output from the register and held in the data latch group XDL for all columns via the data bus YIO (step S26). For this reason, it is possible to supply the update data N2 to the data latch group XDL simultaneously by turning on the switches 26 and 22 in the entire unit structure US. This leads to efficiently holding the update data N2. The result of step S26 for the unit structure groups for COL0 to COL7 is shown in FIG.

  Next, the arithmetic circuit Y calculates the OR of the data in the data latch group XDL and the inverted form of the data in the data latch group UDL for one column in each unit structure group. Repeat for the column (step S27). The order of the eight columns is arbitrary, but the order from the smallest number to the largest number is typical. The result of the operation is overwritten on the data latch group XDL for the column being processed. Specifically, as in step S24 and the like, the OR operation and the result holding for the corresponding bits are repeated for any one column for each column. As a result, for the unit structure groups for COL0 to COL7, as shown in FIG. 12, the data latch group XDL for COL2 holds the update data N2, and the data latches for the other COL0, 1, 3 to 7 The group XDL holds data of all “0”.

  Next, the arithmetic circuit Y calculates the AND of the data in the data latch group UDL and the data in the data latch group LDL for one column in each unit structure group, and repeats this calculation for all eight columns (steps). S28). The order of the eight columns is arbitrary, but the order from the smallest number to the largest number is typical. The result of the operation is overwritten on the data latch group XDL for the column being processed. Specifically, in the same manner as in step S24, etc., the AND operation for the corresponding bits and the holding of the result are repeated for every column of any one COL. As a result, for the unit structure groups for COL0 to COL7, as shown in FIG. 13, the data latch group XDL for COL2 holds the update data N2, and the data latches for the other COL0, 1, 3 to 7 The group XDL holds the original data D0, D1, D3 to D7, respectively.

  Next, the semiconductor memory device 1 receives from the outside a program command for writing data for one page being processed for search and update and an address to be written (step S31). In response to this command, the control circuit 4 controls the bit line control circuit 3, the word line control circuit 11, and the voltage generation circuit 12 to store the data latch group XDL in the page of the designated address. The page size data is written (step S32).

  As described above, the semiconductor memory device according to the second embodiment includes the search circuit 3c in addition to the data latches XDL, UDL, LDL, and the arithmetic circuit Y as in the first embodiment. Furthermore, the search circuit 3c according to the second embodiment has a mechanism for writing data based on the data in the tag latch 34 to the data latches XDL, LDL, and the like. For this reason, as in CAM, it is possible to specify data by search data instead of an address and overwrite the found data by hardware. The search by hardware can be completed at a higher speed than the search by conventional software. The search circuit 3c is an extremely simple logic circuit, and the data latches XDL, UDL, LDL, and the arithmetic circuit Y are originally provided irrespective of the technology of the present application. There is almost no.

  In addition, each embodiment is not limited to the above-described one, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above-described embodiment includes various stages, and various embodiments can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the above embodiments, a configuration from which these configuration requirements are deleted can be extracted as an embodiment.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device, 2 ... Memory cell array, 3 ... Bit line control circuit, 4 ... Control circuit, 6 ... Data circuit, 7 ... I / O interface, 11 ... Word line control circuit, 12 ... Voltage generation circuit, 13 ... Input interface, 14 ... Ready / busy interface, 21-24, 26 ... Switch, 31, 32, 33, 41, 42, 43, 51-53 ... MOSFET, LDL ... Local detection line, DL ... Detection line.

Claims (5)

A sense amplifier connected to each of the memory cells;
A first line connected to the sense amplifier;
A first latch connected to the first line;
A second latch connected to the first line;
An arithmetic circuit connected to the first line and performing a logical operation on the data in the first and second latches;
A plurality of unit structures comprising:
A plurality of units that are connected to a plurality of unit structure groups each including a different part of the plurality of unit structures and detect that the potential of at least one of the first lines in the corresponding unit structure group is L level. A first detection circuit of
A second detection circuit for detecting that the detection has been performed by at least one of the first detection circuits;
A semiconductor memory device comprising: The unit structure includes a plurality of the sense amplifiers, a plurality of the first latches, and a plurality of the second latches,
A plurality of first latches connected to a plurality of different first lines in the unit structure constitute a set for one column;
A plurality of second latches connected to a plurality of different first lines in the unit structure constitute a set for one column;
The arithmetic circuit performs a logical operation on one of the first latches and one of the second latches for the same column as the one first latch;
The first detection circuit performs the detection for each of a plurality of columns;
The semiconductor memory device according to claim 1. The first latch holds data from outside the semiconductor memory device;
The second latch holds data from the memory cell;
The arithmetic circuit calculates an exclusive OR of data in the first and second latches for a common column;
The first detection circuit includes a plurality of first transistors having one end selectively grounded and the other end selectively precharged to H level and receiving the outputs of the plurality of arithmetic circuits at terminals for controlling conduction. Have
The semiconductor memory device according to claim 2. The semiconductor memory device further includes a plurality of third latches each holding a value indicating that the detection is performed by the plurality of detection circuits,
The unit structure further includes a plurality of fourth latches connected to the first line,
The unit structure group further includes a plurality of second transistors having one end selectively grounded and the other end selectively precharged to H level and receiving the output of the third latch at a terminal for controlling conduction. ,
The semiconductor memory device according to claim 3. The first latch holds data from outside the semiconductor memory device;
The second latch holds data from the memory cell;
The arithmetic circuit calculates an exclusive OR of data in the first and second latches for a common column;
The fourth latch receives and holds a value based on the exclusive OR via the second transistor;
The semiconductor memory device according to claim 4.

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