JP2013062732A - Peak factor reduction device, base station, and radio system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a peak factor reduction device which can reduce signal deterioration when having escaped from a non-signal section even in the case of transmitting a signal having the non-signal section such as a burst waveform.SOLUTION: A peak factor reduction device is added with a function for inputting Scheduling information indicating the existence of a non-signal section from a baseband side to execute control so that a peak factor threshold value in the non-signal section is not automatically adjusted. Moreover, a peak factor reduction device 100c is added with a function for detecting whether the non-signal section exists or not, from an input signal by a non-signal section detection circuit 131 to execute the control so that the peak factor threshold value in the non-signal section is not automatically adjusted, by providing an output of the detection to an integrator 112.

Description

  The present invention relates to a peak factor reducing device, a base station, and a wireless system, and more particularly to a peak factor reducing device, a base station, and a wireless system that can be applied to an RF signal transmitter and the like in consideration of a no-signal transmission section.

In recent years, in order to improve frequency use efficiency, an OFDM (Orthogonal Frequency Division Multiplexing) system that modulates and transmits baseband signals with sub-carriers orthogonal to each other is regarded as important in the field of wireless communication. . Since an OFDM signal has a characteristic close to a normal distribution, a peak factor (Peak-to-Average Power Ratio) (also referred to as a crest factor), which is an instantaneous power ratio to average power, is higher than that of CDMA or the like. When transmitting such a signal, nonlinear distortion may occur outside the transmission frequency band if the linearity in the input / output characteristics of the power amplifier is not sufficiently maintained. This non-linear distortion may be an interference wave for other wireless systems.
As countermeasures against this interference wave, the non-linear distortion outside the transmission frequency band is improved by lowering the operating point of the power amplifier and ensuring the backoff with respect to the saturated output power. However, in the case of a signal having a large peak factor such as the OFDM system, a larger back-off is required. For this reason, the transmission power efficiency of the RF signal transmitter is lowered, and as a result, there is a concern that the power consumption of the apparatus increases.
As a method for solving such a problem, for example, there is the following technique.
(1) Distortion compensation technology such as predistortion and feedforward that compensates for nonlinear distortion of the power amplifier and expands the operating range of the amplifier,
(2) A technique for reducing the occurrence of a peak factor in a baseband signal.
The invention particularly relates to the latter.
As a document disclosing the latter, a peak factor reducing device described in Patent Document 1 can be cited. The peak factor reduction device of Patent Document 1 corresponds to a reference filter for band-limiting a complex input signal having two types of white baseband signals having a uniform spectrum as real parts and imaginary parts, respectively, and a propagation delay of the reference filter. A delay unit that delays the complex input signal by time, an amplitude control unit that outputs a complex impulse signal having an amplitude proportional to the excess when the amplitude component of the reference filter output signal exceeds a set value, and a delay output signal And a subtractor for subtracting the amplitude control unit output signal from the subtractor.
In addition, the peak factor reduction device disclosed in Patent Document 2 performs frequency conversion by multiplying a complex baseband signal having at least one carrier having a uniform spectrum by a complex exponential function signal having a frequency corresponding to the complex baseband signal. A peak generation unit that calculates the instantaneous amplitude value of the multicarrier composite signal and detects the maximum peak amplitude value within the detection width, and a peak detection circuit. A threshold comparison unit that compares the calculated peak amplitude value with a peak factor threshold, calculates an excess level from the peak factor threshold, and outputs a signal normalized with the peak amplitude value for the excess level, and peak detection And delaying the plurality of complex baseband signals by the number of samples corresponding to the processing delay between the threshold value comparison unit and the threshold value comparison unit. A first delay unit, a first multiplier that multiplies the output of the threshold comparison unit and the output of the first delay unit, a filter unit that limits the bandwidth of the output of the first multiplier, and a peak A second delay unit that delays the multicarrier composite signal by the number of samples corresponding to a processing delay of the detection unit, the threshold comparison unit, and the filter; and a processing delay of the peak detection unit, the threshold comparison unit, and the filter A third delayer that delays the complex exponential function signal by the number of samples corresponding to the second multiplier, a second multiplier that multiplies the output of the filter by the output of the third delayer, and the second multiplier. An adder for adding and synthesizing the outputs of the multipliers to generate a peak suppression signal, a subtractor for subtracting the peak suppression signal from the output of the second delay unit, the output of the second delay unit and the EVM target value And the signal multiplied by A power calculation unit that performs power calculation with the peak suppression signal and outputs a difference, an integrator that integrates the output of the power calculation unit, and a peak obtained by adding an initial value of a peak factor threshold to the output of the integrator It comprises an adder for calculating a factor threshold, an amplitude comparison unit for comparing the amplitude of the output of the peak factor threshold and the subtractor and outputting a detection width.

JP 2003-124824 A JP 2011-019164 A

In the peak factor reduction device described in Patent Document 1, the peak factor threshold Vt serving as an index when the peak amplitude is set to a certain threshold or less is a fixed value, and the peak factor threshold Vt needs to be set in advance. At this time, if the peak factor threshold value Vt is set low, EVM (Error Vector Magnitude) indicating the effective value (amplitude error or the like) of the vector error increases. An increase in EVM means degradation of signal quality in transmission. On the other hand, when the threshold value for setting the peak factor threshold value Vt is set higher, the EVM is lower, but the peak factor becomes larger and the burden on the power amplifier becomes larger. That is, the setting of the EVM and the peak factor threshold value Vt is in a trade-off relationship.
In many radio base stations, the allowable value of EVM is defined by the standard, and therefore it is preferable to set the peak factor threshold Vt so low that it does not exceed the allowable EVM value. However, the peak occurrence frequency varies depending on the transmission conditions such as the transmission frequency bandwidth and the detuning frequency during multicarrier, and the optimum peak factor threshold Vt varies. The value cannot be calculated uniformly from these transmission conditions.
In order to solve such problems, the peak factor reduction device described in Patent Document 2 automatically adjusts the peak factor threshold Vt according to the signal level by setting a target value of EVM in the peak factor reduction device. To do. As a result, even when the transmission condition is changed, the EVM in the peak factor reduction can be set to the set value.
As a further problem in Patent Document 2, when transmitting a signal having a no-signal section such as a burst waveform, control is required to set the peak factor threshold Vt low from the viewpoint of the load on the power amplifier. As described above, when the peak factor threshold value Vt is lowered, there is a problem that signal deterioration may be significantly increased when the peak factor threshold value Vt is removed. In particular, when transmitting a signal having ABS (Almost Blank Subframe) currently under discussion in 3GPP, which is a standardization organization, the above-mentioned problem becomes serious because a no-signal section occurs, for example, in the order of ms.
In view of the above points, the present invention provides a peak factor reduction device, a base station, and a radio system that can completely or sufficiently cancel a peak without increasing the logical scale even when transmitting a signal having a no-signal section. provide.

The present invention has been made to solve the above-described problems. The peak factor reduction device is provided with a circuit for detecting a no-signal interval, and is controlled so as not to automatically adjust the peak factor reduction threshold Vt in the no-signal interval. Thereby, signal degradation when it leaves | separates from a no signal area can be reduced.
A complex baseband signal of at least one carrier is multiplied by a complex exponential function of a frequency corresponding to each baseband signal generated by an NCO (Numerally Controlled Oscillator) circuit, frequency conversion is performed, and an addition synthesized signal Sin is obtained. Input to the peak detection circuit. The peak detection circuit detects the maximum amplitude value Vp in N consecutive samples. The threshold value comparison circuit compares the amplitude value Vp output from the peak detection circuit with the peak factor threshold value Vt, calculates an excess level Vp−Vt from the peak factor threshold value Vt, and normalizes the peak detection circuit output value Vp. Output the signal. The threshold value comparison circuit output is multiplied by the delay output obtained by delaying the number of D1 samples corresponding to the above processing, and the peak component is converted into the input signal level. Next, the output signal is band-limited by the FIL circuit, and the output signal generated by the NCO circuit is multiplied by a complex exponential function delayed by D2 samples corresponding to the processing delay, and addition synthesis is performed. A peak suppression signal PFRerr is generated. Then, the signal PFRthr delayed by D2 samples corresponding to the processing delay and the peak suppression signal PFRerr are subtracted from the multicarrier composite signal Sin. This output signal Sout is a complex signal after the peak factor is reduced.
In Patent Document 2 (particularly, refer to FIG. 13 and the explanation thereof), in addition to the processing described above, an optimum peak factor threshold that can be reduced within the EVM target value, and a peak detection width that reduces the peak residual ratio. The peak factor reduction device has a function of automatically adjusting the set value. First, in the power calculator, the power level that can be reduced within the EVM target value obtained by multiplying the output signal PFRthr of the delay unit by the EVM target value and the power level that is actually reduced that is the peak suppression signal PFRerr are subtracted. , Output the difference. Next, integration is performed by the integrator until the difference value becomes “0”. When this difference becomes “0”, it means that the actual EVM in the peak factor reduction is equal to the target value. Then, the peak factor threshold value Vt obtained by adding the initial value of the peak factor to the integrator output value is fed back to the threshold value comparison circuit. Next, the amplitude comparison circuit compares the peak factor threshold value Vt and the instantaneous amplitude value of the signal Sout after the peak factor reduction. When the peak factor threshold value Vt is higher, the peak can be detected sufficiently with the current peak detection width, and feedback is performed so as to widen the peak detection width in order to alleviate EVM. On the other hand, when the signal Sout after the reduction of the peak factor is higher, there is a possibility that the cancellation of the peak may be insufficient. Therefore, feedback is performed so as to narrow the peak detection width. Based on the comparison result, the peak detection width is adjusted, and the output result is supplied to the peak detection circuit as the peak detection width N.

In addition to the processing and configuration described above, the present invention is a peak factor reduction device that can detect a no-signal interval in an input signal and control so as not to automatically adjust a peak factor threshold Vt in the no-signal interval. . Regarding detecting a no-signal section in an input signal, there are two types, a technique of inputting Scheduling information indicating whether there is a no-signal section from the baseband side and a technique of detecting within a peak factor device.
For example, if the former is an ABS standardized by 3GPP, the base station performs scheduling according to the ABS pattern, and therefore, the ABS pattern may be input to the peak factor reduction device as it is. In other cases, according to Scheduling information, Scheduling information indicating ON / OFF of data is generated in the baseband circuit and input to the peak factor reduction device. This Scheduling information is supplied to the accumulator, and when “0” is input to the accumulator, the switch is controlled so as not to change the peak factor threshold value. Then, the peak factor threshold value Vt obtained by adding the initial value of the peak factor to the integrator output is fed back to the threshold value comparison circuit.
Next, a method for detecting a no-signal section in an input signal in the latter peak factor device will be described. As a method for detecting a no-signal section in an input signal within the peak factor device, a no-signal section in the input signal is detected using a signal PFRthr obtained by delaying the multicarrier composite signal Sin by D2 samples. In the amplitude determination circuit, an instantaneous amplitude value in the output signal PFRthr of the delay device is calculated. It is determined whether or not the instantaneous amplitude value is equal to or less than a preset no-signal threshold value. When the instantaneous amplitude value is equal to or less than the no-signal threshold value, “0” is output, and “1” is output otherwise. This binary information corresponds to Scheduling information indicating ON / OFF of data. This Scheduling information is supplied to the accumulator, and when “0” is input to the accumulator, the switch is controlled so as not to change the peak factor threshold value. Then, the peak factor threshold value Vt obtained by adding the initial value of the peak factor to the integrator output is fed back to the threshold value comparison circuit.
As a second method for detecting the no-signal section in the input signal in the peak factor device, the signal-free section in the input signal is used by using the signal PFRthr obtained by delaying the multicarrier composite signal Sin by D2 samples, as described above. To detect. In the no-signal section detection circuit, an instantaneous amplitude value in the output signal PFRthr of the delay device is calculated. Next, the instantaneous amplitude value is input to the delay device, delayed by M samples, and supplied to the comparison determination circuit. The comparison determination circuit determines whether all the input M samples or a predetermined number of instantaneous amplitude values are other than “0”. Based on the determination result, when all the M samples or a predetermined number of instantaneous amplitude values detect “0”, a predetermined time, for example, 1 ms is determined as a no-signal interval from the moment when “0” is detected, Outputs “0” for 1 ms. Otherwise, “1” is output. This binary information corresponds to Scheduling information indicating ON / OFF of data. This Scheduling information is supplied to the accumulator, and when “0” is input to the accumulator, the switch is controlled so as not to change the peak factor threshold value. Then, the peak factor threshold value Vt obtained by adding the initial value of the peak factor to the integrator output is fed back to the threshold value comparison circuit.

The above-described problem is that a plurality of complex baseband signals are multiplied by a complex exponential function signal having a frequency corresponding to the complex baseband signal, frequency-converted, and added and synthesized to generate a multicarrier synthesized signal. The peak detection unit that calculates the instantaneous amplitude value of the multicarrier composite signal and detects the maximum peak amplitude value within the detection width is compared with the peak amplitude value calculated by the peak detection circuit and the peak factor threshold value, A threshold comparison unit that calculates an excess level from the peak factor threshold and outputs a signal normalized with the peak amplitude value for the excess level, and a plurality of samples corresponding to the processing delay between the peak detection unit and the threshold comparison unit. A first delay unit that delays the complex baseband signal, a first multiplier that multiplies the output of the threshold comparison unit, and the output of the first delay unit; A filter that limits the band of the output of the first multiplier, a second delayer that delays the multicarrier composite signal by the number of samples corresponding to the processing delay of the peak detector, the threshold comparator, and the filter; Frequency conversion is performed by multiplying the third delay unit that delays the complex exponential function signal by the number of samples corresponding to the processing delay of the detection unit, the threshold comparison unit, and the filter, and the output of the filter and the output of the third delay unit. A second multiplier, an adder that adds and combines the outputs of the second multiplier to generate a peak suppression signal, a subtractor that subtracts the peak suppression signal from the output of the second delay, 2 calculates the instantaneous power in the signal obtained by multiplying the output of the delay unit 2 and the EVM target value, and the peak suppression signal, respectively, and subtracts after performing band limitation with the LPF, and subtracts the power difference between the two signals. A power calculation circuit that calculates the power, an integrator that integrates the output of the power calculation circuit, an adder that adds the integrator output and a PFR (Peak Factor Reduction) initial value, and a peak factor in the adder output and the subtractor output This can be achieved by a peak factor reduction device composed of an amplitude comparison circuit that calculates instantaneous amplitude values in the reduced complex signals, compares the amplitudes, adds the initial value of the peak detection width to the comparison result, and outputs the result. .
Further, in a base station including a remote radio head unit that performs radio signal processing and a baseband signal processing unit, the remote radio head unit performs band limiting on the baseband signal output from the baseband signal processing unit. 2 and the peak factor reducing device as described above for suppressing the instantaneous power with respect to the average power from the output of the second filter, and the output signal of the peak factor reducing device includes a nonlinear component in the power amplifier at the subsequent stage. This can be achieved by a base station comprising a digital predistortion circuit that compensates for the above and a power amplifier that amplifies the output of the digital predistortion circuit.

According to the solution of the present invention,
A first generation unit that multiplies a complex baseband signal by a complex exponential signal having a frequency corresponding to the complex baseband signal, performs frequency conversion, and adds and generates a multicarrier composite signal;
The multi-carrier composite signal is multiplied by the complex baseband signal, and the complex exponential function signal is multiplied by the result of comparing the peak amplitude value in the set detection width with the set peak factor threshold. A second generation unit that performs frequency conversion and summing to generate a peak suppression signal;
A first delay unit that delays the multicarrier composite signal by the number of samples corresponding to the processing delay of the second generation unit;
A subtractor that subtracts the peak suppression signal output by the second generator from the output of the first delay unit and outputs an output signal;
A power calculator that outputs a power difference between a signal obtained by multiplying the output of the first delay device by a predetermined amplitude error target value or EVM target value and the peak suppression signal;
When the output of the power calculator is integrated, a no-signal information signal representing a no-signal section of the plurality of complex baseband signals is input, and the no-signal information signal is a first value representing a no-signal section An integrator that holds the output to hold the current peak factor threshold;
An adder that sets a value obtained by adding an initial value of a predetermined peak factor threshold to the output of the integrator as a peak factor threshold of the second generator;
Provided is a peak factor reduction device including an amplitude comparison unit that sets an output obtained by comparing the amplitude of a peak factor threshold value from the adder and an output signal from the subtractor as the detection width of the second generation unit. Is done.

Also, according to one aspect of the present invention,
A peak factor reduction device as described above,
The no-signal information signal can be provided from a base station, a base station control station, or another baseband device to the accumulator.
According to another aspect of the invention,
A peak factor reduction device as described above,
A peak factor reduction device further comprising: a no-signal detector that detects a no-signal section according to the multi-carrier composite signal to create a no-signal information signal and outputs the no-signal information signal to the accumulator. Can be provided.

As described above, according to the present invention, it is possible to perform a peak factor reduction process within an EVM target value even for an input signal having a no-signal section, and to reduce a peak factor that can reduce a residual factor of a peak factor factor. Devices and base stations can be provided. By applying the present invention, it is possible to suppress EVM degradation after leaving the no-signal section in a signal having a no-signal section.

1 is a circuit block diagram of a first embodiment of a peak factor reduction device. FIG. It is a circuit block diagram of 2nd Embodiment of a peak factor reduction apparatus. It is a circuit block diagram of 3rd Embodiment of the peak factor reduction apparatus. It is a circuit block diagram of an integrator. It is an example of Scheduling information which shows a no signal area. It is a circuit block diagram of an amplitude determination circuit. It is a circuit block diagram of a no-signal section detection circuit. It is a circuit block diagram of a peak detection circuit. It is a circuit block diagram of a threshold value comparison circuit. It is a circuit block diagram of a power calculation circuit. It is a circuit block diagram of an amplitude comparison circuit. It is an input / output waveform in the peak factor reduction circuit. It is a figure which shows the peak factor threshold value control by the switch in an integrator. It is a simulation waveform in this Embodiment. It is an amplitude waveform in a peak factor reduction circuit. It is a circuit block diagram of a remote radio head part. 1 is a block diagram of a wireless system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings using the embodiments.

1. Embodiment 1
The first embodiment will be described with reference to FIG.
FIG. 1 is a circuit block diagram of a peak factor reduction device. In FIG. 1, a peak factor reduction device 100A includes a peak detection circuit 101, a threshold comparison circuit 102, an NCO (Numerically Controlled Oscillators) 103, a delay unit 104, three delay units 105, a FIL (Filter) circuit 107, and a power calculation circuit. 111, an integrator 112, an amplitude comparison circuit 114, a plurality of addition / synthesis circuits 115-1, 115-2, a plurality of multipliers 116-1 to 116-4, a subtractor 117, and an adder 118. The first generation unit 151 can include, for example, a multiplier 116-1 and an addition synthesis circuit 115-1, and generates a multicarrier synthesis signal Sin from an input signal. The second generation unit 152 includes, for example, a delay unit 104, a multiplier 116-2, a FIL (Filter) circuit 107, a delay unit 105-1, a multiplier 116-3, an addition synthesis circuit 115-2, and a peak detection circuit 101. A threshold comparison circuit 102, which generates a peak suppression signal PFRerr from the input signal. The input of the peak factor reduction device 100A is an input signal, an EVM target value, a scheduling pattern (P_S), and a PFR (Peak Factor Reduction) initial threshold. The input signal is a complex signal having I and Q components. The output of the peak factor reduction device 100A is an output signal Sout with a reduced peak factor. In the following drawings, alternate long and short dash lines between blocks mean that there are a plurality of signals.
First, the peak factor reduction apparatus 100 </ b> A has a complex exponent having a frequency corresponding to each baseband signal generated by the NCO circuit 103 by the multiplier 116-1 for a complex baseband signal having at least one carrier having a uniform spectrum. The function is multiplied and frequency conversion is performed, and then addition and synthesis is performed by the addition and synthesis circuit 115-1. The peak factor reduction device 100A inputs the multicarrier combined signal Sin that has been added and combined to the peak detection circuit 101. The peak detection circuit 101 detects the maximum amplitude value Vp within the detection width N samples. The threshold comparison circuit 102 detects a sample that exceeds a preset threshold level Vt, normalizes the peak amplitude value Vp, and outputs the sample. The multiplier 116-2 multiplies the output of the threshold comparison circuit 102 and the input signal obtained by delaying the number of D1 samples corresponding to the processing by the delay unit 104, and converts the peak component into the input signal level. Thereafter, band limitation is performed by the FIL circuit 107.
The multiplier 116-3 multiplies the output of the FIL circuit 107 by the complex exponential function, which is the NCO 103 output obtained by delaying the number of D2 samples corresponding to these processes by the delay unit 105-1, and adds and synthesizes the circuit 115-2. The peak suppression signal PFRerr is generated by performing addition synthesis. Then, the subtractor 117 subtracts the peak suppression signal PFRerr from the signal PFRthr delayed by the delay unit 105-2 by the number of D2 samples corresponding to the processing with respect to the multicarrier composite signal Sin. With the above processing, the peak factor reduction device 100A outputs the baseband signal Sout with the peak factor reduced without degrading the spectrum outside the frequency band.
FIG. 8 is a circuit block diagram of the peak detection circuit.
In FIG. 8, the peak detection circuit 101 includes an instantaneous power calculation circuit 301, a delay unit 302, a maximum value detection circuit 303, a detection width generation circuit 304, and an amplitude conversion circuit 305. The instantaneous power calculation circuit 301 generates an instantaneous power component by taking the square sum of the real part and the imaginary part. The delay unit 302 includes (N−1) stages of delay elements dly, and outputs N signals. Based on the input detection width N, the detection width generation circuit 304 generates a detection width for detecting the maximum value. The tap length of the detection width is predetermined, for example, (N−3) / 2, and the valid tap is indicated by “0” and the invalid tap is indicated by “1”. For example, the array is configured in the order of the number of invalid taps + the number of valid taps. When all taps are enabled, ALL0 is selected. When all taps are disabled, ALL1 is set. The maximum value detection circuit 303 detects the maximum value from the detection width indicated by the effective tap generated by the detection width generation circuit 304 in the consecutive N samples at the output of the delay unit 302. The amplitude conversion circuit 305 converts the power value into an amplitude value by taking the square root, and outputs the amplitude value Vp.
In FIG. 1, the threshold value comparison circuit 102 compares the amplitude value Vp output from the peak detection circuit 101 with the peak factor threshold value Vt.
FIG. 9 is a circuit block diagram of the threshold comparison circuit.
The threshold comparison circuit 102 will be described with reference to FIG. In FIG. 9, the threshold comparison circuit 102 includes a threshold comparison circuit 311 and a normalization circuit 312. The threshold comparison circuit 311 subtracts the peak factor threshold Vt from the output value Vp of the peak detection circuit 101, and forcibly converts the negative output to zero. The normalization circuit 312 outputs a value obtained by normalizing the output value of the threshold comparison circuit 311 with the peak amplitude value Vp.

Returning to FIG. 1, in the peak factor reduction device 100A, the multiplier 116-2 multiplies the output result of the threshold comparison circuit 102 and the input signal obtained by delaying the number of D1 samples corresponding to the processing delay by the delay unit 104. To do. As a result, the peak factor reduction device 100A outputs a complex peak pulse component. Thereafter, the FIL circuit 107 performs band limitation. The peak factor reduction apparatus 100A multiplies the output of the FIL circuit 107 by the output of the NCO circuit 103 obtained by delaying the number of samples corresponding to the above-described processing by the delay unit 105-1, by the multiplier 116-3, and adds the adder 115. -2 is added and combined to generate a peak suppression signal PFRerr. Then, the peak factor reduction device 100A subtracts the peak suppression signal PFRerr by the subtractor 117 from the signal PFRthr delayed by the delay unit 105-2 by the number of D2 samples corresponding to the processing with respect to the multicarrier composite signal Sin. The output signal Sout after the peak factor reduction is output.
FIG. 12 shows input / output waveforms in the peak factor reduction device 100A. The chain line (before PFR) indicates the signal PFRthr delayed by the number of D2 samples corresponding to the processing with respect to the multicarrier composite signal Sin, the solid line (after PFR) indicates the output signal Sout after the peak factor reduction, and the broken line (PFR) Threshold) represents the peak factor threshold Vt.
From here, the peak factor reduction device 100A calculates the optimum peak factor threshold Vt using the signal PFRthr delayed by the number of D2 samples corresponding to the processing and the peak suppression signal PFRerr with respect to the multicarrier composite signal Sin. To do.
FIG. 10 is a circuit block diagram of the power calculation circuit.
The power calculation circuit 111 will be described with reference to FIG. 10, the power calculation circuit 111 includes two power calculation circuits 321-1 and 321-2, and two LPFs (Low-Pass Filters) 322-1 and 322 connected to the output of the power calculation circuit 322. -2 and an adder 323. The power calculation circuit 111 receives the multiplication result of the multicarrier signal PFRthr and the EVM target value by the multiplier 116-4 as an input of In1. The EVM target value can be set, for example, by referring to the allowable degradation value in the peak factor reduction circuit in the EVM rules defined by the specifications. The power calculation circuit 111 receives the peak suppression signal PFRerr as an input of In2. The power calculation circuit 111 calculates the power level that can be reduced within the EVM target value of In1 and the power level of the peak suppression signal PFRerr that is actually reduced in In2 by the power calculation units 321-1 and 321-2, respectively. The power calculation circuit 111 performs band limitation of the power level by applying a steep LPF (Low-Pass Filter) 322-1 and 322-2. Here, the purpose of converting the complex signal into power is to compare EVMs.

First, the EVM of the power level that can be reduced within the target value, multiplied by the EVM target value EVMtgt, is calculated by the equation (1). In Expression (1), S represents a signal PFRthr that is delayed from the multicarrier composite signal Sin by the number of D2 samples corresponding to processing. A general EVM is calculated by the equation (2). S represents the signal PFRthr delayed by the number of D2 samples corresponding to the processing, and E represents the peak suppression signal PFRerr, as in Equation (1). Equation (3) is calculated by solving equation (2) for error component E. For these formulas (1) and (3), the power calculation circuit 111 performs subtraction processing by the adder 323.
FIG. 4 is a circuit block diagram of the integrator.
The integrator 112 will be described with reference to FIG. In FIG. 4, the integrator 112 includes a switch (SW: Switch) 201 and a delay unit 202. The input information in the accumulator 112 is represented by In as the output signal of the power calculation circuit 111 and Pin as the scheduling pattern (P_S) obtained by delaying the delay circuit 105-3 by the number of D2 samples corresponding to the processing.
FIG. 5 shows a scheduling pattern (P_S). The scheduling pattern (P_S) is a signal supplied from the baseband side, for example, and is composed of binary values of “0” and “1”, and “0” corresponds to a no-signal section.
Returning to FIG. 4 again, the integrator 112 outputs the output signal In of the power calculation circuit 111 when the scheduling pattern (P_S) is “1” in the Switch 201. At this time, the integrator 112 in the subsequent stage of the power calculation circuit 111 performs integration until the difference between the expressions (1) and (3) becomes “0”. Therefore, immediately after the operation of the peak factor reduction device 100A, the slope has a positive or negative slope, but the slope gradually becomes gentle, and finally the balance is maintained. At this time, the actual EVM is equal to the target value. On the other hand, the integrator 112 outputs “0” as it is when the scheduling pattern (P_S) is “0” in the Switch 201. At this time, “0” is accumulated in the integrator 112 in the subsequent stage of the power calculation circuit 111.
FIG. 13 is a diagram illustrating peak factor threshold control by a switch in the integrator. As shown in FIG. 13, during the non-signal period, since the value accumulated up to the previous time is output as it is, the peak factor threshold value is held as a result.

Returning to FIG. 1, the adder 118 adds the initial value of the peak factor threshold Vt (PFR initial threshold) to the output of the accumulator 112, and feeds it back to the threshold comparison circuit 102 as the peak fact threshold Vt. The PFR initial threshold value can be set with reference to, for example, a back-off level in the power amplifier.
FIG. 11 is a circuit block diagram of the amplitude comparison circuit.
The amplitude comparison circuit 114 will be described with reference to FIG. In FIG. 11A, the amplitude comparison circuit 114 includes two instantaneous amplitude calculation circuits 331-1 and 331-2, an amplitude comparison unit 332, a delay device 333, a selector 334, and an adder. As shown in FIG. 11B, the amplitude comparison unit 332 includes a comparison unit 335, a negation 336, a gain 337, and an adder. The two instantaneous amplitude calculation circuits 331-1 and 331-2 respectively calculate the peak factor threshold Vt and the instantaneous amplitude value of the signal Sout after the peak factor reduction. The amplitude comparison unit 332 performs amplitude comparison between the two for the output signal. The comparison unit 335 compares the amplitude values of In1 (Vt) and In2 (Sout), and outputs “1” if the peak factor threshold Vt is lower, and outputs “0” otherwise. . A negative 336 swaps 0 and 1. The value of the gain 337 is a value sufficiently smaller than 1. The purpose of the amplitude comparison unit 332 is to detect the peak factor because the error component that is the peak factor factor is sufficiently detected even when the amplitude value of the peak factor threshold Vt is higher, even in the current peak detection width state. The EVM is reduced by increasing the width. On the other hand, when the amplitude value of the signal Sout after the peak factor reduction is higher, the amplitude comparison unit 332 narrows the detection width of the peak factor because the error component is insufficiently detected. The selector 334 adds the peak detection width of the initial value and the output of the amplitude comparison unit 332 in the initial process. Thereafter, the number of taps of the detection width is delayed by the delay unit 333, fed back, and addition processing is performed. Then, the number of taps having a peak detection width corresponding to the output of the amplitude comparison circuit 114 is supplied to the peak detection circuit 101.
As described above, according to the first embodiment, it is possible to realize a peak factor reduction device that performs control so as not to automatically adjust the peak factor threshold value in the no-signal section and reduces the peak factor within the EVM target value.

2. Embodiment 2
FIG. 2 is a circuit block diagram of a second embodiment of the peak factor reduction device.
A second embodiment will be described with reference to FIG. The peak factor reduction technique of the second embodiment is equivalent to that of the first embodiment. In FIG. 2, a peak factor reduction device 100B includes a peak detection circuit 101, a threshold comparison circuit 102, an NCO (Numerically Controlled Oscillators) 103, a delay unit 104, two delay units 105-1 and 105-2, an FIL circuit 107, Power calculation circuit 111, accumulator 112, amplitude comparison circuit 114, threshold determination circuit 121, a plurality of addition synthesis circuits 115-1, 115-2, a plurality of multipliers 116-1 to 116-4, a subtractor 117, an adder 118. The first generation unit 151 can include, for example, a multiplier 116-1 and an addition synthesis circuit 115-1, and generates a multicarrier synthesis signal Sin from an input signal. The second generation unit 152 includes, for example, a delay unit 104, a multiplier 116-2, a FIL (Filter) circuit 107, a delay unit 105-1, a multiplier 116-3, an addition synthesis circuit 115-2, and a peak detection circuit 101. A threshold comparison circuit 102, which generates a peak suppression signal PFRerr from the input signal. The input of the peak factor reduction device 100B is an input signal, an EVM target value, a no-signal threshold value, and a PFR threshold value. The input signal is a complex signal having I and Q components. The output of the peak factor reduction device 100B is an output signal with a reduced peak factor.
The peak factor reduction device 100B detects the no-signal interval by performing threshold determination using the no-signal threshold and the multicarrier composite signal PFRthr by the amplitude determination circuit 121, and automatically adjusts the peak factor threshold in the no-signal interval Do not control. This will be described with reference to FIG.
FIG. 6 is a circuit block diagram of the amplitude determination circuit. In FIG. 6, the amplitude determination circuit 121 includes an instantaneous amplitude calculator 211 and a comparison unit 212.
In FIG. 6, an instantaneous amplitude calculator 211 calculates an instantaneous amplitude value of the multicarrier composite signal PFRthr. The comparison unit 212 performs threshold determination using the output signal of the instantaneous amplitude calculator 211 and the no-signal threshold value which is input information, and sets “0” when the output signal of the instantaneous amplitude calculator 211 is equal to or less than the no-signal threshold value. Otherwise, “1” is output. This binary information corresponds to Scheduling information indicating ON / OFF of data as shown in FIG. Then, the output information of the comparison unit 212 is supplied to the integrator 112 as Scheduling information.

3. Embodiment 3
FIG. 3 is a circuit block diagram of a third embodiment of the peak factor reduction device.
A third embodiment will be described with reference to FIG. The peak factor reduction technique is the same as in the first embodiment. In FIG. 3, a peak factor reduction device 100C includes a peak detection circuit 101, a threshold comparison circuit 102, an NCO (Numerically Controlled Oscillators) 103, a delay unit 104, two delay units 105-1 and 105-2, an FIL circuit 107, A power calculation circuit 111, an integrator 112, an amplitude comparison circuit 114, a no-signal section detection circuit 131, a plurality of addition synthesis circuits 115-1, 115-2, a plurality of multipliers 116-1 to 116-4, a subtractor 117, An adder 118 is provided. The first generation unit 151 can include, for example, a multiplier 116-1 and an addition synthesis circuit 115-1, and generates a multicarrier synthesis signal Sin from an input signal. The second generation unit 152 includes, for example, a delay unit 104, a multiplier 116-2, a FIL (Filter) circuit 107, a delay unit 105-1, a multiplier 116-3, an addition synthesis circuit 115-2, and a peak detection circuit 101. A threshold comparison circuit 102, which generates a peak suppression signal PFRerr from the input signal.
The input of the peak factor reduction device 100C is an input signal, an EVM target value, and a PFR threshold value. The input signal is a complex signal having I and Q components. The output of the peak factor reduction device 100C is an output signal with a reduced peak factor.
In the peak factor reduction device 100C, the no-signal section detection circuit 131 detects the no-signal section using the multicarrier composite signal PFRthr and performs control so that the peak factor threshold in the no-signal section is not automatically adjusted. This will be described with reference to FIG.
FIG. 7 is a circuit block diagram of the no-signal section detection circuit. In FIG. 7, the no-signal section detection circuit 131 includes an instantaneous amplitude calculator 221, a delay unit 222, and a comparison determination circuit 223.
In FIG. 7, an instantaneous amplitude calculator 221 calculates an instantaneous amplitude value of the multicarrier composite signal PFRthr. The delay device 222 includes (M−1) stages of delay elements dly, and outputs the signals as M signals. The comparison determination circuit 223 determines whether the instantaneous amplitude values of all the consecutive M samples are other than “0”. Based on the determination result, when the instantaneous amplitude values of all the consecutive M samples are detected as “0”, it is determined that a predetermined period, for example, 1 ms is a no-signal interval from the moment when “0” is detected. 0 ”is output. Otherwise, “1” is output. This binary information corresponds to Scheduling information indicating ON / OFF of data as shown in FIG. Then, the output information of the comparison unit 212 is supplied to the integrator 112 as Scheduling information.

4). Simulation FIG. 14 shows a simulation waveform in the present embodiment. FIG. 15 is an amplitude waveform in the peak factor reduction circuit.
With reference to FIG. 14, the simulation result in this Embodiment (example, Embodiment 3) and the conventional peak factor reduction apparatus is demonstrated. In FIG. 14, the input signal is a 2-carrier LTE (Long Term Evolution) signal having an ABS obtained by oversampling a complex normal distribution signal having a sampling frequency of 7.68 MHz four times. 14 uses a filter designed for the LTE baseband filter as the baseband filter, and FIG. 14A shows a Gaussian distribution, when the EVM target value is 5.0%, before the peak factor reduction, FIG. 14B shows a conventional technique after the peak factor is reduced, and FIG. 14B shows a Gauss distribution when the EVM target value is 5.0%, before the peak factor is reduced, and after the peak factor is reduced by applying the third embodiment. CCDF (Complementary Cumulative Distribution Function) was plotted. CCDF (complementary cumulative distribution function) indicates the probability of occurrence of an amplitude level, the vertical axis is CCDF, and the horizontal axis is amplitude. In FIG. 14, the broken line is a Gaussian distribution, the alternate long and short dash line is the peak factor before reduction of the peak factor, and the solid line is the CCDF after reduction of the peak factor to which the conventional technique or the third embodiment is applied.
As shown in FIG. 14, the EVM before and after peak factor reduction in the conventional peak factor reduction apparatus is 5.04% before and after the peak factor reduction, whereas the EVM before and after peak factor reduction in the peak factor reduction apparatus of this embodiment is 4.70%. It can be confirmed that This is because the peak factor reduction device according to the prior art automatically adjusts the peak factor threshold value in the ABS section as shown in FIG. 15, so that the peak factor threshold value becomes lower than necessary and the deterioration becomes large. Moreover, because the peak factor threshold value has become lower than necessary, the EVM degradation has increased when the ABS detection section has been removed. As a result, peak factor reduction within the EVM target value cannot be performed or the reduction is not sufficient. However, since the peak factor reduction device in the present embodiment controls the peak factor threshold adjustment in the ABS section, the EVM degradation can be reduced more than in the conventional technique. Therefore, the EVM before and after the peak factor reduction can be improved by applying the peak factor reduction device according to the present invention.
As described above, in the above-described first to third embodiments, the peak factor can be reduced within the range of a desired EVM value by controlling the automatic adjustment function of the peak factor threshold value in the no-signal section. A factor reduction device was realized.

5. Base Station, Radio System FIG. 16 is a circuit block diagram of a remote radio head unit.
Next, a base station using the peak factor reduction device will be described with reference to FIG.
In FIG. 16, an RRH 401 includes a BBFIL (Base Band Filter) circuit 413, a peak factor reduction device (PFR: Peak Factor Reduction) 100, a DPD (Digital Pre-Distortion) circuit 412, and a transmission amplifier (PAU: Power Amplifier 4U). A low noise amplifier (LNA) 415 and a BBFIL circuit 416 are provided. As the PFR 100, the peak factor reduction device 100A, 100B, or 100C of the above-described embodiments is used.
The transmission system will be described. The BBFIL circuit 414 performs band limitation on the baseband signal output from the baseband signal processing unit (BBU: Base Band Unit). For a band-limited signal, the PFR apparatus 100 suppresses instantaneous power with respect to average power without generating a distortion component outside the band. For the signal output from the PFR circuit 100, the DPD circuit 412 compensates for the non-linear component in the power amplifier at the subsequent stage. Since the input / output characteristics of the power amplifier are nonlinear, the DPD circuit 412 adds the inverse characteristics to make the input / output characteristics of the power amplifier linear. Therefore, since the DPD circuit 412 needs to grasp the input / output characteristics of the power amplifier, the output of the PAU 411 is fed back to correct the input / output characteristics of the power amplifier. The PAU 411 performs power amplification and transmits from the antenna end.
For the reception system, the LNA unit 415 performs power amplification of the signal received from the antenna end. Thereafter, the power-amplified received signal is AD converted, and the BBFIL circuit 416 performs band limitation. The RRH 401 supplies the band-limited received signal to the baseband signal processing unit.

FIG. 17 is a block diagram of a wireless system.
Next, the wireless system will be described. In FIG. 17, the wireless system includes a base station 404 and a terminal 403. A plurality of base stations are controlled by the base station controller. The base station 404 includes a BBU 402, an RRH 401, and antennas 405 and 406. The BBU 402 performs baseband signal processing. The RRH 401 performs RF signal processing. The base station 404 performs wireless communication with the terminal 403. The antenna 405 is a transmission antenna. The antenna 406 is a receiving antenna.
The base station 404 includes the above-described peak factor reduction device in the RRH 401. As a result, the base station 404 performs peak factor reduction processing within the EVM target value even for an input signal having a no-signal section.

  DESCRIPTION OF SYMBOLS 100 ... Peak factor reduction apparatus, 101 ... Peak detection circuit, 102 ... Threshold comparison circuit, 103 ... NCO (Numerally Controlled Oscillators) circuit, 104 ... Delay device D1, 105 ... Delay device D2, 107 ... FIL circuit, 111 ... Power calculation Circuit 112 112 accumulator 114 amplitude comparison circuit 121 amplitude determination circuit 131 no signal interval detection circuit 201 switch 202 delay unit 211 instantaneous amplitude calculator 212 comparison unit 221 Instantaneous amplitude calculator, 222 ... delay unit, 223 ... comparison and determination circuit, 301 ... instantaneous power calculation circuit, 302 ... delay unit, 303 ... maximum value detection circuit, 304 ... detection width generation circuit, 305 ... amplitude conversion circuit, 311 ... Threshold comparison circuit, 312 ... normalization circuit, 321 ... instantaneous power calculator, 322 ... L PF circuit, 331 ... instantaneous amplitude calculation circuit, 332 ... amplitude comparison unit, 333 ... delay unit, 334 ... selector, 335 ... comparison unit, 336 ... negation, 337 ... gain, 401 ... RRH (Remote Radio Head), 402 ... BBU (Base Band Unit), 403 ... terminal, 404 ... base station, 405 ... transmission-only antenna, 406 ... reception-only antenna, 411 ... PAU (Power Amplifier Unit), 412 ... DPD (Digital Pre-Distortion), 413 ... BBFIL ( Base Band Filter) circuit, 415... LNA (Low Noise Amplifier), 416... BBFIL circuit

Claims (12)

A first generation unit that multiplies a complex baseband signal by a complex exponential signal having a frequency corresponding to the complex baseband signal, performs frequency conversion, and adds and generates a multicarrier composite signal;
The multi-carrier composite signal is multiplied by the complex baseband signal, and the complex exponential function signal is multiplied by the result of comparing the peak amplitude value in the set detection width with the set peak factor threshold. A second generation unit that performs frequency conversion and summing to generate a peak suppression signal;
A first delay unit that delays the multicarrier composite signal by the number of samples corresponding to the processing delay of the second generation unit;
A subtractor that subtracts the peak suppression signal output by the second generator from the output of the first delay unit and outputs an output signal;
A power calculator that outputs a power difference between a signal obtained by multiplying the output of the first delay device by a predetermined amplitude error target value or EVM target value and the peak suppression signal;
When the output of the power calculator is integrated, a no-signal information signal representing a no-signal section of the plurality of complex baseband signals is input, and the no-signal information signal is a first value representing a no-signal section An integrator that holds the output to hold the current peak factor threshold;
An adder that sets a value obtained by adding an initial value of a predetermined peak factor threshold to the output of the integrator as a peak factor threshold of the second generator;
A peak factor reduction apparatus comprising: an amplitude comparison unit that sets an output obtained by comparing the amplitude of a peak factor threshold value from the adder and an output signal from the subtractor as the detection width of the second generation unit.
The peak factor reduction device according to claim 1,
The second generator is
A peak detection unit that calculates an instantaneous amplitude value of the multicarrier composite signal and detects a peak amplitude value that is maximum within a detection width;
Threshold comparison that compares the peak amplitude value calculated by the peak detection unit with a peak factor threshold, calculates an excess level from the peak factor threshold, and outputs a signal normalized with the peak amplitude value for the excess level And
A second delay device that delays the plurality of complex baseband signals by the number of samples corresponding to a processing delay between the peak detection unit and the threshold value comparison unit;
A first multiplier that multiplies the output of the threshold comparator by the output of the second delay;
A filter for limiting the bandwidth of the output of the first multiplier;
A third delayer that delays the complex exponential function signal by the number of samples corresponding to a processing delay of the peak detection unit, the threshold comparison unit, and the filter;
A second multiplier for frequency conversion by multiplying the output of the filter and the output of the third delay device;
A peak factor reduction device comprising: an addition synthesizer for adding and synthesizing outputs of the second multiplier to generate a peak suppression signal.
The peak factor reduction device according to claim 1,
A peak factor reduction device, further comprising: Numerically controlled oscillators (NCO) that generate complex exponential signals having frequencies corresponding to the plurality of complex baseband signals.
The peak factor reduction device according to claim 1,
2. The peak factor reduction device according to claim 1, wherein the no-signal information signal is input to the accumulator from a base station, a base station control station, or another baseband device.
The peak factor reduction device according to claim 1,
2. The peak factor reduction device according to claim 1, wherein the no-signal information signal is an Almost Blank Subframe (ABS) pattern.
The peak factor reduction device according to claim 1,
A fourth delay for outputting the no-signal information signal by delaying a signal indicating scheduling information in the no-signal section by the number of samples corresponding to the processing delay of the peak detection unit, the threshold comparison unit, and the filter. Further equipped with
The output of the fourth delay unit is input to the accumulator, and the accumulator controls to maintain a current peak factor threshold when the no-signal information signal indicates the first value. A feature of peak fract reduction device.
The peak factor reduction device according to claim 1,
A peak factor reduction device, further comprising: a no-signal detection unit that detects a no-signal section according to the multi-carrier composite signal to create a no-signal information signal and outputs the no-signal information signal to the accumulator.
The peak factor reduction device according to claim 1,
When the instantaneous amplitude value of the second delay device is smaller than the no-signal threshold value by comparing the amplitude of the instantaneous amplitude value of the multi-carrier composite signal with the no-signal threshold value set in advance to detect the no-signal section. An amplitude determination circuit for outputting the first value;
The output of the amplitude determination circuit is input to the accumulator, and the accumulator controls to hold the current peak factor threshold when the output of the amplitude determination circuit indicates the first value. A peak factor reduction device.
The peak factor reduction device according to claim 1,
When it is detected that the instantaneous amplitude of the multi-carrier composite signal is a value indicating a no-signal section for a predetermined number of samples, a no-signal is output for outputting the first value for a predetermined period. It further comprises a section detection circuit,
The output of the no-signal section detection circuit is input to the accumulator, and the accumulator is controlled to hold the current peak factor threshold when the output of the no-signal section detection circuit indicates the first value. A peak-fracture reducing apparatus characterized by:
A base station comprising the peak factor reduction device according to claim 1.
A base station comprising the peak factor reduction device according to any one of claims 1 to 9,
The base station includes a remote radio head unit that performs radio signal processing, and a baseband signal processing unit,
The remote radio head unit is
A baseband filter that limits the band of the baseband signal output from the baseband signal processing unit;
The peak factor reduction device for suppressing instantaneous power relative to average power from the output of the baseband filter;
A digital predistortion circuit that compensates for a non-linear component in a power amplifier at a subsequent stage in the output signal of the peak factor reduction device;
A base station comprising a power amplifier that amplifies the output of the digital predistortion circuit.
A plurality of base stations comprising the peak factor reduction device according to any one of claims 1 to 9,
A radio system comprising: a base station control device for controlling the plurality of base stations.

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