JP2013061814A - Data storage, memory controller and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data storage capable of increasing the data writing efficiency on a flash memory.SOLUTION: When the size of a piece of write data from a host unit 23 is smaller than a predetermined size, a write data processing module 13 reads a piece of data of a predetermined size, which is managed under an address identical to that of the write data, from a flash memory 22 to perform merging processing for setting a piece of data of a predetermined size, which includes the write data, in a buffer memory. Further, when beginning or terminating the reading of the data from the flash memory 22, if a new piece of write data managed under an address identical to that of an old write data is found in the buffer memory, the write data processing module 13 performs the merging processing in the buffer memory using the new write data as a piece of merging target data.

Description

  Embodiments described herein relate generally to a data storage device, a memory control device, and a method using a nonvolatile memory.

  2. Description of the Related Art Conventionally, an SSD (solid state drive) using a NAND-type flash memory (hereinafter sometimes simply referred to as a flash memory), which is a rewritable nonvolatile memory, as a storage medium has been developed as a data storage device.

  In the SSD, data write and read operations are performed on a flash memory in a logical access unit called a cluster. That is, the cluster is a unit of data size that can access the flash memory at one time. Normally, one cluster is a collection of a plurality of sectors, which are physical access units, and is composed of, for example, eight sectors. Hereinafter, cluster unit data may be referred to as cluster data, and sector unit data may be referred to as sector data.

  On the other hand, data smaller than the cluster size may be transferred as a write request from the host. Note that sector-by-sector data is transferred from the host and stored in the SSD buffer memory. The SSD collects sector data into cluster data and writes it to the flash memory.

JP 2004-62328 A

  When there is data of a size less than a cluster as a write request from the host, the logical address of the data may overlap with existing recording data (data written to the flash memory) (WAW: Write After Write) . That is, it is an operation of rewriting a part of the cluster data written in the flash memory. In this case, a so-called RMW (read modify write) operation is required. For this reason, a series of processing processes such as a process of reading data from the flash memory, a process of collecting the data into the cluster data, and a process of writing to the flash memory occur, and it is an issue to improve the processing efficiency for writing the write request data to the flash memory. It is.

  An object of the present invention is to provide a data storage device capable of improving the processing efficiency for writing write request data to a flash memory.

  According to the embodiment, the data storage device includes a flash memory that uses data of a predetermined size as a write unit, a buffer memory, a controller, and write data processing means. The buffer memory sequentially stores write data from the host device. The controller writes the predetermined size data stored in the buffer memory to the flash memory. The write data processing means reads the data of the predetermined size managed at the same address as the write data from the flash memory when the write data from the host device is less than the predetermined size, and stores the data in the buffer memory A merge process for setting the predetermined size data including the write data is executed. Further, the write data processing means may read the new data when there is new write data managed at the same address as the old write data in the buffer memory at the time of reading or completing the data from the flash memory. Merge processing in the buffer memory is executed with write data as data to be merged.

The block diagram for demonstrating the structure of the data storage apparatus regarding embodiment. The block diagram for demonstrating the structure of the write data processing module regarding embodiment. The figure which shows the storage information of the WBE buffer regarding embodiment. The figure for demonstrating the process by the WBE controller regarding embodiment. The figure for demonstrating the merge process during cluster data transfer to the hole-filling read buffer regarding embodiment. 6 is a flowchart for explaining merge processing during transfer of cluster data according to the embodiment. The figure for demonstrating the merge process at the time of completion of cluster data transfer to the hole-filling read buffer regarding embodiment. The figure for demonstrating the 1st relationship of the hole-filling lead process and merge process regarding embodiment of FIG. The figure for demonstrating the 2nd relationship of the hole-filling lead process and merge process regarding embodiment of FIG.

  Embodiments will be described below with reference to the drawings.

[Configuration of data storage device]
FIG. 1 is a block diagram illustrating a main part of the data storage device according to the embodiment.

  The data storage device of the embodiment is an SSD (solid state drive) that uses a NAND flash memory (flash memory) as a storage medium. As shown in FIG. 1, the SSD is roughly divided into a flash memory controller 10, a microprocessor (CPU) 19, a memory (DRAM: dynamic random access memory) 20, a boot ROM (read only memory) 21, and a flash. And a memory 22.

  The boot ROM 21 stores a boot program for enabling access from the external host device 23 to the SSD. The flash memory controller 10 controls data transfer between the flash memory 22 and the host device 23 in accordance with an instruction from the CPU 19. When the program from the boot ROM 21 is transferred to the internal memory of the CPU 19 after the system power is turned on, the flash memory controller 10 can be controlled from the software (CPU 19).

  The flash memory controller 10 includes a control bus 11, a host interface controller (host I / F controller) 12, a write data processing module 13, a read data processing module 14, an address management module 15, an ECC processing and log generation module. 16, a NAND controller (hereinafter simply referred to as controller) 17, and a data bus 18.

  The host I / F controller 12 controls data or command transfer with the host device 23. The host device 23 is, for example, an interface (for example, an SATA (Serial ATA) standard interface) that connects a personal computer and an SSD. As will be described later, the write data processing module 13 executes processing for writing data (write data) transferred from the host I / F controller 12 to the flash memory 22. The read data processing module 14 executes processing for transferring data (read data) read from the flash memory 22 to the host I / F controller 12.

  The address management module 15 has an address conversion table (or LUT: lookup table) for converting between a logical address and a physical address, and manages a physical write destination (address) to the flash memory 22. The ECC processing and log generation module 16 executes data error detection and correction (ECC) processing when reading from the flash memory 22. The ECC processing and log generation module 16 adds an error correction code to the cluster data when writing to the flash memory 22. Further, the module 16 generates a log such as attribute information added to the cluster data. The controller 17 writes or reads cluster data to or from the flash memory 22.

  FIG. 2 is a block diagram showing a main part of the write data processing module 13.

  As shown in FIG. 2, the write data processing module 13 includes a write buffer memory (sometimes referred to as a write buffer) 30, a WBE management information buffer memory (sometimes referred to as a WBE buffer) 31, and a WBE state. Transition controller (may be referred to as a WBE controller) 32, queue management module 33, hole-filling read completion queue (Queue) module 34, hole-filling read buffer memory (case of hole-filling read buffer) 35).

  The write buffer 30 stores the data (sector unit) received by the host I / F controller 12. The WBE buffer 31 manages the storage destination address (WBA) of the data with WBE (write buffer entry) management information (hereinafter sometimes simply referred to as WBE) as specified by the CPU 19. The WBE controller 32 controls the WBE state transition, as will be described later.

  As will be described later, the queue management module 33, the hole filling read completion queue (Queue) module 34, and the hole filling read buffer 35 each combine data for each sector into cluster data (cluster data). This is a configuration for performing (merge processing).

[Data writing process]
Hereinafter, in the flash memory controller 10 of the present embodiment, data write processing mainly by the operation of the write data processing module 13 will be described.

  First, write request data (write data) transferred from the host device 23 is received by the host I / F controller 12 and sent to the write data processing module 13. The host device 23 is accessed by a logical block address (LBA) and transfers write data in units of sectors. When one cluster has an 8-sector configuration, the quotient obtained by dividing LBA by 8 is LCA.

  In short, the write data processing module 13 merges (merges) the write data of the sector unit with the data of other sector units, and sets (regroups) the data in the cluster unit (cluster data), ECC processing and log Transfer to the generation module 16 and the controller 17. The controller 17 executes control for writing cluster data to the flash memory 22 by one access.

  Here, the address management module 15 has a logical and physical address conversion table (LUT), and manages a physical write destination (physical address) to the flash memory 22. The cluster data to be written is managed as a logical address by a logical cluster address (LCA). When the write data processing module 13 recognizes the LCA of the received sector data (write data), it requests the address management module 15 for address resolution processing.

  The address resolution process is a process for obtaining the position (address) of merge source data (merger source data) to be collected (set) into cluster data. Specifically, the address management module 15 determines the latest position (physical address) of the LCA corresponding to the write data when the latest position of the LCA (in short, cluster data one generation before) exists on the flash memory 22. Is returned to the write data processing module 13 (solution processing result 1). This latest position is set as the latest position information 42 in the WBE buffer 31 shown in FIG. Further, when a WBE indicating another entry having the same LCA as the LCA corresponding to the write data is indicated, the address management module 15 stores the address (WBA) of the write buffer 30 in the WBE as will be described later. Address reassignment processing is performed (resolution processing result 2). If an unwritten portion remains after the address change, the write data processing module 13 performs a process according to the solution processing result 3 described later.

  Here, when the write data of the write request corresponds to the unwritten LCA, the write data processing module 13 receives a code indicating it from the address management module 15 (resolution processing result 3). In this case, there is no merge source data to be collected into cluster data. For this reason, the write data processing module 13 uses user-defined data (dummy data, for example, all 0) as merge source data, and performs a process of filling empty areas in cluster units. Further, the host device 23 may be a method of performing a process of filling the dummy data by a write back process. In the present embodiment, the description when the write data of the write request corresponds to the unwritten LCA is omitted.

  Hereinafter, the processing of the write data processing module 13 of this embodiment will be described with reference to FIGS.

  When the write data of the write request transferred from the host device 23 is less than the cluster size, the write data processing module 13 performs the merge process according to the address resolution processing result from the address management module 15 as described above. To execute the process to set the cluster data. That is, the write data processing module 13 reads the cluster data from the flash memory 22 when cluster data one generation before the LCA corresponding to the write data exists on the flash memory 22. The write data processing module 13 stores the read cluster data in the write buffer 30.

  A storage address (WBA: Write Buffer Address) in the write buffer 30 is managed by the WBE buffer 31. FIG. 3 shows information stored in the WBE buffer 31. As shown in FIG. 3, the WBE buffer 31 has an LCA area 40, a sector information area 41, a latest position information 42, a sector valid flag (SECT-VF), and a WBE for each WBE number (WBE # X, WBE # Y). It has a status (WBE-Status) area 43, a sector management information area 44, and a spare management area (Fw management) 45.

  The LCA area 40 stores LCA (indicated by lower 32 bits obtained by shifting 48 bits of LBA to the right by 3 bits). The sector information area 41 indicates the WBA of sector data. SECT-VF indicates the WBA of valid sector data among the 8 sectors. That is, the number of sectors of the write data transferred from the host device 23 is recognized by the last sector address. An effective WBA corresponding to this number of sectors is indicated by a sector valid flag (SECT-VF). WBE-Status indicates the states 50 to 55 shown in FIG. The sector management information area 44 indicates the type of read command or write command.

  FIG. 4 shows a state transition state of data processing by the WBE controller 32.

  As shown in FIG. 4, when data reception processing from the host device 23 is started by the host I / F controller 12, the WBE controller 32 selects a new WBE from the WBE invalid queue of the queue management module 33. The WBE controller 32 stores in the storage destination address of the write buffer 30 in the new WBE. In parallel, the WBE controller 32 makes a transition from the invalid state to the entry state 50 (current) during data reception. The WBE controller 32 sets the WBE transitioned to the entry state 50 (current) in the WBE Valid Queue of the queue management module 33. As described above, the WBE controller 32 requests the address management module 15 for address resolution processing, and accepts the address resolution processing result (1, 2 excluding 3).

  The WBE controller 32 stays in the entry state 50 (current) until the LCA changes, and transitions to the entry state 51 (fresh) after completion of data reception when the LCA changes. When the WBE controller 32 transits to the entry state 51 (fresh), the WBE sector data reception state is confirmed by the sector valid flag (SECT-VF) of the WBE buffer 31.

  The WBE controller 32 transitions to the entry state 53 (read) when the data stored in the write buffer 30 is less than the cluster size in accordance with the reception state of the sector data (write data). When the WBE controller 32 transits to the entry state 53 (read), it issues a cluster data read command (fill-fill read command) for fill-in processing (merge processing). Thereby, the data stored in the hole filling read buffer 35 are merged.

  On the other hand, when the reception state of the sector data is the cluster size, the state transits to a state 54 (ready) in which the cluster data is set. The WBE cluster data in this state 54 (ready) is transferred to the ECC processing and log generation module 16 and the controller 17. The controller 17 writes the cluster data to the flash memory 22 with one access.

  When the WBE can be invalidated after the cluster data is written in the flash memory 22, the address management module 15 notifies the write data processing module 13. As a result, the WBE is set in the WBE invalid Queue of the queue management module 33 (state 55), and is reused as a new WBE.

  Next, a merge process (merge process) in the buffer memory 30 in the entry state 53 (read) will be described with reference to FIGS. Here, the merge source entry (old entry) is set to WBE # X, and the merge target entry (new entry) is set to WBE # Y.

  In the present embodiment, when a hole filling read process for cluster data one generation before the same LCA is executed, a WBE indicating a new entry having the same LCA as the LCA corresponding to the write data is indicated Execute the merge process. In this case, in the buffer memory 30, the old entry WBE # X is updated to the new entry WBE # Y, and address reassignment processing of the address (WBA) is performed.

  The merge process in the write buffer 30 is performed by changing the buffer address (WBA) of the sector data of the merge source entry (old entry) for the invalid sector data of the entry to be merged (new entry). ) Is a process of logically replacing the data associated with ().

  FIGS. 8 and 9 show the relationship between the hole filling read completion queue 34 shown in FIG. 2 and the merge processing shown in FIG.

  As shown in FIG. 8 and FIG. 9, in the hole filling read process, cluster unit data (cluster data) is stored in the hole filling read buffer 35 from the flash memory 22, and the entry (WBE) in the write buffer 30 is processed by the address reassignment process. Complete by associating with.

  As shown in FIG. 8, when the address reassigning process is executed, the WBE controller 32 has completed the transfer of cluster data by the hole filling read process for the merge source entry (assumed to be the old entry WBE # 15). It is checked whether or not (process 901). In this case, the merge target entry (new entry) of the same LCA (100) is set as WBE # 20, and the address reassigning process (process 902) for the old entry WBE # 15 is executed. In other words, processing 902 means that LCA (100) is received in duplicate, and WBE # 20 recognizes that WBE # 15 is the merge source.

  The WBE controller 32 refers to the hole filling read completion waiting queue 34 and checks whether the hole filling read command is issued or completed. In this case, the hole filling lead TagID and the corresponding WBE # are erased. The hole filling read completion waiting queue 34 records entry numbers (WBE #) waiting for completion of hole filling read processing in the order of issuing hole filling read commands. When the transfer of the cluster data is completed, the WBE controller 32 deletes the hole filling read command in the hole filling read completion waiting queue 34.

  As shown in FIG. 8, the WBE controller 32 executes the merge process in the write buffer 30 in advance because the transfer of the cluster data to the old entry WBE # 15 has not been completed. However, the address reassignment process (process 902) for reassigning the buffer address (WBA) of the sector data of the old entry WBE # 15 for the invalid sector data of the new entry WBE # 20 is the same as that of the hole filling read buffer 35 and the old entry. Address reassignment processing between WBE # 15 cannot be executed simultaneously.

  Next, as shown in FIG. 9, the WBE controller 32 updates the old entry WBE # 15 in the hole-filling read completion waiting queue 34 to the new entry WBE # 20, and transitions to the entry state 53 (read). That is, the WBE controller 32 issues a hole filling read command and executes a merge process in the write buffer 30 for the new entry WBE # 20 (process 904). On the other hand, the WBE controller 32 sets the old entry WBE # 15 in the WBE invalid Queue of the queue management module 33 and reuses it as a new WBE (process 903).

  Further, with reference to FIG. 5 to FIG. 7, the merge process in the write buffer 30 will be described separately during the transfer of cluster data by the hole filling read process and when the transfer is completed.

  5 and 6 are diagrams showing merge processing during transfer of cluster data by hole filling read processing. Here, FIG. 5 corresponds to the processing of blocks 104 to 111 shown in FIG.

  First, when the data reception state of the old entry WBE # X is a cluster size, the WBE controller 32 transitions to a state in which cluster data is set (ready) as shown in FIG. 4 (NO in block 101). . In this case, the controller 17 writes the cluster data to the flash memory 22 with one access.

  If it is less than the cluster size, the WBE controller 32 issues a hole filling read command for hole filling processing (merge processing), and transitions to the read state 60 shown in FIG. 5 (block 102). Here, the old entry WBE # X and the new entry WBE # Y are the same LCA (X0). The controller 17 reads the cluster data of the LCA (X0) from the flash memory 22 (state 61) and stores it in the hole filling read buffer 35.

  The WBE controller 32 refers to the hole filling read completion waiting queue 34 and determines that the cluster data is being transferred if there is a read command of the entry number WBE # X of the merge source (NO in block 103). At this time, when the data of the new entry WBE # Y of the same LCA (X0) is received (state 70), the WBE controller 32 refers to the hole filling read completion waiting queue 34 and confirms the existence of the old entry WBE # X. (YES in block 104).

  The WBE controller 32 executes an address reassigning process for the old entry WBE # X and the new entry WBE # Y (block 105). As a result, the old entry WBE # X in the hole filling read completion waiting queue 34 is updated to a new entry WBE # Y (block 106). That is, in the write buffer 30, merge processing in the write buffer 30 for the new entry WBE # Y is executed (state 63). However, during this time, even if the transfer of the cluster data is completed, the hole filling completion process is not executed.

  After the merge process is completed, the WBE controller 32 transitions the new entry WBE # Y to the entry state 63 (read), and sets the old entry WBE # X to the WBE invalid queue of the queue management module 33 (block 107, state 64). .

  Next, the WBE controller 32 refers to the hole filling read completion waiting queue 34 and determines whether or not the cluster data of the entry number WBE # Y has been transferred (block 108). If the transfer of cluster data has been completed, the WBE controller 32 updates the hole filling read completion waiting queue 34 and deletes WBE # Y (block 109).

  The WBE controller 32 completes the hole filling process of the old entry WBE # X and executes the address reassigning process (block 110). After completing the merge process, the WBE controller 32 transitions the new entry WBE # Y to a state in which cluster data is set (ready) (block 111).

  Next, with reference to FIG. 6 and FIG. 7, a merge process when the transfer of cluster data by the hole filling read process is completed will be described. Here, FIG. 7 corresponds to the processing of blocks 112 to 116 shown in FIG. The process 117 is a case where no WAW process occurs.

  The WBE controller 32 waits for the completion of the cluster data transfer, updates the hole filling read completion queue 34, and deletes the entry WBE # X (block 112). The WBE controller 32 completes the hole filling process for the entry WBE # X and executes the address reassignment process (block 113). At this time, when data of a new entry WBE # Y of the same LCA (X0) is received (state 70), the WBE controller 32 executes an address reassigning process of the old entry WBE # X and the new entry WBE # Y ( YES in block 114, 115).

  After the merge process is completed, the WBE controller 32 transitions the new entry WBE # Y to a state in which cluster data is set (ready), and sets the old entry WBE # X in the WBE invalid Queue of the queue management module 33 (block 116). ). If the WBE controller 32 does not receive the data of the entry WBE # Y, the WBE controller 32 transitions the entry WBE # X to a state in which cluster data is set (ready) (block 117).

  As described above, according to the present embodiment, when the write data of the write request transferred from the host device 23 is smaller than the cluster size, the write data processing module 13 sets the data in cluster units by the hole filling read process. . Therefore, it is possible to write to the flash memory 22 with one access. Here, even when the write data of the old entry WBE # X and the new entry WBE # Y with overlapping LCAs is transferred from the host device 23, the hole filling read process and the write process to the flash memory 22 can be performed once. it can. Therefore, cluster data can be set by accessing the minimum necessary flash memory 22 and an efficient write operation to the flash memory can be realized.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10: Flash memory controller,
12: Host interface controller (host I / F controller),
13 ... Write data processing module, 14 ... Read data processing module,
15 ... Address management module, 16 ... ECC processing and log generation module,
17 ... NAND controller, 19 ... Microprocessor (CPU),
22: Flash memory, 30: Write buffer memory,
31 ... WBE management information buffer memory, 32 ... WBE state transition controller,
33 ... Queue management module,
34 ... Queue module for filling hole completion,
35 ... Buffer memory for filling holes.

Claims (10)

A flash memory having a predetermined size of data as a writing unit;
A buffer memory for sequentially storing write data from the host device;
A controller that writes the data of the predetermined size stored in the buffer memory to the flash memory;
When the write data from the host device is less than the predetermined size, the data of the predetermined size managed at the same address as the write data is read from the flash memory, and the write data is included in the buffer memory. Write data processing means for executing merge processing for setting data of a predetermined size,
The write data processing means includes
When there is new write data managed at the same address as the old write data in the buffer memory when reading data from the flash memory or when reading is completed, the new write data is used as merge target data. A data storage device that performs merge processing in a buffer memory. The write data processing means includes
Hole filling read processing means for reading out data of the predetermined size from the flash memory as hole filling data;
Means for determining completion of the hole filling lead processing of the hole filling lead processing means;
When the new write data is stored in the buffer memory before completion of the hole filling read processing, the merge processing in the buffer memory is executed in advance before transferring the hole filling data to the buffer memory. The data storage device according to claim 1, further comprising: The write data processing means includes
Hole filling read processing means for reading out data of the predetermined size from the flash memory as hole filling data;
Means for determining completion of the hole filling lead processing of the hole filling lead processing means;
Means for executing merge processing in the buffer memory after transferring the hole filling data to the buffer memory when the new write data is stored in the buffer memory after completion of the hole filling read processing; The data storage device according to claim 1, comprising: The write data processing means includes
Determine whether the write data from the host device is cluster data of the cluster size as the predetermined size,
2. The cluster data managed by the same address as the old write data is read from the flash memory when the write data is smaller than the cluster size, and the hole filling data is transferred to the buffer memory. The data storage device described. The write data processing means includes
Buffer entry management means for managing an address of a buffer memory for sequentially storing the write data by an entry number;
5. The data storage device according to claim 1, wherein an address reassigning process of the new write data and the old write data is executed to execute a merge process in the buffer memory. 6. In a memory control device of a data storage device having a flash memory in which data of a predetermined size is used as a writing unit,
A buffer memory for sequentially storing write data from the host device;
A controller that writes the data of the predetermined size stored in the buffer memory to the flash memory;
When the write data from the host device is less than the predetermined size, the data of the predetermined size managed at the same address as the write data is read from the flash memory, and the write data is included in the buffer memory. Write data processing means for executing merge processing for setting data of a predetermined size,
The write data processing means includes
When there is new write data managed at the same address as the old write data in the buffer memory when reading data from the flash memory or when reading is completed, the new write data is used as merge target data. A memory control device that performs merge processing in a buffer memory. The write data processing means includes
Hole filling read processing means for reading out data of the predetermined size from the flash memory as hole filling data;
Means for determining completion of the hole filling lead processing of the hole filling lead processing means;
When the new write data is stored in the buffer memory before completion of the hole filling read processing, the merge processing in the buffer memory is executed in advance before transferring the hole filling data to the buffer memory. The memory control device according to claim 6, further comprising: The write data processing means includes
Hole filling read processing means for reading out data of the predetermined size from the flash memory as hole filling data;
Means for determining completion of the hole filling lead processing of the hole filling lead processing means;
Means for executing merge processing in the buffer memory after transferring the hole filling data to the buffer memory when the new write data is stored in the buffer memory after completion of the hole filling read processing. The memory control device according to claim 6. The write data processing means includes
Buffer entry management means for managing an address of a buffer memory for sequentially storing the write data by an entry number;
9. The memory control device according to claim 6, wherein an address reassigning process of the new write data and the old write data is executed to execute a merge process in the buffer memory. 10. A memory control method applied to a data storage device having a flash memory having a predetermined size of data as a writing unit,
Write data from the host device is sequentially stored in the buffer memory,
Writing the predetermined size data stored in the buffer memory to the flash memory;
When the write data from the host device is less than the predetermined size, the data of the predetermined size managed by the same address as the write data is read from the flash memory,
Performing a merge process for setting the data of the predetermined size including the write data in the buffer memory;
The merge process
When there is new write data managed at the same address as the old write data in the buffer memory when reading data from the flash memory or when reading is completed, the new write data is used as merge target data. A memory control method for performing merge processing in a buffer memory.

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