JP2013058906A - Communication network system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication network system, capable of shifting a communication node in a low-power consumption mode which is only to be a communication target to a normal operation mode, without an increased number of signal lines.SOLUTION: By own control, each chip 2 selectively supplies a multiplication clock signal and a reference clock signal, controls the operation of a PLL circuit 7, and includes an interface 5 for transmitting and receiving signals through a communication bus 1. The interface 5 suspends the operation of the PLL circuit 7 in a sleep state; suspends power supply to a logic unit 3; supplies the reference clock signal to the self-chip; on receiving a wake-up signal transmitted from another chip 2, starts the operation of the PLL circuit 7; and supplies the multiplication clock signal to the self-chip.

Description

  The present invention relates to a communication network system in which a plurality of nodes configured to be able to shift between a normal operation mode and a low power consumption mode are connected by a communication line.

  For example, each communication node such as an ECU (Electronic Control Unit) connected to the in-vehicle network shifts to the standby mode by stopping the supply of the system clock when a predetermined condition is satisfied in order to reduce power consumption. It is configured. When any communication node starts communication, the communication node in the standby mode is shifted to the normal operation mode (wake-up). However, since communication is not necessarily performed for all nodes, it is preferable to wake up only a communication node that is a data transmission destination. Therefore, in Patent Document 1, a network that wakes up only a part of communication nodes is realized by adding a signal line for individually transmitting a wakeup signal to the communication line.

JP 2010-280314 A (see FIG. 2)

  However, in the method of Patent Document 1, the number of signal lines naturally increases according to the number of communication nodes, and therefore the reduction in the number of signal lines required for the communication network is reversed. Further, since one node for managing which communication node is to be woken up is set, control cannot be performed flexibly.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to allow a communication node in a low power consumption mode to shift to a normal operation mode for only a communication target without increasing the number of signal lines. To provide a communication network system.

  According to the communication network system of claim 1, each node is selectively supplied with the multiplied clock signal and the reference clock signal by its own control, controls the operation of the multiplied clock output means, and passes through the communication line. An interface unit for transmitting and receiving signals is provided. Then, in the low power consumption mode, the interface unit stops the operation of the multiplied clock output unit, stops the power supply to the control unit, supplies the reference clock signal to itself, and is transmitted from another node. When the activation signal is received, the operation of the multiplied clock output means is started and the multiplied clock signal is supplied to itself.

  That is, since only the interface unit to which the reference clock signal is supplied is operating in the node in the low power consumption mode, power consumption can be sufficiently suppressed. When the interface unit receives the activation signal, the interface unit starts the operation of the multiplied clock output unit and supplies the multiplied clock signal to itself. Therefore, when the control unit performs normal communication, the interface unit can operate at high speed. In addition, since it is not necessary to wire individual signal lines in order to activate only the nodes to be communicated, the number of wirings can be reduced.

  According to the communication network system of the second aspect, the interface unit reduces the input / output response speed or response sensitivity of the receiver that receives the signal in the low power consumption mode. In other words, inter-node communication performed in the low power consumption mode is low speed, so even if the input / output response speed or response sensitivity of the receiver is reduced, communication is not hindered, so that power consumption in the receiver unit can be reduced. .

  According to the communication network system of the third aspect, the interface unit reduces the amount of power supply current supplied to the receiver. That is, if the amount of power supply current consumed to operate the receiver is reduced, the input / output response speed of the receiver can be reduced to reduce power consumption.

  According to the communication network system of the fourth aspect, since the node to transmit the start signal to another node in the normal operation mode is switched to supply the reference clock signal to the interface unit, the start signal is slow. Can be sent.

  According to the communication network system of the fifth aspect, when the interface unit transmits the activation signal to another node in the normal operation mode, the interface unit uses the reference clock signal in a state where the multiplied clock signal is supplied to the interface unit. The activation signal is transmitted at the same communication rate as the set communication rate. Therefore, the activation signal can be transmitted at a low speed without switching the clock signal supplied to itself.

  According to the communication network system of the sixth aspect, one of the plurality of nodes is set as a management node having a function of managing the entire system, and the management node is lower than a node that does not need to be activated. A signal for shifting to the power consumption mode is periodically transmitted. In other words, even a node that has transitioned to the low power consumption mode erroneously received an activation signal due to, for example, the influence of noise or the influence of communication performed by a node in the normal operation mode. It is also assumed that it will be judged and activated. Therefore, if the management node periodically transmits a signal for shifting to the low power consumption mode to a node that does not need to be activated, the node that has been erroneously activated can be shifted to the low power consumption mode.

  According to the communication network system of claim 7, since the activation signal is transmitted by the node that has acquired the master right in communication, the master right can be obtained without deciding which node transmits the activation signal in advance. By acquiring, a node that needs to start a node (slave) as a communication destination can transmit a start signal.

Functional block diagram showing the configuration of a communication network system according to the first embodiment (part 1) Figure 1 equivalent (part 2) Figure 1 equivalent (part 3) The figure which shows the specific structural example of a reference | standard clock circuit The figure which shows the example of a connection form of each component within a chip | tip Diagram showing the power supply control system Diagram showing state transition of chip Diagram showing how each part is turned ON / OFF when the chip is in the Active / Sleep state The figure which shows an example of the command frame of the Wake Up signal Timing chart explaining the case where a chip in the active state transmits a Wake Up signal at a low communication rate The flowchart which is a 2nd Example and shows the process which the chip | tip in an Active state transmits a Wake Up signal The figure which is 3rd Example and shows schematically the internal structure of an interface part The figure which shows an example of the circuit structure of an input buffer FIG. 1 equivalent view showing the fourth embodiment FIG. 1 equivalent view showing the fifth embodiment FIG. 1 equivalent view showing the sixth embodiment FIG. 1 equivalent view showing the seventh embodiment

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 is a functional block diagram schematically showing the configuration of a communication network system. This communication network system is configured by connecting a plurality of chips 2 (1 to 5) as communication nodes to a communication bus (communication line) 1. The basic configuration of each chip 2 is the same, and includes a logic part (Logic) 3, a peripheral circuit part (Others) 4, an interface part (I / F) 5, a reference clock (reference CLK) circuit 6, a PLL (Phase Locked Loop). ) The circuit 7 and the power supply unit 8 are provided.

  The logic unit 3 is a CPU or the like as a control unit that performs communication control, and the peripheral circuit unit 4 is, for example, a timer, an A / D conversion circuit, a memory, or a gate array. The interface unit 5 is directly connected to the communication bus 1 and includes a driver for transmitting signals, a receiver for receiving signals, and the like. The logic unit 3 transmits a signal to the communication bus 1 through the interface unit 5 and receives a signal transmitted on the communication bus 1. The communication protocol includes, for example, UART (Universal Asynchronous Receiver Transmitter), but is not limited thereto.

  The reference clock circuit 6 (reference clock output means), for example, oscillates and outputs a reference clock signal with a frequency of the order of kHz. For example, a CR oscillation circuit as shown in FIG. 4A or a reference clock signal as shown in FIG. Such an oscillation circuit using an external oscillator (not shown, but made up of a crystal oscillator, a resistance element, a capacitor, an inverter gate, etc.), and the like.

  The PLL circuit 7 (multiplied clock output means) multiplies the reference clock signal to generate a multiplied clock signal in the order of MHz and supplies it to the logic unit 3, peripheral circuit unit 4, and interface unit 5. Note that the PLL circuit 7 may have either a configuration in which the multiplication oscillation operation by the PLL is performed digitally or a configuration in which the operation is performed in an analog manner. The power supply unit 8 supplies power for operation to each unit of the chip 2.

  The interface unit 5 may be configured by either a CPU or hardware logic (and may be a PMU: Power Management Unit). By controlling the multiplexer 9 by its own selection, a reference clock signal and a multiplied clock signal Is switched so as to supply either of them to itself. The interface unit 5 performs control such as stopping a part of power supply to each unit by the power source unit 8 as described later. By this control, the operation state of each chip 2 is switched between an Active state (normal operation mode) and a Sleep state (low power consumption mode).

  FIG. 5 shows an example of a connection form of the above-described components (partially omitted) inside the chip 2. In FIG. 5A, the CPU 3C is shown separately from the logic unit 3, and the memory 4M is shown separately from the peripheral circuit unit 4, and these are connected to the interface unit 5 via the internal bus 10. is there. FIG. 5B shows a case where the CPU 3C, the peripheral circuit unit 4 and the memory 4M are connected by a common local bus, and the CPU 3C and the interface unit 5 are separately connected by a dedicated bus. In the case of FIG. 5A, it is possible to make the internal bus into a hierarchical structure, and in the case of FIG. 5B as well, modifications can be made as appropriate, such as directly connecting components other than the interface unit 5 to the CPU 3C. is there.

  FIG. 6 shows a configuration example for the interface unit 5 to intermittently supply power to each unit from the power supply unit 8. The module M corresponds to the logic unit 3, the peripheral circuit unit 4, the PLL circuit 7, and the like that are power supply destinations. FIG. 6A shows an example in which the switch 31 is inserted between the power source and the module M, and the switch 31 is opened and closed by a power cutoff signal output from the interface unit 5 to control the power supply to the module M. The switch 31 is, for example, an analog switch.

  In FIG. 6B, a P-channel MOSFET 32 is inserted between the power supply and the module M, and the P-channel MOSFET 32 is turned on / off by a power cutoff signal output from the interface unit 5. In FIG. 6C, an N-channel MOSFET 33 is inserted between the module M and the ground, and the N-channel MOSFET 33 is turned on / off by a power cutoff signal output from the interface unit 5. In this case, the logic of the power cutoff signal is the reverse of the case of (b). In addition to the case shown in FIG. 6, a switch may be inserted in the middle of the power supply line connected to each supply destination inside the power supply unit 8 to control the connection of the switch.

  Next, the operation of this embodiment will be described with reference to FIG. 2, FIG. 3, and FIGS. FIG. 7 shows the state transition of the chip 2. S1 corresponds to the Active state, and S2 to S7 correspond to the Sleep state. At least one of the chips 2 has a function of managing the power supply of the entire network system (management node), and transmits a sleep signal (command) to the other chips 2 to switch from the active state to the sleep state. Or transition from the Sleep state to the Active state by sending a Wake Up signal (startup signal).

  FIG. 8 shows the operation of each part: ON / OFF when the chip 2 is in the active state or the sleep state. In the active state, power is supplied to all of the core (the logic unit 3 and the peripheral circuit unit 4), the PLL circuit 7, the interface unit 5, and the reference clock circuit (Ref.CLK) 6, and the interface unit 5 is turned on. Is supplied with a multiplied clock signal. On the other hand, in the sleep state, the core and PLL circuit 7 are turned off when the power is cut off, and the interface unit 5 and the reference clock circuit 6 are turned on. The interface unit 5 is supplied with a reference clock signal.

  Again referring to FIG. (S1) When the chip 2 in the active state receives the (S2) Sleep signal, (S3) the interface unit 5 switches so that the reference clock signal (low-speed clock) is supplied to itself. Then, (S4) the power supply to the module that does not require the operation, in this case, the core and the PLL circuit 7 is stopped, and thereafter (S5) enters a standby state for monitoring whether or not a Wake Up signal is received. FIG. 1 shows that chips 2 (1) and 2 (2) are in the sleep state.

FIG. 9 shows an example of a command frame of the Wake Up signal, which is configured as follows.
Identifier (3 bits): Indicates that it is a command frame Command (5 bits): Indicates that it is Wake Up ID (12 bits): Indicates the ID of chip 2 that is the target of Wake Up CRC (16 bits): Error detection data This Wake Up signal is transmitted at a low communication rate based on the reference clock signal.

  FIG. 10 is a timing chart for explaining a case where the chip 2 in the Active state transmits a Wake Up signal at a low communication rate. (A) is the timing of the signal transmitted at the communication rate based on the multiplied clock signal shown in (b), and (c) is the timing of the signal transmitted at the communication rate based on the reference clock signal shown in (d). is there. For convenience of illustration, the period ratios of the clock signals shown in (b) and (d) do not reflect the actual ratio.

  The chip 2 in the active state transmits at the timing shown in FIGS. 10A and 10B, but the wake-up signal is transmitted to the chip 2 in the sleep state. As shown in d), the Wake Up signal is transmitted in synchronization with the low-speed communication rate based on the reference clock signal. That is, data values “1” and “0” are continuously transmitted at a necessary timing at a high speed communication rate, so that transmission is performed in synchronization with the low speed communication rate.

Again referring to FIG. When the chip 2 in the sleep state (S6) receives the Wake Up signal, (S7) the interface unit 5 switches to supply a multiplied clock signal to itself (S1) and supplies power to the core and the PLL circuit 7. . Thereby, each module of the chip 2 operates at a high speed by the multiplied clock signal.
FIG. 2 shows that the chip 2 (2) is switched to the Active state by, for example, the chip 2 (3) transmitting a Wake Up signal to the chip 2 (2). FIG. 3 shows that the Wake Up signal is transmitted to the chip 2 (1) and the chip 2 (1) is also switched to the active state. In this case, for example, the chip 2 (1), the chip High-speed communication is possible between 2 (2).

  As described above, according to the present embodiment, each chip 2 selectively supplies the multiplied clock signal and the reference clock signal by its own control and controls the operation of the PLL circuit 7 via the communication bus 1. Interface unit 5 for transmitting and receiving signals. In the sleep state, the interface unit 5 stops the operation of the PLL circuit 7, stops supplying power to the logic unit 3, supplies a reference clock signal to itself, and a wake-up signal transmitted from another chip 2. , The operation of the PLL circuit 7 is started and the multiplied clock signal is supplied to itself.

That is, since only the interface unit 5 to which the reference clock signal is supplied is operating in the chip 2 in the sleep state, power consumption can be sufficiently suppressed. When the interface unit 5 receives the activation signal Wake Up, the interface unit 5 starts the operation of the PLL circuit 7 and supplies the multiplied clock signal to itself, so that the logic unit 3 operates at high speed when performing normal communication. Can do. In addition, since it is not necessary to wire individual signal lines in order to activate only the chip 2 to be communicated, the number of wirings can be reduced.
In addition, when the interface unit 5 transmits a start signal to another chip 2 in the normal operation mode, the interface unit 5 has the same communication rate as that set by the reference clock signal in a state where the multiplied clock signal is supplied thereto. Send a start signal at the communication rate. Therefore, the activation signal can be transmitted at a low speed without switching the clock signal supplied to itself.

(Second embodiment)
FIG. 11 shows a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Hereinafter, different parts will be described. The second embodiment shows a case where the chip 2 in the Active state transmits a Wake Up signal to the chip 2 in the Sleep state by a method different from that in FIG. FIG. 11 is a flowchart showing the processing contents of the chip 2 in the active state.

  In FIG. 11, the logic unit 3 of the chip 2 in the active state stands by until a factor for transmitting a wake-up signal to another chip 2 is generated (step S11). When the factor occurs (YES), the multiplexer 9 is switched so as to supply the reference clock signal to the interface unit 5 (step S12), and a Wake Up signal is transmitted (step S13). Thereby, the Wake Up signal is transmitted at a low communication rate set by the reference clock signal. When the Wake Up signal is transmitted, the multiplexer 9 is switched to supply the multiplied clock signal to the interface unit 5 (step S14), and the process proceeds to step S11.

  As described above, according to the second embodiment, when the interface unit 5 transmits a wake-up signal to another node in the normal operation mode, the interface unit 5 switches to supply a reference clock signal to itself. A signal can be transmitted at a low communication rate. In this case, the entire chip 2 may be controlled so as to shift to the sleep state only during the processes of steps S12 and S13.

(Third embodiment)
FIGS. 12 and 13 show a third embodiment, and different portions from the first embodiment will be described. The third embodiment shows another processing example performed by the interface unit 5 when the chip 2 in the active state shifts to the sleep state. FIG. 12 schematically shows an internal configuration of the interface unit 5, which includes an interface core 11, an input buffer 12 (receiver), and an output buffer 13 (driver). The input buffer 12 receives a signal transmitted on the communication bus 1 and outputs it to the interface core 11. Then, the interface core 11 performs decoding, demodulation, serial / parallel conversion or the like on the received signal and outputs the signal to the CPU 3C or the like. The interface core 11 transmits the signal input from the CPU 3C or the like onto the communication bus 1 via the output buffer 13 when, for example, parallel / serial conversion, modulation, encoding or the like is performed.

FIG. 13 shows an example of the circuit configuration of the input buffer 12. A current source 14 whose current value is variable is connected to the power source, and the sources of P-channel MOSFETs 15 and 16 are connected to the current source 14. N-channel MOSFETs 17 and 18 are connected between the drains of the P-channel MOSFETs 15 and 16 and the ground. The gates of the N-channel MOSFETs 17 and 18 are connected to the drain of the N-channel MOSFET 17 and constitute a mirror pair.
The gate of the P-channel MOSFET 15 serves as the input terminal Vin of the input buffer 12, and the reference voltage Vref is applied to the gate of the P-channel MOSFET 16. The drain of the N-channel MOSFET 18 serves as the output terminal Vout of the input buffer 12.

  The interface core 11 is set so as to reduce the amount of power supply current supplied by the current source 14 when shifting to the Sleep state. Thereby, the input / output response speed (response sensitivity) of the input buffer 12 is reduced, and the power consumption in the input buffer 12 can be suppressed. That is, in the Sleep state, the input buffer 12 only needs to receive a Wake Up signal transmitted at a low communication rate, so there is no problem even if the sensitivity is lowered.

  In addition, by reducing the sensitivity of the input buffer 12 in this way, the probability that the chip 2 in the sleep state is erroneously activated under the influence of communication performed at a high-speed communication rate becomes lower. Furthermore, in order to prevent such malfunctions, the chip 2 (management node) having a function of managing the power supply of the entire system periodically transmits a sleep signal to the chip 2 that does not need to be activated. Is also possible. In addition, even when each chip 2 is in the active state, the presence / absence of a wake-up signal is monitored as in S5 in the first embodiment, and if a wake-up signal is not received for a predetermined period, it is automatically Alternatively, the sleep state may be entered.

  As described above, according to the third embodiment, the interface unit 5 reduces the input / output response speed of the input buffer 12 that receives a signal in the Sleep state. Specifically, the amount of power supply current supplied to the input buffer 12 is reduced. That is, since the inter-chip communication performed in the Sleep state is low speed, the input buffer 12 can be reduced in power consumption in the input buffer 12 because the input / output response speed of the input buffer 12 is reduced without causing any trouble in communication.

  In addition, as a management node with one of a plurality of chips 2 having a function of managing the entire system, the chip 2 periodically transmits a sleep signal to the chip 2 that does not need to be activated. For example, the chip 2 that is erroneously activated due to the influence of noise or the like can be shifted to the sleep state.

(Fourth embodiment)
FIG. 14 shows the fourth embodiment, and the differences from the first embodiment will be described. In the fourth embodiment, the reference clock circuit 6 is not mounted on each chip 2A, and only one reference clock circuit 21 for supplying a reference clock signal to each chip 2A is provided in the system. A reference clock signal is input to the PLL circuit 7 of each chip 2A via a reference clock line. Thereby, the size of the chip 2A can be reduced, and the operation of each chip 2A can be synchronized with a common reference clock signal.

(5th Example)
FIG. 15 shows a fifth embodiment, and the differences from the first embodiment will be described. In the fifth embodiment, the system is configured such that the two chips 2B (1) and 2B (2) are directly connected by the communication line 23 and communication is performed between them. Even in such a configuration, one of the chips 2B (1) and 2B (2) is given a function for managing the power supply of the entire system, and if necessary, a Wake Up signal is transmitted to the other to Move to Active state for communication. Note that the chip 2 having the power management function does not necessarily have to be always in an active state, for example, is always in a sleep state and is activated at regular intervals by a timer, or activated by an external signal input. Then, after performing necessary communication processing or the like, the sleep state may be changed again.

(Sixth embodiment)
FIG. 16 shows the sixth embodiment, and the differences from the first embodiment will be described. In the sixth embodiment, the chip 2 (1) shown in FIG. 1 is replaced with a chip 2C (1). In the chip 2C (1), the power supply unit 8 is disposed outside the chip 2C (1), and the interface unit 5 outputs a power cutoff signal to the external power supply unit 8 to control power supply to each unit. To do. The power supply control may be performed in the same manner as in the configuration example shown in FIG. Further, the chip 2 (2) may be configured in the same manner as the chip 2C (1) and may be the chip 2C (2). In the case of the sixth embodiment configured as described above, the same effect as that of the first embodiment can be obtained.

(Seventh embodiment)
FIG. 17 shows a seventh embodiment, and shows a state where the master right is transferred when performing communication between chips 2 (1) to 2 (5). Here, the master right is equivalent to the right to transmit the Wake Up signal, and the chip 2 having the master right can transmit the Wake Up signal to the other chips 2. In addition, although a method for giving the master right between the chips 2 is not particularly defined, basically any chip 2 can be a master.

  In the case of FIG. 17A, since the chip 2 (1) acquires the master right and starts the chips (3) and (4) (slave) which are the communication destinations and in the sleep state, An Up signal is being transmitted. In the case of FIG. 17B, the chip 2 (5) acquires the master right and transmits a wake-up signal to the chip (2) (slave) that is the communication destination and is in the sleep state.

  As described above, according to the seventh embodiment, the wake-up signal is transmitted by the chip 2 that has acquired the master right in communication, so it is not necessary to determine in advance which chip 2 transmits the wake-up signal. By acquiring the master right, the chip 2 that needs to start the chip 2 as the communication destination can transmit the Wake Up signal.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The wiring topology of each node is not particularly limited.
The command frame of the Wake Up signal shown in FIG. 9 is merely an example, and the frame configuration is not particularly limited.
A block having a function as a PMU may exist independently of the interface unit 5, and the interface unit 5 may give a command to the PMU to perform power control of each unit.
In the third embodiment, a low-speed input buffer with low power consumption may be provided separately, and switching to use the input buffer may be performed in the Sleep state.
The frequency difference between the reference clock signal and the multiplied clock signal may be set as appropriate according to the individual design.

  In the drawings, 1 is a communication bus (communication line), 2 is a chip (node), 3 is a logic unit (control unit), 5 is an interface unit (I / F), 6 is a reference clock circuit, and 7 is a PLL circuit (multiplication). Clock output means), 8 is a power supply unit, and 12 is an input buffer (receiver).

Claims (7)

In a communication network system in which a plurality of nodes configured to be able to transition to a normal operation mode and a low power consumption mode are connected by a communication line,
Each of the nodes
A multiplied clock output means for outputting a multiplied clock signal obtained by multiplying a reference clock signal;
A control unit that operates by being supplied with the multiplied clock signal and performs communication control;
An interface unit that selectively supplies the multiplied clock signal and the reference clock signal by its own control, controls the operation of the multiplied clock output means, and transmits and receives signals via the communication line;
A power supply unit configured to be capable of stopping the supply of power to the control unit,
The interface unit is
In the low power consumption mode, the operation of the multiplied clock output means is stopped, the supply of power to the control unit is stopped, and the reference clock signal is supplied to itself.
When a start signal transmitted from another node is received, the operation of the multiplied clock output means is started and the multiplied clock signal is supplied to itself.   The communication network system according to claim 1, wherein the interface unit reduces an input / output response speed or a response sensitivity of a receiver that receives the signal in the low power consumption mode.   The communication network system according to claim 2, wherein the interface unit reduces the amount of power supply current supplied to the receiver.   4. The node according to claim 1, wherein when the start signal is transmitted to another node in the normal operation mode, the node switches to supply the reference clock signal to the interface unit. The communication network system according to any one of the above.   When the interface unit transmits the activation signal to another node in the normal operation mode, the interface unit has the same communication rate set by the reference clock signal in a state where the multiplied clock signal is supplied to the node. The communication network system according to claim 1, wherein the activation signal is transmitted at a communication rate of 5. One of the nodes is a management node having a function of managing the entire system,
6. The communication network system according to claim 1, wherein the management node periodically transmits a signal for shifting to the low power consumption mode to a node that does not need to be activated.   The communication network system according to claim 1, wherein the activation signal is transmitted by a node that has acquired a master right in communication.

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