JP2013055586A - Interface circuit for aisg device and aisg device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit for AISG device and AISG device, capable of properly executing communication even when a DC return voltage rises due to a voltage drop in a control cable.SOLUTION: The present invention comprises an input connector 2 and an output connector 3 in compliance with AISG standards, and a voltage shift circuit 8 that boosts a control signal input from the input connector 2 at a fixed voltage before output.

Description

  The present invention relates to an interface circuit for an AISG device and an AISG device mounted on an AISG device compliant with the AISG (Antenna Interface Standards Group) standard.

  In mobile radio base stations, antenna tilt control can generally be performed by remote control. Initially, each manufacturer used a unique method as an antenna control method. However, in recent LTE (Long Term Evolution) radio base stations and the like, antenna control is often performed according to the AISG standard. The AISG standard is a standard standardized to ensure basic interoperability of antennas (see, for example, Patent Document 1).

  As shown in FIG. 20A, an antenna control system 201 that controls an antenna in accordance with the AISG standard includes a RET (Remote Electrical Tilt) unit that controls an antenna (not shown) of a radio base station. An AISG device (AISG terminal device) 202 and a control device (RS485 standard signal) is transmitted to the AISG device 202 to control the antenna by controlling the AISG device 202 and supply power to the AISG device 202 ( An AISG control device) 203, and a control cable (AISG control cable) 204 for connecting the control device 203 and the AISG device 202. Although not shown, the control cable 204 includes a control signal line for transmitting a control signal and a power supply line for supplying power.

  As shown in FIG. 20B, the AISG device 202 includes an input connector (male connector) 2 and an output connector (female connector) 3 conforming to the AISG standard. Corresponding pin terminals of both connectors 2 and 3 are electrically connected by input / output connector connection lines (power supply line 4 and control signal transmission line 5). Accordingly, as shown in FIG. 21, a plurality of AISG devices 202 can be cascade-connected by daisy chain connection using the control cable 204 provided with male connectors 204a and female connectors 204b compliant with AISG standards at both ends. It has become.

  Pin terminal numbers (pin numbers) of connectors 2 and 3 compliant with the AISG standard, signals propagated at each pin terminal (Signal), requirements for mandatory connection (Mandatory) or optional connection (Optional) (Requirement) ) Is shown in Table 1.

  As shown in Table 1, in the AISG standard, there are three types of power lines: + 12V for No. 2, -48V for No. 2, and 10-30V for No. 6, and + 12V and -48V power lines can be connected arbitrarily. , 10-30V power line is essential connection. In Table 1, No. 8 NC means no connection.

  FIG. 20B shows, as an example, a case where the AISG device 202 uses a 10 to 30 V power source that is essential connection. In this case, the 10-30V power supply line 4a for connecting the 6th pin terminals between the connectors 2 and 3 and the DC return line 4b for connecting the 7th pin terminals as the power supply line 4 serve as the AISG device. A power circuit (not shown) of the internal circuit 6 202 is electrically connected.

  A line (RS485A line and RS485B line) connecting the third and fifth pin terminals between the connectors 2 and 3 is a control signal transmission line 5 and a control signal transceiver (in the internal circuit 6 of the AISG device 202). RS485 transceiver) 7 is electrically connected. As a result, the control signal input from the control device 203 via the input connector 2 is input to the control signal transceiver 7 through the control signal transmission line 5.

  As shown in FIG. 22, the control signal transceiver 7 includes a non-inverting input / output terminal A, an inverting input / output terminal B, a receiver output terminal RO, a receiver output enable terminal RE, a driver input terminal DI, a driver output enable terminal DE, a positive This is a general differential signal transceiver having a power input terminal Vcc and a reference power input terminal GND. The non-inverting input / output terminal A and the inverting input / output terminal B are electrically connected to the control signal transmission line 5, the positive power input terminal Vcc is electrically connected to the positive power source, and the reference power input terminal GND is electrically connected to the DC return. The other terminals RO, RE, DI, DE are electrically connected to an appropriate control circuit of the internal circuit 6 or the like.

  From the receiver output terminal RO, the difference between the signal (RS485A) input from the non-inverting input / output terminal A and the signal (RS485B) input from the inverting input / output terminal B is output. A signal input from the driver input terminal DI is output from both the input / output terminals A and B. A signal that is not inverted from the non-inverted input / output terminal A is inverted from the inverted input / output terminal B. Is output.

Special table 2010-519844 gazette

  By the way, since a power supply current flows through the power supply line of the control cable 204 (here, the 10-30V power supply line and the DC return power supply line), a voltage drop occurs due to the conductor resistance component of the control cable 204.

When the conductor resistance per unit length of the power line of the control cable 204 is R ₀ and the cable transmission distance (cable length of the control cable 204) is L, the conductor resistance component of the power line is R ₀ · L. The control system 201 can be represented by an equivalent circuit as shown in FIG. Assuming that the power supply current is I ₀ , a voltage drop of I ₀ · R ₀ · L occurs in the control cable 204.

When outputting a voltage V ₀ by the control unit 203, but will output a voltage V ₀ from the power supply output terminal 203a of the voltage of the DC return output terminal 203b as a reference (0V), the power input of the AISG device 202 The voltage V ₁ input to the terminal (here, the 6th pin terminal of the input connector 2) 202a is expressed by the following equation (1) due to the voltage drop in the control cable 204.
V ₁ = V ₀ −I ₀ · R ₀ · L (1)
It becomes. Similarly, the voltage V ₂ (referred to as DC return voltage) V ₂ of the DC return input terminal (the 7th pin terminal of the input connector 2) 202b of the AISG device 202 rises above 0V, and the following equation (2)
V ₂ = I ₀ · R ₀ · L (2)
It becomes.

From formula (2), when the cable transmission distance L of the control cable 204 becomes long or the positive power supply system AISG device 202 is connected in multiple stages, the power consumption becomes large (the power supply current I ₀ becomes large). It can be seen that the DC return voltage V ₂ increases at.

On the other hand, since the current flowing through the control signal line for transmitting the control signal is very small, the control signal reaches the AISG device 202 at substantially the same voltage as the voltage output from the control device 203. As a result, when the DC return voltage V ₂ is used as a reference, the voltage of the control signal becomes relatively low.

The control signal transceiver 7 is driven by a power source supplied from the control device 203, similarly to the other internal circuits 6 of the AISG device 202. That is, the control signal transceiver 7 uses the DC return voltage V ₂ as a reference voltage. The voltage range that can be received by the normal control signal transceiver 7 is limited to about -7V to + 12V with respect to the reference voltage.

Therefore, as shown in FIG. 24, when the cable transmission distance L is increased, the DC return voltage V ₂ is increased, and the voltage of the control signal received by the control signal transceiver 7 is relatively decreased accordingly, the control is performed. If the signal falls outside the voltage range that can be received by the control signal transceiver 7 (the range indicated by hatching in FIG. 24), it becomes difficult to identify the control signal, and normal communication may not be possible. In FIG. 24, the high level signal voltage of the control signal is shown as V _H , and the low level signal voltage is shown as V _L. However, in this example, when the cable transmission distance L becomes larger than L ₀ , the low level signal voltage V _L is The lower limit voltage that can be received by the control signal transceiver 7 falls below, and normal communication cannot be performed.

  The present invention has been made in view of the above circumstances, and provides an interface circuit for an AISG device and an AISG device that can perform normal communication even when a DC return voltage increases due to a voltage drop in a control cable. The purpose is to do.

  The present invention was devised to achieve the above object, and includes an input connector and an output connector compliant with the AISG standard, and a voltage shift circuit for boosting a control signal input from the input connector by a constant voltage and outputting it. And an interface circuit for an AISG device.

  A control signal transceiver for transmitting and receiving control signals is mounted on an AISG device that controls an antenna in accordance with the AISG standard, and the voltage shift circuit is connected to the control signal transceiver and the input connector. The control signal input from the input connector is stepped up by a constant voltage and output to the control signal transceiver, and the control signal input from the control signal transceiver is stepped down by a constant voltage to the input connector. You may comprise so that it may output.

  The shift voltage boosted by the voltage shift circuit is such that the voltage of the control signal after boosting when the control signal input from the input connector is boosted is within a voltage range that the control signal transceiver can receive. May be set.

  The input connector is connected to a controller that transmits a control signal to the AISG device, controls the AISG device to control the antenna, and transmits a power signal to the AISG device, and The shift voltage stepped down by the shift circuit may be set so that the control device can receive the voltage of the control signal after stepping down when the control signal input from the control signal transceiver is stepped down. .

  A minimum voltage detection circuit for detecting a minimum voltage of the control signal input from the input connector and determining whether the detected minimum voltage is within a voltage range receivable by the control signal transceiver; and the minimum voltage detection When the circuit determines that the minimum voltage of the control signal is not within a voltage range that can be received by the control signal transceiver, the voltage shift circuit is inserted into a control signal transmission line between the control signal transceiver and the input connector. When it is determined that the minimum voltage of the control signal is within a voltage range that can be received by the control signal transceiver, the voltage shift circuit is not inserted into the control signal transmission line between the control signal transceiver and the input connector. And a switching circuit for switching as described above.

  The voltage shift circuit includes a Zener diode or a plurality of diodes connected in series, and a control signal input from the input connector is a constant voltage by a Zener voltage by the Zener diode or a forward voltage drop by the plurality of diodes. The voltage may be boosted and output.

  The voltage shift circuit is provided in a control signal transmission line between the input connector and the output connector, and the control signal input from the input connector is boosted by a constant voltage and output to the output connector, and input from the output connector. The control signal may be configured to be stepped down by a constant voltage and output to the input connector.

  A surge protection circuit for protecting the internal circuit from a surge voltage generated outside may be further provided.

  You may further provide the common mode noise removal filter which removes the common mode noise of a control signal.

  The present invention also provides an AISG device equipped with the AISG device interface circuit.

  According to the present invention, normal communication can be performed even if the DC return input terminal voltage rises due to a voltage drop in the control cable.

(A) is a schematic block diagram of the AISG device which mounts the interface circuit for AISG devices which concerns on one embodiment of this invention, (b) is a circuit block diagram of the voltage shift circuit and the transceiver for control signals. is there. It is a figure for demonstrating how the shift voltage Es of a voltage shift circuit is set in this invention. It is a figure for demonstrating how the shift voltage Es of a voltage shift circuit is set in this invention. In this invention, it is a figure which shows the relationship of the allowable range of the shift voltage Es with respect to the maximum value (maximum Eu) of the raise voltage Eu of DC return voltage. (A) is a circuit block diagram which shows an example of the voltage shift circuit used for the interface circuit for AISG devices of FIG. 1, (b) is when a resistor is used for a constant current source, (c) is a constant current source. It is a circuit block diagram at the time of using a current mirror circuit. (A) is a diagram showing a simulation circuit simulating a voltage shift circuit of FIG. 5 (b), (b), the simulation result of the output voltage V _out to the input voltage V _in determined by using the simulation circuit is a diagram showing a (c) the simulation results of the current I ₀ to the input voltage V _in. (A), the output voltage V _out to the input voltage V _in determined using a simulation circuit simulating a voltage shift circuit shown in FIG. 5 (c) simulation, (b) the current I ₀ to the input voltage V _in It is a figure which shows a simulation result. (A) is a circuit block diagram which shows an example of the voltage shift circuit used for the interface circuit for AISG devices of FIG. 1, (b) is when a resistor is used for a constant current source, (c) is a constant current source. It is a circuit block diagram at the time of using a current mirror circuit. (A) is a circuit block diagram which shows an example of the voltage shift circuit used for the interface circuit for AISG devices of FIG. 1, (b) is when a resistor is used for a constant current source, (c) is a constant current source. It is a circuit block diagram at the time of using a current mirror circuit. (A) is a circuit block diagram which shows an example of the voltage shift circuit used for the interface circuit for AISG devices of FIG. 1, (b) is a circuit block diagram at the time of using resistance for a constant current source. It is a schematic block diagram of the AISG device carrying the interface circuit for AISG devices which concerns on other embodiment of this invention. It is a schematic block diagram of the AISG device which concerns on other embodiment of this invention. (A), (b) is a schematic block diagram of the AISG device which concerns on other embodiment of this invention. (A), (b) is a circuit block diagram which shows an example of the voltage shift circuit suitable for the AISG device of FIG.13 (b). It is a circuit block diagram which shows an example of the voltage shift circuit suitable for the AISG device of FIG.13 (b). (A), (b) is a schematic block diagram of the interface circuit for AISG devices which concerns on other embodiment of this invention. It is a circuit block diagram which shows an example of the minimum voltage detection circuit used for the interface circuit for AISG devices of FIG. In this invention, it is a circuit block diagram which shows an example of the voltage shift circuit incorporating the switching apparatus. (A)-(c) is a schematic block diagram of the interface circuit for AISG devices which concerns on other embodiment of this invention. (A) is a schematic block diagram of a general antenna control system, (b) is a schematic block diagram of the conventional AISG device. It is a figure explaining that an AISG device is daisy chain connectable. It is a circuit block diagram of a general transceiver for control signals. It is a figure which shows the equivalent circuit of the antenna control system of Fig.20 (a). In the antenna control system of FIG. 20A, when the cable transmission distance becomes long, the DC return voltage increases and normal communication cannot be performed.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a schematic configuration diagram of an AISG device equipped with an AISG device interface circuit according to the present embodiment, and FIG. 1B is a circuit configuration diagram of a voltage shift circuit and a control signal transceiver.

  As shown in FIG. 1A, an AISG device 10 includes an AISG device interface circuit (hereinafter simply referred to as an interface circuit) 1 according to the present invention. The AISG device 10 is, for example, a RET unit, and includes a control signal transceiver (RS485 transceiver) 7 that transmits and receives control signals in an internal circuit 6 and controls an antenna in accordance with the AISG standard.

  The interface circuit 1 according to the present embodiment includes an input connector 2 and an output connector 3 compliant with the AISG standard, and a voltage shift circuit (RS485 signal voltage shift circuit) 8. A control device that transmits a control signal to the AISG device 10 via a control cable (not shown), controls the AISG device 10 to control the antenna, and transmits a power supply signal to the AISG device 10. (Not shown) are connected.

  Corresponding pin terminals of both connectors 2 and 3 are electrically connected by input / output connector connection lines (power supply line 4 and control signal transmission line 5).

  In FIG. 1A, as an example, the case where the AISG device 10 uses an essential connection of 10 to 30 V power source is shown. In this case, the 10-30V power supply line 4a for connecting the 6th pin terminals between the connectors 2 and 3 and the DC return line 4b for connecting the 7th pin terminals as the power supply line 4 serve as the AISG device. 10 are electrically connected to a power supply circuit (not shown) of the internal circuit 6.

  A line (RS485A line and RS485B line) connecting the third and fifth pin terminals between the connectors 2 and 3 is a control signal transmission line 5 and a control signal transceiver 7 of the internal circuit 6 of the AISG device 10. Is electrically connected.

  The voltage shift circuit 8 boosts the control signal input from the input connector 2 by a predetermined voltage and outputs it, and is provided in the control signal transmission line 5 between the control signal transceiver 7 and the input connector 2. Here, the voltage shift circuit 8 is provided on the control signal transmission line 5 that branches from the line connecting the third and fifth pin terminals of the input connector 2 and the output connector 3 and extends to the control signal transceiver 7.

As shown in FIG. 1B, the voltage shift circuit 8 includes two DC constant voltage sources B1 and B2 provided on the RS485A line and the RS485B line of the control signal transmission line 5, respectively. The power supply voltages E _B1 and E _B2 of the DC constant voltage sources B1 and B2 are set to be equal to the desired shift voltage Es.

  More specifically, the voltage shift circuit 8 includes low-voltage input / output terminals 11a and 11b and high-voltage input / output terminals 12a and 12b. The low-voltage input / output terminal 11a and the high-voltage input / output terminal 12a Are electrically connected via the DC constant voltage source B1, and the low voltage side input / output terminal 11b and the high voltage side input / output terminal 12b are electrically connected via the DC constant voltage source B2. The RS485A line of the control signal transmission line 5 on the input connector 2 side is electrically connected to the low-voltage input / output terminal 11a, and the RS485B line is electrically connected to the low-voltage input / output terminal 11b. The high-voltage input / output terminals 12a and 12b are electrically connected to the input / output terminals A and B of the control signal transceiver 7 via the RS485A and RS485B lines of the control signal transmission line 5, respectively.

  As a result, the control signals (RS485A, RS485B) input from the input connector 2 are boosted by a constant voltage (desired shift voltage Es) by the voltage shift circuit 8, and the control signal after the boosting (RS485A after voltage shift, voltage shift). RS485B) is input to the input / output terminals A and B of the control signal transceiver 7. The signals output from the input / output terminals A and B of the control signal transceiver 7 are stepped down by a constant voltage (desired shift voltage Es) by the voltage shift circuit 8, and the control signal after the step-down is input to the input connector 2 and the output. It is output to the connector 3.

  The shift voltage Es boosted or lowered by the voltage shift circuit 8 is within a voltage range in which the control signal transceiver 7 can receive the boosted control signal voltage when boosting the control signal input from the input connector 2. Is set to be

  Further, the shift voltage Es stepped up or stepped down by the voltage shift circuit 8 is such that the control device can receive the voltage of the control signal after stepping down when the control signal input from the control signal transceiver 7 is stepped down. (That is, within a voltage range within which the control signal transceiver mounted on the control device can receive).

  Here, a specific setting example of the shift voltage Es will be described.

The rising voltage Eu of the DC return voltage V ₂ from the output portion of the control device to the AISG device 10 (which is equal to the DC return voltage V ₂ because the DC return voltage at the output portion of the control device is 0 V) is Since it is equal to the voltage drop due to the conductor resistance component of the control cables connecting between the AISG devices 10, it increases as the cable transmission distance L increases as shown in FIG.

  Assuming that a general control signal transceiver that can be received in the range of −7 V to +12 V with respect to the reference voltage is used as the control signal transceiver 7, the voltage range that can be received by the control signal transceiver 7 is shown in FIG. The range is indicated by hatching.

Since the high-level signal voltage V _H and the low-level signal voltage V _L of the control signal have almost no voltage drop in the control cable, as shown by a broken line in FIG. Become.

When a 10-30V power supply is used, a maximum power supply voltage of 30V is supplied. Therefore, according to the principle of maximum power supply, the cable transmission distance L at which the supplied voltage is 15V, which is 1/2 of the power supply voltage, is the maximum transmission distance. It becomes. The rising voltage Eu of the DC return voltage V ₂ at this time is 7.5V, which is 1/2 of 15V. That is, the DC return voltage V ₂ may increase by about 7.5V. Note that a low-power AISG device may be connected even with a DC return voltage V ₂ higher than this.

On the other hand, since the low level signal voltage V _L of the control signal is about 0 to 0.2V, if Eu> 7V, the low level signal voltage V _{L based on} the DC return voltage V ₂ (that is, V _L− Eu) becomes smaller than −7V and is out of the voltage range that can be received by the control signal transceiver 7, so that normal communication cannot be performed.

Therefore, in order to receive voltage range at the low-level signal voltage V _L of the control signal transceiver 7 relative to the DC return voltage V ₂ is the shift voltage Es so that V _L -Eu + Es ≧ -7V Must be set. For example, if Eu ≦ 7.5V, Es ≧ 0.5V, and if Eu ≦ 10V, Es ≧ 3V.

On the other hand, in order to set the high level signal voltage V _H with reference to the DC return voltage V ₂ as a voltage range that can be received by the control signal transceiver 7, the shift voltage Es is set so that V _H −Eu + Es ≦ 12. There is a need to. Since the high-level signal voltage V _H is about 2 to 5 V, Es ≦ 7 V needs to be set to enable reception even when Eu = 0 V (cable transmission distance L is 0).

  Furthermore, since the control signal output from the control signal transceiver 7 is stepped down by the shift voltage Es and output from the AISG device 10, the shift voltage Es is set so that the control signal after the step-down can be received by the control device. Must be set.

As shown in FIG. 3, since the control signal transceiver 7 of the AISG device 10 outputs the high level signal voltage V _H and the low level signal voltage V _L with reference to the DC return voltage V ₂ , the voltage shift circuit 8 The voltage after the voltage shift at, that is, the voltage when output from the AISG device 10 is Eu + V _H −Es, Eu + V _L −Es. Therefore, for example, if a general control signal transceiver that can receive signals in the range of −7 V to +12 V with respect to the reference voltage is mounted on the control device, Eu + V _L −Es ≧ −7 V, Eu + V _H −Es ≦ It is necessary to make it 12V.

  From the above, when a general control signal transceiver that can receive signals in the range of −7 V to +12 V with respect to the reference voltage is used for both the AISG device 10 and the control device, if Eu ≦ 10 V, 3 V ≦ Es. If the shift voltage Es is set so that 0.5V ≦ Es ≦ 7V when ≦ 7V and Eu ≦ 7.5V, normal communication is possible.

In other words, when 3V ≦ Es ≦ 7V when the range increases voltage Eu of the DC return voltage V ₂ is 0 to 10V, increase the voltage Eu of the DC return voltage V ₂ is in the range of 0~7.5V 0. If 5V ≦ Es ≦ 7V, the input signal voltage to the control signal transceiver is within the receivable voltage range in both the AISG device 10 and the control device, and normal communication is possible. The relationship between the allowable range of the shift voltage Es and the maximum value (maximum Eu) of the rising voltage Eu of the DC return voltage V ₂ is as shown in FIG.

  Next, the circuit configuration of the voltage shift circuit 8 will be specifically described.

  A voltage shift circuit 8a shown in FIG. 5A includes Zener diodes ZD1 and ZD2, and is configured to perform voltage shift by a Zener voltage by the Zener diodes ZD1 and ZD2.

  The Zener diode ZD1 is provided between the low voltage side input / output terminal 11a and the high voltage side input / output terminal 12a, and is provided such that the anode is on the low voltage side input / output terminal 11a side and the cathode is on the high voltage side input / output terminal 12a side. The cathode of the Zener diode ZD1 is electrically connected to the positive power supply terminal 13 via the constant current source CS1.

  Similarly, the Zener diode ZD2 is provided between the low voltage side input / output terminal 11b and the high voltage side input / output terminal 12b, and is provided such that the anode is on the low voltage side input / output terminal 11b side and the cathode is on the high voltage side input / output terminal 12b side. It is done. The cathode of the Zener diode ZD2 is electrically connected to the positive power supply terminal 13 through the constant current source CS2.

As the zener diodes ZD1 and ZD2, those having the same zener voltages V _ZD1 and V _ZD2 are used. Also, constant current sources CS1 and CS2 are used whose current values I _CS1 and I _CS2 are equal to each other.

In this voltage shift circuit 8a, the control signals input from the low voltage side input / output terminals 11a and 11b are boosted to a voltage equal to the zener voltages V _ZD1 and V _ZD2 of the zener diodes ZD1 and ZD2, and the high voltage side input / output terminals 12a and 12b. Is output from. The control signals input from the high-voltage side input / output terminals 12a and 12b are stepped down to a voltage equal to the Zener voltages V _ZD1 and V _ZD2 of the Zener diodes ZD1 and ZD2, and are output from the low-voltage side input / output terminals 11a and 11b. The Zener voltages V _ZD1 and V _ZD2 of the Zener diodes ZD1 and ZD2 are set equal to the desired shift voltage Es.

  The specific circuit configuration of the constant current sources CS1 and CS2 is not particularly limited. For example, as shown in FIG. 5B, the constant current sources CS1 and CS2 are formed by resistors R1 and R2 (R1 = R2). May be configured.

  Further, as shown in FIG. 5C, the constant current sources CS1 and CS2 may be configured by a current mirror circuit in which resistors R1 to R4 and transistors Q1 to Q3 are combined. The collector terminals of the transistors Q1 to Q3 are electrically connected to the positive power supply terminal 13 via the resistors R1 to R3, respectively. The base terminals of the transistors Q1 to Q3 are electrically connected to each other, and the emitter of the transistor Q1. Electrically connected to the terminal. The emitter terminals of the transistors Q2 and Q3 are electrically connected to the cathodes of the Zener diodes ZD1 and ZD2, and the emitter terminal of the transistor Q1 is electrically connected to the negative power supply terminal 14 via the resistor R4. The negative power supply terminal 14 is electrically connected to a DC return or a negative power supply. In the voltage shift circuit 8a of FIG. 5C, R1 = R2 = R3, and the PNP transistors of the same type are used as the transistors Q1 to Q3.

A simulation circuit as shown in FIG. 6A simulating the voltage shift circuit 8a in FIG. 5B is created, the resistance R1 is 100 kΩ, the Zener voltage V _ZD1 of the Zener diode _ZD1 is 4.7 V, and the positive power supply V _0. was 5V, 10V, 15V, and 20V, the simulation when changing the input voltage V _in from the low voltage side output terminal 11a at the range of -10V～10V, the output voltage V _out from the high pressure side output terminal 12a Determined by The results are shown in FIG. Further, the current I ₀ flowing through the Zener diode ZD1 at this time is shown in FIG.

As shown in FIG. 6 (b), the shift voltage Es of the output voltage V _out to the input voltage V _in is on the order of about 4V, and has a Zener voltage V _ZD1 of Zener diode ZD1 substantially equal shift voltage Es I understand that. Further, in the case where the positive power source V ₀ 5V, and 10V, when the input voltage V _in is high, it can be seen that no normal operation can be obtained. This input voltage V _in increases, when it comes to V _in ≧ V ₀ -V _ZD1, the voltage applied to the Zener diode ZD1 is a Zener voltage V _ZD1 following are the Zener diode ZD1 to malfunction . That is, _in order to obtain a normal operation in the voltage shift circuit 8a, it is necessary to _satisfy V _in <V ₀ −V _ZD1 .

As shown in FIG. 6C, the current I ₀ becomes smaller as the input voltage V _in becomes higher, and a region where V _in > V ₀ (region where V _in > 5V when V ₀ = 5V). ) Shows that the sign is reversed and the current flows backward.

Similarly, a simulation circuit simulating the voltage shift circuit 8a of FIG. 5C is created, and simulation is performed with R1 = R2 = R3 = 20 kΩ, R4 = 200 kΩ, V _ZD1 = V _ZD2 = 4.7 V, and the reference potential is 0 V. Went. The results are shown in FIGS. 7 (a) and (b).

As shown in FIGS. 7A and 7B, in the voltage shift circuit 8a of FIG. 5C, the current I ₀ is substantially constant in the region of V _in <V ₀ −V _ZD1 . although different from the voltage shift circuit 8a in b), in the region of V _in <V ₀ -V _ZD1, shift voltage Es of the output voltage V _out to the input voltage V _in are on the order of about 4V, the Zener diode ZD1 It can be seen that the shift voltage Es is substantially equal to the Zener voltage V _ZD1 (= V _ZD2 ).

  Next, another example of the voltage shift circuit 8 will be described.

  The voltage shift circuit 8b shown in FIG. 8A includes a backflow prevention diode D1, between the low-voltage input / output terminals 11a and 11b and the Zener diodes ZD1 and ZD2 in the voltage shift circuit 8a shown in FIG. D2 is provided. The voltage shift circuit 8b shown in FIG. 8B is obtained by configuring the constant current sources CS1 and CS2 with resistors R1 and R2 in the voltage shift circuit 8b shown in FIG. 8A. The voltage shift circuit 8b shown in FIG. The shift circuit 8b includes constant current sources CS1 and CS2 constituted by a current mirror circuit. By providing the backflow prevention diodes D1 and D2, it is possible to prevent the backflow of the current even when the input voltage is higher than the positive power supply.

In the voltage shift circuit 8c shown in FIG. 9A, in the voltage shift circuit 8a shown in FIG. 5A, the anodes of the Zener diodes ZD1 and ZD2 are connected to the negative power supply terminal 14 through the constant current sources CS3 and CS4, respectively. It is comprised so that it may do. The current values I _{CS1 to} I _CS4 of the constant current sources _{CS1 to CS4} are made equal to each other.

  The voltage shift circuit 8c in FIG. 9B is configured by the constant current sources CS1 to CS4 by resistors R1 to R4 having the same resistance value. The voltage shift circuit 8c in FIG. 9C is formed by a current mirror circuit. The constant current sources CS1 to CS4 are configured. In the voltage shift circuit 8c of FIG. 9C, R1 = R2 = R3, R5 = R6 = R7, the same type of PNP transistor is used as the transistors Q1 to Q3, and the same type of NPN transistor is used as the transistors Q4 to Q6. A circuit configuration using both a resistor and a current mirror circuit is also possible, for example, the constant current sources CS1 and CS2 are configured by current mirror circuits, and the constant current sources CS3 and CS4 are configured by resistors.

  In the voltage shift circuit 8a of FIG. 5, the high-voltage side input / output terminals 12a and 12b are opened when no control signal is input, but in the voltage shift circuit 8c of FIG. 9, the zener diodes ZD1 and ZD2 Since the anode is grounded (or connected to a negative power supply), the high voltage side input / output terminals 12a and 12b are not opened.

Voltage shift circuit 8d shown in FIG. 10 (a), the voltage shift circuit 8c of FIG. 9 (a), in place of the Zener diode ZD1, ZD2, a plurality of diodes D ₁₁ to D _1n connected in series, D ₂₁ ~ D _2n is provided, and a voltage shift is performed by a forward voltage drop caused by a plurality of diodes D _{11 to} D _1n and D _{21 to} D _2n . In FIG. 10B, constant current sources CS1 to CS4 are configured by resistors R1 to R4 having the same resistance value. Although not shown, it is of course possible to configure the constant current sources CS1 to CS4 with current mirror circuits.

  The operation of the present embodiment will be described.

  The interface circuit 1 according to the present embodiment includes a voltage shift circuit 8 that boosts and outputs a control signal input from the input connector 2 by a constant voltage.

By providing the voltage shift circuit 8, the DC return voltage V ₂ rises due to a voltage drop in the control cable, and the voltage of the control signal input to the AISG device 10 falls within a voltage range that the control signal transceiver 7 can receive. Even if it is lower, the control signal can be boosted to a voltage range that can be received by the control signal transceiver 7 to perform normal communication.

For example, when the control signal transceiver 7 can receive a voltage range of −7 V to +12 V and uses a 10 to 30 V power supply, if the rising voltage Eu of the DC return voltage V ₂ is 10 V or less, the shift voltage By setting Es to 3V to 7V, normal transmission / reception of control signals becomes possible.

  Next, another embodiment of the present invention will be described.

  An AISG device 110 shown in FIG. 11 has an interface circuit 111 mounted thereon.

  The interface circuit 111 includes a voltage shift circuit 8 in the control signal transmission line 5 between the input connector 2 and the output connector 3 in the interface circuit 1 of FIG. 1, and boosts the control signal input from the input connector 2 by a constant voltage. The control signal input from the output connector 3 is stepped down by a constant voltage and output to the input connector 2. In the interface circuit 111, the third and fifth pin terminals of the connectors 2 and 3 are not electrically connected to each other.

  According to the interface circuit 111, since the control signal boosted by the voltage shift circuit 8 can be output to the AISG device connected to the output connector 3 in a daisy chain, the AISG device connected to the subsequent stage is the interface of the present invention. Even a general AISG device that does not include the circuits 1 and 111 can perform normal communication with the AISG device.

  An AISG device 120 shown in FIG. 12 is obtained by omitting the internal circuit 6 from the AISG device 10 shown in FIG. That is, the AISG device 120 is a device in which the interface circuit 1 is made alone. By providing the AISG device 120 in the front stage of a general AISG device, it is possible to perform normal communication with the subsequent general AISG device.

  An AISG device 130 shown in FIG. 13 is the same as the AISG device 120 shown in FIG. 12, but includes a distributor (AISG signal distributor) 132 having three output connectors 131 in the same housing. Although a case where the distributor 132 is built in is shown here, the present invention is not limited to this, and an arrester or the like can be provided in the same housing.

  FIG. 13A shows a case where the power supply input from the input connector 2 is converted by the power supply circuit (DC / DC converter) 133 and then input to the voltage shift circuit 8 to be used as a positive power supply for the voltage shift circuit 8. FIG. 13B shows a case where the power supply input from the input connector 2 is directly input to the voltage shift circuit 8 and used as a positive power supply for the voltage shift circuit 8.

  When the power input from the input connector 2 is input as it is to the voltage shift circuit 8 as shown in FIG. 13B, the voltage input as the positive power supply is a constant voltage as in the voltage shift circuit 8e shown in FIG. A device provided with the voltage drop means 141 for dropping may be used as the voltage shift circuit 8. FIG. 14A shows a case where a common Zener diode ZD3 as the voltage drop means 141 is provided between the resistors R1 and R2 and the positive power supply terminal 13, and FIG. 14B shows the resistors R1 and R2. In this example, Zener diodes ZD3 and ZD4 as voltage drop means 141 are individually provided between Zener diodes ZD1 and ZD2. The voltage drop means 141 is not limited to a Zener diode. FIG. 14 shows a case where the voltage drop means 141 is provided in the voltage shift circuit 8a of FIG. 5B as an example, but the present invention is not limited to this.

  Further, as in the voltage shift circuit 8f shown in FIG. 15, a Zener diode ZD3 as a voltage limiting element is provided between the positive power supply terminal 13 and the negative power supply terminal 14, and a constant voltage is provided between the positive power supply terminal 13 and the negative power supply terminal 14. You may comprise so that it may become. The resistor R5 is for suppressing the current flowing through the Zener diode ZD3. FIG. 15 shows, as an example, a case where the Zener diode ZD3 is provided in the voltage shift circuit 8b of FIG. 8C, but is not limited thereto. In the voltage shift circuit 8f, the Zener diode ZD3 can reduce the change in the current value of the constant current source due to the change in the voltage of the positive power supply. Therefore, the voltage shift circuit 8f is preferably used even when the voltage of the positive power supply is not stable. Can do.

  The interface circuit 161 shown in FIG. 16 further includes a minimum voltage detection circuit (RS485 signal minimum voltage detection circuit) 162 and a switching circuit 163 in the interface circuit 1 of FIG. In FIG. 16, for the sake of simplification, the output connector 3, the power supply line 4, and the input / output connector connection lines connecting the connectors 2 and 3 are omitted.

The minimum voltage detection circuit 162 detects the minimum voltage (that is, the low level signal voltage V _L ) of the control signal input from the input connector 2, and the detected minimum voltage is a voltage range that can be received by the control signal transceiver 7. It is a circuit that determines whether or not it is inside. In the present embodiment, the minimum voltage detection circuit 162 outputs a switching control signal to the switching circuit 163 when determining that the detected minimum voltage is not within the voltage range that can be received by the control signal transceiver 7. Composed.

  An example of a specific circuit configuration of the minimum voltage detection circuit 162 is shown in FIG. In the lowest voltage detection circuit 162 in FIG. 17, the inverting amplifier circuits 173 and 174 are connected to the input terminals 171 and 172 to which the control signals RS485A and RS485B are input, the control signal is inverted, and the inverting amplifier circuits 173 and 174 are connected. Is output to the peak hold circuit 175, the maximum voltage is detected, and the detected maximum voltage is compared with the reference voltage by the comparator 176. If the detected voltage is larger than the reference voltage (that is, the minimum voltage of the control signal is smaller than the predetermined value). In this case, a high level signal is output from the output terminal 177 as the switching control signal.

  The inverting amplifier circuit 173 electrically connects the input terminal 171 and the inverting input terminal of the operational amplifier OP1 through the resistor R21, and grounds the non-inverting input terminal of the operational amplifier OP1 (connected to the DC return). The inverting input terminal and output terminal of OP1 are electrically connected via a resistor R22. The same applies to the inverting amplifier circuit 174. The configuration of the inverting amplifier circuits 173 and 174 is not limited to this.

  The peak hold circuit 175 has diodes D1 and D2 whose anodes are electrically connected to the outputs of the inverting amplifier circuits 173 and 174 (output terminals of the operational amplifiers OP1 and OP2), respectively, and one end electrically connected to the cathodes of the diodes D1 and D2. The other end of the capacitor C1 is grounded (connected to the DC return), one end is electrically connected to the cathodes of the diodes D1 and D2 (one end of the capacitor C1), and the other end is grounded (connected to the DC return). ) Resistor R25.

  In the peak hold circuit 175, when the voltage output from the inverting amplifier circuits 173 and 174 is higher than the voltage charged in the capacitor C1, a current flows through the diodes D1 and D2, and the capacitor 177 is charged. The maximum voltage can always be output from one end. The output of the peak hold circuit 175 is grounded via the resistor R25, so that the capacitor C1 is discharged naturally.

  Returning to FIG. 16, the switching circuit 163 determines that the minimum voltage of the control signal 162 is not within the voltage range that can be received by the control signal transceiver 7 (the switching control from the minimum voltage detection circuit 162 is performed). When a signal is input), a voltage shift circuit 8 is inserted in the control signal transmission line 5 between the control signal transceiver 7 and the input connector 2 so that the minimum voltage of the control signal can be received by the control signal transceiver 7 Is switched so that the voltage shift circuit 8 is not inserted into the control signal transmission line 5 between the control signal transceiver 7 and the input connector 2 when the switching control signal is not input from the minimum voltage detection circuit 162. Is.

  In the present embodiment, a bypass transmission line 164 that bypasses the voltage shift circuit 8 is provided separately from the control signal transmission line 5 provided with the voltage shift circuit 8, and the control signal transmission line 5 is switched to the voltage shift circuit 8 side. Alternatively, the switching circuit 163 is configured to control whether to switch to the bypass transmission line 164 side.

  The interface circuit 161 does not use the voltage shift circuit 8 when the minimum voltage of the control signal is within the voltage range that the control signal transceiver 7 can receive. Therefore, it is desirable to configure the switching circuit 163 so that the power supply of the voltage shift circuit 8 is cut off when the minimum voltage of the control signal is within the voltage range that the control signal transceiver 7 can receive.

  The switching circuit 163 may be provided on both the input connector 2 side and the control signal transceiver 7 side of the voltage shift circuit 8 as shown in FIG. 16A, or as shown in FIG. It may be provided only on the control signal transceiver 7 side. When the switching circuit 163 is provided only on the control signal transceiver 7 side, the end of the bypass transmission line 164 on the input connector 2 side is electrically connected directly to the control signal transmission line 5 between the input connector 2 and the voltage shift circuit 8. Good.

  Further, the switching circuit 163 can be incorporated in the voltage shift circuit 8. A voltage shift circuit 8g shown in FIG. 18 is provided with short-circuit switches SW1 and SW2 for switching whether or not to bypass the Zener diodes ZD1 and ZD2 in the voltage shift circuit 8a of FIG. . The short-circuit switches SW1 and SW2 are controlled by the minimum voltage detection circuit 162.

  According to the interface circuit 161, when the voltage of the control signal is in a voltage range that can be received by the control signal transceiver 7, the control signal is directly input to the control signal transceiver 7 without going through the voltage shift circuit 8. It becomes possible. At this time, if the switching circuit 163 is configured to cut off the power supply of the voltage shift circuit 8 that is not used, it is possible to save power.

  The interface circuit 191 shown in FIG. 19A further includes a surge protection circuit 192 between the input connector 2 and the voltage shift circuit 8 for protecting the internal circuit from an externally generated surge voltage.

  The interface circuit 193 shown in FIG. 19B further includes a common-mode noise removal filter 194 that removes the common-mode noise of the control signal between the surge protection circuit 192 and the voltage shift circuit 8 in the interface circuit 191 of FIG. It is provided.

  When the control signal input from the input connector 2 is boosted by the voltage shift circuit 8 and output to the output connector 3 (see FIG. 11), the interface circuit 195 shown in FIG. As described above, the common-mode noise removal filter 194 may be provided between the voltage shift circuit 8 and the control signal transceiver 7. A surge protection circuit 196 may also be provided on the output connector 3 side.

  The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

1 Interface circuit for AISG devices (interface circuit)
2 Input connector 3 Output connector 4 Power line 5 Control signal transmission line 6 Internal circuit 7 Control signal transceiver 8 Voltage shift circuit

Claims (10)

An input connector and an output connector compliant with the AISG standard;
A voltage shift circuit for boosting and outputting a control signal input from the input connector by a constant voltage;
An interface circuit for an AISG device, comprising: It is equipped with a control signal transceiver that transmits and receives control signals, and is mounted on an AISG device that controls antennas in accordance with the AISG standard.
The voltage shift circuit is provided in a control signal transmission line between the control signal transceiver and the input connector;
The control signal input from the input connector is boosted by a constant voltage and output to the control signal transceiver.
The interface circuit for an AISG device according to claim 1, wherein the control signal input from the control signal transceiver is stepped down by a constant voltage and output to the input connector. The shift voltage boosted by the voltage shift circuit is:
The AISG device according to claim 2, wherein when the control signal input from the input connector is boosted, the voltage of the boosted control signal is set within a voltage range that can be received by the control signal transceiver. Interface circuit. The input connector is connected to a control device that transmits a control signal to the AISG device, controls the AISG device to control the antenna, and transmits a power signal to the AISG device.
The shift voltage stepped down by the voltage shift circuit is:
The interface for an AISG device according to claim 2 or 3, wherein when the control signal input from the control signal transceiver is stepped down, the voltage of the stepped down control signal can be received by the control device. circuit. A minimum voltage detection circuit that detects a minimum voltage of the control signal input from the input connector and determines whether the detected minimum voltage is within a voltage range that can be received by the control signal transceiver;
When the minimum voltage detection circuit determines that the minimum voltage of the control signal is not within a voltage range that can be received by the control signal transceiver, the voltage is applied to the control signal transmission line between the control signal transceiver and the input connector. When a shift circuit is inserted and it is determined that the minimum voltage of the control signal is within a voltage range that can be received by the control signal transceiver, the voltage shift is performed on the control signal transmission line between the control signal transceiver and the input connector. The interface circuit for an AISG device according to claim 2, further comprising: a switching circuit that switches so as not to insert the circuit. The voltage shift circuit includes a Zener diode or a plurality of diodes connected in series, and a control signal input from the input connector is a constant voltage by a Zener voltage by the Zener diode or a forward voltage drop by the plurality of diodes. The interface circuit for an AISG device according to any one of claims 1 to 5, wherein the interface circuit is configured to boost and output. The voltage shift circuit is provided in a control signal transmission line between the input connector and the output connector,
A control signal input from the input connector is boosted by a constant voltage and output to the output connector,
The interface circuit for an AISG device according to any one of claims 1 to 6, wherein the control signal input from the output connector is stepped down by a constant voltage and output to the input connector. The interface circuit for an AISG device according to claim 1, further comprising a surge protection circuit for protecting an internal circuit from a surge voltage generated outside. The interface circuit for an AISG device according to claim 1, further comprising a common-mode noise removal filter that removes common-mode noise of the control signal.   An AISG device comprising the AISG device interface circuit according to claim 1.