JP2013055188A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor that implements a stable operation by preventing a voltage applied between a gate electrode and a source electrode from lowering owing to a voltage drop by an electrical resistance of a source electrode pad.SOLUTION: In the GaN HFET, a second pad portion 16B-2 of a bonding part 16B is positioned opposite a first pad portion 16B-1 with respect to a virtual extension line L1 extended in an electrode extension direction from an outer end in a second direction (direction of opposition of source electrode 12 and drain electrode 11) of one of a plurality of connection portions 19 included in an electrode connection part 16A which is disposed at one end in the second direction. A position in the second direction of a bonding point of a second source wire 24 connected to the second pad portion 16B-2 is made different from a position in the second direction of the connection portion 19 of the electrode connection part 16A to the source electrode 12 to complicate a flow of current from the source electrode 12 to the second source wire 24.

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor used as a power device for passing a large current.

  In recent years, with the increase in current of power devices, a configuration in which a gate width is increased or a configuration in which a large number of transistors are connected in parallel is generally used. In these configurations, the resistance of the transistor is as low as several tens of mΩ to several hundreds of mΩ, and a large current flows through the transistor. For this reason, the resistance of the source pad that performs bonding by electrically connecting the transistors connected in parallel cannot be ignored.

  A specific adverse effect of this is that the voltage actually applied between the gate electrode and the source portion of the transistor due to the voltage drop at the source pad is different from the drive gate voltage applied between the gate terminal and the source terminal. There is a problem of being different. For this reason, the voltage actually applied between the gate electrode and the source electrode becomes unstable, causing a problem that the operation is not stable.

JP 2006-25567 A JP 2002-217416 A

  Accordingly, an object of the present invention is to provide a field effect transistor capable of preventing a voltage applied between a gate electrode and a source electrode from fluctuating due to a voltage drop due to an electric resistance of a source electrode pad and realizing a stable operation. There is to do.

In order to solve the above problems, a field effect transistor of the present invention comprises a substrate,
A semiconductor layer formed on the substrate and including an active region;
A source electrode formed on the active region of the semiconductor layer so as to extend in a first direction;
The semiconductor layer is formed on the active region of the semiconductor layer so as to extend in the first direction and has a predetermined interval in a second direction intersecting the first direction with respect to the source electrode. A drain electrode spaced apart;
A gate electrode formed on the active region of the semiconductor layer so as to extend in the first direction and disposed between the source electrode and the drain electrode;
A source electrode pad formed on the semiconductor layer and disposed on one end side in the first direction with respect to the electrode facing region where the source electrode and the drain electrode are opposed to each other and connected to the source electrode And
The source electrode pad is
An electrode connection connected to the source electrode;
A bonding portion connected to the electrode connection portion;
The bonding part is
A first pad portion located on one end side in the first direction with respect to the electrode facing region and bonded with a first source wiring;
The electrode connection portion is located on the opposite side of the first pad portion with respect to a virtual extension line extending in the first direction at the outer end of the connection portion of the electrode connection portion with the source electrode. And a second pad portion to which the second source wiring is bonded.

  Here, the active region is a region of the semiconductor layer where carriers flow between the source electrode and the drain electrode by a voltage applied to the gate electrode disposed between the source electrode and the drain electrode on the semiconductor layer. is there.

  According to the field effect transistor of the present invention, the current flowing between the drain electrode and the source electrode when turned on is transferred from the electrode connection portion of the source electrode pad connected to the source electrode to the first pad portion of the bonding portion. It flows to the bonded first source wiring. On the other hand, a driving gate voltage is applied between the second source wiring bonded to the second pad portion of the bonding portion and the gate electrode. As described above, the driving gate voltage is applied to the gate electrode by using the second source wiring bonded to the second pad portion of the bonding portion of the source electrode pad separately from the first source wiring. Thus, the drive gate voltage can be prevented from being affected by a voltage drop due to the wiring resistance of the first source wiring.

  Further, the second pad portion of the bonding portion has an outer end in the second direction (electrode facing direction) of the connection portion of the electrode connection portion with the source electrode in the first direction (electrode extending direction). ) Is located on the opposite side to the first pad portion with respect to the virtual extension line extended to). A second source wiring is connected to the second pad portion. Thereby, the position of the bonding position of the second source wiring in the electrode facing direction can be prevented from overlapping the position of the connecting portion of the electrode connecting portion with the source electrode in the electrode facing direction. Current is less likely to flow through the second source wiring, and the potential of the second source wiring is less susceptible to the voltage drop caused by the source electrode pad. For example, the bonding location of the second source wiring to the second pad portion can be a location having substantially the same potential as the electrode connection portion. Therefore, by applying a gate-source voltage (drive gate voltage) between the second source line and the gate electrode, the drive gate voltage is reduced by a voltage drop due to the electric resistance of the source electrode pad. Instead, it can be applied between the source electrode and the gate electrode.

  Therefore, according to the field effect transistor of the present invention, the voltage applied between the gate electrode and the source electrode due to the driving gate voltage can be suppressed from fluctuating due to the voltage drop at the source electrode pad, and stable. Operation can be realized.

In one embodiment, the semiconductor layer includes:
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer and forming a heterointerface with the first semiconductor layer;
The bonding portion of the source electrode pad is formed on a recess formed to reach the first semiconductor layer from the second semiconductor layer;
A heterojunction field effect transistor using a two-dimensional electron gas formed at a heterointerface between the first semiconductor layer and the second semiconductor layer.

  According to this embodiment, since the bonding portion of the source electrode pad is formed on the recess, a two-dimensional electron gas is not formed under the bonding portion, and leakage current can be suppressed.

In one embodiment of the field effect transistor, the source electrode and the drain electrode are
In the second direction, a plurality of them are alternately arranged substantially parallel to each other at intervals, and extend in a finger shape in the first direction.

  According to this embodiment, a plurality of source electrodes and drain electrodes extending in a finger shape can be provided to allow a large current to flow, and a voltage at the source electrode pad that is particularly problematic when a large current flows It is possible to avoid a phenomenon in which the drop causes the voltage applied between the source electrode and the gate electrode to fluctuate, stabilize the driving gate voltage, and realize a power device capable of stable operation.

  According to the field effect transistor of the present invention, the second pad portion of the bonding portion of the source electrode pad is a virtual one in which the outer end in the electrode facing direction of the connection portion of the electrode connection portion with the source electrode is extended in the electrode extending direction. The extension line is located on the opposite side of the first pad portion, and the second source wiring is connected to the second pad portion. As a result, the position in the electrode facing direction of the bonding portion of the second source wiring can be made not to overlap the position in the electrode facing direction of the connection portion of the electrode connecting portion of the source electrode pad, and the current from the source electrode can be reduced. The second source wiring is less likely to flow, and the potential of the second source wiring is less susceptible to the voltage drop caused by the source electrode pad.

  Accordingly, by applying the driving gate voltage to the gate electrode using the second source wiring bonded to the second pad portion, the driving gate voltage is reduced in voltage drop due to the electric resistance of the source electrode pad. It can be made unaffected. Therefore, according to the field effect transistor of the present invention, the voltage applied between the gate electrode and the source electrode due to the drive gate voltage can be suppressed from fluctuating due to the voltage drop at the source electrode pad, and stable. Operation can be realized.

1 is a plan view of a first embodiment of a field effect transistor of the present invention. It is sectional drawing which shows the AA line cross section of FIG. 1A. It is sectional drawing which shows the BB line cross section of FIG. 1A. It is sectional drawing which shows the CC line cross section of FIG. 1A. It is a figure which shows the equivalent circuit of the said 1st Embodiment. It is a figure which shows a specific example of the source electrode pad for simulating the potential distribution of the source electrode pad of the said 1st Embodiment. It is a figure which shows the simulation result of the electric potential distribution of the said source electrode pad. It is a top view which shows the 1st modification of the said 1st Embodiment. It is a top view which shows the 2nd modification of the said 1st Embodiment. It is a top view of 2nd Embodiment of the field effect transistor of this invention. It is sectional drawing which shows the AA line cross section of FIG. 6A. It is a top view which shows the comparative example of the said embodiment. It is a figure which shows the equivalent circuit of the said comparative example.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1A is a schematic plan view of a GaN HFET according to the first embodiment of the present invention. Moreover, FIG. 1B is a figure which shows the AA line cross section of FIG. 1A. Moreover, FIG. 1C is a figure which shows the BB sectional view of FIG. 1A, and FIG. 1D is a figure which shows the CC sectional view of FIG. 1A.

As shown in FIGS. 1B and 1C, in the first embodiment, an undoped GaN layer 2 and an undoped AlGaN layer 3 are formed on a Si substrate 1. The undoped GaN layer 2 and the undoped AlGaN layer 3 constitute a GaN-based laminate having a heterojunction. 2DEG (two-dimensional electron gas) 6 is generated at the interface between the undoped GaN layer 2 and the undoped AlGaN layer 3. A protective film 7 and an interlayer insulating film 8 are sequentially formed on the GaN-based laminate. As the material of the protective film 7, for example, SiN is used here, but SiO ₂ , Al ₂ O ₃ or the like may be used. Further, as the material of the interlayer insulating film 8, for example, polyimide is used here, but an insulating material such as SOG (Spin On Glass) or BPSG (Boron Phosphorous Silicate Glass) may be used. The thickness of the SiN protective film 7 is 150 nm as an example here, but may be set in a range of 20 nm to 250 nm.

  In the GaN-based laminate, a recess reaching the undoped GaN layer 2 is formed, and a drain electrode 11 and a source electrode 12 are formed as ohmic electrodes in the recess. As an example, the drain electrode 11 and the source electrode 12 are Ti / Al / TiN electrodes in which a Ti layer, an Al layer, and a TiN layer are sequentially stacked. An opening is formed in the protective film 7, and a gate electrode 13 is formed in the opening. The gate electrode 13 is made of, for example, TiN, and is formed as a Schottky electrode that forms a Schottky junction with the undoped AlGaN layer 3.

  Further, as shown in FIGS. 1B and 1C, a drain electrode pad 15 and a source electrode pad 16 are formed on the interlayer insulating film 8 and the SiN protective film 7. As shown in FIG. 1C, the drain electrode pad 15 has an electrode connection portion 15A connected to the drain electrode 11 and a bonding portion 15B connected to the electrode connection portion 15A. The electrode connecting portion 15A is electrically connected to the drain electrode 11 through a connecting portion 14 in a via hole 20 formed in the interlayer insulating film 8. The bonding portion 15B is formed on the SiN protective film 7 formed on the recess 17 reaching the undoped GaN layer 2. A drain wiring 22 is bonded to the bonding portion 15 B of the drain electrode pad 15.

  On the other hand, as shown in FIG. 1B, the source electrode pad 16 has an electrode connecting portion 16A connected to the source electrode 12 and a bonding portion 16B connected to the electrode connecting portion 16A. The electrode connection portion 16 </ b> A is electrically connected to the source electrode 12 through a connection portion 19 in a via hole 21 formed in the interlayer insulating film 8. The bonding portion 16B is formed on the SiN protective film 7 formed on the recess 18 reaching the undoped GaN layer 2. A first source wiring 23 is bonded to the bonding portion 16B of the source electrode pad 16.

  As shown in FIG. 1A, the source electrode 12 and the drain electrode 11 extend in a finger shape in the first direction and are spaced from each other in a second direction substantially orthogonal to the first direction. A plurality are alternately arranged substantially in parallel. A two-dimensional electron gas 6 formed at the interface between the undoped GaN layer 2 and the undoped AlGaN layer 3 is present in the active region U1 depicted by a one-dot chain line in FIG. 1A. Here, the active region U1 is a carrier between the source electrode 12 and the drain electrode 11 due to a voltage applied to the gate electrode 13 disposed between the source electrode 12 and the drain electrode 11 on the AlGaN layer 3. This is a region of the semiconductor layer (GaN layer 2, AlGaN layer 3) through which. The electrode facing region U2 surrounded by the two-dot chain line is a region where the source electrode 12 and the drain electrode 11 are opposed to each other. In FIG. 1A, the interlayer insulating film 8 is omitted.

  As shown in FIG. 1A, the bonding portion 16B of the source electrode pad 16 includes a first pad portion 16B-1 to which the first source wiring 23 is bonded and a second pad to which the second source wiring 24 is bonded. Pad portion 16B-2. The first pad portion 16B-1 extends from the electrode connecting portion 16A to the side opposite to the electrode facing region U2. Further, the first pad portion 16B-1 is opposed to the electrode facing region U2 in the first direction (electrode extending direction). Further, the second pad portion 16B-2 is in the second direction (the direction in which the source electrode 12 and the drain electrode 11 face each other) among the plurality of connection portions 19 included in the electrode connection portion 16A. The connection portion 19 disposed at one end is located on the opposite side to the first pad portion 16B-1 with respect to a virtual extension line L1 extending in the first direction at the outer end in the second direction. That is, the virtual extension line L1 forms a boundary line in the second direction (electrode facing direction) between the first pad portion 16B-1 and the second pad portion 16B-2. As the drain electrode pad 15 and the source electrode pad 16, Ti / Au or Ti / Al is used.

  As shown in FIG. 1A, the gate electrode 13 extends in an annular shape so as to surround the drain electrode 11 and is connected to the gate electrode pad 28 by a gate electrode connection wiring 27.

  FIG. 2 shows an equivalent circuit of the field effect transistor of this embodiment. The drain electrode 11 of the transistor portion 31 formed in the electrode facing region U2 is connected to the drain terminal 41 via the drain electrode pad 15 and the drain wiring 22. The gate electrode 13 is connected to the gate terminal 42 through the gate electrode connection wiring 27 and the gate electrode pad 28. In the equivalent circuit of FIG. 2, the electrical resistance due to the drain electrode pad 15 and the drain wiring 22 and the electrical resistance due to the gate electrode connection wiring 27 and the gate electrode pad 28 are omitted.

  The source electrode 12 is connected to the source terminal 43 via the electrode connecting portion 16A of the source electrode pad 16, the first pad portion 16B-1 of the bonding portion 16B, and the first source wiring 23. This source terminal 43 is connected to the ground. In FIG. 2, R <b> 1 represents the electrical resistance due to the source electrode pad 16. R2 represents the electrical resistance due to the first source wiring 23.

  The source electrode 12 is connected to the gate-source potential source terminal 44 via the electrode connection portion 16A of the source electrode pad 16, the second pad portion 16B-2 of the bonding portion 16B, and the second source wiring 24. It is connected to the. In a specific example to be described later, the electrode connection portion 16A of the source electrode pad 16 and the bonding portion of the second source wiring 24 to the second pad portion 16B-2 of the bonding portion 16B are set to substantially the same potential when turned on. The electrical resistance of the second pad portion 16B-2 is substantially negligible.

  According to the GaN HFET of this embodiment, the gate-source potential source terminal 44 connected to the second source wiring 24 bonded to the second pad portion 16B-2 of the bonding portion 16B and the gate electrode 13 are connected. A drive gate voltage Vgs (drive) is applied between the gate terminal 42 connected to the gate terminal 42.

  When the transistor unit 31 is turned on by the driving gate voltage Vgs (drive), the current flowing between the drain electrode 11 and the source electrode 12 is connected to the source electrode pad 16 connected to the source electrode 12. The current flows from the portion 16A to the first source wiring 23 bonded to the first pad portion 16B-1 of the bonding portion 16B, and flows from the source terminal 43 to the ground.

  In this embodiment, the first source wiring 23 bonded to the first pad portion 16B-1 of the bonding portion 16B of the source electrode pad 16 is connected to the source terminal 43 for flowing current, while the bonding portion A second source wiring 24 bonded to the 16B second pad portion 16B-2 is connected to a source terminal 44 for applying a driving gate voltage. Therefore, by applying the drive gate voltage Vgs (drive) between the source terminal 44 and the gate terminal 42, the transistor 31 is actually connected between the source and gate with the drive gate voltage Vgs (drive). The applied voltage Vgs (tr) can be prevented from being affected by the voltage drop due to the electric resistance R2 of the first source line 23.

  In this embodiment, the second pad portion 16B-2 of the bonding portion 16B of the source electrode pad 16 is related to the virtual extension line L1 from the outer edge of the connection portion 19 between the source electrode 12 and the electrode connection portion 16A. It is arranged on the opposite side of the first pad portion 16B-1. That is, the virtual extension line L1 forms a boundary line in the second direction (electrode facing direction) between the first pad portion 16B-1 and the second pad portion 16B-2. Thereby, the position in the second direction of the bonding portion of the second source wiring 24 is not overlapped with the position in the second direction of the connection portion 19 of the electrode connection portion 16A with the source electrode 12. Thus, the current from the source electrode 12 can be made difficult to flow through the second source wiring 24. As a result, the potential of the second source wiring 24 is not easily affected by the voltage drop caused by the source electrode pad 16. For example, in a specific example to be described later, it has been found that the second source wiring 24 can be bonded to a portion of the second pad portion 16B-2 that has substantially the same potential as the electrode connection portion 16A. Therefore, according to this embodiment, the transistor portion is actually used by the drive gate voltage Vgs (drive) applied between the source terminal 44 for applying the drive gate voltage connected to the second source line 24 and the gate terminal 42. The voltage Vgs (tr) applied between the source electrode 31 and the gate electrode 31 can be prevented from being affected by the voltage drop due to the electric resistance R1 of the source electrode pad 16.

  Therefore, according to the GaN HFET of this embodiment, the voltage Vgs (tr) that is actually applied between the gate electrode 13 and the source electrode 12 by the drive gate voltage Vgs (drive) is the electric resistance of the source electrode pad 16. Can be prevented from being reduced by a voltage drop due to the above, and the voltage applied between the gate electrode 13 and the source electrode 12 can be stabilized, and a stable operation can be realized.

  Further, according to this embodiment, since the bonding portion 16B of the source electrode pad 16 is formed on the recess 18, the two-dimensional electron gas 6 is not formed under the bonding portion 16B, and leakage occurs. Current can be suppressed. In addition, according to this embodiment, a large current can flow through the plurality of source electrodes 12 and drain electrodes 11 extending in the above finger shape. The phenomenon that the voltage drop at the electrode pad 16 fluctuates the voltage applied between the source electrode and the gate electrode can be avoided. Therefore, the voltage applied between the source electrode and the gate electrode can be stabilized by the driving gate voltage, and a power device capable of stable operation can be realized.

(Comparative example)
Next, a GaN HFET of a comparative example of the above embodiment will be described with reference to the plan view of FIG.

  This comparative example is different from the above-described embodiment in that a source electrode pad 116 is provided instead of the source electrode pad 16 shown in FIG. 1A. Therefore, in this comparative example, the same reference numerals are given to the same parts as those of the above-described embodiment, and different parts from the above-described embodiment will be mainly described.

  As shown in FIG. 7, the source electrode pad 116 provided in this comparative example includes an electrode connection portion 116A and a bonding portion 116B. This electrode connection portion 116A is the same as the electrode connection portion 16A of the source electrode pad 16 shown in FIG. 1A.

  On the other hand, the source electrode pad 116 has a bonding portion 116B different from the bonding portion 16B of the source electrode pad 16 of FIG. 1A. The bonding portion 116B is a portion 116B-2 protruding from the virtual extension line L101 at the outer edge in the second direction of the connection portion 119 between the source electrode 12 and the electrode connection portion 116A disposed at one end of the electrode facing region U2. However, the protruding portion 116B-2 is narrow and not so wide that the second source wiring 24 can be bonded. Therefore, in this comparative example, a portion 116B of the bonding portion 116B that is adjacent to the electrode connection portion 116A in the first direction (the direction in which the source electrode 11 extends in a finger shape). Both the first source line 23 and the second source line 24 are bonded to -1.

  FIG. 8 shows an equivalent circuit of the field effect transistor of this comparative example. The drain electrode 11 of the transistor portion 31 formed in the electrode facing region U2 is connected to the drain terminal 141 via the drain electrode pad 15 and the drain wiring 22. The gate electrode 13 is connected to the gate terminal 142 via the gate electrode connection wiring 27 and the gate electrode pad 28. In the equivalent circuit of FIG. 8, the electrical resistance due to the drain electrode pad 15 and the drain wiring 22 and the electrical resistance due to the gate electrode connection wiring 27 and the gate electrode pad 28 are omitted. In this comparative example, the source electrode 12 is connected to the source terminal 143 via the electrode connecting portion 116A of the source electrode pad 116, the adjacent portion 116B-1 of the bonding portion 116B, and the first source wiring 23. The source terminal 143 is connected to the ground. In FIG. 8, R1 represents the electrical resistance due to the source electrode pad 116. R2 represents the electrical resistance due to the first source wiring 23. In this comparative example, the source electrode 12 is connected to the gate-source potential source via the electrode connecting portion 116A of the source electrode pad 116, the adjacent portion 116B-1 of the bonding portion 16B, and the second source wiring 24. It is connected to the terminal 144.

  In this comparative example, the bonding position of the second source wiring 24 connected to the adjacent portion 116B-1 of the bonding portion 116B of the source electrode pad 116 is located at the position in the second direction (electrode facing direction). It overlaps with the connecting portion 119 between the connecting portion 116A and the source electrode 12. Therefore, since the current from the electrode connection portion 116A easily flows through the second source wiring 24, the potential of the second source wiring 24 is easily affected by the voltage drop caused by the source electrode pad 116. That is, in this comparative example, the second source wiring 24 is bonded to a portion having a potential lower than the potential of the electrode connection portion 116A of the adjacent portion 116B-1 of the bonding portion 116B.

  Therefore, according to this comparative example, the drive gate voltage Vgs (drive) applied between the source terminal 144 for applying the drive gate voltage connected to the second source line 24 and the gate terminal 142 is equal to the source electrode. The voltage drops due to the voltage drop due to the electric resistance R1 of the pad 116. That is, the voltage Vgs (tr) = (Vgs (drive) −R1 × I) in which the drive gate voltage Vgs (drive) is reduced by the voltage drop (R1 × I (current flowing through the transistor)) due to the electric resistance R1 is the source Applied between the electrode 12 and the gate electrode 13. In particular, when a large current flows between the drain terminal 141 and the source terminal 143, the voltage drop (R1 × I) due to the electric resistance R1 of the source electrode pad 116 becomes large, and between the source electrode and the gate electrode of the transistor portion 31. The actually applied voltage Vgs (tr) is clearly reduced from the drive gate voltage Vgs (drive), and the actually applied voltage Vgs (tr) is clearly different from the drive gate voltage Vgs (drive). When the source electrode pad 116 is large, when the source electrode pad 116 is thin, or when a material having a high resistivity is used for the source electrode pad 116, the value of the electric resistance R1 of the source electrode pad 116 is further increased. Since the voltage increases, the influence of the actually applied voltage Vgs (tr) being lowered from the drive gate Vgs (drive) becomes more remarkable.

  In addition, the voltage drop (R1 × I) at the source electrode pad 116 varies depending on the electric resistance R1 of the source electrode pad 116 and the current I flowing through the transistor unit 31, so that the voltage Vgs (tr) is stabilized. Cannot be achieved. Therefore, in this comparative example, the voltage Vgs (tr) actually applied between the source electrode and the gate electrode of the transistor unit 31 is likely to fluctuate and the operation becomes unstable.

(simulation result)
Next, the potential distribution of the source electrode pad 16 was simulated using a specific example of the above-described embodiment.

  In this specific example, as shown in FIG. 3A, the arrangement pitch P of the source electrodes 12 is 60 μm, the dimension D in the first direction (source electrode extending direction) of the source electrode pad 16 is 500 μm, and the source The dimension W in the second direction (source electrode arrangement direction) of the electrode pad 16 was set to 900 μm. In this specific example, ten source electrodes 12 are connected to the electrode connection portion 16 </ b> A of the source electrode pad 16. In this specific example, the position of the distance X1 = 330 μm from the end of the second direction of the source electrode pad 16 and the distance Y1 = 250 μm from the end of the first direction is set to the bonding of the first source wiring 23. It was set as the location B.

  In this specific example, a simulation result of equipotential lines when a predetermined voltage V = 1 V is applied to the bonding location B and the wiring locations K1 to K10 to the source electrodes 12 are set to the ground potential is shown in FIG. Shown in 3B. The wiring points K1 to K10 are contact holes, the contact hole width is 10 μm, and the distance between the contact holes is 50 μm. The equipotential line S1 in FIG. 3B indicates a region having a potential of 0.1 V, and the equipotential lines S2, S3, S4, S5, S6, and S7 are potentials of 0.2 V, 0.3 V, 0.4 V, and 0, respectively. .5V, 0.6V, 0.7V regions are shown. From the simulation result of FIG. 3B, the region Z1 farther from the position separated from the wiring part K10 at the end in the second direction (electrode arrangement direction) among the wiring parts K1 to K10 of the source electrode pad 16 by a substantially distance Z0 = 100 μm. Is a region where the potential of the equipotential line S1 is 0.1 V or less, and is close to the potential (ground potential) of the wiring locations K1 to K10. Therefore, by bonding the second source wiring 24 in the region Z1 of the second pad portion 16B-2 of the source electrode pad 16, the second potential of the electrode connection portion 16A is approximately equal to that of the electrode connection portion 16A. Two source wirings 24 can be connected. As a result, the drive gate voltage Vgs (drive) applied between the source terminal 44 for applying the drive gate voltage connected to the second source wiring 24 and the gate terminal 42 is actually used between the source electrode 12 and the gate electrode 13. Thus, the voltage Vgs (tr) applied to the source electrode pad 16 can be prevented from being affected by the voltage drop due to the electric resistance R1 of the source electrode pad 16. Therefore, according to the field effect transistor of this specific example, the voltage Vgs (tr) actually applied between the gate electrode 13 and the source electrode 12 by the drive gate voltage Vgs (drive) is changed to the source electrode pad 16. Fluctuation due to the voltage drop can be suppressed, and stable operation can be realized.

  In the above simulation, in order to obtain the potential distribution, the bonding location B is 1 V, and the wiring locations K1 to K10 to the source electrode 12 are the ground potential. Since the source electrode pad 16 can be regarded as a resistance, that is, a linear element, the potential distribution is also obtained when the voltage value at the bonding point B and the voltage values at the wiring points K1 to K10 to the source electrode 12 are different from the above values. The potential distribution is similar to the simulation result described above. That is, assuming that the voltage at the bonding point B is V1 and the voltage at the wiring points K1 to K10 to the source electrode 12 is V2, the potential of the equipotential line S1 = V2 + (V1-V2) × 0.1. Further, the potential of the equipotential line S2 = V2 + (V1-V2) × 0.2 or the like.

(First modification)
Next, a first modification of the above embodiment will be described with reference to FIG. This first modification includes a comb-shaped source electrode 212 and a comb-shaped drain electrode 211, and the following points (1) and (2) are different from the above-described embodiment. Therefore, in the first modified example, the same reference numerals are given to the same parts as those in the above embodiment, and different parts from the above embodiment will be described.

    (1) Instead of the plurality of source electrodes 12, a plurality of source electrode portions 222 are provided with one comb-shaped source electrode 212 in which the connection portions 223 at the end on the source electrode pad 16 side are connected.

    (2) Instead of the plurality of drain electrodes 11, a single comb-shaped drain electrode 211 in which a plurality of drain electrode portions 221 are connected by connecting portions 225 at the end on the drain electrode pad 15 side is provided.

  In the first modification, the direction in which the source electrode portion 222 and the drain electrode portion 221 extend is the first direction, and the source electrode portion 222 and the drain electrode portion 221 face each other. The direction that is present is the second direction. A region where the source electrode portion 222 and the drain electrode portion 221 face each other is an electrode facing region U21. Moreover, in this 1st modification, although it has the active region U1 similar to the said embodiment, illustration is abbreviate | omitted in FIG. In the first modification, a gate electrode connection wiring 29 is provided instead of the gate electrode connection wiring 27 of the above embodiment.

  In the first modification, the connecting portion 223 of the comb-shaped source electrode 212 is electrically connected to the electrode connecting portion 16 A of the source electrode pad 16 through the connecting portion 19 in the via hole 21 formed in the interlayer insulating film 8. It is connected. The connecting portion 225 of the comb-shaped drain electrode 211 is electrically connected to the electrode connecting portion 15A of the drain electrode pad 15 through the connecting portions 14 in the plurality of via holes 20 formed in the interlayer insulating film 8. .

  Also in the first modification, the second pad portion 16B-2 of the bonding portion 16B of the source electrode pad 16 is a virtual extension line from the outer edge of the connection portion 19 between the source electrode 212 and the electrode connection portion 16A. It is arranged on the opposite side of the first pad portion 16B-1 with respect to L1. Accordingly, the position in the second direction of the bonding portion of the second source wiring 24 is not overlapped with the position in the second direction of the connection portion 19 of the electrode connection portion 16A with the source electrode 212. The current from the source electrode 212 can be made difficult to flow through the second source wiring 24. As a result, the potential of the second source wiring 24 is not easily affected by the voltage drop caused by the source electrode pad 16.

(Second modification)
Next, a second modification of the above embodiment will be described with reference to FIG. This second modification is provided with a comb-shaped source electrode 312 and a comb-shaped drain electrode 211, and the following points (1), (2), and (3) are different from the above-described embodiment. Therefore, in the second modification, the same reference numerals are given to the same parts as those in the above embodiment, and different parts from the above embodiment will be described.

    (1) A source electrode pad 316 is provided instead of the source electrode pad 16.

    (2) A point that a plurality of source electrode portions 322 are connected to each other by a connecting portion 323 at the end on the source electrode pad 316 side instead of the plurality of source electrodes 12 is provided.

    (3) A point that a plurality of drain electrode portions 221 are connected to each other by connecting portions 225 at the end on the drain electrode pad 15 side in place of the plurality of drain electrodes 11.

  In the second modification, the direction in which the source electrode portion 322 and the drain electrode portion 221 extend is the first direction, and the source electrode portion 322 and the drain electrode portion 221 face each other. The direction that is present is the second direction. A region where the source electrode portion 322 and the drain electrode portion 221 face each other is an electrode facing region U32. Moreover, in this 2nd modification, although it has the active region U1 similar to the said embodiment, illustration is abbreviate | omitted in FIG. In the second modification, a gate electrode connection wiring 29 is provided in place of the gate electrode connection wiring 27 of the above embodiment.

  In the second modification, the connecting portion 323 of the comb-shaped source electrode 312 is electrically connected to the electrode connecting portion 316 A of the source electrode pad 316 through the connecting portion 19 in the via hole 21 formed in the interlayer insulating film 8. It is connected. The connecting portion 225 of the comb-shaped drain electrode 211 is electrically connected to the electrode connecting portion 15A of the drain electrode pad 15 through the connecting portions 14 in the plurality of via holes 20 formed in the interlayer insulating film 8. .

  Further, as shown in FIG. 5, the bonding portion 316B of the source electrode pad 316 is formed by bonding the first pad portion 316B-1 to which the first source wiring 23 is bonded and the second source wiring 24. Second pad portion 316B-2. The first pad portion 316B-1 extends from the electrode connection portion 316A to the opposite side to the electrode facing region U31 (a region where the plurality of source electrode portions 322 and the plurality of drain electrode portions 221 face each other). doing. The first pad portion 316B-1 is opposed to the electrode facing region U32 in the first direction (the direction in which the source electrode portion 322 extends). The second pad portion 316B-2 is in the second direction (the direction in which the source electrode portion 322 and the drain electrode portion 211 face each other) among the plurality of connection portions 19 included in the electrode connection portion 316A. The imaginary extension line L31 obtained by extending the outer end in the second direction of the connecting portion 19 disposed at one end of the connecting portion 19 in the first direction is located on the opposite side to the first pad portion 316B-1. . That is, the virtual extension line L31 forms a boundary line in the second direction (electrode facing direction) between the first pad portion 316B-1 and the second pad portion 316B-2.

  Thus, the position in the second direction of the bonding portion of the second source wiring 24 is not overlapped with the position in the second direction of the connection portion 19 between the source electrode 312 and the electrode connection portion 316A. As a result, the current from the source electrode 312 can hardly flow through the second source wiring 24. As a result, the potential of the second source wiring 24 is not easily affected by the voltage drop caused by the source electrode pad 316.

  That is, as in the second modification, even if the position in the second direction of the second pad portion 316B-2 overlaps the position in the second direction of the electrode facing region U31, the second pad portion If the position in the second direction of the bonding portion of the second source wiring 24 at 316B-2 does not overlap the position in the second direction of the connection portion 19 to the source electrode 312, the second source wiring The potential of 24 is less susceptible to the voltage drop caused by the source electrode pad 316.

(Second embodiment)
FIG. 6A is a schematic plan view of a GaN HFET according to the second embodiment of the present invention. Moreover, FIG. 6B is a figure which shows the AA line cross section of FIG. 6A.

As shown in FIG. 6B, in the second embodiment, an undoped GaN layer 502 and an undoped AlGaN layer 503 are formed on a Si substrate 501. The undoped GaN layer 502 and the undoped AlGaN layer 503 constitute a GaN-based stacked body having a heterojunction. 2DEG (two-dimensional electron gas) 506 is generated at the interface between the undoped GaN layer 502 and the undoped AlGaN layer 503. A protective film 507 and an interlayer insulating film 508 are sequentially formed on the GaN-based laminate. As the material of the protective film 507, for example, SiN is used here, but SiO ₂ , Al ₂ O ₃ or the like may be used. In addition, as the material of the interlayer insulating film 508, for example, polyimide is used here, but an insulating material such as SOG (Spin On Glass) or BPSG (Boron Phosphorous Silicate Glass) may be used. The thickness of the SiN protective film 507 is 150 nm as an example here, but may be set in a range of 20 nm to 250 nm.

  Further, a recess reaching the undoped GaN layer 502 is formed in the GaN-based laminate, and a drain electrode 511 and a source electrode 512 are formed as ohmic electrodes in the recess. As an example, the drain electrode 511 and the source electrode 512 are Ti / Al / TiN electrodes in which a Ti layer, an Al layer, and a TiN layer are sequentially stacked. An opening is formed in the protective film 507, and a gate electrode 513 is formed in the opening. The gate electrode 513 is made of, for example, TiN, and is formed as a Schottky electrode that forms a Schottky junction with the undoped AlGaN layer 503.

  As shown in FIG. 6B, a drain electrode pad 515 and a source electrode pad 516 are formed on the interlayer insulating film 508. The drain electrode pad 515 has an electrode connection portion 515A and a bonding portion 515B. The electrode connecting portion 515A is connected to the drain electrode 511 by a connecting portion 514. The electrode connection portion 514 of the electrode connection portion 515A is electrically connected to the drain electrode 511 through the via hole 520 formed in the interlayer insulating film 508. A drain wiring 522 is bonded to the bonding portion 515 B of the drain electrode pad 515.

  The source electrode pad 516 includes an electrode connection portion 516A and a bonding portion 516B. The electrode connection portion 516A is connected to the source electrode 512 at a connection portion 519. The connection portion 519 is formed in the via hole 521 formed in the interlayer insulating film 508. The bonding portion 516B is formed on the interlayer insulating film 508. A first source wiring 523 is bonded to the bonding portion 516B of the source electrode pad 516.

  As shown in FIG. 6A, the drain electrode 511 has a comb shape, and connects a plurality of drain electrode portions 511A extending in a finger shape in the first direction and the base ends of the plurality of drain electrode portions 511A. Connecting portion 511B. The source electrode 512 has a comb shape, and a plurality of source electrode portions 512A extending in a finger shape in the first direction and a connecting portion 512B connecting base ends of the plurality of source electrode portions 512A. And have. The source electrode portions 512A and the drain electrode portions 511A are alternately arranged in parallel and spaced apart from each other in a second direction substantially orthogonal to the first direction. A two-dimensional electron gas 506 formed at the interface between the undoped GaN layer 502 and the undoped AlGaN layer 503 exists in the active region U61 depicted by a one-dot chain line in FIG. 6A. Here, the active region U61 is a carrier between the source electrode 512 and the drain electrode 511 due to a voltage applied to the gate electrode 513 disposed between the source electrode 512 and the drain electrode 511 on the AlGaN layer 503. This is a region of the semiconductor layer (GaN layer 502, AlGaN layer 503) through which flows. An electrode facing region U62 surrounded by a two-dot chain line is a region where the source electrode portion 512A of the source electrode 512 and the drain electrode portion 511A of the drain electrode 511 face each other. In FIG. 6A, the interlayer insulating film 508 is omitted.

  As shown in FIG. 6A, the bonding portion 516B of the source electrode pad 516 includes a first pad portion 516B-1 to which the first source wiring 523 is bonded and a second source wiring 524 to be bonded. Pad portion 516B-2. The first pad portion 516B-1 extends from the electrode connection portion 516A to the electrode facing region U26 side. The first pad portion 516B-1 covers the electrode facing region U62. Further, the second pad portion 516B-2 is in the second direction (the direction in which the source electrode portion 512A and the drain electrode portion 511A face each other) among the plurality of connection portions 519 of the electrode connection portion 516A. The connection portion 519 disposed at one end is located on the opposite side of the first pad portion 16B-1 with respect to the virtual extension line L61 extending the outer end in the second direction in the first direction. That is, the virtual extension line L61 forms a boundary line between the first pad portion 516B-1 and the second pad portion 516B-2. As the drain electrode pad 515 and the source electrode pad 516, Ti / Au or Ti / Al is used.

  As shown in FIG. 6A, the gate electrode 513 extends in an annular shape so as to surround the drain electrode 511, and is connected to the gate electrode pad 528 through a gate electrode connection wiring 527.

  In this embodiment, the second pad portion 516B-2 of the bonding portion 516B of the source electrode pad 516 is related to the virtual extension line L61 from the outer edge of the connection portion 519 between the source electrode 512 and the electrode connection portion 516A. It is arranged on the opposite side of the first pad portion 516B-1. That is, the virtual extension line L61 forms a boundary line between the first pad portion 516B-1 and the second pad portion 516B-2. Accordingly, the position of the bonding portion of the second source wiring 524 in the second direction (electrode facing direction) is changed to the position in the second direction of the connection portion 519 of the electrode connection portion 516A with the source electrode 512. So that the current from the source electrode 512 does not easily flow to the second source wiring 524. Accordingly, the potential of the second source wiring 524 is not easily affected by a voltage drop caused by the source electrode pad 516. Therefore, according to this embodiment, the source electrode 512 is actually generated by the drive gate voltage applied between the source terminal for applying the drive gate voltage connected to the second source line 524 and the gate terminal (not shown). The voltage applied between the gate electrodes 513 can be prevented from being affected by the voltage drop due to the electric resistance of the source electrode pad 516.

  Therefore, according to the GaN HFET of this embodiment, the voltage Vgs (tr) actually applied between the gate electrode 513 and the source electrode 512 is a voltage drop due to the electric resistance of the source electrode pad 516 due to the drive gate voltage. The voltage can be prevented from being lowered, the voltage applied between the gate electrode 13 and the source electrode 12 can be stabilized, and a stable operation can be realized.

  In the second embodiment, one comb-shaped drain electrode 511 and one comb-shaped source electrode 512 are provided. However, as in the first embodiment, a plurality of finger-shaped drain electrodes and a plurality of finger-shaped drain electrodes are provided. The finger-shaped source electrode may be provided.

  In the first and second embodiments, the heterojunction field effect transistor in which the GaN layer 2 and the AlGaN layer 3 are sequentially stacked on the substrate 1 has been described. However, instead of the GaN layer and the AlGaN layer, a GaAs layer and an n− The present invention may be applied to a heterojunction field effect transistor in which an AlGaAs layer is sequentially stacked on a substrate. In the above embodiment, the substrate is a Si substrate. However, a sapphire substrate or a SiC substrate may be used, a nitride semiconductor layer may be grown on the sapphire substrate or the SiC substrate, or an AlGaN layer is formed on the GaN substrate. A nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor.

  In the above embodiment, a finger type heterojunction field effect transistor having a plurality of gate electrodes, source electrodes, and drain electrodes has been described. However, the field effect transistor of the present invention is not limited to this, and the gate electrode, the source electrode, The present invention may be applied to a field effect transistor having one set of drain electrodes. In the above embodiment, a normally-on type heterojunction field effect transistor has been described. However, the present invention may be applied to a normally-off type heterojunction field effect transistor. The present invention is not limited to a heterojunction field effect transistor, and may be applied to a field effect transistor in which carriers such as a lateral junction FET and a lateral power MOSFET move laterally along the substrate surface.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

1,501 Si substrate 2,502 Undoped GaN layer 3,503 Undoped AlGaN layer 6,506 Two-dimensional electron gas 7,507 Protective film 8,508 Interlayer insulating film 11 Drain electrode 12 Source electrode 12A Outer edge 13 Gate electrode 14, 19 Connection Part 15 Drain electrode pad 15A Electrode connection portion 15B Bonding portion 16 Source electrode pad 16A Electrode connection portion 16B Bonding portion 16B-1 First pad portion 16B-2 First pad portion 17, 18 Recess 20, 21 Via hole 22,522 Drain wiring 23,523 First source wiring 24,524 Second source wiring 27,29 Gate electrode connection line 28 Gate electrode pad 31 Transistor portion 41 Drain terminal 42 Gate terminal 43 Source terminal 44 Source terminal for gate-source potential 211,51 1 comb-shaped drain electrode 212, 312, 512 comb-shaped source electrode 221, 511A drain electrode part 222, 322, 512A source electrode part 223, 225, 323 connection part 316, 516 source electrode pad 316A, 516A electrode connection part 316B Bonding part 316B-1, 516B-1 First pad part 316B-2, 516B-2 Second pad part 515 Drain electrode pad 515A Electrode connection part 515B Bonding part B Bonding part K1-K10 Wiring part S1-S7 Equipotential Line L1, L31, L61 Virtual extension line P Arrangement pitch U1, U61 Active area U2, U32, U62 Electrode facing area

Claims (3)

A substrate,
A semiconductor layer formed on the substrate and including an active region;
A source electrode formed on the active region of the semiconductor layer so as to extend in a first direction;
The semiconductor layer is formed on the active region of the semiconductor layer so as to extend in the first direction and has a predetermined interval in a second direction intersecting the first direction with respect to the source electrode. A drain electrode spaced apart;
A gate electrode formed on the active region of the semiconductor layer so as to extend in the first direction and disposed between the source electrode and the drain electrode;
A source electrode pad formed on the semiconductor layer and disposed on one end side in the first direction with respect to the electrode facing region where the source electrode and the drain electrode are opposed to each other and connected to the source electrode And
The source electrode pad is
An electrode connection connected to the source electrode;
A bonding portion connected to the electrode connection portion;
The bonding part is
A first pad portion located on one end side in the first direction with respect to the electrode facing region and bonded with a first source wiring;
The electrode connection portion is located on the opposite side of the first pad portion with respect to a virtual extension line extending in the first direction at the outer end of the connection portion of the electrode connection portion with the source electrode. 2. A field effect transistor comprising: a second pad portion to which a second source wiring is bonded. The field effect transistor according to claim 1.
The semiconductor layer is
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer and forming a heterointerface with the first semiconductor layer;
The bonding portion of the source electrode pad is formed on a recess formed to reach the first semiconductor layer from the second semiconductor layer;
A field effect transistor, which is a heterojunction field effect transistor using a two-dimensional electron gas formed at a heterointerface between the first semiconductor layer and the second semiconductor layer. The field effect transistor according to claim 1 or 2,
The source electrode and the drain electrode are
A field effect transistor, wherein a plurality of the electrodes are alternately arranged substantially parallel to each other in the second direction and extend in a finger shape in the first direction.

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