JP2013054699A - Bus arbiter, bus arbiter system and processing method of bus arbiter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arbiter in which use efficiency of a bust master of a higher priority is prevented from being oppressed with respect to a plurality of bus masters of approximately equal priorities.SOLUTION: A bus arbiter 100 arbitrates bus acquisition requests from a plurality of bus masters 110 connected to a common bus 12 on the basis of preset priorities of the bus masters. The bus arbiter 100 comprises bus acquisition request monitor means 14 which monitors a first bus acquisition request from a first bus master of a highest priority and a second bus acquisition request from a second bus master of a priority approximately equal to the first bus master, specific event detection means 15 which acquires a monitor result of the bus acquisition request monitor means and detects a specific event in which a frequency of the first bus acquisition request and a frequency of the second bus acquisition request meet a predetermined criterion, and bus acquisition control means 13 which acquires a specific event detection signal from the specific event detection means and restricts the frequency of the second bus acquisition request.

Description

  The present invention relates to a bus arbiter that arbitrates bus acquisition requests from a plurality of bus masters connected to a common bus based on preset priority of each bus master.

  In an information processing apparatus, a plurality of devices often perform processing by sharing a bus and performing read / write to a memory. For example, in an image forming apparatus, several image processing units each access a high-speed memory before printing data for printing on paper.

  FIG. 1 is an example of a diagram for explaining memory access by each image processing means. When an application on a PC (Personal Computer) 300 transmits PDL data (page description language) to the image forming apparatus 200 using an OS or a printer driver, the communication controller 201 stores the PDL data in a memory. Next, the CPU (software) 202 reads the PDL data from the memory, generates a drawing command, and writes it back to the memory 400. Next, the drawing apparatus 203 analyzes the drawing command from the memory 400 and writes the gradation-processed image data into the memory 400. Next, the encoding device 204 writes the image data obtained by encoding the gradation-processed image data using a compression algorithm (JBIG or the like) into the memory 400. Next, the decoding device 205 reads and decodes the encoded image data from the memory 400, and transfers raster data corresponding to the C, M, Y, and K plates to the printer engine 206. In this way, a plurality of image processing means access one memory 400 one after another.

  For this reason, an arbiter 100 that arbitrates memory access is generally provided between a plurality of image processing means and a memory. The arbiter 100 determines an image processing unit that gives a right to use the bus 500 connecting the image processing unit and the memory 400 according to a predetermined rule when a plurality of image processing units request memory access at the same time.

  As an arbitration method in which the arbiter 100 arbitrates when bus requests occur simultaneously, there is a fixed priority method in which priority is set in advance in the image processing means and the bus use right is given to the higher one. In addition, there is a round robin method in which the priority is not fixed, and the right to use the bus is given to the image processing means in order, but in this application, the fixed priority method is mainly handled.

FIG. 2 is an example for explaining the fixed priority order method. Of the bus masters 110 (referred to as bus masters 1 to 5 when distinguished), it is assumed here that the bus master 1 has the highest priority.
When the bus master 1 requests the arbiter 100 to acquire a bus, the arbiter 100 gives the bus master 1 the right to use the bus.
If there is no bus acquisition request from the bus master 1 and the low priority bus masters 2 and 3 request the arbiter 100 to acquire a bus, the arbiter 100 sends the bus masters 2 and 3 to the bus masters 2 and 3 without masking the acquisition requests. Gives the right to use the bus.

  However, when the bus master 1 generates a bus acquisition request and the bus masters 2 and 3 generate a bus acquisition request, a situation occurs in which the bus masters 2 and 3 cannot acquire the bus. In this case, if the bus master 1 generates a bus acquisition request for a long period, the bus acquisition requests of the bus masters 2 and 3 are continuously ignored.

  Therefore, an arbiter 100 has been proposed that gives priority to the bus master 1 and does not completely ignore the bus acquisition requests of the bus masters 2 and 3 (see, for example, Patent Document 1). Patent Document 1 discloses a technique for temporarily reducing the bus use frequency of the bus masters 2 and 3 when the bus masters 2 and 3 request acquisition of the bus while the bus master 1 acquires the bus. Yes.

  FIG. 3 is an example of a diagram for explaining acquisition requests to the arbiters of the conventional bus masters 1 to 3. In the figure, the bar-shaped vertical lines indicate bus acquisition requests of the bus masters 1 to 3. When there is no bus acquisition request from the bus master 1, the other bus masters 2 and 3 acquire the bus without masking the acquisition request. However, if the bus master 1 requests acquisition of the bus and the bus master 2 or 3 requests acquisition of the bus, the bus masters 2 and 3 are masked for a certain period of time. As a result, the bus masters 2 and 3 are restricted in the bus use frequency. According to such a configuration, the arbiter 100 can temporarily reduce the bus usage frequency of the other bus masters 2 and 3, and the data of the bus master 1 can be obtained without ignoring the request from the bus master having a low priority. Transfer efficiency can be guaranteed.

  However, the technique described in Patent Document 1 has a problem that inconvenience arises when there is a bus master that requires a priority equivalent to that of the bus master 1 (this is referred to as a bus master 1 ′). For example, if the bus master 1 has few bus acquisition requests and the bus master 1 ′ has many bus acquisition requests, the arbiter 100 gives the bus master 1 ′ the right to use the bus rather than the bus master 1. A tendency to decrease occurs.

FIG. 4 is an example of a diagram illustrating the bus master 1 and the bus master 1 ′ in more specific examples. Conventionally, an image processing unit called a rotator may perform processing of rotating image data written in the memory 400 by 180 degrees. In FIG. 4, this rotation process is performed at the time of reading from the memory 400 by adjusting the address read by the bus master 1. Therefore, in FIG. 4, in addition to FIG. 1, the LSI 120 has an image output device.
(i) Image processing means (not shown) reads the encoded image data from the HDD 130 and develops it on the memory 400.
(ii) The bus master 1 ′ (decoding device) reads the encoded image data from the memory 400.
(iii) The bus master 1 ′ decompresses the encoded image data to generate raw data, divides the data into bands (area obtained by dividing one page into several parts in the sub-scanning direction), and develops them on the memory 400. .
(iv) The bus master 1 (image output device) adjusts the order of addresses for reading the raw data on the memory 400 divided into band units so as to rotate 180 degrees, and outputs the read raw data to the printer engine.

  By doing so, it is possible to rotate 180 degrees at the time of reading from the memory 400, so that the speed can be increased as compared with the case where the raw data obtained by the rotation in the LSI is rotated 180 degrees.

  However, in order to realize the method of FIG. 4, the operations of the bus master 1 (image output device) and the bus master 1 ′ (decoding device) must be linked in band units. This means that the arbiter 100 needs to handle the priority of the bus master 1 (image output device) and the bus master 1 ′ (decoding device) equally. In the case of a laser printer, the image output device must output image data at a constant speed, so the priority of the bus master 1 needs to be the highest. Therefore, the image output device = bus master 1. On the other hand, the decoding device that needs to operate in conjunction with the image output device = bus master 1 ′.

  As described above, if the priority levels of the bus master 1 and the bus master 1 'remain at the same level, the following inconvenience occurs. In brief, the read request of the bus master 1 is compressed by the write request and write data of the bus master 1 ′.

FIG. 5 is an example of a diagram for explaining inconveniences when the priorities of the bus master 1 and the bus master 1 ′ are approximately the same. FIG. 5A shows a case where the bus master 1 is not pressed by the bus master 1 ′ for the sake of explanation. The bus master 1 only reads, but the bus master 1 'reads and writes. Therefore, the bus master 1 and the bus master 1 ′ have the following number of read channels and write channels.
Bus master 1 has 2 read channels (2 read DMACs)
Bus master 1 'has 2 channels of read channel (2 DMACs for read)
Bus master 1 'has 2 write channels (2 write DMACs)
In the left diagram of FIG. 5A, a command when the bus master 1 and the bus master 1 ′ request writing to the arbiter 100 is a circle, and a data when writing is requested is a rectangle. In the right diagram of FIG. 5A, the read data that the memory 400 makes a transfer request to the arbiter 100 is represented by a rectangle. The path through which the command and data on the left side in FIG. 5A flow is collectively referred to as a write path, and the path through which the data on the right side in FIG. 5A flows is collectively referred to as a read path. The following information flows.
Write path: Write request command, Read request command, Write data Read path: Read data According to the write path in the left diagram of FIG.
Read request command for CH1, CH2 of bus master 1,
Bus master 1 'CH1, CH2 read request command Bus master 1' CH1, CH2 write request command,
The write data of CH 1 and CH 2 of the bus master 1 ′ is flowing to the arbiter 100.

According to the lead path on the right side of FIG.
Read data of CH1 and CH2 of the bus master 1 Read data of CH1 and CH2 of the bus master 1 ′ is flowing to the arbiter 100.

  The arbiter 100 arbitrates between read requests and write requests, and after the arbitration, permits transmission of write data and read data. However, since any request is output to the arbiter, the arbiter has a tendency to give the right to use the bus master with more requests if the priority is equal. In FIG. 5A, since the read channel of the bus master 1 is 2CH and the read channel of the bus master 1 'is two channels, the number of channels is the same, so the read request of the bus master 1 is pressed against the write request of the bus master 1'. Not. As described above, even when the bus master 1 and the bus master 1 ′ having the same priority request bus acquisition at the same time, there is little inconvenience if the number of channels is the same.

FIG. 5B shows a case where the bus master 1 is pressed by the bus master 1 ′. The bus master 1 and the bus master 1 'have the following channels.
The read channel of the bus master 1 is 1 channel. The read channel of the bus master 1 'is 2 channels. The write channel of the bus master 1' is 2 channels.
As shown in FIG. 5B, when there is a difference in the number of channels simultaneously requesting bus acquisition between the bus master 1 and the bus master 1 ′, the bus master 1 is pressed by the bus master 1 ′ in the write path and the read path. In the write path, the read command of the bus master 1 is compressed, and in the read path, the read data of the bus master 1 is compressed.

Hereinafter, the reason why the bus master 1 is compressed by the bus master 1 ′ will be described in comparison with FIG.
1. Since the read request command of the bus master 1 that makes a bus acquisition request to the arbiter is small, the write request command of the bus master 1 ′ having the same priority enters the arbiter.
2. The amount of write data of the bus master 1 'increases as the write request command of the bus master 1' requesting the bus acquisition to the arbiter increases.
3. As the amount of write data of the bus master 1 'increases, it becomes difficult for the read request command of the bus master 1 that requests bus acquisition to reach the arbiter.
4). Since it becomes difficult for the read request command of the bus master 1 to reach the arbiter, the transfer efficiency of the read data of the bus master 1 flowing from the memory to the arbiter decreases.

  In view of the above problems, an object of the present invention is to provide an arbiter that does not impose the use efficiency of a bus master having a higher priority on a plurality of bus masters having the same priority.

  The present invention provides a bus arbiter that arbitrates bus acquisition requests from a plurality of bus masters connected to a common bus based on a preset priority of each bus master, the first bus master having the highest priority. Bus acquisition request monitoring means for monitoring the first bus acquisition request from the second bus acquisition request from the second bus master having the same priority as the first bus master, and the bus acquisition request monitoring Specific event detection means for acquiring a monitoring result of the means and detecting a specific event in which the frequency of the first bus acquisition request and the frequency of the second bus acquisition request satisfy a predetermined criterion; and the specific event Bus acquisition control means for acquiring a specific event detection signal from the detection means and limiting the frequency of the second bus acquisition request.

  To provide an arbiter that does not impair the usage efficiency of higher priority bus masters for multiple bus masters of similar priority.

It is an example of the figure explaining the memory access by each image processing means. It is an example of the figure explaining a fixed priority order system. It is an example of the figure explaining the process of the acquisition request of the conventional bus masters 1-3. It is an example of the figure demonstrated to a more specific example about the bus master 1 and bus master 1 '. FIG. 10 is an example of a diagram for explaining inconveniences when the priorities of the bus master 1 and the bus master 1 ′ are approximately the same. It is an example of the figure explaining the schematic characteristic of the arbiter of this embodiment. It is an example of the block diagram of the memory utilization system using an arbiter. It is an example of the figure explaining a request command. It is an example of the figure explaining the detection of a specific event. It is an example of the figure which shows typically the acquisition frequency of the request command and data in an arbiter. It is an example of a flowchart for explaining an operation procedure of an LSI. FIG. 3 is an example of a block diagram of an LSI using a memory (second embodiment). FIG. 10 is an example of a block diagram of an LSI using a memory (third embodiment).

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

FIG. 6 is an example of a diagram illustrating a schematic feature of the arbiter 100 of the present embodiment. The bus master 1 and the bus master 1 'have the same priority and are higher than the bus masters 2 and 3. The bus masters 4 and 5 are bus masters that are not subject to a bus acquisition request by the arbiter 100. Therefore, the arbiter 100 masks the bus acquisition request of the bus masters 2 and 3 when the bus master 1 or the bus master 1 ′ requests acquisition of the bus. However, since the bus masters 4 and 5 are not masked by the arbiter 100, the bus master 4 or 5 does not mask the bus acquisition request even if the bus master 1 or the bus master 1 'requests the bus acquisition.
The I event occurrence detection unit 15 detects that there is a possibility that the bus master 1 and the bus master 1 'may simultaneously press the read request or read data of the bus master 1 because the bus acquisition request is generated simultaneously.
The II bus acquisition control unit 13 receives notification of detection of a specific event, and generates a dummy request command (dummy bus acquisition request) for the bus master 5 (or 4) that is not to be masked.

  By inserting a dummy read request command of the bus master 5 into the arbiter 100, the bus occupancy rate of the bus master 1 'can be reduced, and the bus usage frequency of the bus master 1' can be temporarily reduced. Therefore, it is possible to prevent the read request command and read data of the bus master 1 from being pressed by the write request command and write data of the bus master 1 ′.

  Since the bus acquisition requests of the bus masters 4 and 5 are dummy, the arbiter 100 can be ignored. Therefore, the bus acquisition request of the bus masters 4 and 5 does not affect the read-side path, and the transfer efficiency of the bus master 1 does not decrease.

[Configuration example]
FIG. 7 is an example of a block diagram of a memory utilization system 600 using an arbiter. The LSI 120 and the memory 400 are connected via the system bus 12. The memory 400 is a high-speed memory such as an SDRAM.

  The LSI 120 includes bus masters 1 to 5 connected to the bus acquisition control unit 13, an arbiter 100, and a memory controller 11. The bus masters 1 and 1 ′ are connected to a request monitoring unit 14 (hereinafter referred to as request monitoring units 1 and 1 ′, respectively), and the two request monitoring units 1 and 1 ′ are connected to an arbiter 100. The request monitoring units 1 and 1 ′ are connected to the event occurrence detection unit 15, and the event occurrence detection unit 15 is connected to the bus acquisition control unit 13.

  In the image forming apparatus 200, the bus master 1, the bus master 1 ′, the bus master 2, and the bus master 3 are, for example, a bus master 1 = image output device, a bus master 1 ′ = decoding device, a bus master 2 = encoding device, and a bus master 3 = drawing device. .

  For example, the PC 300 or the scanner stores data to be printed in the image forming apparatus 200. As a result, the print data is stored in the memory 400.

  The CPU 202 executes a program, reads print data from the memory 400, analyzes it, and generates print data (drawing command) in an intermediate language. The CPU 202 stores the generated drawing command in the memory 400.

  The drawing device 203 reads the drawing command from the memory 400, analyzes the drawing command, applies gradation processing to the image data, and writes the binarized image data to the memory 400. Gradation processing is often performed in band units (an area obtained by dividing one page into 8 to 16 equal parts in the sub-scanning direction), and thus binarized image data may be referred to as band data.

  Next, the encoding device 204 reads the band data from the memory 400, encodes it with a binary image compression algorithm such as JBIG, and stores it in the memory 400.

  Next, the decoding device 205 reads the encoded data from the memory 400, decodes it, and stores it in the memory 400. The image output unit reads the decoded image data from the memory from the end of the address for each band, and transfers it to an engine controller (not shown). The engine controller controls the printer engine and prints print data on paper or the like with the printer engine. Therefore, the image output device needs to access the memory 400 with the highest priority so that the printer engine can print at a constant speed. Also, a decoding device that supplies image data to the image output device needs to have the same priority.

  Such a relationship can vary depending on the type and number of image processing until output, whether or not the processed data is stored in the memory 400, and whether or not there is a bus acquisition conflict. Therefore, the correspondence between each bus master and the image processing means is only an example. Further, it is not necessary that a plurality of bus masters be mounted on one LSI 120. For example, the CPU 202 is often arranged outside the LSI 120.

Below,
Bus master 1, bus master 1 ': highest priority Bus master 2, bus master 3: Assume that the priority is the next highest.

  The request monitoring unit 1 counts the number of read requests in the bus master 1 within a certain period, and notifies the event occurrence detection unit 15 directly or via the request monitoring unit 1 ′. Similarly, the request monitoring unit 1 ′ counts the number of read requests and write requests within a certain period (request number measurement time described later) of the bus master 1 ′ and notifies the event occurrence detection unit 15. The request monitoring unit 1 transparently transfers the read request of the bus master 1 as it is to the arbiter 100, and the request monitoring unit 1 ′ transparently transfers the read request and the write request of the bus master 1 ′ as it is to the arbiter 100. .

  The event occurrence detection unit 15 detects a specific event based on the number of read requests of the bus master 1 within a certain period and the number of read requests and write requests within the certain period of the bus master 1 ′. The detection of the specific event will be described later. The event occurrence detection unit 15 notifies the bus acquisition control unit 13 that a specific event has been detected by transmitting an event detection signal.

  When acquiring the event detection signal, the bus acquisition control unit 13 causes a dummy read request command to be issued to at least one of the bus master 4 and the bus master 5 that are not masked. At this time, information indicating a dummy is added to the dummy header of the read request command. The dummy header will be described later.

  The dummy acquisition request may be a read request in order to suppress the compression of the read request command of the bus master 1, but may be a write request to limit the write request command of the bus master 1 ′.

  Although the bus acquisition control unit 13, the request monitoring units 1, 1 ', and the event occurrence detection unit 15 are illustrated outside the arbiter 100, the arbiter 100 is a means for supporting arbitration of acquisition requests by the arbiter 100. Is part of.

  The arbiter 100 has a command determination unit 16 for interpreting the command. The command determination unit 16 detects a dummy request command. The arbiter 100 analyzes the command headers of the read request and write request that the command determination unit 16 determines to be not a dummy request command, distinguishes between read and write, and specifies the access destination address.

  The arbiter 100 compares the priority of the request source bus master in each of the read request command and the write request command, gives priority to the request having the higher priority, and outputs the request to the memory controller 11. Further, while processing a request from a bus master having a high priority, a request from a bus master having a low priority is masked.

  In the case of this embodiment, based on the dummy header of the request command, the command determination unit 16 determines whether the read request or the write request is a dummy, and if it is determined to be a dummy, issues a request command to the memory controller 11. Discard without.

  Thereby, the read request of the bus masters 4 and 5 can reach the arbiter 100, and the bus use frequency of the bus master 1 'can be temporarily reduced. Further, since the arbiter 100 does not output a dummy read request command to the memory controller 11 side of the arbiter 100, the bus congestion between the memory controller 11 and the memory is not affected.

[Dummy request command]
FIG. 8 is an example of a diagram illustrating the format of the request command. The request command has fields of a dummy header, a transfer content protocol, transfer data, and a transfer end protocol.
-"Dummy" or "No Dummy" is stored in the dummy header.
In the transfer content protocol, write request / read request identification information, a transfer destination address and data size in the case of a read request, a transfer destination address and data size in the case of a write request, and the like are stored.
In the case of a write request, the transfer data or transfer source address is stored in the transfer data.
The transfer end protocol is a field for notifying the end of transfer.

  Therefore, a request command in which “Dummy” is stored in the dummy header is a dummy request command.

[Detection of specific events]
FIG. 9 is an example of a diagram illustrating detection of a specific event. FIG. 9 illustrates a case where there is a difference in the number of channels that are simultaneously issuing bus acquisition requests between the bus master 1 and the bus master 1 ′.

  The number of read request channels of the bus master 1 is four (CH1 to CH4), the number of read request channels of the bus master 1 'is two (CH1 and CH2), and the number of write request channels is two (CH3 and CH4). is there. Of these, the bus master 1 outputs a read request command only to CH1, but the bus master 1 'outputs a request command to all of CH1-4. As described above, in such a state, it becomes difficult for the read request command and read data of the bus master 1 to reach the arbiter 100.

  The request monitoring unit 1 counts the number of read request commands of CH1 to CH4 at regular time intervals indicated by dotted lines. The request monitoring unit 1 ′ also counts the number of CH1 to CH4 write request commands and the number of read request commands at the same fixed time. In the illustrated example, the count result of the request monitoring unit 1 is 3, and the count result of the request monitoring unit 1 ′ is 16.

  The event occurrence detection unit 15 acquires these count results, and detects the occurrence of a specific event when the difference between the two count results is a predetermined value or more. The predetermined value may be about n to 2n, for example, where n is the maximum number of request commands counted in a certain time in one channel, but the predetermined value can be set as appropriate.

[Handling of data inside the arbiter]
FIG. 10 is an example of a diagram schematically showing the frequency of acquisition of a read request command, a write request command, write data, or read data inside the arbiter. FIG. 10A is the same as FIG. 5A described above, and shows an example in which the transfer of the read request command and read data of the bus master 1 is under pressure.

  On the other hand, FIG. 10B shows an example in which the transfer of the read request command and read data of the bus master 1 is not compressed by the dummy request command.

In the left diagram of FIG. 10B, the request command for the arbiter 100 of the bus master 1, the bus master 1 ′, and the bus master 5 is circular, and the write data is rectangular. In the right diagram of FIG. 10B, the read data that the memory 400 requests to transfer to the arbiter 100 is represented by a rectangle. As shown in the left diagram of FIG. 10B, each bus master has the following channels.
The read request command of bus master 1 is 1CH,
The read request command of the bus master 1 'is 2CH,
The bus master 1 'write request command is 2CH,
The read request command of the bus master 5 is 1CH,
That is, when a specific event is detected, the bus master 5 generates a dummy read request command, so that 1 CH of the read request command for the bus master 5 is secured as shown in the left diagram of FIG. According to such a configuration, the read request command and read data of the bus master 1 are prevented from being pressed by the write request command and write data of the bus master 1 ′ by the following operation.

1. Even if the number of read request commands of the bus master 1 that requests the arbiter to acquire a bus is small, the read request command of the bus master 5 that is not masked reaches the arbiter 100.
2. For this reason, the number of write request commands of the bus master 1 ′ reaching the arbiter is difficult to increase, and the amount of write data flowing from the bus master 1 ′ to the arbiter does not increase.
3. Since the amount of write data of the bus master 1 'does not increase, the read request command of the bus master 1 that makes a bus acquisition request to the arbiter is not compressed.
4). Since the read request of the bus master 5 is a dummy and is discarded by the arbiter 100, the transfer efficiency of read data transmitted from the memory to the arbiter 100 is not reduced.

[Operation procedure]
FIG. 11 is an example of a flowchart for explaining the operation procedure of the arbiter 100.

  The bus master 1 outputs a read request command to the request monitoring unit 1 asynchronously with the bus master 1 ′ (S1). The request monitoring unit 1 outputs a read request command to the arbiter 100 (S2).

  The bus master 1 ′ outputs a read request command or a write request command to the request monitoring unit 1 ′ asynchronously with the bus master 1 (S3). The request monitoring unit 1 ′ outputs a read request command or a write request command to the arbiter 100 (S4).

  The request monitoring unit 1 outputs a read request command to the event occurrence detection unit 15 (S5).

  The request monitoring unit 1 ′ outputs a read request command or a write request command to the event occurrence detection unit 15 (S6).

  Since the priority of the read request commands from the bus master 1 and the bus master 1 ′ is equal, the arbiter 100 gives the right to use the bus master that has output the request earlier, for example. The arbiter 100 gives the right to use the bus master 1 'to the write request command from the bus master 1' because the bus master 1 'has the highest priority. Such a large number of requests to the arbiter 100 of the bus master 1 ′ and transfer of write data cause the read request of the bus master 1 to be pressed.

  The event occurrence detection unit 15 generates a specific event when the difference between the number of read request commands of the bus master 1 and the number of read request commands of the bus master 1 ′ and the total of the read request commands is equal to or greater than a predetermined value. Is detected (S7). The event occurrence detection unit 15 that has detected the occurrence of the specific event outputs an event detection signal to the bus acquisition control unit 13 (S8).

  When acquiring the event detection signal, the bus acquisition control unit 13 causes at least one of the bus masters 4 and 5 to output a read request command (S9).

  In response to the request from the bus acquisition control unit 13, the bus master 5 outputs a dummy read request command to the arbiter 100 (S10).

  The command determination unit 16 of the arbiter 100 refers to the dummy header of the read request command and discards it when it is detected as a dummy. Therefore, read data does not flow between the memory and the memory controller 11.

  As described above, the arbiter 100 of this embodiment inserts the read request command of the bus masters 4 and 5 when the bus masters 1 and 1 'having the same priority output requests to the arbiter. As a result, the bus usage frequency of the bus master 1 'can be temporarily reduced. Therefore, it is possible to prevent the read request and read data of the bus master 1 from being pressed by the write request command and write data of the bus master 1 ′.

  In this embodiment, an arbiter 100 capable of stopping a function associated with detection of a specific event will be described.

  FIG. 12 is an example of a block diagram of a memory utilization system 600 using an arbiter. In FIG. 12, the description of the same part as in FIG. 7 is omitted.

  The LSI 120 of this embodiment newly has an ON / OFF switching unit 17. When there is no use case where the bus master 1 ′ compresses the bus master 1, the ON / OFF switching unit 17 stops the request monitoring units 1, 1 ′, the event occurrence detection unit 15, and the command determination unit 16. For example, the ON / OFF switching unit 17 disconnects the clock signal line of the clock supplied to the request monitoring unit 1, 1 ′, the event occurrence detection unit 15, and the command determination unit 16. Thereby, the power consumption of the LSI 120 can be reduced.

  Whether or not there is a use case is determined by the manufacturer or user of the LSI 120 (hereinafter simply referred to as a developer). The developer determines whether or not there is a use case in which the bus master 1 ′ compresses the bus master 1, and describes initial setting parameters in a ROM or main program (not shown). The main program sets parameters in the register of the ON / OFF switching unit 17 when the LSI 120 is activated. The ON / OFF switching unit 17 stops the request monitoring units 1 and 1 ′, the event occurrence detection unit 15, and the command determination unit 16 according to the parameters stored in the register.

  Since the bus master 1 and the bus master 1 ′ are directly connected to the arbiter 100, the request monitoring units 1 and 1 ′ can output a request command to the arbiter 100 even when the operation is stopped.

  According to the present embodiment, the power consumption of the LSI 120 can be suppressed when there is no bus master 1 and bus master 1 ′ to which an equivalent priority should be given, or when there is no significant influence on the processing even if it exists.

In the present embodiment, an LSI 120 capable of controlling the frequency of occurrence of dummy request commands will be described.
FIG. 13 is an example of a block diagram of a memory utilization system 600 using an arbiter. In FIG. 13, the description of the same part as in FIG. 7 is omitted.

The LSI 120 of this embodiment newly has a condition storage unit 18. The condition storage unit 18 stores conditions for the event occurrence detection unit 15 to detect the occurrence of a specific event. The condition storage unit 18 is a storage medium such as a ROM or a register. The event occurrence detection unit 15 switches the condition for detecting the occurrence of the specific event based on the bit pattern stored in the condition storage unit 18. For example, in the following bit pattern, the conditions for detecting the occurrence of a specific event are as follows. “X” is undefined.
XX01: A specific event is detected when the difference between the number of read request commands of the bus master 1 and the sum of the write request command and the read request command of the bus master 1 ′ is a predetermined number or more.
XX10: A specific event is detected when the difference between the number of read request commands of the bus master 1 and the number of read request commands of the bus master 1 ′ is equal to or greater than a predetermined number.
0011: A specific event is detected when the difference between the number of read request commands of the bus master 1 and the number of write request commands of the bus master 1 ′ is equal to or greater than a predetermined number.
01XX: The predetermined number is 3
10XX: The predetermined number is 6
11XX: Predetermined number is 9
The method of setting conditions for detecting the occurrence of a specific event is the same as in the second embodiment. That is, the developer describes a condition (bit pattern) for detecting the occurrence of a specific event in a ROM or main program (not shown). The main program sets the bit pattern in the register of the condition storage unit 18 when the LSI 120 is activated.

  When detecting the occurrence of a specific event, the event occurrence detection unit 15 determines whether a specific event has occurred according to the bit pattern stored in the condition storage unit 18.

  As described above, by changing the conditions for detecting the occurrence of the specific event, it is possible to prevent the data read by the dummy request command from being excessively generated and the transfer efficiency of the bus master 1 'from being lowered. . Further, since dummy leads are less likely to occur than expected, it is possible to cope with a case where the effect of the present embodiment cannot be obtained as expected.

  In FIG. 13, the ON / OFF switching unit 17 is not illustrated, but the ON / OFF switching unit 17 may be mounted together with the condition storage unit 18. In this case, the condition for detecting the occurrence of the specific event can be made variable, and the power consumption can be suppressed by the ON / OFF switching unit 17.

DESCRIPTION OF SYMBOLS 11 Memory controller 12 System bus 13 Bus acquisition control part 14 Request monitoring part 15 Event generation | occurrence | production detection part 16 Command judgment part 17 ON / OFF switching part 18 Condition storage part 100 Arbiter 110 Bus master 200 Image forming apparatus 600 Memory utilization system

JP 2002-269032 A

Claims (9)

A bus arbiter that arbitrates bus acquisition requests from a plurality of bus masters connected to a common bus based on a preset priority of each bus master,
A bus acquisition request for monitoring a first bus acquisition request from the first bus master having the highest priority and a second bus acquisition request from the second bus master having the same priority as the first bus master. Monitoring means;
A specific event detection unit that acquires a monitoring result of the bus acquisition request monitoring unit and detects a specific event in which the frequency of the first bus acquisition request and the frequency of the second bus acquisition request satisfy a predetermined criterion. When,
Bus acquisition control means for acquiring a specific event detection signal from the specific event detection means and limiting the frequency of the second bus acquisition request;
Having a bus arbiter. The specific event detection means counts the number of the first bus acquisition requests and the number of the second bus acquisition requests within a predetermined time, thereby determining the frequency of the first bus acquisition requests and the second bus acquisition requests. Find the frequency of bus acquisition requests
The bus arbiter according to claim 1. When the specific event detection signal is acquired, the bus acquisition control unit generates a third bus acquisition request from a third bus master whose bus acquisition request is not masked by the second bus acquisition request of the second bus master. ,
The bus arbiter according to claim 1 or 2, characterized by the above. When the bus acquisition control unit causes the third bus master to generate the third bus acquisition request, the bus acquisition control unit indicates to the third bus master that the third bus acquisition request is a dummy. Add a dummy header,
The bus arbiter according to claim 3, wherein If the dummy header is detected, discard the third bus acquisition request without arbitrating the bus acquisition request based on the third bus acquisition request;
The bus arbiter according to claim 4, wherein A function stop unit capable of stopping at least one of the bus acquisition request monitoring unit or the specific event detection unit;
The bus arbiter according to any one of claims 1 to 5, wherein A determination condition storage means for storing a determination condition of an arbitrary reference,
The specific event detection means detects a specific event based on the determination condition stored in the determination condition storage means;
The bus arbiter according to any one of claims 1 to 6, wherein The bus arbiter according to any one of claims 1 to 7,
Multiple bus masters,
A memory connected via a bus;
A memory controller that accesses the memory according to an instruction from the bus arbiter that arbitrated a bus acquisition request;
A bus arbiter system. A bus arbiter processing method for arbitrating bus acquisition requests from a plurality of bus masters connected to a common bus based on a preset priority of each bus master,
The bus acquisition request monitoring means obtains the first bus acquisition request from the first bus master having the highest priority and the second bus acquisition from the second bus master having the same priority as the first bus master. Monitoring the request;
The specific event detection means acquires a monitoring result of the bus acquisition request monitoring means, and detects a specific event in which the frequency of the first bus acquisition request and the frequency of the second bus acquisition request satisfy a predetermined standard. Detecting step;
A bus acquisition control means for acquiring a specific event detection signal from the specific event detection means and limiting the frequency of the second bus acquisition request;
A method for processing a bus arbiter having

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