JP2013054625A - Information processor and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which can share a result of an operation in each processor effectively.SOLUTION: An information processor comprises: program storage means 11 to store a program; operation result storage means 45 to store a result of an operation in each core; command readout means 21 to readout an instruction set of command as many as cores from the program storage means in execution order and to store the instruction set in a primary storage unit; command distribution means 32 to store the command included in the instruction set in a command queue of each core; command dependencies determination means 33 to determine whether the command whose operation target is the result of an operation that the command included in a first instruction set stored in the primary storage unit is operated by a first core is included in a second instruction set executed later than the first instruction set, and whether a second core different from the first core executes the command; and a copying means 34 to copy the value of the operation result storage means of the first core in the operation result storage means of the second core when the command dependencies determination means determines that the second core execute the command included in the second instruction set.

Description

  The present invention relates to an information processing apparatus in which a plurality of cores execute instructions in parallel.

  As an approach for improving the processing speed of a processor, not only an increase in operating frequency but also a multiprocessor with a plurality of processors and a multicore with a plurality of CPU cores in a processor are known. In multiprocessors and multicores, processing efficiency improves as the degree of parallelism of processing increases. Therefore, it is important to distribute processing so that the degree of parallelism increases. Conventionally, a technique for improving the degree of parallelism has been proposed (see, for example, Patent Document 1). Patent Document 1 discloses a multiprocessor in which tasks are assigned to a plurality of processors in units of tasks, and tasks that are in an executable state are assigned to processors that are not executing any task.

  However, in the conventional technique, processing is executed in units of tasks, so it is actually difficult to realize parallel operation due to bus connection between task processes, shared memory access, and the like, and it is difficult to maximize the performance of multicore. In addition, in order to assign a task to a processor having a surplus capacity, the load on the OS for monitoring the processing load of the processor increases, and the control for assignment becomes complicated.

  In addition, a technique has been proposed in which a certain processor controls a plurality of other processors to execute processing in parallel (see, for example, Patent Document 2). Patent Document 2 discloses a microprocessor system in which one RISC type processor controls a plurality of VLIW processors. The RISC processor decodes the instruction and instructs the VLIW processor about the control signal, the operation clock frequency, and the power supply voltage. Each VLIW processor executes an application program.

  In addition, a technique for distributing processing in units of instructions instead of in units of tasks has been proposed (see, for example, Patent Document 3). In Patent Document 3, the dependency relationship of instructions stored in the instruction buffer is checked, an instruction having no dependency relationship is issued to a plurality of processors, and if there is a dependency relationship, the execution cycle of the execution unit of one instruction is delayed A superscalar processor is disclosed.

JP 2008-146503 A JP 2002-032218 A JP 2011-128672 A

  However, the technique described in Patent Document 2 has a problem that no consideration is given to the case where data needs to be used between processors. In Patent Document 2, when an operation result performed by one of a plurality of VLIW processors is used in another operation by another processor, the operation result is not stored in the register of the other processor. I need it. In other words, the other processor needs to acquire the operation result from the processor having the operation result. This is processing that does not need to be considered in a processing method in which sequential processing is performed by one processor.

  On the other hand, in Patent Document 3, since the operation results of the two execution units are stored in a common register file, data exchange between processors is possible. However, if the register file is common, writing to and reading from the register file may become a bottleneck, and in a multiprocessor system, it can be said that it is easier to improve the processing efficiency if each processor has an independent register file. In Patent Document 3, it is not considered how to share an operation result between processors when the register file is independent.

  In view of the above problems, an object of the present invention is to provide an information processing apparatus that can efficiently share an operation result between processors.

  In view of the above problems, the present invention provides an information processing apparatus in which a plurality of cores execute instructions in parallel, operation result storage means for storing operation results for each core, program storage means for storing programs, and the number of cores Instruction reading means for reading out the instruction set including the instructions from the program storage means in the execution order and storing it in the primary storage section, instruction distribution means for storing the instructions included in the instruction set in the instruction queue of each core, and the primary storage section The second core is a second instruction set that is executed after the first instruction set. An instruction dependency relationship determining means for determining whether or not a second core different from the first core is executed, and the instruction dependency relationship determining means is configured such that the second core has a second instruction set. When determining to execute the dependent instructions contained, it has a copy unit for the value of the computation result storage means of the first core, copying to the arithmetic result storage means of the second core, the.

  It is possible to provide an information processing apparatus that can efficiently share a calculation result between processors.

It is an example of the figure explaining the schematic characteristic of this embodiment. It is an example of the hardware block diagram of the multi-core microcomputer mounted in ECU. It is an example of the figure which illustrates execution of the instruction by CPU1-3 typically. It is an example of the figure which illustrates typically execution of the command by CPU1-3 when a failure is detected. It is a figure which shows an example of the operation | movement procedure of an operation sequence control circuit. It is an example of a diagram for explaining the wait of the CPU due to instruction dependency. It is a figure which shows an example of the operation | movement procedure of an operation | movement sequence control circuit when an instruction dependence relationship is detected. It is an example of the figure explaining adjustment by processing latency and Wait. An example of an operation procedure of the operation sequence control circuit when each CPU executes an instruction having a different processing latency is shown. It is an example of the figure explaining refresh of a register. It is a figure which shows an example of the operation | movement procedure of an operation | movement sequence control circuit when there exists an instruction dependence relationship between instruction sets.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is an example of a diagram illustrating schematic features of the present embodiment. The multi-core microcomputer has three CPUs (CPU1 to CPU3). Each of them executes a series of instruction codes (hereinafter simply referred to as instructions) of one program in a distributed manner. In FIG. 1, the following instructions are executed.
CPU1: A + B → C
CPU2: Z + D → E
CPU3: F + G → H
The alphabet at the end of the arrow is the calculation result, and this calculation result is stored in a register of each CPU.

Assume that the next instruction of the program executed by the CPU 1 is the following instruction.
A + E → I
The operand A is stored in the CPU 1 register, while the operand E is stored in the CPU 2 register. For this reason, the CPU 1 cannot perform the operation as it is. Therefore, the operation sequence control circuit copies the operation result E stored in the register of CPU2 to the register of CPU1. Hereinafter, this operation may be referred to as register refresh.

  Thus, by distributing the processing in units of instructions, it is possible to improve the degree of parallelism of processing compared to distributing the processing in units of tasks. In addition, since the degree of parallelism of processing is improved, even if a situation occurs in which operation results are distributed to each CPU, the dependency of instructions can be eliminated by refreshing the registers.

  First, multi-core microcomputers generally include the normal cores because if one core fails even though there are multiple cores, the influence of the failed core will propagate to the normal core via the bus etc. It is said that it is necessary to stop all cores (that is, the entire microcomputer). Stopping the multi-core microcomputer in engine control, etc. has little effect on the user, but if the multi-core microcomputer such as EPS (Electric Power Steering) or ECB (Electric Control Braking system) is suddenly stopped, the driver feels awkward Makes you feel. For this reason, it is common to prepare a backup device in the case of an EPS or ECB failure in the vehicle, and redundant installation of functions brings an increase in cost. Therefore, it is desired that multi-core microcomputers are designed based on a fault-tolerant design policy (which can provide necessary functions even if a failure occurs). To do so, it is necessary to use the characteristics of multi-core microcomputers. It is considered effective.

  Conventionally, a multi-core microcomputer equipped with a lock step function for executing the same processing with a plurality of cores is known. However, the lockstep function is a technique for improving the reliability and the failure detection rate, and only one calculation result can be obtained with a plurality of cores.

  In the present embodiment, a multi-core microcomputer that improves the robustness by stopping only the core that has failed at the time of failure and continuing the calculation by the normal core using the characteristics of the multi-core microcomputer will be described.

  FIG. 2 shows an example of a hardware configuration diagram of the multi-core microcomputer 100 mounted on the ECU. The multi-core microcomputer 100 can be mounted not only on the engine ECU, EPS-ECU and ECB-ECU described above but also on various things such as an HV (hybrid) -ECU and a gateway ECU. Moreover, you may mount in integrated ECU in which the function of several ECU was integrated.

  The multi-core microcomputer 100 includes a flash ROM 11 and an operation sequence control circuit 13 connected to the instruction bus 12, a plurality of CPUs 14 (referred to as CPU 1 to n when distinguished), a failure diagnosis device 16, and an I / O 17 connected to the data bus 15. , RAM 18, DMAC 19, and INTC 20.

  The multi-core microcomputer 100 has a plurality of CPUs 1 to n. Therefore, the processor of the multi-core microcomputer 100 is sometimes called a multi-CPU, but the microcomputer itself is often mounted on a single chip, so that it is not meaningful to distinguish from the multi-core. As long as a plurality of cores are mounted, a processor called multi-CPU or multi-core can be applied to the multi-core microcomputer 100 of this embodiment. The multi-core microcomputer 100 includes a homogeneous multi-core having a plurality of the same processor cores and a heterogeneous multi-core having a plurality of different types of cores. In this embodiment, each core distributes one program in units of instructions. It is homogeneous multicore in that it performs. However, some cores may have different configurations.

  The CPU 14 includes a register set 44 connected to the data bus 15, a CPU register 45, a register set 44, an arithmetic device 46 connected to the CPU register 45, a program counter 41, an instruction queue 42, and an instruction decoder 43. Data stored in the RAM 18, sensor detection values input to the I / O 17, and the like are read out to the register set 44 via the data bus 15. The CPU register 45 is written back with the calculation result of the calculation device 46. The register set 44 and the CPU register 45 are a set of a plurality of registers.

  The program counter 41 stores an address of an instruction executed by the CPU stored in the flash ROM 11. In this embodiment, since the operation sequence control circuit 13 sets instructions to each of the CPUs 1 to n, the program counter 41 is not necessary. The CPU 14 can also execute the program independently regardless of the operation sequence control circuit 13. In this case, the program counter 41 outputs the address to the instruction bus 12 and reads the instruction at that address to the instruction queue 42. Each time one instruction is read, the program counter 41 increases the stored address value to prepare for reading the next instruction.

  The instruction queue 42 is a FIFO (First In, First Out) type storage means and can hold a plurality of instructions (for example, about 5 to 20). Instructions are read into the instruction queue 42 in the order of execution. The instruction decoder 43 decodes the instruction in the instruction queue 42 and outputs a signal to the arithmetic unit 46 and peripheral circuits through a control line. Depending on the decoding result, for example, the arithmetic unit 46 is instructed to perform addition, multiplication, subtraction, shift, division, and the like. Further, since the operand to be operated by the instruction is specified by decoding, data is input from the register set 44 and the CPU register 45 to the arithmetic unit 46 according to the decoding result.

  The arithmetic unit 46 includes an ALU (Arithmetic and Logic Unit), an LSU (Load Store Unit), a MUL (multiplier), and a DIV (divider). The arithmetic unit 46 performs various arithmetic operations on the data input from the register set 44 and the CPU register 45. The calculation result is written back to the CPU register 45 and again becomes a calculation target or written to the RAM 18.

  The arithmetic unit 46 includes pipeline control that divides the execution procedure of one instruction for each stage and executes each stage simultaneously. The number of stages varies depending on the design, but each stage includes IF (Instruction Fetch), ID (Instruction Decode), EX (Execute), MA (Memory Access), and WB (Write Back). By pipeline control, one instruction can be executed in one clock.

  The operation sequence control circuit 13 includes a common instruction queue 21, a CPU bus control unit 22, and an instruction scheduler 23. The operation sequence control circuit 13 operates the CPUs in parallel in units of instructions. Further, it is determined whether or not the register needs to be refreshed. If necessary, data is exchanged between the CPUs 1 to n.

  The operation sequence control circuit 13 and the CPUs 1 to n are connected so as to be connectable and disconnectable, and the operation sequence control circuit 13 physically disconnects the CPU 14 in which a failure is detected. In this case, the execution of the program can be continued only by the normal CPU 14. If the failed part cannot be specified, the entire microcomputer is stopped.

  The common instruction queue 21 reads and stores instructions (instruction codes 1 to n in the figure) executed by the CPUs 1 to n from the flash ROM 11. The common instruction queue 21 monitors the pipeline stage of each CPU, and each time the pipeline stage progresses, instructions for the number of CPUs (three instructions when there are three CPUs; hereinafter, instructions for the number of CPUs). Read “instruction set”) from the flash ROM 11. Each instruction in the instruction set is set in the instruction queue 42 of CPU 1 to CPUn by the instruction queue control unit 32.

  The CPU bus control unit 22 includes a pipeline synchronization unit 31, an instruction queue control unit 32, an instruction dependency determination unit 33, a CPU register synchronization unit 34, and an external access control unit 35. The pipeline synchronization unit 31 synchronizes the pipeline stages of the CPUs 1 to n. With this control, when the CPU 1 executes the IF stage, the other CPUs 2 to n also execute the IF, and when the ID stage is executed, the other CPUs 2 to n also execute the ID. It is possible to synchronize timing and timing at which execution results are obtained. The EX stage differs in the number of clocks (processing latency) consumed by instructions. For this reason, as will be described in the third embodiment, the pipeline synchronization unit 31 is configured so that the CPU executing the instruction with the largest processing latency completes the other CPUs so that the clocks consumed by the CPUs are the same. Wait. Thereby, each CPU can synchronously execute the stage from the IF at the same timing.

  The instruction queue control unit 32 decomposes the instruction set acquired from the common instruction queue 21 into instructions and sets the instruction sets in the instruction queues 42 of the CPUs 1 to n. If the number of CPUs 14 is three, instruction code 1 is set in CPU 1, instruction code 2 is set in CPU 2, and instruction code 3 is set in CPU 3. In the next cycle, the instruction queue control unit 32 sets the instruction code 4 in the CPU 1, sets the instruction code 5 in the CPU 2, and sets the instruction code 6 in the CPU 3. As described above, the order of instructions and the order of assignment to the CPU are fixed, but are not necessarily fixed.

  The instruction dependency determination unit 33 determines whether each instruction is an instruction having an instruction dependency that requires an execution result of an instruction prior to the instruction. The instruction dependency determining unit 33 notifies the pipeline synchronization unit 31 of instructions having an instruction dependency relationship and instructions that require execution results.

  The CPU register synchronization unit 34 refreshes the register set 44 or the CPU register 45 of each CPU 1 to n to the same data. That is, when the data of the register set 44 or CPU register 45 of the CPU 1 is necessary for the calculation of the CPU 2, the CPU register synchronization unit 34 converts the data of the register set 44 or CPU register 45 of the CPU 1 into the register set 44 or CPU register of the CPU 2. Copy to 45.

  The external access control unit 35 arbitrates external access (bus access) from each of the CPUs 1 to n and gives an access right to one CPU. Arbitration methods are determined in advance, such as priority order and round robin.

  The instruction scheduler 23 updates the common instruction queue 21 when receiving a notification of an external interrupt from the INTC 20. That is, when an external interrupt occurs, the CPU 14 needs to execute a task according to the content of the interrupt, so the instruction set is read from the address where the program of the task is stored and set in the common instruction queue 21.

  The instruction scheduler 23 also updates the common instruction queue 21 for branch instructions and the like. That is, the instruction queue control unit 32 determines the branch destination address when the instruction executed by the CPU 14 is a branch instruction, and the address determined by the CPU with reference to the status flag when the instruction is a comparison instruction. The scheduler 23 is notified. The instruction scheduler 23 reads the instruction set from the branch destination address and sets it in the common instruction queue 21.

  An example of the failure diagnosis apparatus 16 is WDT. The WDT is a timer that monitors the execution state of the program for each of the CPUs 1 to n, and detects an abnormality of the CPUs 1 to n because the CPUs 1 to n do not reset the timer within a predetermined time. Alternatively, the distributed execution in units of instructions may be temporarily stopped, and a failure may be detected based on whether each CPU 1 to n executes the same instruction and the result is the same. Moreover, the distributed execution of the instruction unit is temporarily stopped, and each of the CPUs 1 to n executes a self-diagnosis program separately from the application, and based on whether or not the value matches the expected value, the failure of the CPUs 1 to n is determined. It may be detected.

  Various sensors, ADC, DAC, CANC (CAN Controller), an actuator, a driver circuit of the actuator, and the like are connected to the I / O 17. The DMAC 19 records the data input from the I / O 17 in the RAM 18 without going through the CPUs 1 to n, receives the request from the CPUs 1 to n, and transfers the data from the designated address of the RAM 18 to the sensor or actuator.

  The INTC 20 receives an interrupt from the failure diagnosis device 16, the I / O 17, etc., and interrupts the operation sequence control circuit 13. By the interruption, the operation sequence control circuit 13 can switch the processes executed by the CPUs 1 to n.

[Execution mode]
FIG. 3 is an example of a diagram schematically illustrating execution of instructions by the CPUs 1 to 3. The commands 1 to 15 in the vertical direction are the execution order of one program. Moreover, 1 to 10 in the horizontal direction means the passage of time, for example, the number of clocks or the number of cycles.

  Time 1: CPU 1 fetches instruction 1 from instruction queue 42, CPU 2 fetches instruction 2 from instruction queue 42, and CPU 3 fetches instruction 3 from instruction queue 42.

  Time 2: CPU 1 decodes instruction 1, CPU 2 decodes instruction 2, and CPU 3 decodes instruction 3.

          Also, by pipeline control, the CPU 1 fetches the instruction 4 from the instruction queue 42, the CPU 2 fetches the instruction 5 from the instruction queue 42, and the CPU 3 fetches the instruction 6 from the instruction queue 42.

  At times 3-5, the CPUs 1-3 advance each stage, and at time 5, the five stages IF, ID, EC, MA, and WB are executed simultaneously. Therefore, after time 5, the execution results of the three instructions of the CPUs 1 to 3 are obtained every clock. That is, a total of 15 execution results are obtained during the time 5-9. As described above, the CPUs 1 to 3 execute instructions in parallel by three instructions, so that the multicore performance can be maximized.

  FIG. 4 is an example of a diagram schematically illustrating execution of instructions by the CPUs 1 to 3 when a failure is detected. The instructions 1 to 6 are normally executed as in FIG. The failure diagnosis device 16 notifies the operation sequence control circuit 13 of the failed CPU. As a result, the operation sequence control circuit 13 is physically disconnected from the CPU 14 in which the failure is detected, and is excluded from the instruction execution target.

  When the CPU 1 fails, the operation sequence control circuit 13 distributes and executes instructions only with the CPUs 2 and 3. For this reason, after the CPU 1 has failed, execution results of two instructions are obtained every clock.

  Note that when a failure of the CPU 1 is detected, any CPU that has already been assigned to the CPU 1 by the instruction queue control unit 32 is not executed. For this reason, the instruction queue control unit 32 assigns again to the CPUs 2 and 3 from the instruction next to the last instruction executed by the CPUs 1 to 3 until the CPU 1 fails. For example, when the CPUs 1 to 3 execute instructions 6 until the CPU 1 breaks down, the instruction queue control unit 32 assigns the instructions 7 and 8 to the CPUs 2 and 3. As a result, the instructions 7, 9, 11, and 13 are executed in parallel by the CPU 2, and the instructions 8, 10, 12, and 14 are executed in parallel by the CPU 3.

  Therefore, as long as no failure of all the CPUs 14 is detected, the multi-core microcomputer 100 can continue the operation even if the processing speed decreases.

  FIG. 5 is a diagram illustrating an example of an operation procedure of the operation sequence control circuit 13. For example, the operation sequence control circuit 13 determines whether or not a failure is notified from the failure diagnosis device 16 for each clock (S10).

  If no failure is detected, the instruction scheduler 23 reads the instruction sets for the number of CPUs 14 into the common instruction queue 21 (S20).

  On the other hand, when a failure is detected (Yes in S20), the operation sequence control circuit 13 disconnects the failed CPU 14 (S50). Further, the operation sequence control circuit 13 notifies the instruction scheduler 23 and the common instruction queue 21 of the number of CPUs that have not failed or the number of failed CPUs, thereby adjusting the number of instructions to be read at a time as an instruction set. To do. Further, the operation sequence control circuit 13 notifies the instruction queue control unit 32 of the CPU 14 that has not been disconnected.

  The subsequent processing is common regardless of whether or not the CPU 14 has failed. That is, the common instruction queue 21 reads instructions for the number of CPUs 14 as an instruction set (S20).

  Next, the instruction queue control unit 32 assigns each instruction of the instruction set read from the common instruction queue 21 to the CPUs 1 to n (S30).

  The pipeline synchronization unit 31 advances one stage while synchronizing the execution stages of the CPUs 1 to n (S40). Thereafter, the process is repeated from step S10.

  According to the multi-core microcomputer 100 of the present embodiment, a failed CPU can be physically disconnected, and processing can be continued only with a normal CPU. Even if the number of operating CPUs 14 changes, the calculation can be continued by adjusting the number of instructions included in the instruction set and the CPU to which the instructions are assigned. Therefore, complicated control such as task replacement (context switch) is not required as in the case where processing is distributed in units of tasks.

  In addition, since the multi-core microcomputer 100 according to the present embodiment can distribute the processing in units of instructions, it is difficult to realize parallel operation by distributing the processing in units of tasks, but can maximize the performance of the multi-core. In addition, since it can be distributed in units of instructions, it is easy to divert already used single-core programs.

When processing is distributed in units of instructions, each CPU may not be able to execute instructions in parallel due to instruction dependency. For example, when the instructions 1 to 3 are as follows, the instruction 2 has an instruction dependency with the instruction 1 and cannot be executed in parallel.
Command 1: A + B → C
Command 2: C + D → E
Command 3: F + G → H
When the CPUs 1 to 3 execute the instructions 1 to 3, respectively, the execution result of the instruction 1 of the CPU 1 is necessary for the CPU 2 to execute the instruction 2. For this reason, CPU1 and CPU2 cannot perform a process in parallel.

  In the present embodiment, a description will be given of the multi-core microcomputer 100 in which the instruction dependency determination unit 33 detects such an instruction dependency and the pipeline synchronization unit 31 waits for the CPU 14 that executes the instruction dependency instruction.

  The instruction dependency determining unit 33 determines whether or not the instructions 1 to 3 included in the instruction set executed at the same time have an instruction dependency. The determination method is as follows, for example. The instruction dependency determining unit 33 focuses on one instruction in the order of instructions in one instruction set and specifies a register name or a variable name (address address) in which an operation result is stored. Then, it is determined whether or not this register name or variable name is described in the operand to be operated on in the subsequent instruction. If it is described, the subsequent instruction has an instruction dependency. In the above example, the register name that stores the operation result of the instruction 1 is “C”, and the register name “C” is described in the operand (C + D “C”) that is the operation object of the subsequent instruction 2. ing. Therefore, the instruction 2 has an instruction dependency relationship with the instruction 1. Hereinafter, the instruction 2 is referred to as an “instruction having an instruction dependency” and the instruction 1 is referred to as a “preceding instruction”.

FIG. 6 is an example of a diagram for explaining the wait of the CPU 14 by the instruction dependency relationship, and FIG. 7 shows an example of an operation procedure of the operation sequence control circuit 13 when the instruction dependency relationship is detected. Here, in step S25, it is assumed that the instruction dependency determining unit 33 determines that the instruction 2 has an instruction dependency relationship with the instruction 1.
(S25-1) The instruction queue control unit 32 assigns the instruction 1 of the preceding instruction that requires the execution result of the instruction 2 to the CPU 1. By doing so, the CPU 1 can complete the execution of the instruction 1 before the instruction 2.
(S25-2) The instruction queue control unit 32 causes the CPUs 2 and 3 other than the CPU 1 to wait.
(S25-3) The pipeline synchronization unit 31 causes the CPUs 1 to 3 to execute one stage. The CPUs 2 and 3 do not do anything because they are waiting. Thereby, only the CPU 1 can advance the stage of the instruction 1 of the preceding instruction.
(S25-4) The instruction queue control unit 32 uses the instructions 2 to 4 as an instruction set, and assigns the instruction 2 having the instruction dependency among them to the CPU 1 that is the CPU that executes the preceding instruction. As a result, the same CPU 1 can execute the instruction 2 having the instruction dependency and the instruction 1 which is the preceding instruction.

  The instruction queue control unit 32 assigns the remaining instructions 3 and 4 in the instruction set to the CPUs 2 and 3. That is, the CPUs 2 and 3 execute the instructions 3 and 4 instead of the instructions 2 and 3.

  The subsequent processing is the same as in the first embodiment, and the pipeline synchronization unit 31 executes one stage while matching the execution stages of the CPUs 1 to 3 (S40). Thereafter, the process is repeated from step S10.

  The multi-core microcomputer 100 of this embodiment causes the other CPUs 2 and 3 to wait while the CPU 1 is executing the preceding instruction, and the instruction 2 having the instruction dependency relationship is the same CPU 1 as the CPU that executes the instruction 1 that is the preceding instruction. Assign to. As a result, even if an instruction dependency relationship is detected in the instruction set, processing can be distributed in units of instructions.

  This embodiment can be applied to the multi-core microcomputer 100 together with the first embodiment.

  In this embodiment, a description will be given of the multi-core microcomputer 100 that adjusts the difference in instruction processing latency for each CPU. As already described, the number of clocks required for the ALU to execute the shift instruction and the number of clocks required for the MUL to execute the multiply instruction, or the number of clocks required for the DIV to execute the divide instruction. Are very different. This number of clocks is called processing latency, and if the processing latency is different for one instruction set, the time required for CPUs 1 to n to complete execution of instructions differs.

  An inconvenience when the execution completion time of the instruction is different for each CPU will be described. For example, consider a case where the CPUs 1 to 3 execute the instructions 4 to 6 after executing the instructions 1 to 3. When CPU 1 has a large delay for executing instruction 1 and instruction 4 executed by CPU 1 has an instruction dependency relationship with instruction 1, execution of instruction 1 is completed when CPU 1 executes the EX stage of instruction 4 It may not have been done.

  When execution completion times of instructions executed by the CPUs 1 to n are different, the CPUs 1 to n output a bus acquisition request asynchronously according to the execution result. For example, it is assumed that the CPU 2 completes the execution of the instruction 2 before the CPU 1 and outputs a bus acquisition request due to a difference in processing latency. However, when the CPU 1 needs to use the bus for executing the instruction 1, the CPU 1 further delays the completion of the execution of the instruction 1.

  Therefore, in this embodiment, Wait is inserted into the stage according to the processing latency of the instructions executed by the CPUs 1 to n. That is, when the execution completion timings of the instructions executed by the CPUs 1 to n are shifted, the pipeline synchronization unit 31 inserts a wait in a CPU with a short processing latency so that the CPUs 1 to n synchronize with each other. Adjust to complete execution.

FIG. 8 is an example of a diagram illustrating adjustment by processing latency and wait. It is assumed that the instructions 1 to 3 are the next processing latency. Note that the processing latency of each instruction is known to the operation sequence control circuit 13.
Instruction 1: Processing latency is 2
Instruction 2: Processing latency is 3
Instruction 3: Processing latency is 1
The pipeline synchronization unit 31 specifies the EX stage (time 3 to 5) of the CPU 2 that has executed the instruction 2 having the largest processing latency among the instructions 1 to 3. After time 6, each of the CPUs 1 to 3 can execute the EX stage of the next instruction set. Therefore, the pipeline synchronization unit 31 aligns the EX stages of the instructions 4 to 6 of the CPUs 1 to 3 at time 6.

  Similarly, at time 6, the ID stages of the instructions 7 to 9 of the CPUs 1 to 3 are aligned. Similarly, at time 6, the IF stages of the instructions 10 to 12 of the CPUs 1 to 3 are aligned. It is because of pipeline control that the stage aligned at time 6 is advanced for each subsequent instruction set.

  In this way, the stages of the CPUs 1 to 3 can be synchronized by delaying the stage of the subsequent instruction set in accordance with the completion of the execution of the instruction of the CPU 2 that has executed the instruction having a large processing latency. In this embodiment, the instruction set of instructions 1 to 3 is “detection instruction set”, the instruction set of instructions 4 to 6 is “next instruction set”, the instruction set of instructions 7 to 9 is “next instruction set”, the instruction 10 The instruction set of ˜12 is called “next instruction set”.

  FIG. 9 shows an example of an operation procedure of the operation sequence control circuit when the CPUs 1 to 3 execute instructions having different processing latencies. The procedure of FIG. 9 is executed following, for example, step S30 of FIGS.

  The pipeline synchronization unit 31 monitors the execution results of the EX stages of the CPUs 1 to 3 and determines whether the processing latencies are different (S110). The processing latencies do not need to be completely matched, and a certain amount of deviation can be allowed.

  If the processing latencies are not different, the pipeline synchronization unit 31 terminates the process of FIG. 9 without inserting a wait, and advances the stages of the CPUs 1 to 3 (S40).

  If there are instructions with different processing latencies (Yes in S110), the pipeline synchronization unit 31 inserts Wait before the EX stage of the next instruction set (S120). In FIG. 8, waits for instructions 4 to 6 at time 4 correspond.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the ID stage of the next instruction set (S130). In FIG. 8, Wait of instructions 7 to 9 at time 4 corresponds.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the IF stage of the next instruction set (S140). In FIG. 8, Waits corresponding to instructions 10 to 12 at time 4 correspond.

  Then, the pipeline synchronization unit 31 advances one stage of each of the CPUs 1 to 3 (S150). Since the instructions 4 to 12 are Wait, the stage does not advance, but the instructions 1 to 3 are processed in one stage or in one stage.

  Next, the pipeline synchronization unit 31 determines whether or not the instruction with the largest processing latency is completed from the detected instruction set in which the instructions with different processing latencies are detected (S160). That is, in FIG. 8, the CPU 2 determines whether or not the execution of the instruction 2 has been completed. Here, it is only necessary that the calculation result can be used in the same CPU, and thus the completion of execution means the end of the EX stage.

  If execution of the instruction with the largest processing latency has not been completed (No in S160), the pipeline synchronization unit 31 inserts Wait before the EX stage of the next instruction set (S120). In FIG. 8, waits for instructions 4 to 6 at time 5 correspond.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the ID stage of the next instruction set (S130). In FIG. 8, waits for instructions 7 to 9 at time 5 correspond.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the IF stage of the next instruction set (S140). In FIG. 8, waits for instructions 10 to 12 at time 5 correspond.

  Then, the pipeline synchronization unit 31 advances the stage of each CPU by one (S150). Thereby, the CPU 2 can complete the execution of the instruction 2.

  When the execution of the instruction with the largest processing latency is completed (Yes in S160), the processing in FIG. 9 ends. That is, since the pipeline synchronization unit 31 does not insert Wait, one stage of the instructions 1 to 12 of the CPUs 1 to 3 is advanced (S40).

  The multi-core microcomputer 100 according to the present embodiment can synchronize the execution stages of the CPUs by inserting waits in the respective stages even when the processing latencies of the instructions processed by the CPUs 1 to n in the instruction set are different. . Therefore, even if there are instructions with different processing latencies in the instruction set, the stages of the CPUs 1 to 3 can be synchronized to suppress the occurrence of instruction dependency.

  This embodiment can be applied to the multi-core microcomputer 100 together with the first and second embodiments.

  In this embodiment, a multi-core microcomputer 100 in which different CPUs 1 to n synchronize operation results will be described. As described with reference to FIG. 1, the operand of the instruction executed by the CPU 1 may be stored in the CPU register 45 of another CPU such as the CPU 2. Since the CPU 1 cannot execute the operation as it is, the CPU register synchronization unit 34 copies the operation result stored in the register of the CPU 2 to the CPU 1.

  FIG. 10 is an example of a diagram illustrating register refresh. For the sake of explanation, the instruction sets are referred to as instruction sets A to D in order.

(i) The instruction dependency determining unit 33 determines whether an instruction in the instruction set B has an instruction dependency relationship with an instruction in the immediately preceding instruction set A. Specifically, the following instruction dependency is determined.
Whether the instruction 4 executed by the CPU 1 has an instruction dependency with the instructions 2 and 3, the instruction 5 executed by the CPU 2 has an instruction dependency with the instructions 1 and 3, and the instruction 6 executed by the CPU 3 has Whether or not there is an instruction dependency relationship with the instructions 1 and 2 is generated for each instruction set before and after the instruction sets C and B and instruction sets D and C. For example, in instruction sets C and B,
Whether the instruction 7 executed by the CPU 1 has an instruction dependency with the instructions 5 and 6, the instruction 8 executed by the CPU 2 has an instruction dependency with the instructions 4 and 6, and the instruction 9 executed by the CPU 3 has It is determined whether or not there is an instruction dependency with the instructions 4 and 5.

  The determination method is as follows, for example. It is determined whether or not the register name or variable name (address address) in which the operation results of the instructions 2 and 3 are stored is described in the operand to be operated by the instruction 4. If it is described, the instruction 4 has an instruction dependency relationship with the instruction 2 or the instruction 3. Further, the instruction 2 or 3 is a preceding instruction. Here, it is assumed that instruction 4 is an instruction dependency instruction and instruction 2 is a preceding instruction.

  (ii) The pipeline synchronization unit 31 copies the data of the CPU register 45 of the CPU 2 to the register of the CPU 1 at the timing when the execution of the instruction 2 of the preceding instruction is completed. Since the CPU 1 cannot execute the instruction 4 until copying, the pipeline synchronization unit 31 inserts Wait in each stage as in the third embodiment. The data of the CPU register 45 of the CPU 2 may be copied to the register of the CPU 1 during the wait.

  Specifically, for example, the CPU register 45 of the CPU 2 and the register set 44 of the CPU 1 are directly connected. The CPU register synchronization unit 34 copies the data in the CPU register 45 of the CPU 2 to the CPU 1 at the timing when the CPU 2 completes the execution of the instruction 2.

  FIG. 11 shows an example of an operation procedure of the operation sequence control circuit 13 when there is an instruction dependency between instruction sets. Note that the procedure of FIG. 11 is executed following, for example, step S30 of FIGS.

  The instruction dependency determining unit 33 determines in advance whether there is an instruction dependency between instruction sets. For example, two or more instruction sets A and B are read to the instruction queue 42, and the instruction dependency between the instruction set B and the immediately preceding instruction set A is determined. If there is an instruction dependency, the CPU that executes the instruction having the instruction dependency and the CPU that executes the preceding instruction are recorded.

  In this embodiment, the next instruction set (instructions 7 to 9) of the instruction set of instructions 4 to 6 including the instruction 4 having the instruction dependency relationship is “next instruction set”, and the instruction set of instructions 10 to 12 is “next”. It is called “Instruction Set”.

  The pipeline synchronization unit 31 determines whether or not a preceding instruction is being executed (S210). This determination may be performed before the EX stage of the preceding instruction. When the preceding instruction is not executed (No in S210), the pipeline synchronization unit 31 advances the stages of the CPUs 1 to 3 without inserting Wait (S40).

  When the preceding instruction is being executed (Yes in S210), the pipeline synchronization unit 31 inserts Wait before the EX stage of the instruction set including the instruction having the instruction dependency (S220). In FIG. 10, waits for instructions 4 to 6 at time 4 correspond.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the ID stage of the next instruction set that is the next instruction set including the instruction having the instruction dependency (S230). In FIG. 10, waits for instructions 7 to 9 at time 4 correspond.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the IF stage of the next instruction set (S240). In FIG. 10, waits for instructions 10 to 12 at time 4 correspond.

  Then, the pipeline synchronization unit 31 advances one stage of each of the CPUs 1 to 3 (S250). Since the instructions 4 to 12 are Wait, the stage does not advance, but the instructions 1 to 3 are processed in one stage or in one stage.

  Next, the pipeline synchronization unit 31 determines whether the execution of the preceding instruction is completed (S260). That is, in FIG. 10, the CPU 2 determines whether or not the execution of the instruction 2 has been completed. Since the CPU 1 is different between the CPU 1 that executes the instruction 4 having the instruction dependency and the CPU 2 that executes the instruction 2 of the preceding instruction, whether or not the execution is completed is determined by whether or not the write back is performed.

  When the preceding instruction is being executed (Yes in S210), the pipeline synchronization unit 31 inserts Wait before the EX stage of the instruction set including the instruction having the instruction dependency (S220). In FIG. 10, waits for instructions 4 to 6 at time 5 correspond.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the ID stage of the next instruction set (S230). In FIG. 10, Wait of instructions 7 to 9 at time 5 corresponds.

  Similarly, the pipeline synchronization unit 31 inserts Wait before the IF stage of the next instruction set (S240). In FIG. 10, Waits corresponding to instructions 10 to 12 at time 5 correspond.

  When the execution of the preceding instruction is completed (Yes in S260), the CPU register synchronization unit 34 refreshes the register (S270). That is, the CPU register synchronization unit 34 copies the data in the CPU register 45 of the CPU 2 to the register set 44 of the CPU 1. Thereby, the CPU 1 can execute the instruction 4 using the calculation result of the CPU 2. Thereafter, the process proceeds to step S40 in FIGS. 5 and 7, and the CPUs 1 to 3 advance the stages of the instructions 4 to 12 without inserting Wait.

  The multi-core microcomputer 100 of this embodiment can distribute and execute instructions in units of instructions by refreshing the registers even if there is an instruction dependency between different CPUs between instruction sets.

  This embodiment can be applied to the multi-core microcomputer 100 together with the first to third embodiments.

13 Operation Sequence Control Circuit 14 CPU
DESCRIPTION OF SYMBOLS 16 Failure diagnostic device 21 Common instruction queue 22 CPU bus control part 23 Instruction scheduler 31 Pipeline synchronization part 32 Instruction queue control part 33 Instruction dependence determination part 34 CPU register synchronization part 35 External access control part 100 Multi-core microcomputer

Claims (6)

In an information processing apparatus in which multiple cores execute instructions in parallel,
Program storage means for storing a program;
Calculation result storage means for storing calculation results for each core;
Instruction reading means for reading an instruction set including instructions for the number of cores in the execution order from the program storage means, and storing the instruction set in a primary storage unit;
Instruction distribution means for storing instructions included in the instruction set in an instruction queue of each core;
A dependent instruction whose operation target is an operation result obtained by the first core calculating an instruction included in the first instruction set stored in the primary storage unit is executed after the first instruction set. Instruction dependency determination means for determining whether or not a second core different from the first core executes, included in the instruction set;
When the instruction dependency relationship determining unit determines that the second core executes the dependency instruction included in the second instruction set, the value of the operation result storage unit of the first core is set to the second core. Copying means for copying to the calculation result storage means of the core;
An information processing apparatus. A stage in which a plurality of cores control the progress of the stage so that each instruction is executed while synchronizing each stage of instruction reading from the instruction queue, instruction decoding, instruction execution, and storage in the operation result storage means Having synchronization means;
The stage synchronization means is executed by the plurality of cores until the first core stores the calculation result to be calculated by the second core in the calculation result storage means of the first core. Stopping the stages of multiple cores so that the stage of each instruction in the instruction set after one instruction set does not reach the stage of instruction execution,
The information processing apparatus according to claim 1. When the instruction dependency relationship determining unit determines that the second instruction included in the instruction set is the operation target of the operation result of the first instruction in the same instruction set,
The instruction distribution means stores the first instruction included in the instruction set in the instruction queue of any one of a plurality of cores,
The stage synchronization means stops a stage of a core other than the core in which the first instruction is stored in the instruction queue, and reads the instruction in the core in which the first instruction is stored in the instruction queue. And execute
The instruction distribution means stores the second instruction in the instruction queue of the core that executed the first instruction, and stores the remaining instructions of the instruction set starting with the second instruction to another core. Stored in the instruction queue of
The stage synchronization means causes each core to execute instructions subsequent to the second instruction while synchronizing the stages of a plurality of cores.
The information processing apparatus according to claim 2. If the instruction set includes instructions with different processing latencies required for the instruction execution stage,
The stage synchronization means is configured such that each instruction stage of an instruction set following an instruction set including an instruction having a different processing latency becomes an instruction execution stage until a core executing an instruction having a different processing latency finishes the instruction execution stage. Stop multiple core stages to avoid reaching
The information processing apparatus according to claim 2. It has a failure detection means for detecting a failure for each core,
When the failure detection unit detects a core failure, the failure detection unit includes a cutting unit that disconnects the core from which the failure has been detected and the program storage unit, the command reading unit, the command distribution unit, and the stage synchronization unit. ,
The instruction reading means reads an instruction set including instructions for the number of cores excluding the disconnected core from the program storage means and stores it in a primary storage unit,
The instruction distribution means stores instructions for the number of cores included in the instruction set, excluding the disconnected core, in the instruction queue of each core.
The information processing apparatus according to claim 2, wherein the information processing apparatus is an information processing apparatus. Program storage means for storing a program;
Calculation result storage means for storing calculation results for each core,
In an instruction execution method of an information processing apparatus in which a plurality of cores execute instructions in parallel,
Instruction reading means reads an instruction set including instructions for the number of cores in the execution order from the program storage means and stores it in the primary storage unit;
An instruction distribution means for storing instructions included in the instruction set in an instruction queue of each core;
The instruction dependency relation determining means has a dependency instruction whose operation target is an operation result obtained by the first core calculating an instruction included in the first instruction set stored in the primary storage unit, as compared to the first instruction set. Determining whether a second core included in a second instruction set to be executed later and different from the first core executes;
When the instruction dependency determining means determines that the second core executes the dependent instruction included in the second instruction set, the copying means sets the value of the operation result storage means of the first core, Copying to the operation result storage means of the second core;
An information processing method comprising:

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