JP2013041919A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of an influence of semiconductor wafer charge-up caused by a plasma treatment and the like studied by the inventors, which makes it apparent that, when dry etching and the like is performed on a semiconductor wafer and the like, the semiconductor wafer is generally subjected to an inhomogeneously charged state that is an electrically biased state mainly to a positive side, as a result; because it shows that positive movable ions and the like remain on a wafer surface and neighborhood thereof by dry etching and the like and inhomogeneously distributed and still remain after being separated into individual semiconductor chips, there is a possibility of adverse effect on operations.SOLUTION: In a semiconductor device manufacturing method of an embodiment, an entire wafer is negatively charged by friction with a conductive processing liquid like the polymer remover after removal of a processing resist film in a metal film processing process which needs not use a polymer remover and the like, generally.

Description

  The present invention relates to a technique effective when applied to a static electricity control technique on a wafer in a method of manufacturing a semiconductor device (or a semiconductor integrated circuit device).

  In Japanese Unexamined Patent Publication No. 2007-123812 (Patent Document 1), when forming a via in a damascene process, the charge accumulated in the wiring under the via is neutralized in the middle of the via opening, and then the remaining insulating film is formed. A technique for removing and completing a via is disclosed.

  Japanese Patent Application Laid-Open No. 11-111660 (Patent Document 2) discloses a technique that uses acidic ionized water instead of HPM in order to solve the problem of hydrochloric acid atmosphere caused by HPM (Hydrogen Hydrogen Peroxide Mix) in RCA cleaning. ing.

  In Japanese Patent Laid-Open No. 6-252076 (Patent Document 3), in order to prevent an undesired effect caused by charge-up by dry etching or ashing of a wafer with resist, ultraviolet rays are irradiated after dry etching or the like. Thereafter, a technique for performing organic cleaning is disclosed.

JP 2007-123812 A JP-A-11-111660 JP-A-6-252076

  The inventors of the present application have examined the effect of charge-up of a semiconductor wafer due to plasma processing or the like. When dry etching or the like is performed on a semiconductor wafer or the like, the semiconductor wafer is usually electrically It became clear that the charged state was unevenly biased to the positive side. This indicates that positive movable ions etc. remain on the wafer surface and its vicinity by dry etching, etc., and are unevenly distributed, and remain even after individual semiconductor chips are formed. May adversely affect operation.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one invention of the present application, in a metal film processing step that does not normally require the use of a polymer removal solution, etc., after removal of the processing resist film, friction with a conductive treatment solution similar to the polymer removal solution is caused. The whole wafer is negatively charged.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, normally, in a metal film processing process that does not require the use of a polymer removal solution, the entire wafer is negatively charged by friction with a conductive treatment solution similar to the polymer removal solution after the processing resist film is removed. By doing so, undesired charging due to plasma treatment or the like can be prevented.

It is a chip | tip upper surface layout figure of IGBT (Insulated Gate Bipolar Transistor) which is an example of the object device in the manufacturing method of the semiconductor device of embodiment of this application. FIG. 2 is a chip cross-sectional view of a cell portion corresponding to an A-A ′ cross section in an active cell portion extraction region R <b> 2 of FIG. 1. FIG. 2 is a chip cross-sectional view of a chip peripheral region corresponding to an X-X ′ cross section in a chip end cutout region R1 of FIG. 1. It is a process block flow figure after the barrier metal formation process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a schematic cross section of the dry etching apparatus used for the barrier metal processing process in the manufacturing method of the semiconductor device of the one embodiment of the present application. It is a schematic cross section of a spin wet processing apparatus for explaining a negative charge imparting step (wet surface treatment step) which is a main process in the method of manufacturing a semiconductor device according to one embodiment of the present application. FIG. 2 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during the manufacturing process (P-type well region introducing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application; It is. 3 relates to a cross section corresponding to the chip peripheral section cutout region R3 in FIG. 3 during the manufacturing process (P-type well region introducing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. It is device sectional drawing (chip peripheral region). FIG. 2 is a device cross-sectional view (active cell region) relating to the cross-section corresponding to FIG. 2 during the manufacturing process (P-type body region introducing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application; It is. 3 relates to a cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (P-type body region introducing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. It is device sectional drawing (chip peripheral region). FIG. 5 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during a manufacturing process (trench forming step) for explaining an outline of a wafer process in the method for manufacturing a semiconductor device according to the embodiment of the present application; FIG. 3 is a device cross-sectional view relating to a cross section corresponding to the chip peripheral cross-sectional cutout region R3 in FIG. 3 during the manufacturing process (trench forming step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application; (Chip peripheral area). FIG. 4 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during the manufacturing process (polysilicon film processing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application; is there. A device relating to a cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (polysilicon film processing step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is sectional drawing (chip peripheral region). FIG. 5 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during a manufacturing process (emitter introduction step) for explaining an outline of a wafer process in the method for manufacturing a semiconductor device according to the embodiment of the present application; 3 is a device cross-sectional view relating to a cross section corresponding to the chip peripheral cross-sectional cutout region R3 in FIG. 3 during the manufacturing process (emitter introduction step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application; (Chip peripheral area). FIG. 5 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during a manufacturing process (contact groove forming step) for explaining an outline of a wafer process in the method for manufacturing a semiconductor device according to the embodiment of the present application; . 3 is a device cross section relating to the cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (contact groove forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is a figure (chip peripheral area). Device sectional view (active cell region) regarding the section corresponding to FIG. 2 during the manufacturing process (barrier metal layer forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is. 3 relates to a cross section corresponding to the chip peripheral section cutout region R3 in FIG. 3 during the manufacturing process (barrier metal layer forming step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. It is device sectional drawing (chip peripheral region). FIG. 4 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during a manufacturing process (metal film processing step) for explaining an outline of a wafer process in the method for manufacturing a semiconductor device according to the embodiment of the present application; . 3 is a device cross section relating to the cross section corresponding to the chip peripheral section cutout region R3 in FIG. 3 during the manufacturing process (metal film processing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. It is a figure (chip peripheral area). FIG. 4 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during a manufacturing process (final passivation film forming step) for explaining an outline of a wafer process in the method for manufacturing a semiconductor device according to the embodiment of the present application; is there. A device relating to a cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (final passivation film forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is sectional drawing (chip peripheral region). FIG. 4 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during the manufacturing process (metal collector electrode forming step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application; is there. A device relating to a cross section corresponding to the chip peripheral section cutout region R3 in FIG. 3 during the manufacturing process (metal collector electrode forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is sectional drawing (chip peripheral region). 6 is a comparative chart showing wafer-like potential distributions at the time of completion of a barrier metal film dry etching step and at the time of completion of negative charge application processing in the method for manufacturing a semiconductor device according to one embodiment of the present application. FIG. 28 is a potential distribution diagram of an uncharged wafer for comparison with the result of FIG. 27. FIG. 29 is a potential distribution diagram of a wafer in which pure water is used for the wafer in FIG. 28 to perform the same process as the negative charge imparting process for comparison with the result in FIG.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A semiconductor device manufacturing method including the following steps:
(A) forming a metal film on substantially the entire surface of the first main surface of the semiconductor wafer having the first main surface and the second main surface;
(B) forming a resist film having a pattern on the metal film;
(C) patterning the metal film by etching without using anisotropic dry etching in the presence of the resist film;
(D) a step of removing the resist film after the step (c);
(E) After the step (d), a step of negatively charging substantially the whole of the first main surface side of the semiconductor wafer;
Here, the step (c) includes the following substeps:
(C1) A step of patterning the first metal layer constituting the metal film by isotropic dry etching.

2. In the method of manufacturing a semiconductor device according to the item 1, the metal film has the following:
(X1) the lower first metal layer;
(X2) an upper second metal layer,
Here, the first metal layer is a barrier metal layer, and the second metal layer is an aluminum-based metal layer.

3. In the method for manufacturing a semiconductor device according to the item 2, the step (c) includes the following sub-steps:
(C2) A step of patterning the second metal layer by performing wet etching on the second metal layer using the resist film as a mask before the substep (c1).

  4). In the method of manufacturing a semiconductor device according to any one of items 1 to 3, the step (e) is performed by a wet process using a conductive process liquid.

  5). In the method of manufacturing a semiconductor device according to any one of 1 to 4, the metal film is mainly formed on an insulating film on the first main surface of the semiconductor wafer.

6). 6. The method for manufacturing a semiconductor device according to any one of items 1 to 5 further includes the following steps:
(F) A step of forming a final passivation film on substantially the entire surface of the metal film after the step (e).

  7). In the method for manufacturing a semiconductor device according to any one of 1 to 6, the step (d) is performed by an ashing process.

  8). 8. The method for manufacturing a semiconductor device according to any one of 4 to 7, wherein the conductive treatment liquid is a polymer stripping liquid.

  9. In the method for manufacturing a semiconductor device according to any one of 4 to 8, the conductive processing liquid is supplied to the first main surface side in a state where the wafer is spun.

  10. In the method for manufacturing a semiconductor device according to any one of 4 to 9, the conductive treatment liquid is an aqueous solution containing acetic acid and ammonia as main components.

11. A semiconductor device manufacturing method including the following steps:
(A) forming a metal film on substantially the entire surface of the first main surface of the semiconductor wafer having the first main surface and the second main surface;
(B) forming a resist film having a pattern on the metal film;
(C) patterning the metal film by etching in the presence of the resist film without using dry etching that substantially involves formation of a sidewall polymer;
(D) a step of removing the resist film after the step (c);
(E) After the step (d), a step of negatively charging substantially the whole of the first main surface side of the semiconductor wafer;
Here, the step (c) includes the following substeps:
(C1) A step of patterning the first metal layer constituting the metal film by dry etching without substantially forming a sidewall polymer.

12 In the method for manufacturing a semiconductor device according to the item 11, the metal film has the following:
(X1) the lower first metal layer;
(X2) an upper second metal layer,
Here, the first metal layer is a barrier metal layer, and the second metal layer is an aluminum-based metal layer.

13. In the method of manufacturing a semiconductor device according to the item 12, the step (c) includes the following substeps:
(C2) A step of patterning the second metal layer by performing wet etching on the second metal layer using the resist film as a mask before the substep (c1).

  14 14. In the method for manufacturing a semiconductor device according to any one of 11 to 13, the step (e) is performed by a wet process using a conductive process liquid.

  15. 15. In the method for manufacturing a semiconductor device according to any one of 11 to 14, the metal film is mainly formed on an insulating film on the first main surface of the semiconductor wafer.

16. 16. The method for manufacturing a semiconductor device as described above in any one of 11 to 15, further includes the following steps:
(F) A step of forming a final passivation film on substantially the entire surface of the metal film after the step (e).

  17. 17. In the method for manufacturing a semiconductor device as described above in any one of 11 to 16, the step (d) is executed by an ashing process.

  18. 18. In the method for manufacturing a semiconductor device according to any one of items 14 to 17, the conductive treatment liquid is a polymer stripping liquid.

  19. 19. In the method for manufacturing a semiconductor device according to any one of items 14 to 18, the conductive processing liquid is supplied to the first main surface side in a state where the wafer is spun.

  20. 20. In the method for manufacturing a semiconductor device as described above in any one of 14 to 19, the conductive treatment liquid is an aqueous solution containing acetic acid and ammonia as main components.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts and sections for convenience, if necessary. However, unless otherwise specified, they are not independent from each other. Rather, each part of a single example, one of which is a partial detail of the other or a part or all of a modification. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a device in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). Say. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors).

  In the present application, “semiconductor active element” refers to a transistor, a diode, or the like.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of an IGBT (Insulated Gate Bipolar Transistor) chip structure as an example of a target device in the method of manufacturing a semiconductor device according to the embodiment of the present application (mainly FIGS. 1 to 3)
Here, the IGBT will be specifically described by way of example, but it goes without saying that the present invention is not limited to the IGBT but can be applied to power MOSFETs, power diodes, other power semiconductor active elements, semiconductor integrated circuit devices, and the like.

  FIG. 1 is a top surface layout diagram of an IGBT (Insulated Gate Bipolar Transistor) which is an example of a target device in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 2 is a chip cross-sectional view of the cell portion corresponding to the A-A ′ cross section in the active cell extraction region R <b> 2 of FIG. 1. FIG. 3 is a chip cross-sectional view of the chip peripheral region corresponding to the X-X ′ cross section in the chip end cutout region R <b> 1 of FIG. 1. Based on these, an IGBT chip structure, which is an example of a target device in the method of manufacturing a semiconductor device according to the embodiment of the present application, will be described.

  First, referring to FIG. 1, a chip top surface layout (a layout on the first main surface 1a) of a typical silicon-based IGBT will be described. As shown in FIG. 1, a ring-shaped metal guard ring 3 is provided in the peripheral portion of the semiconductor chip 2, and the metal guard ring 3 is composed of, for example, a metal layer of the same layer as this. The metal gate wiring 8 is provided. A part of the metal gate wiring 8 is widened to be a metal gate electrode, and a gate pad opening 7 is provided in that part. Most of the area inside the metal gate wiring 8 is covered with, for example, a metal emitter electrode 5 made of the same metal layer as that of the metal gate wiring 8, and an emitter pad opening is formed at the center of the metal emitter electrode 5. 42 is provided. The outer side of the emitter pad opening 42 is covered with a final passivation film 33 such as a polyimide film up to a little outside of the metal guard ring 3 except for the gate pad opening 7. Most of the portion under the metal emitter electrode 5 is an active cell region 4, and the peripheral portion (chip peripheral region 26) has a ring-shaped cell peripheral P-type main junction region 6 p and a P-type well from the inside. Region 9 is provided.

  Next, the A-A ′ cross section of the active cell extraction region R <b> 2 in FIG. 1 will be described with reference to FIG. 2. As shown in FIG. 2, the active cell region 4 has a repeating structure of the unit cell region 10. A metal collector electrode 24 is provided on the back surface 1b (second main surface) of the semiconductor chip 2, a P + type collector region 23 is formed on the inner surface of the semiconductor region, and an N + type is further formed on the inner side. A field stop region 22 is provided. The main part of the semiconductor substrate 2 is composed of a lower N-type drift region 16 and an upper P-type body region 6 (P-type channel region). A plurality of trenches 15 are formed in the surface 1 a (first main surface) of the semiconductor chip 2 so as to penetrate the P-type body region 6 and reach the inside of the N-type drift region 16. The polysilicon gate electrode 18 is embedded through the gate insulating film 17. An interlayer insulating film 11 is provided on the surface 1 a of the semiconductor substrate 2, and an N + type emitter region 12 is provided in the surface 1 a of the semiconductor substrate 2 between adjacent trenches 15. Further, on the surface 1a side of the semiconductor substrate 2, a contact portion 21 (contact groove) that penetrates through the interlayer insulating film 11 and the N + type emitter region 12 and reaches the P type body region 6 is provided. A P + type body contact region 14 is provided in the P type body region 6 in contact with the lower end of the contact groove 21. A barrier metal film 19 (first metal layer) is provided on the interlayer insulating film 11 including the inner wall of the contact groove 21, and a tungsten plug 20 is provided in the contact groove 21. A metal emitter electrode 5 is provided on the barrier metal film 19 and the tungsten plug 20.

  Next, the X-X ′ cross section of the chip end cutout region R1 (the end of the active cell region 4 and the chip peripheral region 26) of FIG. As shown in FIG. 3, a metal collector electrode 24 is provided on the back surface 1 b (second main surface) of the semiconductor chip 2, and a P + type collector region 23 is further formed on the inner surface of the semiconductor region. Inside, an N + type field stop region 22 is provided. The main part of the semiconductor substrate 2 is composed of a lower N-type drift region 16. In the surface region of the N-type drift region 16 on the semiconductor substrate surface 1a side, there is a cell peripheral P-type main junction region 6p surrounding the active cell region 4, and on the outside of this, the active cell region is connected to this. 4 is provided with a P-type well region 9 and the like. In the figure, the depletion layer 25 in the blocking mode is drawn with a broken line. An N + type channel stop region 30 and a P + type chip peripheral contact region 31 are provided in the surface region on the semiconductor substrate surface 1a side of the N type drift region 16 at the chip end. A surface insulating film 32 such as a silicon oxide-based insulating film is provided on the semiconductor substrate surface 1a of the N-type drift region 16, on which a polysilicon gate wiring 28 for extracting a gate, a metal guard ring, and the like. 3 is provided with a polysilicon guard ring 29 and the like. An interlayer insulating film 11 such as a silicon oxide insulating film is provided on the semiconductor substrate surface 1 a and the surface insulating film 32 in the N-type drift region 16, and a metal emitter electrode is formed on the interlayer insulating film 11. 5. Surface metal electrodes such as a metal gate wiring 8 electrically connected to the polysilicon gate wiring 28 and a metal guard ring 3 electrically connected to the polysilicon guard ring 29 are provided. These surface metal electrodes are composed of, for example, an aluminum-based electrode layer. On the interlayer insulating film 11 and the surface metal electrodes 5, 8, 3, a final passivation film 33 made of, for example, a polyimide film is formed as necessary.

  Here, if there is an undesired positive charge (positive movable ion 27p) or the like at the interface between the interlayer insulating film 11 and the final passivation film 33, the breakdown voltage is deteriorated in the blocking mode, or between the emitter and the gate. This may cause a leakage or a poor reliability. Such a defect can usually be confirmed by a high temperature stress test or the like. As a typical high temperature stress test, there is a HTRB (High Temperature Reverse Bias) test. For example, in a chip state, 150 degrees Celsius, an emitter and a gate are applied with 0 volts, and a collector is applied with 400 volts. It is performed for a relatively long time (for example, 1000 hours).

2. Description of outline of wafer process in manufacturing method of semiconductor device of one embodiment of the present application (mainly FIG. 4 and FIGS. 7 to 26)
Here, a method of forming two epitaxial layers on a P + type silicon single crystal wafer by a CZ (Czochralski) method will be specifically described as an example, but the present invention is not limited to this. Needless to say, the present invention can also be applied to an N + type field stop region 22 and a P + type collector region 23 formed by ion implantation or the like on a wafer formed by the FZ method or an N type wafer formed by the FZ (Floating Zone) method.

  FIG. 4 is a process block flow diagram after the barrier metal formation process in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 7 is a device cross-sectional view (active view) corresponding to the cross-section corresponding to FIG. 2 during the manufacturing process (P-type well region introducing step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. Cell region). FIG. 8 corresponds to the chip peripheral section cutout region R3 in FIG. 3 during the manufacturing process (P-type well region introducing step) for explaining the outline of the wafer process in the manufacturing method of the semiconductor device according to the one embodiment of the present application. It is device sectional drawing (chip peripheral area | region) regarding the cross section to perform. 9 is a device cross-sectional view (active view) corresponding to the cross-section corresponding to FIG. 2 during the manufacturing process (P-type body region introducing step) for explaining the outline of the wafer process in the manufacturing method of the semiconductor device according to the embodiment of the present application. Cell region). FIG. 10 corresponds to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (P-type body region introduction step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is device sectional drawing (chip peripheral area | region) regarding the cross section to perform. FIG. 11 is a device cross-sectional view (active cell region) relating to the cross-section corresponding to FIG. 2 during the manufacturing process (trench formation step) for explaining the outline of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. It is. FIG. 12 relates to a cross section corresponding to the chip peripheral section cutout region R3 in FIG. 3 during the manufacturing process (trench forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is device sectional drawing (chip peripheral region). FIG. 13 is a device cross-sectional view (active cell) regarding the cross-section corresponding to FIG. 2 during the manufacturing process (polysilicon film processing step) for explaining the outline of the wafer process in the manufacturing method of the semiconductor device according to the embodiment of the present application. Area). 14 corresponds to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (polysilicon film processing step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is device sectional drawing (chip peripheral area | region) regarding a cross section. FIG. 15 is a device cross-sectional view (active cell region) regarding a cross-section corresponding to FIG. 2 during the manufacturing process (emitter introduction step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is. FIG. 16 relates to a cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (emitter introduction process) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is device sectional drawing (chip peripheral region). FIG. 17 is a device cross-sectional view (active cell region) relating to the cross-section corresponding to FIG. 2 during the manufacturing process (contact groove forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. ). 18 is a cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (contact groove forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 6 is a device cross-sectional view (chip peripheral region). FIG. 19 is a device cross-sectional view (active cross-sectional view) corresponding to FIG. 2 during the manufacturing process (barrier metal layer forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. Cell region). FIG. 20 corresponds to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (barrier metal layer forming step) for explaining the outline of the wafer process in the semiconductor device manufacturing method of the embodiment of the present invention. It is device sectional drawing (chip peripheral area | region) regarding the cross section to perform. FIG. 21 is a device sectional view (active cell region) relating to the section corresponding to FIG. 2 during the manufacturing process (metal film processing step) for explaining the outline of the wafer process in the manufacturing method of the semiconductor device according to the embodiment of the present application. ). FIG. 22 is a cross section corresponding to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (metal film processing step) for explaining the outline of the wafer process in the manufacturing method of the semiconductor device of the embodiment of the present application. FIG. 6 is a device cross-sectional view (chip peripheral region). FIG. 23 is a device cross-sectional view (active cell) relating to the cross-section corresponding to FIG. 2 during the manufacturing process (final passivation film forming step) for explaining the outline of the wafer process in the method for manufacturing a semiconductor device according to one embodiment of the present application. Area). FIG. 24 corresponds to the chip peripheral section cut-out region R3 of FIG. 3 during the manufacturing process (final passivation film forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. It is device sectional drawing (chip peripheral area | region) regarding a cross section. FIG. 25 is a device cross-sectional view (active cell) regarding the cross-section corresponding to FIG. 2 during the manufacturing process (metal collector electrode forming step) for explaining the outline of the wafer process in the manufacturing method of the semiconductor device according to the embodiment of the present application. Area). 26 corresponds to the chip peripheral section cutout region R3 of FIG. 3 during the manufacturing process (metal collector electrode forming step) for explaining the outline of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present invention. It is device sectional drawing (chip peripheral area | region) regarding a cross section. Based on these, the outline of the wafer process in the manufacturing method of the semiconductor device of the one embodiment of the present application will be described.

  First, a P-type silicon single crystal (for example, boron high-concentration doped) 200φ wafer (wafers of various diameters such as 150φ, 100φ, 300φ, 450φ, etc.) may be prepared. Here, for example, a wafer by the CZ (Czochralski) method is most suitable, but a wafer by the FZ (Floating Zone) method may be used.

  Next, as shown in FIG. 7 and FIG. 8, on the surface 1a (first main surface) side of the P− type silicon single crystal wafer 1, that is, the semiconductor substrate portion 1s (P + type silicon single crystal semiconductor substrate portion). Then, the N + type epitaxial layer 1n and the N type epitaxial layer 1e are sequentially formed by, for example, epitaxial growth. Subsequently, an insulating film 34a for introducing a P-type well region such as a silicon oxide insulating film is formed on the surface 1a of the wafer 1 by, for example, thermal oxidation.

  Next, the P-type well region introducing insulating film 34a is partially removed by ordinary lithography, for example, and the semiconductor substrate surface is re-oxidized by thermal oxidation or the like to form a thin silicon oxide film 35 (sacrificial oxidation) for ion implantation. Film). Next, in this state, boron ions are selectively implanted under the thin silicon oxide film 35 to introduce the P-type well region 9.

  Next, as shown in FIGS. 9 and 10, the insulating film on the surface 1a of the wafer 1 is once removed entirely, and a P-type body such as a silicon oxide insulating film is formed by, for example, CVD (Chemical Vapor Deposition). A region introducing insulating film 34b is formed. Subsequently, the entire surface of the P-type body region introducing insulating film 34b is partially removed by, for example, normal lithography. Subsequently, a thin silicon oxide film 35 (sacrificial oxide film) for ion implantation is formed again by re-oxidizing the removed portion. Next, in this state, boron ions are selectively implanted under the thin silicon oxide film 35 to introduce the P-type body region 6 (P-type channel region). Thereafter, the P-type body region introducing insulating film 34b that has become unnecessary is entirely removed.

  Next, as shown in FIGS. 11 and 12, a trench forming hard mask film 36 such as a silicon oxide insulating film is formed on the surface 1a of the wafer 1 by, for example, CVD. Next, the trench forming hard mask film 36 is patterned by, for example, ordinary lithography. Subsequently, the trench 15 is formed by anisotropic dry etching using the patterned trench forming hard mask film 36 as a mask.

  Next, as shown in FIGS. 13 and 14, the trench forming hard mask film 36 is patterned again by, for example, ordinary lithography. Next, an insulating film 37 formed simultaneously with the gate insulating film 17 and the gate insulating film is formed by, for example, thermal oxidation. Next, a gate electrode polysilicon film is formed on the surface 1a of the wafer 1 by, for example, CVD. Subsequently, the polysilicon film for gate electrode is patterned by, for example, ordinary lithography to form the polysilicon gate electrode 18, the polysilicon gate wiring 28, the polysilicon guard ring 29, and the like.

  Next, as shown in FIGS. 15 and 16, a thin silicon oxide film 39 is formed on the surface of the polysilicon gate electrode 18, the polysilicon gate wiring 28, the polysilicon guard ring 29, etc. by thermal oxidation or the like. In this state, N + type emitter region 12 and N + type channel stop region 30 are introduced by ion implantation of arsenic or the like using the resist film as a mask. Thereafter, the resist film that is no longer needed is entirely removed.

  Next, as shown in FIGS. 17 and 18, interlayer insulation such as a silicon oxide insulating film is formed on the surface 1a of the wafer 1, the surface insulating film 32, the thin silicon oxide film 39, etc. by, for example, CVD. A film 11 is formed. Next, the contact portion 21 (contact groove) is formed by etching the interlayer insulating film 11 and the semiconductor substrate 1 by, for example, ordinary lithography.

Next, as shown in FIGS. 19 and 20, boron is ion-implanted into the semiconductor substrate through the contact groove 21 to introduce the P + type body contact region 14 and the P + type chip peripheral contact region 31. Next, a barrier metal film 19 (first metal layer) such as a titanium nitride film is formed on almost the entire surface of the wafer 1 on the surface 1a side by, for example, sputtering (TiN sputtering step 101 in FIG. 4). . Subsequently, a tungsten film is formed on almost the entire surface of the barrier metal film 19 by, eg, CVD (W film forming step 102 in FIG. 4), thereby filling the contact groove 21. Subsequently, a tungsten plug 20 is formed by removing the tungsten film outside the contact groove 21 by etch back or the like (W etch back process 103 in FIG. 4). This etch back is performed by, for example, isotropic dry etching using SF ₆ -based gas.

  Next, as shown in FIGS. 21 and 22, an aluminum-based metal layer 40 (second metal layer) containing aluminum as a main component is formed on almost the entire surface on the surface 1a side of the wafer 1 by, for example, sputtering film formation. (Al sputtering step 104 in FIG. 4). Here, the metal film 41 is constituted by the barrier metal film 19 (first metal layer), the aluminum-based metal layer 40 (second metal layer), and the like. Thus, the metal film forming step 121 composed of the TiN sputtering step 101 to the Al sputtering step 104 in FIG. 4 is completed.

Next, a photoresist film is formed on almost the entire surface 1a side of the wafer 1 by, for example, coating. Subsequently, this photoresist film is patterned by, for example, ordinary lithography (resist pattern forming step 105 in FIG. 4). Using this patterned photoresist film as a mask, the aluminum-based metal layer 40 is patterned, for example, by wet etching (Al wet etching step 106 in FIG. 4). As a chemical | medical solution used for Al wet etching process 106, the aqueous solution which consists of an acetic acid, nitric acid, phosphoric acid etc. can be illustrated as a suitable thing, for example. The patterning of the aluminum-based metal layer 40 may be performed by isotropic dry etching (when a chlorine-based gas is used, anticorrosion treatment such as H ₂ O ashing or O ₂ plasma treatment is required). Is).

Subsequently, the barrier metal film 19 is patterned by isotropic dry etching (see FIG. 5) (barrier dry etching step 107 in FIG. 4). Here, as an etching gas system in the barrier dry etching step 107, for example, CF ₄ / O ₂ or the like can be exemplified as a suitable one. Thus, the metal film patterning step 122 constituted by the Al wet etching step 106 and the barrier dry etching step 107 in FIG. 4 is completed.

  Subsequently, the photoresist film is removed by plasma ashing (oxygen atmosphere) or the like (resist removal step 108 in FIG. 4). As a result, the metal emitter electrode 5, the metal gate wiring 8, the metal guard ring 3, and the like are formed.

  Here, as shown in FIG. 4, a wet process 109 (negative charge imparting process) for stabilizing the charge distribution on the surface 1a of the wafer 1 is executed. Details will be described in the next section.

  After the wet treatment 109, as shown in FIGS. 23 and 24, a polyimide organic insulating film or the like is formed on almost the entire surface of the wafer 1 on the surface 1a side by, for example, coating. Subsequently, by patterning a polyimide organic insulating film or the like, this is used as a final passivation film 33 (protective film forming step 110 in FIG. 4).

  Next, as shown in FIGS. 25 and 26, the backside grinding process is performed on the back surface 1b of the wafer 1, and the original wafer thickness (for example, about 750 micrometers) is set to about 80 to 280 micrometers (for example). That is, the thickness is reduced to less than 300 micrometers (BG treatment step 111 in FIG. 4).

  Further, a metal back surface drain electrode 24 is formed on the back surface 1b of the wafer 1 by sputtering (back electrode forming step 112 in FIG. 4). The back metal electrode film 24 is formed from the side close to the wafer 1, for example, a back titanium film (gold and nickel diffusion prevention layer), a back nickel film (adhesion layer with a chip bonding material), and a back gold film (nickel oxidation prevention). Layer).

  Thereafter, the chip is divided into individual chips (dicing step 113 in FIG. 4), and transfer molding or the like is performed with a sealing resin to form a packaged device (assembly step 114 in FIG. 4).

3. Description of main process in manufacturing method of semiconductor device according to one embodiment of the present application (refer mainly to FIGS. 5, 6, and 4)
In this section, the details of the wet treatment process 109 (negative charge imparting process) described in section 2, the charging mechanism in the barrier dry etching process 107, and the like will be described.

  Here, as a specific method for imparting a negative charge, spin cleaning (wet processing using a spin table) will be specifically described as an example. However, the present invention is not limited to this, and spray processing and immersion are used. Any method may be used as long as it is a stirring method or other processing method in which friction occurs between the wafer and the chemical solution.

  FIG. 5 is a schematic cross-sectional view of a dry etching apparatus used for a barrier metal processing step in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 6 is a schematic cross-sectional view of a spin wet processing apparatus for explaining a negative charge imparting step (wet surface treatment step) which is a main process in the method of manufacturing a semiconductor device according to the embodiment of the present application. Based on these drawings, a description will be given of essential processes and the like in the method of manufacturing a semiconductor device according to the embodiment of the present application.

  First, the mechanism by which undesired mobile ions are added to the wafer in the barrier dry etching step 107 and the like will be described. FIG. 5 shows a schematic cross-sectional view of an example of a dry etching apparatus (isotropic dry etching apparatus) used in the barrier dry etching step 107. As shown in FIG. 5, a lower electrode 52 (wafer stage) is provided in the lower part of the chamber 51, and the wafer 1 is placed on the lower electrode 52 with its surface 1a facing up. . Here, the lower electrode 52 is grounded. An upper electrode 53 is provided in the upper part of the chamber 51, and the upper electrode 53 is grounded via a high frequency power source 59. When high frequency power is applied by the high frequency power supply 59, plasma 54 is generated between the lower electrode 52 and the upper electrode 53. The plasma 54 is composed of neutral atoms 27a, negative charges 27n (electrons, negative ions), positive charges 27p (positive ions), radicals 27r, and the like. In the case of isotropic dry etching, radicals 27r are mainly used. However, some positive charges 27p (positive ions) remain on the wafer 1 to charge the wafer. Note that the processing gas 56 and the like related to the reaction are supplied from the gas inlet 55, and the exhaust gas 58 of the chamber 51 is exhausted from the gas outlet 57.

  Next, a mechanism for forming a uniform negative charge distribution on the wafer 1 in the wet processing step 109 (FIG. 4) will be described with reference to FIG. As shown in FIG. 6, a wafer suction stage 61 (spin table) is fixed on a rotating shaft 62, and the wafer 1 is suction-held on the surface 1a thereof facing upward. When the chemical liquid 64 is supplied from the chemical liquid nozzle 63, triboelectricity is mutually applied by friction with the wafer 1, the wafer 1 is negatively charged, and the chemical liquid 64 is positively charged.

  As specific conditions for the wet treatment by the spin cleaning apparatus of FIG. 6, the following can be presented as an example. That is, the liquid temperature is, for example, about 60 to 80 degrees Celsius, the liquid flow rate is, for example, about 180 cc / min, the spin speed is, for example, about 1000 rpm, and the processing time is, for example, about 60 seconds to 120 seconds.

Further, as the chemical solution 64, a solvent such as a polymer removal solution used in polymer removal after anisotropic dry etching of an aluminum electrode film (aluminum wiring film) is preferable. Can be presented. That is, a mixed solution of CH ₃ COOH / NH ₄ OH / H ₂ O (composition of about 3: 2: 30) or the like. In addition to this, it is possible to raise a polymer removal solution mainly composed of a mixed solution such as ammonium phosphate polymer removal solution and dimethylsulfoxide / H ₂ O / NHF ₄ / HF.

  These polymer removing liquids are relatively weak but have electrical conductivity, and need to impart negative static electricity to an object such as a silicon wafer (in the case of other materials, the material).

4). Supplementary explanation and general consideration for the above embodiment of the present application (mainly FIGS. 27 to 29)
FIG. 27 is a comparative chart showing the wafer-like potential distribution at the completion of the barrier metal film dry etching process and at the completion of the negative charge application process in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 28 is a potential distribution diagram of an uncharged wafer for comparison with the result of FIG. FIG. 29 is a potential distribution diagram of a wafer obtained by performing the same process as the negative charge applying process on the wafer of FIG. 28 using pure water for comparison with the result of FIG. Based on these, a supplementary explanation for the above embodiment of the present application and a general consideration will be given.

  As shown in FIG. 27, the charge distribution (potential distribution due to static electricity) on the wafer 1 after performing barrier etching (at the time of barrier etching completion) with various etching apparatuses (including the same model) is different for each apparatus. There is a big difference in distribution shape between different models. However, in any case, the distribution is greatly uneven and rich in change. On the other hand, when the negative charge imparting process is performed, the distribution becomes relatively flat, and it can be seen that the entire wafer is largely shifted to the negative side.

  In order to compare with this, the charge distribution on the uncharged wafer and the charge distribution on the wafer after performing pure water spin cleaning on the wafer in the same configuration as the negative charge application process, respectively, It shows in FIG. 28 and FIG. As can be seen from FIGS. 28 and 29, the charge distribution on the uncharged wafer, which was very flat, has changed to a distribution with extremely large fluctuations after cleaning with pure water.

  As described above, in the negative charge imparting process described above, the wafer can be almost uniformly converted into the negatively charged state regardless of the state of the charge distribution of the wafer before the process, which is caused by an undesired positive charge distribution. It is considered that the reliability failure can be effectively reduced.

  As described above, in the above-described embodiment, in the patterning of the metal film (member film), the post-treatment is usually performed after the etching process including isotropic dry etching that does not require the post-treatment with the sidewall polymer removal solution or the like. The negative charge imparting treatment is performed with a chemical solution similar to the sidewall polymer removal solution. This neutralizes the positive charges accumulated on the wafer 1 during isotropic dry etching, and further imparts a relatively deep and uniform negative potential distribution to stabilize the wafer 1 electrostatically. Yes.

  In other words, after the etching step which includes a dry etching which does not substantially involve the formation of the sidewall polymer and which does not substantially involve the formation of the sidewall polymer, a post-treatment is similar to the sidewall polymer removal solution. A negative charge imparting process using chemicals is performed. That is, normally, in such a case, the side wall polymer removal process is not necessary. However, in the above-described embodiment, the side wall polymer removal is purposely performed for electrostatic stabilization of the wafer 1. Then, the treatment with the chemical solution similar to the side wall polymer removing solution is performed.

5. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the IGBT having the trench type gate structure has been specifically described as an example. However, the present invention is not limited thereto, and it is needless to say that the present invention can be applied to the planar structure in the same manner.

  In the above embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the P + silicon single crystal substrate. However, the present invention is not limited to this, and the N + silicon is not limited thereto. A P channel device may be formed on the upper surface of the P epitaxial layer on the single crystal substrate.

  In the above-described embodiments, devices mainly made on a silicon-based semiconductor substrate have been specifically described. However, the present invention is not limited thereto, and a GaAs-based semiconductor substrate, a silicon carbide-based semiconductor substrate, and a silicon nitride. Needless to say, the present invention can be applied almost as it is to a device made on a ride-type semiconductor substrate.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a The surface of a semiconductor wafer or chip (first main surface)
1b Rear surface of semiconductor wafer or chip (second main surface)
1e N type epitaxy layer 1n N + type epitaxy layer 1s Semiconductor substrate part (P + type silicon single crystal semiconductor substrate part)
2 Semiconductor chip (semiconductor substrate)
3 Metal guard ring 4 Active cell region 5 Metal emitter electrode 6 P-type body region (P-type channel region)
6p Cell peripheral P-type main junction region 7 Metal gate electrode (gate pad opening)
8 Metal gate wiring 9 P type well region 10 Unit cell region 11 Interlayer insulating film 12 N + type emitter region 14 P + type body contact region 15 Trench 16 N type drift region 17 Gate insulating film 18 Polysilicon gate electrode 19 Barrier metal film (first 1 metal layer)
20 Tungsten plug 21 Contact part (contact groove)
22 N + type field stop region 23 P + type collector region 24 Metal collector electrode 25 Depletion layer 26 Chip peripheral region 27a Neutral atom 27n Negative mobile ion (or negative charge)
27p Positive mobile ion (or positive charge)
27r radical 28 polysilicon gate wiring 29 polysilicon guard ring 30 N + type channel stop region 31 P + type chip peripheral contact region 32 surface insulating film 33 final passivation film 34a insulating layer for introducing P type well region 34b insulating for introducing P type body region Film 35 Thin silicon oxide film for ion implantation 36 Hard mask film for trench formation 37 Insulating film formed simultaneously with gate insulating film 38 Tungsten CVD film 39 Thin silicon oxide film on polysilicon 40 Aluminum-based metal layer (second Metal layer)
41 Metal film 42 Emitter pad opening 51 Chamber 52 Lower electrode (wafer stage)
53 Upper electrode 54 Plasma 55 Gas inlet 56 Processing gas 57 Gas outlet 58 Exhaust gas 59 High frequency power supply 61 Wafer adsorption stage (spin table)
62 Rotating shaft 63 Chemical liquid nozzle 64 Chemical liquid 101 TiN sputtering process 102 W film forming process 103 W etch back process 104 Al sputtering process 105 Resist pattern forming process 106 Al wet etching process 107 Barrier dry etching process 108 Resist removing process 109 Wet processing process ( Negative charge application process)
110 Protective film forming process 111 BG treatment process 112 Back electrode forming process 113 Dicing process 114 Assembly process 121 Metal film forming process 122 Metal film patterning process R1 Chip edge cutout area R2 Active cell cutout area R3 Chip peripheral cutout area

Claims (20)

A semiconductor device manufacturing method including the following steps:
(A) forming a metal film on substantially the entire surface of the first main surface of the semiconductor wafer having the first main surface and the second main surface;
(B) forming a resist film having a pattern on the metal film;
(C) patterning the metal film by etching without using anisotropic dry etching in the presence of the resist film;
(D) a step of removing the resist film after the step (c);
(E) After the step (d), a step of negatively charging substantially the whole of the first main surface side of the semiconductor wafer;
Here, the step (c) includes the following substeps:
(C1) A step of patterning the first metal layer constituting the metal film by isotropic dry etching. In the method of manufacturing a semiconductor device according to the item 1, the metal film has the following:
(X1) the lower first metal layer;
(X2) an upper second metal layer,
Here, the first metal layer is a barrier metal layer, and the second metal layer is an aluminum-based metal layer. In the method for manufacturing a semiconductor device according to the item 2, the step (c) includes the following sub-steps:
(C2) A step of patterning the second metal layer by performing wet etching on the second metal layer using the resist film as a mask before the substep (c1).     In the method for manufacturing a semiconductor device according to the item 3, the step (e) is performed by wet processing using a conductive processing solution.     In the method for manufacturing a semiconductor device according to item 4, the metal film is mainly formed on an insulating film on the first main surface of the semiconductor wafer. The method for manufacturing a semiconductor device according to the item 5, further includes the following steps:
(F) A step of forming a final passivation film on substantially the entire surface of the metal film after the step (e).     In the method of manufacturing a semiconductor device according to item 6, the step (d) is performed by an ashing process.     8. The method for manufacturing a semiconductor device according to item 7, wherein the conductive treatment liquid is a polymer stripping liquid.     In the method for manufacturing a semiconductor device according to the item 8, the conductive processing liquid is supplied to the first main surface side in a state where the wafer is spun.     In the method for manufacturing a semiconductor device according to the item 9, the conductive treatment liquid is an aqueous solution containing acetic acid and ammonia as main components. A semiconductor device manufacturing method including the following steps:
(A) forming a metal film on substantially the entire surface of the first main surface of the semiconductor wafer having the first main surface and the second main surface;
(B) forming a resist film having a pattern on the metal film;
(C) patterning the metal film by etching in the presence of the resist film without using dry etching that substantially involves formation of a sidewall polymer;
(D) a step of removing the resist film after the step (c);
(E) After the step (d), a step of negatively charging substantially the whole of the first main surface side of the semiconductor wafer;
Here, the step (c) includes the following substeps:
(C1) A step of patterning the first metal layer constituting the metal film by dry etching without substantially forming a sidewall polymer. In the method for manufacturing a semiconductor device according to the item 11, the metal film has the following:
(X1) the lower first metal layer;
(X2) an upper second metal layer,
Here, the first metal layer is a barrier metal layer, and the second metal layer is an aluminum-based metal layer. In the method of manufacturing a semiconductor device according to the item 12, the step (c) includes the following substeps:
(C2) A step of patterning the second metal layer by performing wet etching on the second metal layer using the resist film as a mask before the substep (c1).     In the method for manufacturing a semiconductor device according to the item 13, the step (e) is performed by wet processing using a conductive processing solution.     In the method for manufacturing a semiconductor device according to the item 14, the metal film is mainly formed on an insulating film on the first main surface of the semiconductor wafer. The method for manufacturing a semiconductor device according to the item 15, further includes the following steps:
(F) A step of forming a final passivation film on substantially the entire surface of the metal film after the step (e).     In the method for manufacturing a semiconductor device according to the item 16, the step (d) is performed by an ashing process.     In the method for manufacturing a semiconductor device according to the item 17, the conductive treatment liquid is a polymer stripping liquid.     In the method of manufacturing a semiconductor device according to the item 18, the conductive processing liquid is supplied to the first main surface side in a state where the wafer is spun.     20. In the method for manufacturing a semiconductor device according to the item 19, the conductive treatment liquid is an aqueous solution containing acetic acid and ammonia as main components.

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