JP2013041649A - Write-in circuit of resistance change type nonvolatile storage element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a write-in circuit of a resistance change type nonvolatile storage element capable of simply and independently performing write-in avoiding multiple write-in at a high speed.SOLUTION: A write-in circuit 1 for a resistance change element 2 applies voltage for causing the resistance change element 2 to transition to a low resistance state to the resistance change element 2 only when the resistance change element 2 is in a high resistance state, and applies voltage for causing the resistance change element 2 to transition to a high resistance state to the resistance change element 2 only when the resistance change element 2 is in a low resistance state.

Description

  The present invention relates to a resistance variable nonvolatile memory element writing circuit.

  A variable resistance nonvolatile memory element represented by a variable resistance element (ReRAM) (hereinafter also simply referred to as “nonvolatile memory element”) has a large capacity, high speed operation, low power consumption, low bit cost, and the like. Therefore, it is expected as a next-generation new type non-volatile memory element, and various developments are being continued.

  Such a nonvolatile memory element has at least one of a high resistance state (for example, a logical value “1”) and a low resistance state (for example, a logical value “0”), and a positive voltage pulse. And when a negative voltage pulse is applied, it has the property of transitioning from one resistance state to the other according to the polarity of the voltage pulse. For example, when a nonvolatile memory element is in a high resistance state (hereinafter also referred to as “reset state”), a pulse having a constant positive voltage with respect to the other end with respect to one end of the nonvolatile memory element (hereinafter referred to as “reset state”). , (Also referred to as “set pulse”), the nonvolatile memory element transitions to a low resistance state (hereinafter referred to as “set state”). On the other hand, when the nonvolatile memory element is in a low resistance state (“set state”), a pulse having a constant negative voltage with respect to the other end with respect to one end of the nonvolatile memory element (hereinafter referred to as “reset pulse”). ”Is applied (hereinafter also referred to as“ reset ”), the nonvolatile memory element transitions to a high resistance state (“ reset state ”).

  Assume that a nonvolatile memory element having such characteristics is now written in a set state. As the simplest writing method, it is conceivable to apply a set pulse to the nonvolatile memory element regardless of the resistance state of the nonvolatile memory element. However, in such a writing method, there is a possibility that multiple writing in which a set pulse is applied to a nonvolatile memory element already in a set state may be performed. Multiple writing, such as applying a set pulse to a nonvolatile memory element in a set state and vice versa, applying a reset pulse to a nonvolatile memory element in a reset state is performed on the nonvolatile memory element. On the other hand, it not only increases power consumption by applying unnecessary energy, but also causes deterioration of characteristics of the nonvolatile memory element (reduction of the number of rewrites, etc.) due to electrical stress applied to the nonvolatile memory element. End up.

  Therefore, conventionally, a technique for avoiding such multiple writing has been proposed (see, for example, Patent Document 1). FIG. 12 is a flowchart showing a procedure of a conventional writing method. Here, when writing to a non-volatile memory element, first, the resistance state of the non-volatile memory element is read (S1), and it is determined whether or not it is necessary to write (that is, it is necessary to invert the resistance state) (S2). Only when it is necessary to write (Yes in S2), writing to the nonvolatile memory element is performed (S3). For example, when setting a non-volatile memory element, first, the resistance state of the non-volatile memory element is read (S1), and whether or not the non-volatile memory element is in a reset state according to the read result. Judgment is made (S2), and only in the reset state (Yes in S2), a set pulse is applied to the nonvolatile memory element (S3). Thereby, multiple writing is avoided.

Japanese Patent Laid-Open No. 07-220479

  However, in the conventional writing method, a read circuit, a determination circuit, and a write circuit are required for writing to the nonvolatile memory element, as can be seen from the flowchart of FIG. For this reason, the conventional technique has a problem that the scale of the write circuit of the nonvolatile memory element is increased, power consumption is increased, and the circuit is complicated.

  Therefore, the present invention has been made in view of such a problem, and writing of a variable resistance nonvolatile memory element that can perform writing while avoiding multiple writing in a simple and high speed manner. An object is to provide a circuit or the like.

  In order to achieve the above object, one embodiment of a resistance change nonvolatile memory element write circuit according to the present invention is a write circuit for a resistance change nonvolatile memory element, wherein the nonvolatile memory element has a high resistance. A voltage for causing the nonvolatile memory element to transition to a low resistance state is applied to the nonvolatile memory element only when the nonvolatile memory element is in a low resistance state, and only when the nonvolatile memory element is in a low resistance state Is applied to the non-volatile memory element. Thereby, when setting a non-volatile memory element, a set pulse is applied only when the non-volatile memory element is in a reset state. On the other hand, when resetting a non-volatile memory element, the non-volatile memory element is Since the reset pulse is applied only in the set state, writing that avoids multiple writing is simple and fast without the need for circuits such as a read circuit, a determination circuit, and a write circuit. It is done automatically (independently).

  More specifically, the resistance state is connected to one end of the nonvolatile memory element, and the resistance state at the one end depends on whether the nonvolatile memory element is in a high resistance state or a low resistance state. A voltage generation circuit for generating a voltage for making a transition. More specifically, the voltage generation circuit reads and holds the resistance state of the nonvolatile memory element, and applies a voltage corresponding to the resistance state held by the holding part to one end of the nonvolatile memory element. And an applying unit.

  At this time, the holding unit has a reference resistance having a resistance value between a resistance value in a high resistance state and a resistance value in a low resistance state of the nonvolatile memory element, and the resistance value of the reference resistance and the nonvolatile memory element The magnitude relationship with the resistance value of the volatile memory element is held as the resistance state, and the application unit has a first voltage and a second voltage lower than the first voltage according to the magnitude relationship held in the holding unit. Is preferably applied to one end of the nonvolatile memory element. Thereby, when setting the nonvolatile memory element, the set pulse is applied only when the resistance value of the nonvolatile memory element is larger than the resistance value of the reference resistance, while when resetting the nonvolatile memory element. The reset pulse is applied only when the resistance value of the nonvolatile memory element is smaller than the resistance value of the reference resistance.

  Further, a fourth voltage lower than the third voltage and the third voltage is connected to the other end of the nonvolatile memory element and the nonvolatile memory element is set to one of a high resistance state and a low resistance state. When one of the voltages is applied to the other end and the nonvolatile memory element is set to the other of the high resistance state and the low resistance state, the other of the third voltage and the fourth voltage is set to the other A switch unit to be applied to the end may be provided. As a result, writing that avoids multiple writing is performed in conjunction with the switch unit.

  In addition, the write circuit for the variable resistance nonvolatile memory element is connected to one end of the nonvolatile memory element, and applies a first voltage to the one end when the nonvolatile memory element is in a high resistance state. A first write circuit that applies a second voltage lower than the first voltage to the one end when the nonvolatile memory element is in a low resistance state, and is connected to the other end of the nonvolatile memory element; The second voltage is applied to the other end when the nonvolatile memory element is in a high resistance state, and the first voltage is applied to the other end when the nonvolatile memory element is in a low resistance state. The nonvolatile memory element has a resistance value lowered when a first voltage is applied to the one end and a second voltage is applied to the other end. A second voltage is applied to the If the first voltage is applied to the other end, the resistance value may be configured to have a property of being high resistance. Thereby, writing avoiding multiple writing is performed using two writing circuits.

  In addition, the multi-value writing circuit sets the resistance change type nonvolatile memory element to a resistance value between a first resistance value and a second resistance value larger than the first resistance value. When the nonvolatile memory element is connected to one end of the element and has a resistance value smaller than the first resistance value, a first voltage is applied to the one end, and the nonvolatile memory element is more than the first resistance value. A first write circuit that applies a second voltage lower than the first voltage to the one end and the other end of the non-volatile memory element, and the non-volatile memory element is When the resistance value is smaller than the second resistance value, the second voltage is applied to the other end, and when the nonvolatile memory element has a resistance value larger than the second resistance value, the other end A second write circuit for applying the first voltage to The nonvolatile memory element has a high resistance when a first voltage is applied to the one end and a second voltage is applied to the other end, and the second voltage is applied to the one end. When the first voltage is applied to the other end, the resistance value may be reduced. Thereby, multi-value writing in which the resistance value of the nonvolatile memory element can be set between two reference resistance values using two write circuits is performed. Therefore, by adding a circuit for changing two reference resistance values, it becomes possible to set the resistance value of one nonvolatile memory element to any one of three or more multi-values. Memory cells that can be stored are realized, and the memory capacity per memory cell is increased.

  In addition, the multi-value writing circuit sets the resistance change type nonvolatile memory element to a resistance value between a first resistance value and a second resistance value larger than the first resistance value. When the nonvolatile memory element is connected to one end of an element and has a resistance value smaller than the first resistance value, a first voltage is applied to the one end and output from the output terminal, and the nonvolatile memory element is A first write circuit for applying a second voltage lower than the first voltage to the one end and outputting the output from an output terminal when the non-volatile memory element has the resistance value larger than the first resistance value; When the resistance value is smaller than the second resistance value, the second voltage is output from the output terminal, and when the nonvolatile memory element has a resistance value larger than the second resistance value, the first voltage is output. Output from the output terminal. A second write circuit; and at least two switch elements connected to the other end of the nonvolatile memory element, wherein one of the two switch elements is connected to the first voltage from an output terminal of the first write circuit. Is output to the other end, and the other one of the two switch elements is when the first voltage is output from the output terminal of the second write circuit. The first voltage is applied to the other end, and the nonvolatile memory element has a high resistance value when the first voltage is applied to the one end and the second voltage is applied to the other end. It is good also as a structure which has a characteristic which resistance is made low, when a 2nd voltage is applied to the said one end, and a 1st voltage is applied to the said other end when it resistance-izes. Thereby, multi-value writing in which the resistance value of the nonvolatile memory element can be set between two reference resistance values using two write circuits is performed. Therefore, by adding a circuit for changing two reference resistance values, it becomes possible to set the resistance value of one nonvolatile memory element to any one of three or more multi-values. Memory cells that can be stored are realized, and the memory capacity per memory cell is increased.

  The present invention can be realized not only as a write circuit and a multi-value write circuit of the variable resistance nonvolatile memory element as described above, but also by performing a write procedure using these write circuit and multi-value write circuit, or a write procedure. It may be realized as a driving method of a writing circuit for controlling the above.

  According to the variable resistance nonvolatile memory element writing circuit and the like according to the present invention, writing of the variable resistance nonvolatile memory element that can perform writing while avoiding multiple writing in a simple and fast manner is possible. A circuit or the like is realized.

  Therefore, the practical value of the present invention is extremely high today when electronic devices requiring a large capacity, high-speed operation and low power consumption nonvolatile memory have become widespread.

4 is a circuit diagram of a write circuit of a resistance change type nonvolatile memory element according to an embodiment of the present invention. The figure which shows operation | movement (1st step; equalization) of the voltage generation circuit with which the same write circuit is equipped The figure which shows operation | movement (2nd step; amplification) of the voltage generation circuit The figure which shows the operation | movement (3rd step; writing) of the voltage generation circuit Circuit diagram showing an example of a voltage generation circuit capable of generating a large power voltage A circuit diagram showing another example of a voltage generation circuit capable of generating a voltage of large power The circuit diagram of the voltage generation circuit of the voltage differential sense system in the modification 1 of this invention Timing chart showing operation of the voltage generator Circuit diagram of another voltage generation circuit of the current differential sense system in the second modification of the present invention Timing chart showing operation of the voltage generator Circuit diagram of write circuit in application example 1 of the present invention The figure which shows the resistance change characteristic of a general resistance change element The flowchart which shows the drive method of the write circuit in the application example 2 of this invention. The figure which shows the change of the write time in the drive method of the write circuit Block diagram of multi-value write circuit in application example 3 of the present invention The figure explaining the multi-value writing circuit in the application example 4 of this invention The flowchart which shows the procedure of the conventional writing method

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Each of the embodiments described below shows a preferred specific example of the present invention. Circuit elements, connection modes, transistor types, operation procedures, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. The invention is limited only by the claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present invention are not necessarily required to achieve the object of the present invention. It will be described as constituting a preferred form.

  FIG. 1 is a circuit diagram of a write circuit of a variable resistance nonvolatile memory element according to an embodiment of the present invention. In this figure, the variable resistance element 2 is used as the variable resistance nonvolatile memory element. However, if the nonvolatile memory element has a variable resistance value, other types of nonvolatile memory elements (for example, It may be a phase change memory (PRAM), a magnetoresistive memory (MRAM), or the like. In the present embodiment, the resistance change element 2 transitions to a low resistance state when a high voltage (for example, voltage Vdd) is applied to the upper terminal with the lower terminal as a reference in the illustrated connection state ( On the other hand, it is assumed that when a high voltage (for example, voltage Vdd) is applied to the lower terminal with reference to the upper terminal, a transition is made to a high resistance state (reset).

  The writing circuit 1 is a writing circuit for a resistance change type nonvolatile memory element (here, the resistance change element 2), and the resistance change element only when the resistance change element 2 is in a high resistance state (reset state). A voltage for transitioning 2 to the low resistance state is applied (set) to the resistance change element 2, and the resistance change element 2 is transitioned to the high resistance state only when the resistance change element 2 is in the low resistance state (set state). It has a function of applying (resetting) a voltage for causing the resistance change element 2 to be applied.

  Specifically, the write circuit 1 includes a voltage generation circuit 25 and a switch unit 40. The voltage generation circuit 25 is connected to one end (the upper terminal in the drawing) of the variable resistance element 2, and depends on whether the variable resistance element 2 is in a high resistance state or a low resistance state. A voltage for transitioning the resistance state is generated at the upper terminal). Here, the voltage generation circuit 25 applies a High voltage (for example, the voltage Vdd) to one end (upper terminal) of the resistance change element 2 when the resistance change element 2 is in a high resistance state, When 2 is in a low resistance state, a Low voltage (for example, a GND potential) is applied to one end (upper terminal) of the resistance change element 2.

  The switch unit 40 is connected to the other end (the lower terminal in the drawing) of the variable resistance element 2, and when the variable resistance element 2 is set to one of a high resistance state and a low resistance state, a third voltage (here Then, one of a high voltage) and a fourth voltage (here, low voltage) lower than the third voltage is applied to the other end (lower terminal), and the variable resistance element 2 is in a high resistance state and a low resistance state. When the other voltage is set to the other, the other of the third voltage (High voltage) and the fourth voltage (Low voltage) is applied to the other end. Specifically, the switch unit 40 includes a power supply 41 for voltage Vdd and a switch 42 connected in series, and the resistance change element is controlled by the switch 42 from a control circuit (not shown). 2 is set (set) in a low resistance state, a low voltage is applied to the other end (lower terminal) of the resistance change element 2 and the resistance change element 2 is set (reset) in a high resistance state. A High voltage is applied to the other end (lower terminal) of the resistance change element 2.

  With such a configuration, the write circuit 1 according to the present embodiment performs the following operation.

(1) When the resistance change element 2 is set (set) in the low resistance state The lower terminal of the resistance change element 2 is fixed to the low potential (GND) by the switch unit 40 described above.

  On the other hand, when the variable resistance element 2 is in a high resistance state by the voltage generation circuit 25 described above, a high voltage is applied to the upper terminal of the variable resistance element 2, and the variable resistance element 2 is in a low resistance state. In some cases, a Low voltage is applied.

  As a result, only when the variable resistance element 2 is in a high resistance state (reset state), a voltage (here, a high voltage at the upper terminal with respect to the lower terminal) is applied to both ends of the variable resistance element 2. As a result, the resistance change element 2 transitions (sets) from the high resistance state to the low resistance state. That is, when the variable resistance element 2 is already in a low resistance state, no voltage is applied to both ends of the variable resistance element 2, and multiple writing is avoided.

(2) When the variable resistance element 2 is set (reset) to the high resistance state The lower terminal of the variable resistance element 2 is fixed to the high potential (voltage Vdd) by the switch unit 40 described above.

  On the other hand, when the variable resistance element 2 is in a high resistance state by the voltage generation circuit 25 described above, a high voltage is applied to the upper terminal of the variable resistance element 2, and the variable resistance element 2 is in a low resistance state. In some cases, a Low voltage is applied.

  As a result, only when the resistance change element 2 is in a low resistance state (set state), a voltage (here, a high voltage at the lower terminal with respect to the upper terminal) is applied to both ends of the resistance change element 2. As a result, the resistance change element 2 transitions from the low resistance state to the high resistance state (reset). That is, when the variable resistance element 2 is already in a high resistance state, no voltage is applied to both ends of the variable resistance element 2, and multiple writing is avoided.

  Hereinafter, the voltage generation circuit 25 constituting the write circuit 1 will be described in more detail.

  As shown in FIG. 1, the voltage generation circuit 25 reads and holds the resistance state of the resistance change element 2, and a voltage corresponding to the resistance state held by the holding part 10 is applied to the resistance change element 2. This is a sense amplifier having an application unit 30 that applies to one end (upper end).

  The holding unit 10 includes a reference resistor 21 having a resistance value between the resistance value in the high resistance state and the resistance value in the low resistance state of the resistance change element 2, and the resistance value of the reference resistance 21 and the resistance change element 2. This is a latch circuit that holds the magnitude relationship with the resistance value as the resistance state of the variable resistance element 2. In addition to the reference resistor 21, the holding unit 10 includes transistors (NMOS transistors 11, 13 to 15, 17 to 20, PMOS transistors 12 and 16) that form an SRAM.

  The source of the PMOS transistor 12 is connected to the power supply voltage Vdd, the drain of the PMOS transistor 12 is connected to the drain of the NMOS transistor 13, the source of the NMOS transistor 13 is connected to the drains of the NMOS transistors 14 and 11, and the source of the NMOS transistor 14 Is connected to the drain of the NMOS transistor 19, and the source of the NMOS transistor 19 is connected to GND. Similarly, the source of the PMOS transistor 16 is connected to the power supply voltage Vdd, the drain of the PMOS transistor 16 is connected to the drain of the NMOS transistor 17, the source of the NMOS transistor 17 is connected to the drains of the NMOS transistors 18 and 20, and the NMOS transistor The source of 18 is connected to the drain of the NMOS transistor 19.

  The gate of the PMOS transistor 12, the gates of the NMOS transistors 13 and 14, the one end of the NMOS transistor 15, and the drain of the PMOS transistor 16 are connected to each other. Similarly, the gate of the PMOS transistor 16, the gates of the NMOS transistors 17 and 18, the other end of the NMOS transistor 15, and the drain of the PMOS transistor 12 are connected to each other.

  The source of the NMOS transistor 11 is connected to one end (upper terminal) of the variable resistance element 2 and the drain of the PMOS transistor 31. Similarly, the source of the NMOS transistor 20 is connected to one end (upper terminal) of the reference resistor 21 and the drain of the PMOS transistor 32. The other end (lower terminal) of the reference resistor 21 is connected to GND.

  A control signal wl is sent from a control circuit (not shown) to the gate of the NMOS transistor 11 and the gate of the NMOS transistor 20. A control signal re is sent to the gate of the NMOS transistor 19 from a control circuit (not shown).

  The application unit 30 has a first voltage and a second voltage lower than the first voltage depending on the state held by the holding unit 10 (the magnitude relationship between the resistance value of the resistance change element 2 and the resistance value of the reference resistor 21). Is applied to one end (upper terminal) of the resistance change element 2. Here, when the resistance change element 2 is in a high resistance state, a high voltage is applied to the upper terminal of the resistance change element 2. When the variable resistance element 2 is in a low resistance state, the variable resistance element 2 includes transistors (PMOS transistors 31 and 32) for applying a low voltage to the upper terminal of the variable resistance element 2.

  The operation of the voltage generating circuit 25 according to the present embodiment configured as described above will be described with reference to FIGS. 2A to 2C. The voltage generation circuit 25 always shows 3 in FIG. 2A to FIG. 2C without depending on the write contents (set or reset) of the variable resistance element 2 and the current resistance state of the variable resistance element 2. The write operation is performed in one step.

  First, as a first step, as indicated by timing 1 in the timing chart of FIG. 2A, the control signal wl, the control signal re, the control signal se, and the control signal we_inv become High (for example, the voltage Vdd). In this state, the application unit 30 (PMOS transistors 31 and 32) is turned off and all the transistors constituting the holding unit 10 are turned on. At this time, since the NMOS transistor 15 is turned on, the gates of the NMOS transistor 14 and the NMOS transistor 18 have the same potential, and as a result, the drains of the NMOS transistor 14 and the NMOS transistor 18 have the same potential (equalized state). Since the NMOS transistors 11 and 20 are ON, a voltage having the same potential is applied to the upper terminals of the resistance change element 2 and the reference resistor 21. As a result, depending on the resistance value Rm of the resistance change element 2 and the resistance value Rref of the reference resistance 21, currents Im and Iref flow through the resistance change element 2 and the reference resistance 21, respectively. For example, when Rm> Rref, Iref> Im. In the first step, in the switch unit 40 in FIG. 1, the switch 42 is connected to GND.

  Next, as a second step, as indicated by timing 2 in the timing chart of FIG. 2B, only the control signal se that has become High becomes Low (for example, GND). In this state, the application unit 30 (PMOS transistors 31 and 32) remains OFF, and in the holding unit 10, positive feedback (amplification) occurs, and the variable resistance element 2 and the reference resistor 21 function as SRAMs (latch circuits). Maintains the magnitude relationship of resistance. For example, when Rm> Rref (that is, Iref> Im), the potential of the node vout_left (the connection point between the PMOS transistor 12 and the NMOS transistor 13) approaches the voltage Vdd, while the node vout_right (with the PMOS transistor 16 and the PMOS transistor 16). The potential at the connection point with the NMOS transistor 17 is close to GND. In the second step, in the switch unit 40 in FIG. 1, the switch 42 is connected to GND.

  Finally, as a third step, as indicated by timing 4 in the timing chart of FIG. 2C, the control signal we_inv that has become High becomes Low while the control signal wl is Low. As a result, since the NMOS transistors 11 and 20 are OFF, the holding unit 10 maintains the holding state and the PMOS transistors 31 and 32 are turned ON. Therefore, in the applying unit 30, the potential of the node vout_left is set. In addition to being applied to the upper terminal of the resistance change element 2, the potential of the node vout_right is applied to the upper terminal of the reference resistor 21 (that is, writing is performed). For example, when Rm> Rref (that is, Iref> Im), a high voltage is applied to the upper terminal of the resistance change element 2 and a low voltage is applied to the upper terminal of the reference resistor 21. On the other hand, when Rm <Rref (that is, Iref <Im), the Low voltage is applied to the upper terminal of the resistance change element 2 and the High voltage is applied to the upper terminal of the reference resistor 21. In the third step, in the switch unit 40 in FIG. 1, the switch 42 is switched to the GND connection at the time of setting, and to the voltage Vdd connection at the time of resetting.

  As described above, according to the voltage generation circuit 25 in the present embodiment, the High voltage is applied to the upper terminal of the resistance change element 2 when the resistance change element 2 is in the high resistance state, and the resistance change element 2 Is in a low resistance state, a low voltage is applied. Therefore, when the variable resistance element 2 is set (set) in the low resistance state by the combination of the voltage generation circuit 25 and the switch unit 40, the resistance change element 2 is only in resistance when the variable resistance element 2 is in the high resistance state. A voltage (here, a High voltage at the upper terminal with respect to the lower terminal) is applied to both ends of the change element 2, and as a result, the resistance change element 2 transitions from the high resistance state to the low resistance state. On the other hand, when the resistance change element 2 is set (reset) to the high resistance state, the voltage (here, the upper terminal is used as a reference) only when the resistance change element 2 is in the low resistance state. As a result, the resistance change element 2 transits from the low resistance state to the high resistance state. Therefore, multiple writing to the variable resistance element 2 is automatically (autonomous) avoided.

  In the third step (writing), when a large amount of power is required, a buffer amplifier (here, a buffer amplifier) is connected to the sources of the PMOS transistors 31 and 32 as in the application unit 30a shown in FIG. 3A. , A single-stage inverter) 33 and 34 may be additionally connected, or a buffer amplifier (here, two-stage inverter) may be connected to the sources of the PMOS transistors 31 and 32, respectively, as in the application unit 30b shown in FIG. 3B. Inverters) 35 and 36 may be added and connected. As a result, writing to the variable resistance element 2 is performed with a larger current.

  Next, a modified example of the present embodiment and an application example of the write circuit according to the present invention will be described.

(Modification 1)
First, a write circuit according to the first modification will be described.

  As a method of sensing the resistance value of the variable resistance element to be written, the difference between the current Im flowing through the variable resistance element 2 and the current Iref flowing through the reference resistor 21 is detected as in the write circuit 1 shown in FIG. The current differential sense method is not limited to the voltage differential sense method.

  FIG. 4 is a circuit diagram of the voltage differential sensing type voltage generating circuit 25a according to the present invention. The voltage generating circuit 25a reads and holds the resistance state of the resistance change element 2, and a voltage corresponding to the resistance state held by the holding part 10a at one end (upper terminal) of the resistance change element 2. And an applying unit 30c for applying.

  The holding unit 10a includes a reference resistor 121 having a resistance value Rref between a resistance value in a high resistance state and a resistance value in a low resistance state of the resistance change element 2, and the resistance value Rref of the reference resistor 121 and the resistance change element 2 is a latch circuit that senses the magnitude relationship with the resistance value Rm of 2 by voltage differential and holds the sensed magnitude relationship as the resistance state of the resistance change element 2. The holding unit 10a includes transistors (NMOS transistors 105 to 107, PMOS transistors 101 to 104, and 108) that form an SRAM in addition to the reference resistor 121. Note that the capacitances Cout and Cin in the figure are parasitic capacitances.

  The application unit 30c has a lower voltage than the first voltage and the first voltage according to the state held by the holding unit 10a (the magnitude relationship between the resistance value Rm of the resistance change element 2 and the resistance value Rref of the reference resistor 21). This is a circuit that applies one of two voltages to one end (upper terminal) of the resistance change element 2. Specifically, like the application unit 30 in FIG. 1, the application unit 30c applies a high voltage to the upper terminal of the resistance change element 2 when the resistance change element 2 is in a high resistance state, When the change element 2 is in a low resistance state, the change element 2 includes transistors (NMOS transistors 109 to 112) for applying a low voltage to the upper terminal of the resistance change element 2.

  In the voltage generation circuit 25a, NMOS transistors 123 and 124 are connected in series with the variable resistance element 2 and the reference resistor 121, respectively, and a so-called 1T1R memory cell is provided. Further, from a control circuit not shown, a control signal rw is sent to the gates of the NMOS transistors 109 and 110, a control signal se_control is sent to the gates of the NMOS transistors 111 and 112, and a control signal se is sent to the gate of the NMOS transistor 107. The control signal WL is sent to the NMOS transistors 123 and 124. The voltages at the upper terminals of the resistance change element 2 and the reference resistor 121 are denoted as Vin and Vin_ref, respectively, and the voltages at the output terminals of the holding unit 10a (the drains of the PMOS transistors 103 and 104) are denoted as Vout and Vout_ref, respectively. The lower terminal of the resistance change element 2 and the reference resistor 121 (more precisely, the lower terminals of the NMOS transistors 123 and 124) is referred to as SL.

  FIG. 5 is a timing chart showing the operation of the voltage generation circuit 25a. Here, writing to set the resistance change element 2 to the low resistance state (“set” in the figure), writing to set the resistance change element 2 to the high resistance state (“reset” in the figure), and the resistance change element 2 The operation timing is shown for three cases of reading (“read” in the figure).

  First, in the first step (“Equalization” in the figure), the control signal WL is held high when the control signal WL changes from high to low while the control signal rw is high and a constant potential is applied to the terminal SL. Charging to the two capacitors Cin of the unit 10a is started. That is, the current from the left terminal SL is charged to the capacitor Cin connected to the gate of the PMOS transistor 101 via the NMOS transistor 123, the resistance change element 2, and the NMOS transistor 109, and as a result, the waveform of the voltage Vin Is a rising waveform as shown by Vin in FIG. Similarly, the current from the right terminal SL is charged into the capacitor Cin connected to the gate of the PMOS transistor 102 via the NMOS transistor 124, the reference resistor 121 and the NMOS transistor 110, and as a result, the waveform of the voltage Vin_ref. Is a rising waveform as shown by Vin_ref in FIG.

  Next, in the second step (“amplification” in the figure), writing to the low resistance state (“set”), writing to the high resistance state (“reset”), and reading (“read”) are performed. Depending on which one is performed, a predetermined voltage is applied to various control signals and the terminal SL as shown in the figure. However, in any operation, voltage levels that amplify the difference between the input voltages Vin and Vin_ref are output to the voltages Vout and Vout_ref at the output terminal, respectively. For example, when the resistance value of the resistance change element 2 is smaller than the resistance value of the reference resistor 121, the current flowing into the left capacitor Cin is larger than the current flowing into the right capacitor Cin, so that the input voltage Vin is As shown in FIG. 5, the wave height is higher than the input voltage Vin_ref. As a result, the drain current of the PMOS transistor 102 becomes larger than the drain current of the PMOS transistor 101, and the potential of the connection point (that is, the voltage Vout_ref) between the PMOS transistor 104 and the NMOS transistor 106 rises. Positive feedback in which the potential at the connection point with the NMOS transistor 105 (that is, the voltage Vout) is lowered works.

  As described above, the voltages Vout and Vout_ref at the two output terminals are determined depending on the magnitude relationship between the resistance value Rm of the resistance change element 2 and the resistance value Rref of the reference resistor 121 (in this case, Rm> Rref). Vout = Vdd and Vout_ref = GND, and when Rm <Rref, Vout = GND and Vout_ref = Vdd). Therefore, such a voltage (Vout or Vout_ref) is used as a voltage applied to one end of the resistance change element 2 at the time of writing to the resistance change element 2 (for example, the voltage Vout by setting the control signal se_control to High). Is applied to the upper terminal of the resistance change element 2), so that the voltage differential sense type write circuit having the same function as the write circuit 1 (or voltage generation circuit 25) in the above embodiment, that is, multiple write Can be automatically (independently) avoided.

  Note that the third step in FIG. 5 (“Reset” in the figure) shows the initial state of the voltage generation circuit 25a (the state in which neither writing nor reading is performed).

(Modification 2)
Next, a write circuit according to the second modification will be described.

  The voltage generation circuit of the current differential sense system used in the write circuit according to the present invention is not limited to the voltage generation circuit 25 shown in FIG. 1, and may be composed of other circuits.

  FIG. 6 is a circuit diagram of another voltage generation circuit 25b of the current differential sense system. The voltage generation circuit 25b functions as a holding unit that reads and holds the resistance state of the resistance change element 2, and one end (upper end) of the voltage corresponding to the resistance state held by the holding unit. And a function as an application unit for applying to the. However, in this modification, the holding unit and the application unit are not clearly separated, and the holding unit and the application unit are configured by the same transistor.

  That is, the voltage generation circuit 25 b includes the reference resistor 221 having a resistance value between the resistance value in the high resistance state and the resistance value in the low resistance state of the resistance change element 2. The magnitude relationship with the resistance value of the change element 2 is sensed by a current differential (difference between the current Iref and the current Idata), and the sensed magnitude relation is held as the resistance state of the resistance change element 2 and the held state is maintained. In response, either the first voltage or the second voltage lower than the first voltage is applied to one end (upper terminal) of the resistance change element 2. For this purpose, the voltage generation circuit 25b includes, in addition to the reference resistor 121, transistors (NMOS transistors 203 to 208, 211, and 212, and PMOS transistors 201, 202, 209, and 210) that constitute an SRAM.

  In the voltage generation circuit 25b, NMOS transistors 223 and 224 are connected in series with the variable resistance element 2 and the reference resistor 221, respectively, and a so-called 1T1R memory cell is provided. Further, from a control circuit (not shown), a control signal OPE is sent to the gates of four transistors (PMOS transistors 209 and 210, NMOS transistors 211 and 212), and a control signal SE is sent to the gate of the NMOS transistor 207. A control signal RE is sent to the gate of the transistor 208, and a control signal WL is sent to the NMOS transistors 223 and 224. The voltages at the two output terminals (the drains of the PMOS transistors 201 and 202) are denoted as Vout and Vout_ref, respectively, and the lower terminals of the resistance change element 2 and the reference resistor 221 (more precisely, the NMOS transistors 223 and The lower terminal of H.224 is called SL. The control signal OPE is used for switching whether the NMOS transistors 203 and 204 are caused to function as a part of the SRAM (that is, a latch circuit) or to function as a write (driver) to the resistance change element 2 and the reference resistor 221. It is a control signal.

  FIG. 7 is a timing chart showing the operation of the voltage generation circuit 25b. Here, writing to set the resistance change element 2 to the low resistance state (“set” in the figure), writing to set the resistance change element 2 to the high resistance state (“reset” in the figure), and the resistance change element 2 The operation timing is shown for three cases of reading (“read” in the figure).

  First, in the first step (“precharge” in the figure), the control signals SE, RE, and OPE become High while the control signal WL is High and a constant potential is applied to the terminal SL. Therefore, the voltage generation circuit 25b functions as an SRAM, and currents Idata and Iref depending on the magnitudes of the resistance values flow through the resistance change element 2 and the reference resistance 221 (that is, are precharged).

  Next, in the second step (“amplification” in the figure), writing to the low resistance state (“set”), writing to the high resistance state (“reset”), and reading (“read”) are performed. Depending on which one is performed, a predetermined voltage is applied to various control signals and the terminal SL as shown in the figure. In any step, amplification by positive feedback is performed in this step, and the magnitude relationship between the resistance value Rm of the resistance change element 2 and the resistance value Rref of the reference resistance 121 is applied to the upper terminal of the resistance change element 2. Depending on the voltage (here, the voltage Vdd when Rm> Rref, the GND potential when Rm <Rref).

  When writing is performed (“write” in the figure), the control signal OPE becomes Low, and as a result, the voltage Vdd is applied to the gates of the NMOS transistors 203 and 204, and the NMOS transistors 203 and 204 are , And functions as a driver that performs writing (that is, current amplification) to the resistance change element 2 and the reference resistor 221.

  As described above, according to the voltage generation circuit 25b in the present modification, when the variable resistance element 2 is in the high resistance state, the high voltage is applied to the upper terminal of the variable resistance element 2, and the variable resistance element 2 When 2 is in a low resistance state, a Low voltage is applied. Therefore, when the resistance change element 2 is set (set) in the low resistance state, the voltage (here, the resistance change element 2 is applied only when the resistance change element 2 is in the high resistance state (reset state)). As a result, the resistance change element 2 transitions from the high resistance state to the low resistance state. On the other hand, when the resistance change element 2 is set (reset) to the high resistance state, a voltage (here, the resistance change element 2 is applied to both ends of the resistance change element 2 only when the resistance change element 2 is in the low resistance state (set state). High voltage is applied to the lower terminal with reference to the upper terminal, and as a result, the resistance change element 2 transitions from the low resistance state to the high resistance state. Therefore, multiple writing to the variable resistance element 2 is automatically (autonomous) avoided.

  Note that the third step in FIG. 7 (“reset” in the figure) shows the initial state (state where neither writing nor reading) of the voltage generating circuit 25b is performed.

(Application 1)
Next, an application example 1 of the write circuit according to the present invention will be described.

  FIG. 8 is a circuit diagram of a write circuit according to Application Example 1 in which multiple writing is automatically (autonomous) avoided using two voltage generation circuits. This write circuit includes a first write circuit (write circuit 1) having an output terminal connected to the upper terminal of the resistance change element 2, and a second write circuit (output circuit connected to the lower terminal of the resistance change element 2). A writing circuit 1a).

  The first write circuit (write circuit 1) applies a first voltage (High voltage) to the upper terminal of the resistance change element 2 when the resistance change element 2 is in a high resistance state, while the resistance change element 2 is low. In the resistance state, a second voltage (Low voltage) lower than the first voltage is applied to the upper terminal of the resistance change element 2.

  The second write circuit (write circuit 1a) applies a second voltage (Low voltage) to the lower terminal of the resistance change element 2 when the resistance change element 2 is in a high resistance state, while the resistance change element 2 is When in the low resistance state, a first voltage (High voltage) is applied to the lower terminal of the resistance change element 2.

  In the variable resistance element 2, the first voltage (High voltage) is applied to the upper terminal of the variable resistance element 2, and the second voltage (Low voltage) is applied to the lower terminal of the variable resistance element 2. In addition, the resistance value is lowered, the second voltage (Low voltage) is applied to the upper terminal of the resistance change element 2, and the first voltage (High voltage) is applied to the lower terminal of the resistance change element 2. In this case, the point that the resistance value is increased is the same as the above embodiment.

  Hereinafter, the two write circuits 1 and 1a will be described in more detail.

  The voltage generation circuit 25 in the write circuit 1 on the right side is the same as that shown in FIG. The output voltage Vout1 from the voltage generation circuit 25 is applied to one end (upper terminal) of the variable resistance element 2 via the switch 45.

  On the other hand, the voltage generator circuit 325 on the left side is basically a current differential sense type latch circuit similar to the voltage generator circuit 25 on the right side, but outputs the output voltage Vout1a with the logic opposite to that of the voltage generator circuit 25. In order to do so, the internal circuit is connected. That is, the voltage generation circuit 325 includes a holding unit 310 including NMOS transistors 311, 313 to 315 and 317 to 320, PMOS transistors 312 and 316, and a reference resistor 321 having the same resistance value Rref as the reference resistor 21. And an application unit 330 including PMOS transistors 331 and 332. Here, the connection destination of the source of the PMOS transistor 331 and the connection destination of the source of the PMOS transistor 332 constituting the application unit 330 are opposite to the connection destination in the right voltage generation circuit 25. The output voltage Vout1a from the voltage generation circuit 325 is applied to the other end (lower terminal) of the resistance change element 2 via the switch 45a.

  The switch 45 sets the upper terminal of the resistance change element 2 of the voltage generation circuit 25 when the resistance change element 2 is set (set) in a low resistance state under the control of a control circuit (not shown). When connecting to the output terminal (Vout) and setting (resetting) the variable resistance element 2 to the high resistance state, the upper terminal of the variable resistance element 2 is connected to GND. Similarly, the switch 45a connects the lower terminal of the resistance change element 2 to GND when the resistance change element 2 is set (set) in a low resistance state under the control of a control circuit (not shown). On the other hand, when the resistance change element 2 is set to a high resistance state (reset), the lower terminal of the resistance change element 2 is connected to the output terminal (Vout) of the voltage generation circuit 325.

  According to the writing circuit according to this application example configured as described above, the following operation is performed.

(1) When the resistance change element 2 is set (set) to the low resistance state The lower terminal of the resistance change element 2 is fixed to the low potential (GND) by the switch 45a.

  On the other hand, a high voltage is applied to the upper terminal of the resistance change element 2 when the resistance change element 2 is in a high resistance state by the voltage generation circuit 25 on the right side, and the resistance change element 2 is in a low resistance state. In some cases, a Low voltage is applied.

  As a result, only when the variable resistance element 2 is in a high resistance state (reset state), a voltage (here, a high voltage at the upper terminal with respect to the lower terminal) is applied to both ends of the variable resistance element 2. As a result, the resistance change element 2 transitions (sets) from the high resistance state to the low resistance state. That is, when the variable resistance element 2 is already in a low resistance state, no voltage is applied to both ends of the variable resistance element 2, and multiple writing is avoided.

(2) When the resistance change element 2 is set (reset) to the high resistance state The upper terminal of the resistance change element 2 is fixed to the low potential (GND) by the switch 45.

  On the other hand, a low voltage is applied to the lower terminal of the resistance change element 2 when the resistance change element 2 is in a high resistance state by the voltage generation circuit 325 on the left side, and the resistance change element 2 is brought into a low resistance state. In some cases, a high voltage is applied.

  As a result, only when the resistance change element 2 is in a low resistance state (set state), a voltage (here, a high voltage at the lower terminal with respect to the upper terminal) is applied to both ends of the resistance change element 2. As a result, the resistance change element 2 transitions from the low resistance state to the high resistance state (reset). That is, when the variable resistance element 2 is already in a high resistance state, no voltage is applied to both ends of the variable resistance element 2, and multiple writing is avoided.

(Application example 2)
Next, application example 2 of the write circuit according to the present invention will be described.

  This application example 2 is a method for driving a write circuit according to the present invention, and is a method for adjusting the resistance value of a nonvolatile memory element (here, a resistance change element) with a verify operation.

  Generally, the resistance value of the variable resistance element varies as shown in the characteristic diagram of FIG. 9A. FIG. 9A shows the resistance value of the resistance change element when the resistance change element is alternately switched between the high resistance state and the low resistance state by alternately applying positive and negative voltage pulses to the resistance change element. Is plotted. The horizontal axis is the time corresponding to the number of times that positive and negative voltage pulses are applied, and the vertical axis is the resistance value of the resistance change element 2. As can be seen from this figure, the resistance value of the variable resistance element does not always take the same value in each of the high resistance state and the low resistance state, and varies randomly. In particular, the resistance value in the high resistance state varies greatly.

  Therefore, in this application example, as a method of writing the variable resistance element, writing with a verify operation is performed as shown in the flowchart of FIG. 9B. That is, after writing to the variable resistance element (S11), the resistance value of the variable resistance element is read (S11), and it is determined whether the read resistance value is within a specified range (S13). If it is not within the specified range (Fail in S13), writing is performed again (S11 to S13). Such a process is repeated until the resistance value falls within the specified range (pass in S13). Here, within the specified range, for example, when writing (setting) a resistance change element in a low resistance state, a resistance value Rh in a high resistance state and a resistance value Rl in a low resistance state of a typical resistance change element. On the other hand, when the resistance change element is written (reset) in the high resistance state, the resistance of the typical resistance change element in the high resistance state is smaller than the intermediate value (Rh + Rl) / 2. A range of resistance values greater than the intermediate value (Rh + Rl) / 2 between the value Rh and the resistance value Rl in the low resistance state.

  Here, in this application example, instead of repeating the same write step in the case of “Fail” in the verify (S13), as shown in FIG. 9C, the resistance change element is transferred to the variable resistance element with a write time longer than the previous write time. Write. For example, in the first writing, writing is performed such that the time in the writing phase (the operation shown in FIG. 2C) is the initial value (t seconds), and “Fail” is performed in the subsequent verification (S13). When writing is performed by setting the time in the writing phase to twice the previous time (2 t seconds) and “Fail” in the subsequent verification (S13), the time in the writing phase is further doubled to the previous time. The writing is repeated with the writing time doubled immediately before the “Pass” in the verify (S13), such as writing at time (4 tsec).

  By such a writing method, the resistance value of the variable resistance element is surely adjusted to a value within the specified range. In the resistance change element, the probability that the resistance state transitions increases with the time of the applied voltage pulse. However, if a voltage pulse for a long time is always applied unnecessarily, the characteristics of the resistance change element are deteriorated. Therefore, writing is performed reliably and without applying extra stress to the resistance change element by the writing method in which the writing time is gradually increased while accompanying the verify operation.

(Application example 3)
Next, a multi-value write circuit will be described as an application example 3 of the write circuit according to the present invention.

  FIG. 10 is a block diagram of a multi-value write circuit in application example 3 of the present invention. The multi-value writing circuit can set (write) the resistance change element 2 to a resistance value between the first resistance value R1 and the second resistance value R2 larger than the first resistance value R1. A first write circuit 1a (325) connected to one end (left terminal) of the variable resistance element 2 and a second write circuit 1 (connected to the other end (right terminal) of the variable resistance element 2; 25).

  The first write circuit 1a (325) has the same circuit configuration as the voltage generation circuit 325 shown in FIG. 8 (however, the resistance value Rref of the reference resistor 321 = the first resistance value R1), and the resistance from the output terminal OUT1 This is a circuit for applying a voltage to one end (left terminal) of the change element 2. Specifically, the first write circuit 1a (325) has a first voltage applied to one end (left terminal) of the resistance change element 2 when the resistance change element 2 has a resistance value smaller than the first resistance value R1. (High voltage) is applied, and when the variable resistance element 2 has a resistance value larger than the first resistance value, a second voltage lower than the first voltage (High voltage) is applied to one end (left terminal) of the variable resistance element 2. A voltage (Low voltage) is applied.

  On the other hand, the second write circuit 1 (25) has the same circuit configuration as that of the voltage generation circuit 25 shown in FIGS. 8 and 1 (where the resistance value Rref of the reference resistor 21 is the second resistance value R2), In this circuit, a voltage is applied from the output terminal OUT2 to the other end (right terminal) of the variable resistance element 2. Specifically, the second write circuit 1 (25) is connected to the second end (right terminal) of the resistance change element 2 when the resistance change element 2 has a resistance value smaller than the second resistance value R2. When a voltage (Low voltage) is applied and the resistance change element 2 has a resistance value larger than the second resistance value R2, the first voltage (High voltage) is applied to the other end (right terminal) of the resistance change element 2. To do.

  The resistance change element 2 has the same characteristics as those shown in FIG. That is, the resistance change element 2 has a resistance when a first voltage (High voltage) is applied to one end (left terminal) and a second voltage (Low voltage) is applied to the other end (right terminal). When the value is increased (reset), the second voltage (Low voltage) is applied to one end (left terminal), and the first voltage (High voltage) is applied to the other end (right terminal), It has a property that the resistance value is lowered (set).

  According to such a multi-value writing circuit, as shown in the lower right of FIG. 10, the relationship between the resistance value Rm of the resistance change element 2, the resistance value R1 of the reference resistor 321 and the resistance value R2 of the reference resistor 21 is obtained. The following write operation is performed.

(1) When Rm <R1 and R2, the voltage at the output terminal OUT1 becomes a high voltage (voltage Vdd), the voltage at the output terminal OUT2 becomes a low voltage (GND), and the resistance change element 2 has a voltage (high voltage). RESET voltage) is applied.

(2) When R1, R2 <Rm, the voltage at the output terminal OUT1 becomes the Low voltage (GND), the voltage at the output terminal OUT2 becomes the High voltage (voltage Vdd), and the resistance change element 2 has a low resistance voltage ( SET voltage) is applied.

(3) When R1 <Rm <R2 The voltage at the output terminal OUT1 is the Low voltage (GND), the voltage at the output terminal OUT2 is the Low voltage (GND), and no voltage is applied across the resistance change element 2.

  From the above, according to this multi-value write circuit, the resistance value Rm of the resistance change element 2 is adjusted to a resistance value between the first resistance value R1 and the second resistance value R2 by such a write operation. Is done. That is, by setting the first resistance value R1 to the lower limit value of the target resistance value to be set and setting the second resistance value R2 to the upper limit value of the target resistance value, the resistance value of the resistance change element 2 is The resistance value between the lower limit value and the upper limit value is set.

  Therefore, as shown in the lower left of FIG. 10, for example, the combination of the first resistance value R1 and the second resistance value R2 is switched according to the value of the 2-bit control signal (a combination of four different resistance values). A multi-value write circuit that sets the resistance value of the resistance change element 2 to a desired one of the four values by adding a circuit to the multi-value write circuit. Realized. As a result, a resistance state of 2 bits or more can be stored in one memory cell, the number of bits per memory cell can be increased, and the effective memory capacity can be increased.

(Application 4)
Next, as a fourth application example of the writing circuit according to the present invention, another multilevel writing circuit will be described.

  FIG. 11 is a diagram for explaining the multi-value write circuit 50 in the application example 4 of the present invention. FIG. 11A is a block diagram of the multi-value write circuit 50 in this application example. The multi-value write circuit 50 is configured to connect a resistance change type nonvolatile memory element (here, the resistance change element 2) between a first resistance value REFA and a second resistance value REFB larger than the first resistance value REFA. A multi-value write circuit for setting a resistance value, mainly a first write circuit (sense amplifier ampR) connected to one end (lower terminal RRAMB) of the resistance change element 2, and a second write circuit (sense amplifier) ampL) and at least two switch elements (here, NMOS transistors 52 and 53) connected to the other end (upper terminal RRAMU) of the resistance change element 2 (here, connected via the NMOS transistor 54a); Is provided.

  When the variable resistance element 2 has a resistance value smaller than the first resistance value REFA, the first write circuit (sense amplifier ampR) supplies the first voltage (High voltage) to one end (lower terminal) of the variable resistance element 2. RRAMB) and output from the output terminal ampRout. On the other hand, when the variable resistance element 2 has a resistance value larger than the first resistance value REFA, the second voltage (Low voltage) lower than the first voltage (High voltage). Voltage) is applied to one end (lower terminal RRAMB) of the variable resistance element 2 and output from the output terminal ampRout.

  The second write circuit (sense amplifier ampL) outputs the second voltage (Low voltage) from the output terminal ampLout when the variable resistance element 2 has a resistance value smaller than the second resistance value REFB, while the resistance change element When the element 2 has a resistance value larger than the second resistance value REFB, the first voltage (High voltage) is output from the output terminal ampLout.

  One of the at least two switch elements (NMOS transistors 52 and 53 in this case) (NMOS transistor 53) connected to the other end (upper terminal RRAMU) of the variable resistance element 2 has its gate at the first write circuit (sense). Is connected to the output terminal ampRout of the amplifier ampR), and when the first voltage (High voltage) is output from the output terminal ampRout, the second voltage (voltage Vreset (Low voltage)) connected to the drain is turned on. The voltage is applied to the other end (upper terminal RRAMU) of the variable resistance element 2 via the NMOS transistor 54a.

  Further, the gate of the other one (NMOS transistor 52) of at least two switch elements (NMOS transistors 52 and 53 in this case) connected to the other end (upper terminal RRAMU) of the resistance change element 2 is the second. Connected to the output terminal ampLout of the write circuit (sense amplifier ampL) and turned on when the first voltage (High voltage) is output from the output terminal ampLout, the first voltage connected to the drain (voltage Vset (High) Voltage)) is applied to the other end (upper terminal RRAMU) of the variable resistance element 2 via the NMOS transistor 54a.

  The variable resistance element 2 has the same characteristics as those shown in FIG. That is, in the resistance change element 2, the first voltage (High voltage) is applied to one end (lower terminal RRAMB) of the resistance change element 2, and the second voltage is applied to the other end (upper terminal RRAMU) of the resistance change element 2. When a voltage (Low voltage) is applied, the resistance value is increased (reset), the second voltage (Low voltage) is applied to one end (lower terminal RRAMB) of the resistance change element 2, and the resistance When the first voltage (High voltage) is applied to the other end (upper terminal RRAMU) of the change element 2, the resistance value is reduced (set).

  Hereinafter, the configuration of the multi-value write circuit 50 will be described in more detail.

  The multi-value write circuit 50 mainly includes three NMOS transistors 51 to 53, a resistance change element 2 (resistance value Rm) to be written, two sense amplifiers ampR and ampL, and two reference resistors ( Resistance values REFA and REFB).

  The three NMOS transistors 51 to 53 are switch elements for reading, low resistance (set), and high resistance (reset), respectively, and the drains are the read voltage Vread and the set voltage, respectively. Vset is connected to the reset voltage Vreset, and the gates have a control signal re, a control signal sete (signal from the output terminal ampLout of the sense amplifier ampL), and a control signal resete (output terminal of the sense amplifier ampR, respectively). signal from ampRout). The source of the NMOS transistor 51 is connected to the upper terminal RRAMU of the resistance change element 2, and the sources of the NMOS transistors 52 and 53 are connected to the upper terminal RRAMU of the resistance change element 2 via the NMOS transistor 54a.

  The sense amplifiers ampR and ampL are circuits corresponding to the above-described voltage generation circuit (however, a circuit excluding the reference resistance), and each terminal connected to the resistance change element 2 and the reference resistance is used as an input terminal, and an output node It is shown by a triangular symbol whose output terminal is a node (vout_left or vout_right in FIG. 1). The sense amplifier ampR includes a buffer amplifier (in this case, a two-stage inverter) and an NMOS between its output terminal ampRout and one of its input terminals (input terminal connected to the resistance change element 2). The transistor 54b is connected.

  As in the write circuit 1a (325) of FIG. 10, the sense amplifier ampR has a high voltage at the output terminal ampRout when the relationship between the resistance value Rm of the resistance change element 2 and the resistance value REFA of the reference resistance is REFA> Rm. On the other hand, when REFA <Rm, the Low voltage is output to the output terminal ampRout. The sense amplifier ampL outputs a low voltage to the output terminal ampRout when REFB> Rm as in the write circuit 1 (25) of FIG. 10, while the sense amplifier ampL outputs to the output terminal ampRout when REFB <Rm. High voltage is output.

  FIG. 11B is a diagram for explaining an operation target of the multi-level write circuit 50. There are three cases between the resistance value Rm of the variable resistance element 2 and the resistance values REFA and REFB of the two reference resistors (REFA <REFB). Case 1 is Rm <REFA, REFB. In this case, it is necessary to increase the resistance by performing a reset operation on the resistance change element 2. In addition, since Case 2 is REFA <Rm <REFB and is a target final state, nothing is done in this case. In case 3, REFA and REFB <Rm. In this case, it is necessary to reduce the resistance by performing the set operation on the resistance change element 2.

  FIG. 11C is a truth table showing the operation result of such a multi-value write circuit 50, and the voltage (H (High voltage) / L) corresponding to the three cases 1 to 3 in FIG. (Low voltage)). As shown in FIG. 11C, the multilevel write circuit 50 operates as follows.

(1) Case 1 (Rm <REFA, REFB)
The output terminal ampLout of the sense amplifier ampL has a low voltage, and the output terminal ampRout of the sense amplifier ampR has a high voltage. As a result, only the NMOS transistor 53 whose gate is supplied with the signal (reset) from the output terminal ampRout is turned on, and the voltage Vreset (here, the upper terminal RRAMU of the resistance change element 2 is turned on. , Low voltage). On the other hand, the High voltage from the output terminal ampRout of the sense amplifier ampR is applied to the lower terminal RRAMB of the resistance change element 2 via the buffer amplifier and the NMOS transistor 54b.

  As a result, a high voltage is applied to the lower terminal RRAMB of the resistance change element 2 and a low voltage is applied to the upper terminal RRAMU, so that the resistance change element 2 as shown in case 1 of FIG. 2 is reset to increase the resistance of the variable resistance element 2.

(2) Case 2 (REFA <Rm <REFB)
The output terminal ampLout of the sense amplifier ampL has a low voltage, and the output terminal ampRout of the sense amplifier ampR has a low voltage. As a result, all of the NMOS transistors 51 to 53 are turned off, and no voltage is applied to the upper terminal RRAMU of the resistance change element 2 (the float state is set). On the other hand, the Low voltage from the output terminal ampRout of the sense amplifier ampR is applied to the lower terminal RRAMB of the resistance change element 2 via the buffer amplifier and the NMOS transistor 54b.

  As a result, a low voltage is applied to the lower terminal RRAMB of the resistance change element 2 and the upper terminal RRAMU is in a floating state. Therefore, as shown in Case 2 of FIG. Thus, no voltage is applied, and the resistance value of the resistance change element 2 does not change.

(3) Case 3 (REFA, REFB <Rm)
The output terminal ampLout of the sense amplifier ampL has a high voltage, and the output terminal ampRout of the sense amplifier ampR has a low voltage. As a result, only the NMOS transistor 52 whose gate is supplied with the signal (set) from the output terminal ampLout is turned on, and the voltage Vset (here, the upper terminal RRAMU of the resistance change element 2 is turned on. , High voltage). On the other hand, the Low voltage from the output terminal ampRout of the sense amplifier ampR is applied to the lower terminal RRAMB of the resistance change element 2 via the buffer amplifier and the NMOS transistor 54b.

  As a result, a low voltage is applied to the lower terminal RRAMB of the variable resistance element 2 and a high voltage is applied to the upper terminal RRAMU, so that the variable resistance element 2 as shown in case 3 of FIG. 2 is set, and the resistance change element 2 is lowered in resistance.

  From the above, according to the multi-value write circuit 50, the resistance value Rm of the resistance change element 2 is adjusted to a resistance value between the first resistance value REFA and the second resistance value REFB by the write operation. . That is, by setting the first resistance value REFA to the lower limit value of the target resistance value to be set and setting the second resistance value REFB to the upper limit value of the target resistance value, the resistance value of the resistance change element 2 is The resistance value between the lower limit value and the upper limit value is set. Thereby, like Application Example 3, by adding a circuit that changes the combination of two reference resistance values, the resistance value of one nonvolatile memory element can be set to any one of three or more multi-values. Thus, a memory cell capable of storing multiple values with 1 bit is realized, and the memory capacity per memory cell is increased.

  As described above, the write circuit and the multi-value write circuit of the variable resistance nonvolatile memory element according to the present invention have been described based on the embodiments, the modified examples, and the application examples. However, the present invention is not limited to these embodiments and modified examples. It is not limited to examples and applications. Without departing from the gist of the present invention, these embodiments, modifications, and applications may be obtained by applying various modifications that a person skilled in the art can think of, and these embodiments, modifications, and applications. Circuits and procedures realized by arbitrarily combining circuit elements and procedures in the above are also included in the present invention.

  For example, the write circuit (or voltage generation circuit) in the application examples 1 to 4 may be configured by any of the write circuits (or voltage generation circuits) of the embodiment, the first modification, and the second modification. . This is because these application examples 1 to 4 can be realized without depending on the sense method (current differential sense method, voltage differential sense method) in the write circuit (or voltage generation circuit).

  The present invention relates to a write circuit and a multi-value write circuit of a resistance change type nonvolatile memory element, in particular, writing of a nonvolatile memory for an electronic device that requires a large capacity, high speed operation and low power consumption nonvolatile memory. It can be used as a circuit.

1, 1a Write circuit 2 Resistance change element 10, 10a, 310 Holding part 11, 13-15, 17-20, 51-53, 54a, 54b, 105-107, 109-112, 123, 124, 203-208, 211, 212, 223, 224, 311, 313 to 315, 317 to 320 NMOS transistor 12, 16, 31, 32, 101 to 104, 108, 201, 202, 209, 210, 312, 316, 331, 332 PMOS transistor 21, 121, 221, 321 Reference resistor 25, 25 a, 25 b, 325 Voltage generation circuit 30, 30 a, 30 b, 30 c, 330 Application unit 33, 34, 35, 36 Buffer amplifier 40 Switch unit 41 Power supply 41
42, 45, 45a switch 50 multi-value write circuit ampR, ampL sense amplifier

Claims (8)

A write circuit for a variable resistance nonvolatile memory element,
Only when the nonvolatile memory element is in a high resistance state, a voltage for causing the nonvolatile memory element to transition to a low resistance state is applied to the nonvolatile memory element, and the nonvolatile memory element is in a low resistance state A writing circuit that applies a voltage to the nonvolatile memory element only when the nonvolatile memory element is shifted to a high resistance state. A voltage is connected to one end of the nonvolatile memory element, and a voltage for transitioning the resistance state is applied to the one end depending on whether the nonvolatile memory element is in a high resistance state or a low resistance state. The write circuit according to claim 1, further comprising a voltage generation circuit that generates the voltage. The voltage generation circuit includes:
A holding unit that reads and holds the resistance state of the nonvolatile memory element;
The writing circuit according to claim 2, further comprising: an application unit that applies a voltage corresponding to the resistance state held by the holding unit to one end of the nonvolatile memory element. The holding unit has a reference resistance having a resistance value between a resistance value in a high resistance state and a resistance value in a low resistance state of the nonvolatile memory element, and the resistance value of the reference resistance and the nonvolatile memory element Holding the magnitude relationship with the resistance value of the resistance state,
The application unit applies one of a first voltage and a second voltage lower than the first voltage to one end of the nonvolatile memory element according to a magnitude relationship held in the holding unit. Writing circuit. Further, when the nonvolatile memory element is connected to the other end of the nonvolatile memory element and is set to one of a high resistance state and a low resistance state, a third voltage and a fourth voltage lower than the third voltage are set. When one of them is applied to the other end and the nonvolatile memory element is set to the other of the high resistance state and the low resistance state, the other of the third voltage and the fourth voltage is set to the other end. The write circuit according to claim 3, further comprising a switch unit to be applied. A write circuit for a variable resistance nonvolatile memory element,
Connected to one end of the non-volatile memory element, applies a first voltage to the one end when the non-volatile memory element is in a high resistance state, and applies to the one end when the non-volatile memory element is in a low resistance state. A first write circuit for applying a second voltage lower than the first voltage;
When the nonvolatile memory element is connected to the other end of the nonvolatile memory element, the second voltage is applied to the other end when the nonvolatile memory element is in a high resistance state, and the nonvolatile memory element is in a low resistance state A second write circuit for applying the first voltage to the other end;
The nonvolatile memory element has a low resistance when a first voltage is applied to the one end and a second voltage is applied to the other end, and a second voltage is applied to the one end. And a writing circuit having a property that a resistance value is increased when a first voltage is applied to the other end. A multi-value writing circuit that sets a resistance variable nonvolatile memory element to a resistance value between a first resistance value and a second resistance value larger than the first resistance value,
When the nonvolatile memory element is connected to one end of the nonvolatile memory element and has a resistance value smaller than the first resistance value, a first voltage is applied to the one end, and the nonvolatile memory element is A first writing circuit that applies a second voltage lower than the first voltage to the one end when the resistance value is larger than one resistance value;
When the nonvolatile memory element is connected to the other end of the nonvolatile memory element and has a resistance value smaller than the second resistance value, the second voltage is applied to the other end, and the nonvolatile memory element A second write circuit that applies the first voltage to the other end when the first resistance value is larger than the second resistance value,
The nonvolatile memory element has a high resistance when a first voltage is applied to the one end and a second voltage is applied to the other end, and a second voltage is applied to the one end. A multi-value writing circuit having a property that the resistance value is lowered when a first voltage is applied to the other end. A multi-value writing circuit that sets a resistance variable nonvolatile memory element to a resistance value between a first resistance value and a second resistance value larger than the first resistance value,
When the nonvolatile memory element is connected to one end of the nonvolatile memory element and has a resistance value smaller than the first resistance value, a first voltage is applied to the one end and output from an output terminal, and the nonvolatile memory element A first write circuit that applies a second voltage lower than the first voltage to the one end and outputs from the output terminal when the volatile memory element has a resistance value greater than the first resistance value;
When the nonvolatile memory element has a resistance value smaller than the second resistance value, the second voltage is output from an output terminal, and the nonvolatile memory element has a resistance value larger than the second resistance value. A second write circuit for outputting the first voltage from an output terminal;
And at least two switch elements connected to the other end of the nonvolatile memory element,
One of the two switch elements applies the second voltage to the other end when the first voltage is output from the output terminal of the first write circuit.
The other one of the two switch elements applies the first voltage to the other end when the first voltage is output from the output terminal of the second write circuit,
The nonvolatile memory element has a high resistance when a first voltage is applied to the one end and a second voltage is applied to the other end, and a second voltage is applied to the one end. A multi-value writing circuit having a property that the resistance value is lowered when a first voltage is applied to the other end.

Images