JP2013041632A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a constant voltage generation circuit which enables a quick operation start of an internal circuit that is connected to an output terminal.SOLUTION: A semiconductor device comprises: a booster circuit 20 that performs a pumping operation at a plurality of internal nodes when a clock signal VOSC is input, that sequentially transfers charge, which is supplied to an input terminal, to an output terminal via the plurality of nodes, and that generates an output voltage from the output terminal; a voltage detection circuit 30 that outputs a detection signal VUPT at an inactive level when the output voltage reaches a predetermined voltage; and a clock signal control circuit 40 that outputs a clock signal to the booster circuit when the detection signal is at an active level, and stops the output of the clock signal to the booster circuit when the detection signal is at an inactive level. The clock signal control circuit outputs the clock signal to the booster circuit according to the level of an incoming control signal RESETT even when the detection signal is at an inactive level.

Description

  The present invention relates to a semiconductor device equipped with a constant voltage generation circuit.

In recent years, a constant voltage (for example, a voltage boosted with respect to a power supply voltage supplied from the outside) necessary for the operation of an internal circuit is generated in a semiconductor device according to a power supply voltage supplied from the outside. A constant voltage generation circuit that outputs a voltage to an internal circuit is mounted.
For example, Patent Document 1 discloses a constant voltage generation circuit including a booster circuit, a voltage detection circuit, and a clock signal control circuit.

The booster circuit has an input terminal to which a power supply voltage is supplied and an output terminal for outputting the boosted voltage. A charge pump including a diode-connected MOS transistor and a capacitor is provided between the input terminal and the output terminal. A plurality are connected in series. The plurality of charge pumps are connected in series so that the diode polarities of the MOS transistors are in the same direction. One end of the capacitor is connected to each connection point (internal node of the charge pump) of the charge pumps connected in series, and the other end of the capacitor is connected to the clock signal control circuit.
Clock signals having opposite phases from each other are input from the clock signal control circuit to the other ends of the capacitors of the adjacent charge pumps. In response to this clock signal, each charge pump transfers the charge flowing in from the input terminal to the internal node of the next-stage charge pump (performs a pumping operation for boosting the voltage), and boosts the voltage level of the output terminal.

Further, in order to set the output voltage of the booster circuit to a constant voltage, the constant voltage generation circuit is provided with a voltage detection circuit and a clock signal control circuit. The voltage detection circuit compares the output voltage of the booster circuit with a preset reference voltage and outputs the comparison result as a detection signal. The clock signal control circuit has an oscillator inside, and outputs a clock signal for controlling the pumping operation of the charge pump based on the detection signal and the output of the oscillator.
Specifically, when the output voltage of the booster circuit is higher than the reference voltage, the voltage detection circuit determines that the output voltage of the booster circuit has reached a constant voltage and deactivates the detection signal to stop the oscillator. To level. When the inactive level detection signal is input, the clock signal control circuit stops the oscillator. Thereby, each of the charge pumps stops the pumping operation, and the booster circuit stops increasing the output voltage. On the other hand, when the output voltage of the booster circuit is lower than the reference voltage, the voltage detection circuit determines that the output voltage of the booster circuit has not reached the constant voltage, and keeps the detection signal at the active level for operating the oscillator. To maintain. In this case, the clock signal control circuit does not stop the oscillator because the active level detection signal is continuously input. As a result, each of the charge pumps receives a clock signal, and thus continues the pumping operation to raise the output voltage.

Japanese Patent Laid-Open No. 7-154692

  In the constant voltage generation circuit disclosed in Patent Document 1, a clock signal control circuit starts an oscillator based on an external clock (a clock supplied from an external terminal of a semiconductor device). If the semiconductor device equipped with this constant voltage generation circuit does not allow input of an external clock at power-on, even if the detection voltage detected by the voltage detection circuit is lower than the reference voltage, in the clock signal control circuit, The oscillator is not started. Therefore, the booster circuit cannot perform the pumping operation at the internal node of the charge pump, and cannot supply a preset voltage (constant voltage) to the internal circuit. If the internal circuit operates in a state in which no constant voltage is supplied, it cannot operate at a normal operating voltage, so that there is a high possibility of malfunction. Therefore, in order not to cause the internal circuit to malfunction, it is conceivable to take measures to stop the operation of the internal circuit until the constant voltage generation circuit generates a constant voltage. However, if the operation is stopped until the normal operating voltage is supplied to the internal circuit, the operation start time of the internal circuit is delayed.

  Further, a semiconductor device equipped with a constant voltage generation circuit shifts to an operation mode (power down mode) in which the internal circuit is in a standby state (standby state in which no operation is performed) in a normal operation in which input of an external clock signal is permitted. There is a case. In this power-down mode, the internal circuit does not consume current, so a constant voltage is already supplied unlike when the power is turned on. For this reason, the clock signal control circuit stops the oscillator. However, since each of the charge pumps in the booster circuit is constituted by a capacitor, as the period of the power down mode becomes longer, the potential of the internal state of the charge pump is a potential in a state where a constant voltage is output due to the leakage current of the capacitor ( It drops from the precharge potential. Therefore, when the semiconductor device exits (exits) from the power down mode and the internal circuit shifts from the standby state to the operating state, the detection voltage detected by the voltage detection circuit becomes lower than the reference voltage, and the clock signal control circuit Start the oscillator. As a result, each of the charge pumps in the booster circuit starts the pumping operation. However, since the pumping operation is performed from the state where the potential of the internal node is lower than the precharge potential, the output voltage of the booster circuit decreases. (Dropped), the internal circuit cannot operate at a constant voltage. In other words, the possibility that the internal circuit malfunctions is increased as when the power is turned on. In order to prevent the internal circuit from malfunctioning, it is possible to take measures to stop the operation of the internal circuit until the constant voltage generation circuit generates a constant voltage, just as when the power is turned on. Like the time, the operation start time of the internal circuit is delayed.

  In the present invention, when a clock signal is input, a pumping operation is performed at a plurality of internal nodes, charges supplied to the input terminal are sequentially transferred to the output terminal via the plurality of nodes, and the output terminal When the booster circuit for generating an output voltage and the first control signal are at an active level and the output voltage does not reach a preset voltage, a detection signal at an inactive level is output and the first control signal is output. When the signal is at the active level and the output voltage reaches a preset voltage, the voltage detection circuit that outputs the detection signal at the active level; and when the detection signal is at the inactive level, the clock signal is A clock signal control circuit that outputs to the booster circuit and stops the output of the clock signal to the booster circuit when the detection signal is at an active level. Even if the detection signal is at an active level, the clock signal is set according to the level of the second control signal input before the first control signal is input to the voltage detection circuit. The semiconductor device is characterized in that it outputs to a booster circuit.

According to the present invention, the clock signal control circuit outputs the clock signal to the booster circuit according to the level of the second control signal input before the first control signal becomes the active level. . Therefore, when the power is turned on, the second control signal is input to the clock signal control circuit, so that even if the detection voltage detected by the voltage detection circuit is lower than the reference voltage, the clock signal control circuit A signal can be supplied to each charge pump. The booster circuit can generate a constant voltage by performing a pumping operation at the internal node, and supply the constant voltage to the internal circuit. Therefore, since the internal circuit does not malfunction, it is not necessary to stop the operation of the internal circuit, and the operation start time of the internal circuit can be advanced as compared with the conventional case.
Further, even when the power down mode period of the semiconductor device becomes long, the potential of the internal node of the booster circuit is pre-established by exiting from the power down mode and applying the second control signal before the first control signal. By returning to the charge potential, the output voltage drop (drop) of the booster circuit can be suppressed. Therefore, since the internal circuit does not malfunction, it is not necessary to stop the operation of the internal circuit, and the operation start time of the internal circuit can be advanced as compared with the conventional case.

2 is a block diagram showing a configuration of a constant voltage generation circuit 10. FIG. 4 is a timing waveform diagram of the constant voltage generation circuit 10. FIG. It is a block diagram which shows the structure of the constant voltage generation circuit 10a. It is a timing waveform diagram of the constant voltage generation circuit 10a. It is a block diagram which shows the structure of the constant voltage generation circuit 10b. It is a timing waveform diagram of the constant voltage generation circuit 10b. 1 is a block diagram of a semiconductor device 100 including a constant voltage generation circuit 10. FIG.

First, a problem of a semiconductor device including a constant voltage generation circuit 10b having a booster circuit, a voltage detection circuit, and a clock signal control circuit will be described with reference to FIG.
FIG. 5 is a diagram showing a circuit configuration of the constant voltage generation circuit 10b. The constant voltage generation circuit 10b includes a booster circuit 20 (charge pump circuit), a voltage detection circuit 30, and a clock signal control circuit 40b.
The booster circuit 20 includes an NMOS transistor 21, a charge pump 20a, a charge pump 20b, and a charge pump 20c.
In the NMOS transistor 21 (N-type channel MOS transistor), the drain is connected to the power supply VCC, the source is connected to the connection point N23, and the gate is connected to the power supply VCC.

  The charge pump 20a includes a switching element 23a and a capacitor C23. The switching element 23a is composed of an NMOS transistor 23, and its drain and gate are connected to the connection point N23, and its source is connected to the connection point N24. Capacitor C23 has one end connected to connection point N23 and the other end connected to clock signal generation circuit 50 to receive clock signal φ1. The switching element 23a is a rectifying element that prevents charge from flowing backward and lowering the potential of the connection point N24 when the potential of the output-side connection point N24 (node) becomes higher than the input-side connection point N23 due to the pumping operation. It is.

  The charge pump 20b includes a switching element 24a and a capacitor C24. The switching element 24 a is configured by an NMOS transistor 24, the drain and gate are connected to the connection point N 24, and the source is connected to the connection point N 25 of the booster circuit 20. Capacitor C24 has one end connected to connection point N24 and the other end connected to clock signal generation circuit 50 to receive clock signal φ2. Similarly to the switching element 23a, the switching element 24a prevents the charge from flowing backward and the potential at the connection point N25 from dropping when the potential at the output side connection point N25 becomes higher than the input side connection point N24 by the pumping operation. This is a rectifying element.

The charge pump 20c includes a switching element 25a and a capacitor C25. The switching element 25a is constituted by an NMOS transistor 25. The drain and gate are connected to the connection point N25, and the source is connected to the connection point N26 of the booster circuit 20. The capacitor C25 has one end connected to the connection point N25 and the other end connected to the clock signal generation circuit 50 to receive the clock signal φ1. Similarly to the switching element 23a and the switching element 24a, when the potential at the output-side connection point N26 becomes higher than the input-side connection point N25 by the pumping operation, the switching element 25a reverses the charge and the potential at the connection point N26. This is a rectifying element that prevents the lowering of the current.
The booster circuit 20 outputs an output voltage VPP (constant voltage) to the connection point N26 of the charge pump 20c.
In the constant voltage generation circuit 10b, the booster circuit 20 is constituted by three stages of charge pumps (charge pump 20a to charge pump 20c), but of course is not limited to three stages, and is not limited to the three stages. Depending on the voltage level, it may be constituted by four or more stages of charge pumps. Further, although the MOS transistor is used as the switching element constituting the booster circuit 20, a diode may be used.

The voltage detection circuit 30 detects whether or not the final stage charge pump 20c has generated the output voltage VPP (constant voltage). The voltage detection circuit 30 includes a voltage dividing circuit including a resistor R1 and a resistor R2, a comparator 31, an inverter circuit 32, and an AND circuit 33.
The voltage dividing circuit divides the output voltage VPP from the GND by the resistors R1 and R2, and outputs the divided voltage Vd obtained by the voltage division to the normal input terminal (+) of the comparator 31.
The comparator 31 compares a preset reference voltage VREF and the divided voltage Vd, and outputs a comparison result signal. The comparison result signal output from the comparator 31 is H level when the divided voltage Vd> reference voltage VREF, and is L level when the divided voltage Vd <reference voltage VREF. Here, since the divided voltage Vd is expressed by the output voltage VPP × R2 / (R1 + R2), the comparator 31 reaches the voltage (reference voltage VREF × (R1 + R2) / R2) where the output voltage VPP is set in advance. If not, an L level comparison result signal is output, and if reached, an H level comparison result signal is output.
The inverter circuit 32 inverts the level of the comparison result signal output from the comparator 31 and outputs the inverted signal to one input terminal of the AND circuit 33.
The AND circuit 33 calculates the logical product of the charge pump enable signal CPE input to the other input terminal and the logical inversion signal of the comparison result signal output from the inverter circuit 32 input to the one input terminal, and the operation result The detection signal VUPT is output to the clock signal control circuit 40b.

Here, the charge pump enable signal CPE is a signal corresponding to the clock in the prior art document. That is, the charge pump enable signal CPE is not a signal input from the outside of the semiconductor device, but is a signal that is reset to an inactive level (L level) when the power is turned on. The charge pump enable signal CPE is a signal for activating the charge pump, becomes an activation level (H level) later than a control signal RESETT described later, and is input to the AND circuit 33.
With the above configuration, the voltage detection circuit 30 changes the detection signal VUPT from the inactive level (L level) to the active level only when the charge pump enable signal CPE is at the H level and the divided voltage Vd <the reference voltage VREF. Change to (H level). When the detection signal VUPT is at the H level, the oscillator 51 oscillates and the boosting circuit 20 performs the pumping operation.

The clock signal control circuit 40b includes an inverter circuit 60a, an oscillator 51, an AND circuit 57, and a NAND circuit 58. The oscillator 51, the AND circuit 57, and the NAND circuit 58 constitute a clock signal generation circuit 50.
The inverter circuit 60 a inverts the level of the detection signal VUPT, and outputs an oscillator drive signal OSCACTB, which is a signal obtained by inverting the detection signal VUPT, to one input of the NOR circuit 52 of the oscillator 51. The oscillator 51 starts oscillating when the oscillator drive signal OSCACTB becomes an active level (L level).
The oscillator 51 includes a NOR circuit 52 and inverter circuits 53 to 56.
The AND circuit 57 receives the output signal of the NOR circuit 52 and the output signal of the inverter circuit 55, and generates a clock signal φ1 that is at H level during the period when both output signals are at H level.
The NAND circuit 58 is a negative logic two-input NAND circuit, to which the output signal of the NOR circuit 52 and the output signal of the inverter circuit 55 are input, and both output signals are at the H level during the L level. Clock signal φ2 is generated.

  With the above configuration, when the detection signal VUPT input to the clock signal control circuit 40b is at the H level, the inverter circuit 60a sets the oscillator drive signal OSCACTB to the L level. As a result, the oscillator 51 starts oscillating. During the oscillation period in which the oscillator drive signal OSCACTB is at the L level, the clock signal φ1 and the clock signal φ2 whose H level periods do not overlap each other periodically. Generated and output to the booster circuit 20.

The operation at power-on of the constant voltage generation circuit 10b having the above configuration will be described with reference to the timing waveform diagram shown in FIG.
For the sake of simplicity, the amplitude of the clock signal φ1 and the clock signal φ2 is VCC, and it is assumed that the amplitude is between 0 V (L level) and VCC (H level). The capacitances of the capacitors C23, C24, and C25 are as follows. It is assumed that the capacitance is sufficiently larger than the parasitic capacitance at each connection point to which one end of each capacitor is connected. The threshold voltages of the NMOS transistors 23 to 25 constituting the switching elements 23a to 25a are assumed to be VTH, respectively.

  When power is turned on at time t0, the potentials at the connection point N23, connection point N24, connection point N25, and connection point N26 (output voltage VPP) are (VCC-VTH), (VCC-2VTH), and (VCC-3VTH), respectively. , (VCC-4VTH). This is because the power supply voltage VCC appears at the connection point N23 by dropping by the threshold voltage VTH of the NMOS transistor 21. Further, this is because the potential (VCC−VTH) at the connection point N23 appears to drop at the connection point N24 by the threshold voltage VTH of the NMOS transistor 23. Further, the potential at the connection point N24 (VCC-2VTH) appears to drop at the connection point N25 by the threshold voltage VTH of the NMOS transistor 24. Further, this is because the potential (VCC-3VTH) at the connection point N25 appears to drop at the connection point N26 by the threshold voltage VTH of the NMOS transistor 25.

At time t1, when the charge pump enable signal CPE input to the AND circuit 33 of the voltage detection circuit 30 becomes H level, the divided voltage Vd <reference voltage VREF is still satisfied at this time, so the comparator 31 compares the L level. Output the result signal. As a result, the voltage detection circuit 30 outputs an H level detection signal VUPT from the AND circuit 33.
In the clock signal control circuit 40b, the inverter circuit 60a changes the oscillator drive signal OSCACTB from H level (inactive level) to L level (active level). The oscillator 51 starts oscillating, and the AND circuit 57 and the NAND circuit 58 receive the clock signal φ1 and the clock signal φ2 whose H level periods do not overlap each other, the other ends of the capacitor C23 and the capacitor C25 of the booster circuit 20, Output to the other end of the capacitor C24.

At time t2, when the clock signal φ1 output from the clock signal control circuit 40b becomes H level, the capacitor C23 raises the potential at the connection point N23 to which one end thereof is connected from (VCC-VTH) to (2VCC-VTH). Let Capacitor C25 raises the potential at node N25 to which one end thereof is connected from (VCC-3VTH) to (2VCC-3VTH).
As a result, the NMOS transistor 23 and the NMOS transistor 25 become conductive, and charge is transferred to the connection point N24 and the connection point N26, respectively. The potentials of the connection point N24 and the connection point N26 rise, and are respectively VTH lower than the potential at the connection point N23 from (VCC-2VTH) (2VCC-2VTH), and VTH lower than the potential at the connection point N25 from (VCC-4VTH) (2VCC). −4VTH).
When the clock signal φ1 becomes L level, the capacitor C23 lowers the potential of the connection point N23 to which one end thereof is connected from (2VCC−VTH) to (VCC−VTH). Capacitor C25 lowers the potential at node N25 to which one end thereof is connected from (2VCC-3VTH) to (VCC-3VTH). At this time, since the NMOS transistor 23 and the NMOS transistor 25 block the flow of charges in the reverse direction, the potentials at the connection point N24 and the connection point N26 are the increased potentials (2VCC-2VTH) and (2VCC-4VTH), respectively. ).

At time t3, when the clock signal φ2 output from the clock signal control circuit 40b becomes H level, the capacitor C24 raises the potential of the connection point N24 to which one end is connected from (2VCC-2VTH) to (3VCC-2VTH). . As a result, the NMOS transistor 24 becomes conductive, and charges are transferred to the connection point N25. The potential at the connection point N25 rises from (VCC-3VTH) to (3VCC-3VTH).
At this time, since the NMOS transistor 23 prevents the flow of charges in the reverse direction, the potential at the node N23 remains VTH lower than the power supply voltage VCC (VCC-VTH).
When the clock signal φ2 becomes L level, the capacitor C24 lowers the potential of the connection point N24 to which one end thereof is connected from (3VCC-2VTH) to (2VCC-2VTH). However, since the NMOS transistor 25 blocks the flow of charges in the reverse direction, the potential at the connection point N25 remains (3VCC-3VTH).

At time t4, when the clock signal φ1 output from the clock signal control circuit 40b becomes H level again, the capacitor C23 changes the potential at the connection point N23 to which one end thereof is connected from (VCC-VTH) to (2VCC-VTH). Raise. Capacitor C25 raises the potential at node N25 to which one end is connected from (3VCC-3VTH) to (4VCC-3VTH).
As a result, the NMOS transistor 23 and the NMOS transistor 25 become conductive, and charge is transferred to the connection point N24 and the connection point N26, respectively. Even if the potential at the connection point N24 is lower than (2VCC-2VTH), the charge is replenished from the connection point N23 and becomes the same as the potential at time t2 (2VCC-2VTH). Further, the potential of the connection point N26 increases and becomes VTH lower than the potential of the connection point N25 (4VCC-4VTH).
When the clock signal φ1 becomes L level, the capacitor C23 lowers the potential of the connection point N23 to which one end thereof is connected from (2VCC−VTH) to (VCC−VTH). Capacitor C25 lowers the potential at node N25 to which one end thereof is connected from (4VCC-3VTH) to (3VCC-3VTH). At this time, since the NMOS transistor 23 and the NMOS transistor 25 block the flow of charges in the reverse direction, the potentials at the connection point N24 and the connection point N26 remain (2VCC-2VTH) and (4VCC-4VTH), respectively. .

  In this way, in the constant voltage generation circuit 10b, the number of charge pumps of the booster circuit 20 is three, so that the clock signal is three times (clock signal φ1 is two times and clock signal φ2 is one time three times in total). , The potential at the connection point N26 becomes (4VCC-4VT), and the booster circuit 20 generates a constant voltage equal to this potential. In general, in the case of an n-stage charge pump, (n + 1) × (VCC−VTH) can be obtained as a constant voltage by inputting clock signals n times (total of clock signal φ1 and clock signal φ2). . Note that the constant voltage is reached n times when the necessary charge transfer between the connection points is performed ideally once as described above, and the internal connection is actually performed by more pumping operations. The potential at the point reaches the precharge potential, and the output voltage VPP reaches a predetermined constant voltage (in this case, 4VCC-4VTH).

Further, by setting the reference voltage VREF so as to be equal to the divided voltage Vd obtained by dividing the constant voltage by the resistors R1 and R2, the comparator 31 outputs an H level comparison result signal. To do.
Thereby, at time t5, the voltage detection circuit 30 changes the detection signal VUPT to L level (inactive level). In the clock signal control circuit 40b, the inverter circuit 60a changes the oscillator drive signal OSCACTB to an inactive level (H level). As a result, the oscillator 51 stops oscillating and maintains both the clock signal φ1 and the clock signal φ2 at the L level (inactive level) (time t5 to t6).
The potential at the connection point N23 is maintained at (VDD−VTH) by the NMOS transistor 21, and the potentials at the connection point N24 and the connection point N25 are respectively set to (2VCC-2VTH) by the capacitor C24 and (3VCC-3VTH) by the capacitor C25. Maintained. These potentials are potentials corresponding to the precharge potential of the internal node in the booster circuit 20.

At time t6, when an internal circuit (not shown in FIG. 5) to which the booster circuit 20 supplies the output voltage VPP (constant voltage) starts operating, the current supplied by the booster circuit 20 is consumed, so the output voltage VPP decreases. To do.
Since the divided voltage Vd <the reference voltage VREF, the comparator 31 outputs an L level comparison result signal. At this time, since the charge pump enable signal CPE input to the AND circuit 33 of the voltage detection circuit 30 is at the H level, the voltage detection circuit 30 outputs an H level detection signal VUPT from the AND circuit 33.
In the clock signal control circuit 40b, the inverter circuit 60a changes the oscillator drive signal OSCACTB from H level (inactive level) to L level (active level). The oscillator 51 starts oscillating, and the AND circuit 57 and the NAND circuit 58 receive the clock signal φ1 and the clock signal φ2 whose H level periods do not overlap each other, the other ends of the capacitor C23 and the capacitor C25 of the booster circuit 20, Output to the other end of the capacitor C24.
The output times of these clock signals are time t8, time t9, and time t10, and these times correspond to the time t2, time t3, and time t4 described above, respectively.

  However, when the potentials of the connection point N23, the connection point N24, and the connection point N25 are maintained at the precharge potential as shown in FIG. 6, the operation was performed from time t8 to time t10 and from time t2 to time t4. As much charge transfer is not necessary. For example, the charge corresponding to (VCC × capacitance value of the capacitor C24) is transferred from the connection point N23 to the connection point N24, and the precharge at the connection point N24 is charged to the potential. Further, at time t3, a charge corresponding to (2VCC × capacitance value of capacitor C25) is transferred from connection point N24 to connection point N25, and charging to the precharge potential at connection point N25 is performed. In addition, at time t2, time t3, and time t4, the charge transfer corresponding to (VCC × capacity of the internal circuit with respect to the wiring to which the output voltage VPP is supplied) is transferred from the connection point N25 to the connection point N26. The connection point N26 and the internal circuit are charged.

On the other hand, from time t8 to time t10, the booster circuit 20 only needs to supply the internal circuit with a charge corresponding to the current consumed by the internal circuit. For this reason, the movement of charges is less than the movement of charges accompanying the precharge of each internal connection point described above, and a constant voltage can be supplied with a small pumping operation.
However, in the configuration of the constant voltage generation circuit 10b, it is necessary to move charges from time t2 to time t4 when the power is turned on. Therefore, the number of pumping operations until reaching the constant voltage increases, and the start time at the constant voltage of the internal circuit to which the operating current is supplied from the booster circuit is delayed. Referring to FIG. 6, after the charge pump enable signal CPE is input at time t1, a time for performing a pumping operation in which the connection point of each charge pump reaches the precharge potential is required, and after this time has elapsed. Otherwise, the internal circuit cannot operate at a regular voltage (at a constant voltage).

Further, even if the precharge potential is secured, if the time from time t5 to time t6 is long, the capacitor maintains the precharge potential at the connection point. As a result, the precharge potential drops. For example, when all charges are leaked, the potentials at the connection point N24 and the connection point N25 are (VCC-2VTH) and (VCC-3VTH), respectively, from time t0 to time t1 (up to this potential, the NMOS transistor 21).
As a case where the time from the time t5 to the time t6 is long, a case where the semiconductor device on which the constant voltage generation circuit 10b is mounted has a power down mode as an operation mode is considered. In the case of a semiconductor device that does not have such a power down mode, charge is supplied from the booster circuit 20 to the internal circuit at the time when the internal circuit to which the booster circuit 20 supplies the output voltage VPP operates (time t6 in FIG. 6). When the internal circuit operates, the output voltage VPP drops (drops) in FIG. On the other hand, in the case of a semiconductor device having a power-down mode, this voltage drop becomes larger when the potentials at the connection point N24 and the connection point N25 that are internal nodes of the booster circuit 20 drop (indicated by the broken line in FIG. 5). ). When the voltage drop is large, the number of pumping operations in the booster circuit 20 also increases, and it takes time to recover the output voltage VPP to a constant voltage level. Therefore, the internal circuit connected to the booster circuit 20 is in a normal state until each node of the booster circuit 20 is restored to the precharge potential and the pumping capacity of the booster circuit 20 is restored to the maximum capacity, similar to when the power is turned on. It cannot operate with voltage (at constant voltage).

  As described above, in the related constant voltage generation circuit 10b, the internal nodes (connection point N24, connection point N25) in the booster circuit 20 are set to potentials (precharge potentials) after the power is turned on or after the long-term power down mode. It may not be. For this reason, even if the detection signal VPUT becomes an active level (H level) and the oscillator 51 operates, the pumping capacity of the booster circuit 20 (each internal node performs a pumping operation, and a constant voltage is applied to the internal circuit within a predetermined time. To prevent the output voltage VPP from dropping), and the operation start time of the internal circuit to which the constant voltage is supplied is delayed.

[First Embodiment]
Therefore, in the constant voltage generation circuit of this embodiment, in order to prevent this voltage drop, the internal node (each connection point) of the booster circuit 20 is charged to the precharge potential before the operation of the internal circuit, and the pumping capacity does not decrease. It is characterized by doing so.
FIG. 1 is a block diagram showing the configuration of the constant voltage generation circuit 10.
The constant voltage generation circuit 10 includes a booster circuit 20, a voltage detection circuit 30, and a clock signal control circuit 40. 1, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.
The clock signal VOSC shown in FIG. 1 is a clock signal corresponding to the clock signal φ1 and the clock signal φ2 described with reference to FIG.

As shown in FIG. 1, the clock signal control circuit 40 includes a clock signal generation circuit 50, a drive signal generation circuit 60, and a delay signal generation circuit 70.
In the clock signal control circuit 40, the same components as those of the clock signal control circuit 40b shown in FIG.
The drive signal generation circuit 60 includes an inverter circuit 62 and a NOR circuit 61.
The inverter circuit 62 has an input connected to the connection point A that is the output of the delay signal generation circuit 70, and an output connected to one input of the NOR circuit 61. The inverter circuit 62 inverts the potential appearing at the connection point A and outputs it to the NOR circuit 61.
The NOR circuit 61 is a circuit corresponding to the inverter circuit 60a shown in FIG. 5, and performs an OR operation between the detection signal VPPT that is an output signal of the voltage detection circuit 30 and the inverter circuit 62, and an oscillator drive signal that is an operation result. OSCACTB is output to the clock signal generation circuit 50.
With this configuration, the drive signal generation circuit 60 allows the output of the delay signal generation circuit (connection point A) to be at the active level from the inactive level (H level) even when the detection signal VPUT is at the inactive level L level. When (L level) is reached, the oscillator drive signal OSCACTB is changed to the active level (L level).

The delay signal generation circuit 70 includes a NOR circuit 71, a NOR circuit 72, an inverter circuit 73, and a delay circuit 74.
The NOR circuit 71 performs a negative OR operation between the control signal RESETT input to one input terminal and the output signal of the NOR circuit 72 input to the other input terminal, and outputs the operation result to the inverter circuit 62. Output.
The NOR circuit 72 performs a negative OR operation on the output signal of the NOR circuit 71 input to one input terminal and the output signal of the inverter circuit 73 input to the other input terminal, and the operation result is output to the NOR circuit 71. Output to the other input terminal.
The inverter circuit 73 inverts the level of the output signal of the delay circuit 74 and outputs it to the other input terminal of the NOR circuit 72.
The delay circuit 74 has an input connected to the connection point A, delays the output signal of the NOR circuit 71, and outputs the delayed output signal to the inverter circuit 73.

Here, the control signal RESETT is a signal that is input to the delay signal generation circuit 70 when the semiconductor device in which the constant voltage generation circuit 10 is mounted is turned on. In the present embodiment, it does not matter whether the control signal RESETT is input from the outside or generated inside the semiconductor device. For example, the semiconductor device may have a dedicated terminal, and the control signal RESETT may be directly input through the dedicated terminal. Alternatively, the semiconductor device includes a command decoder, and the command decoder is a command for transferring a command supplied from the outside of the semiconductor device to the internal node (each connection point in FIG. 5) of the booster circuit 20 to the precharge potential. Interpreting this, the control signal RESETT may be output to the delay signal generation circuit 70.
When the semiconductor device has a power down mode as an operation mode, the control signal RESETT is changed from the power down mode in which the internal circuit connected to the booster circuit 20 is changed from the operating state to the standby state. It is also possible to adopt a configuration in which the signal is input to the delay signal generation circuit 70 when shifting to the power down exit mode in which the operation becomes possible.

  Further, the delay time set in the delay circuit 74 is such that the clock signal generation circuit 50 periodically generates the clock signal and the internal nodes (the connection points in FIG. 5) that perform the pumping operation in the booster circuit 20 are precharged. It is only necessary to set a time until the potential is reached (the potential at time t5 in FIG. 6).

FIG. 2 is a timing waveform diagram of the constant voltage generation circuit 10.
When the control signal RESETT is input to the delay signal generation circuit 70 at time t1, the delay signal generation circuit 70 sets the potential at the connection point A to L level (activation level) during the period from time t1 to time t2. As a result, the drive signal generation circuit 60 sets the oscillator drive signal OSCACTB to the active level (L level) for the same period as the period from the time t1 to the time t2.
The clock signal generation circuit 50 outputs the clock signal VOSC (clock signal φ1 and clock signal φ2) to the booster circuit 20 while the oscillator drive signal OSCACTB is at the active level.
In the booster circuit 20, the potential of the internal node (each connection point) is charged to the precharge potential.
Thereby, before the internal circuit to which the output voltage VPP is supplied from the booster circuit 20 operates after the power is turned on, the booster circuit 20 can supply a constant voltage to the internal circuit with a high pumping capability. That is, the charge pump enable signal CPE is input to activate the voltage detection circuit 30 and then the internal circuit operates to drop the output voltage VPP. At this time, the pumping capacity of the booster circuit 20 should be set to the maximum capacity. Voltage drop can be suppressed. For this reason, the internal circuit is close to a regular constant voltage, does not malfunction in a state where voltage drop is suppressed, and starts operating earlier than before (that is, without waiting for recovery of pump capacity as in the past). Can do.

[Second Embodiment]
FIG. 3 is a block diagram showing a configuration of the constant voltage generation circuit 10a.
The constant voltage generation circuit 10a includes a booster circuit 20, a voltage detection circuit 30, and a clock signal control circuit 40a. 3, the same components as those in FIGS. 1 and 5 are denoted by the same reference numerals, and the description thereof is omitted.
As shown in FIG. 3, the clock signal control circuit 40a includes a clock signal generation circuit 50, a drive signal generation circuit 60, a delay signal generation circuit 70, and an overshoot suppression circuit 80 (the output voltage by the pumping operation when the control signal RESETT is input). And a circuit for suppressing the VPP from excessively rising above a constant voltage.
In the clock signal control circuit 40a, the same components as those in the clock signal control circuit 40 shown in FIG.

The overshoot suppression circuit 80 includes a delay circuit 82, a PMOS transistor 81 (P-type channel MOS transistor), a comparator 83, and an NMOS transistor 84.
The delay circuit 82 (second delay circuit) generates a signal obtained by delaying the output signal (delay signal) of the NOR circuit 71 from the connection point B and outputs the signal to the gate of the PMOS transistor 81.
The PMOS transistor 81 has a source connected to the power supply line that supplies the power supply voltage VCC, a gate connected to the connection point B (output of the delay circuit 82), and a drain connected to the power supply terminal of the comparator 83.
The comparator 83 operates with the power supply terminal connected to the drain of the PMOS transistor 81, and compares the output voltage VPP of the booster circuit 20 with the reference voltage VR (which may be the same potential as the reference voltage VREF shown in FIG. 5). Then, the comparison result signal is output to the gate of the NMOS transistor 84. The comparator 83 outputs an H level comparison result signal when the output voltage VPP is equal to or higher than the reference voltage VR, and outputs an L level comparison result signal when the output voltage VPP is less than the reference voltage VR.
The NMOS transistor 84 (charge / discharge circuit) has a drain connected to the output of the booster circuit 20, a gate connected to the output of the comparator 83, and a source grounded. The NMOS transistor 84 is turned on (conducted) when the comparison result signal of the comparator 83 is at the H level to lower the level of the output voltage VPP, and is turned off (non-conducted) when the comparison result signal is at the L level.
Note that the delay time set in the delay circuit 82 is obtained, for example, by measuring the degree of increase of the output voltage VPP with respect to the reference voltage VR in advance by measurement or computer simulation, and using the NMOS transistor to increase the output voltage VPP to the reference voltage VR. It is enough time to descend.

FIG. 4 is a timing waveform diagram of the constant voltage generation circuit 10a.
At time t1, the booster circuit 20 starts the pumping operation and supplies the output voltage VPP. When the output voltage VPP becomes the reference voltage VREF, the voltage detection circuit 30 sets the detection signal VPUT to the active level (H level). . As a result, the clock signal generation circuit 50 stops supplying the clock signal VOSC to the booster circuit 20, but the output voltage VPP increases excessively until the supply of the clock signal is stopped. For this reason, the comparator 83 and the NMOS transistor 84 cause the output voltage VPP to decrease by an excessively increased voltage, that is, by an increase from the reference voltage VR, during the period from time t1 to time t3.

[Third Embodiment]
FIG. 7 shows a case where the above-described constant voltage generation circuit 10 (or constant voltage generation circuit 10a) is applied to a semiconductor device 100, for example, an SDRAM (Synchronous Dynamic Random Access Memory) that operates in synchronization with a clock. The schematic structure of is shown. Each circuit block shown in FIG. 7 is formed on a single semiconductor chip such as single crystal silicon. Each circuit block includes a plurality of transistors such as a PMOS transistor and an NMOS transistor, for example. In addition, a circle indicates a pad as an external terminal provided in the semiconductor chip. In addition to the illustrated external terminal, a power supply voltage terminal to which a power supply voltage supplied from the outside is applied is provided. Provided.
The semiconductor device 100 includes a constant voltage generation circuit 10, a memory cell array 11, an address buffer 12, a row decoder 13, a column decoder 14, a sense amplifier 15, a command decoder 16, a mode register 17, a data input / output circuit 19, and a clock generation circuit 16a. It is comprised including.
The memory cell array 11 includes, for example, four banks (BANK 0 to 4) in which a plurality of memory cells are arranged in a matrix of rows and columns. Each bank has a memory cell area 111 which is a storage area.
For example, the memory cell 111m in the memory cell region 111 is disposed at the intersection of the word line 11a and the bit line 11b.

The clock generation circuit 16a has an internal circuit (command decoder 16, control circuit 18, data input / output circuit 19) based on a clock signal CLK having a constant frequency supplied from the outside and a clock enable signal CKE indicating that the clock is valid. An internal clock signal for operating is generated.
As control signals supplied from the outside to the semiconductor device 100, there are the following control signals in addition to the clock signal CLK and the clock enable signal CKE. A chip select signal / CS (hereinafter referred to as an external memory control signal CS) for selecting a chip, a row address strobe signal / RAS (hereinafter referred to as an external memory control signal RAS), a column address strobe signal / CAS (hereinafter referred to as an external memory control signal CS). An external memory control signal CAS), a write enable signal / WE (hereinafter referred to as an external memory control signal WE) for instructing a data write operation. Among these signals, those having “/” in front of the sign mean that the low level (L level) is the effective level.

The command decoder 16 decodes the CS signal, the RAS signal, the CAS signal, the WE signal, and a part of the address signal, which are these external memory control signals, and decodes a command supplied from the outside. The commands supplied to the semiconductor device 100 of this embodiment include an ACT command for instructing activation of an internal circuit of the semiconductor device, a READ command for instructing reading, a WRT command for instructing writing, and an operation mode to the mode register 17 There are an MRS command for instructing the setting of the above, a PRE command for instructing deactivation of the internal circuit activated by the ACT command, and the like. In the present embodiment, a command supplied to the command decoder 16 includes a reset command. In the present embodiment, as a command supplied to the command decoder 16, there is a power-down entry command for instructing the transition of the internal circuit to the standby state. When this power down entry command is supplied, the internal circuit of the semiconductor device 100 shifts to a standby state. In order to shift the internal circuit from the standby state to the operable state, it is necessary to supply a power down exit command to the command decoder 16 to instruct to return the internal circuit to the operable state.
The command decoder 16 takes in and decodes the CS signal, RAS signal, CAS signal, and WE signal, which are external memory control signals, as command signals in synchronization with the internal clock signal. Further, the command decoder 16 responds to an internal command signal corresponding to the decoded command, for example, an active command (ACT command), a write command (WRT command), a read command (READ command), and a precharge command (PRE command). Correspondingly, an internal active signal, an internal write signal, an internal read signal, an internal precharge signal, etc. are output to the control circuit 18. In this embodiment, the command decoder 16 outputs an internal reset signal to the control circuit 18 when a reset command is supplied. In this embodiment, the command decoder 16 outputs an internal precharge signal to the control circuit 18 when a power-down entry command is supplied, and outputs an internal reset signal when the power-down exit command is supplied. Output to.
The mode register 17 holds an address signal by a combination input of the activation levels of the CS signal, RAS signal, CAS signal, and WE signal that are external memory control signals, and initializes each operation mode such as entry to the test operation mode. Do.

The control circuit 18 responds to each operation mode set in the mode register and the internal command signal from the command decoder 16 in accordance with each circuit (address buffer 12, row decoder 13, column decoder 14, sense amplifier) in the semiconductor device 100. 15. Generate a control signal for controlling the data input / output circuit 19). For example, the control circuit 18 generates an active / inactive control signal indicating activation for controlling the activation of the row decoder 13, the column decoder 14, the sense amplifier 15, and the data input / output circuit 19. The timing is controlled in response to the change in output and output. In addition, the control circuit 18 outputs a write control signal for controlling the activation of the data input / output circuit 19 with timing control corresponding to the change in the logic level of the internal write signal. Further, the control circuit 18 controls the timing of the charge pump enable signal CPE corresponding to the change in the logic level of the internal active signal, and outputs it to the voltage detection circuit 30 in the constant voltage generation circuit 10. In the present embodiment, the control circuit 18 controls the timing of the control signal RESETT corresponding to the change in the logic level of the internal reset signal, and outputs the control signal RESETT to the clock signal control circuit 40 in the constant voltage generation circuit 10. .
Thus, the control signal RESETT is input to the clock signal control circuit 40 when a reset command or a power down exit command is supplied to the semiconductor device 100.

The address buffer 12 is activated by an ACT command and takes in address data (hereinafter abbreviated as an address) indicating the position of a memory cell input from the outside in a multiplex manner. The multiplex method is a method in which a row address (row address) indicating the position of the memory cell is acquired by an ACT command, and a column address (column address) indicating the position of the memory cell is acquired in time series by a READ command or a WRT command. .
The row decoder 13 decodes the row address fetched by the address buffer 12 while being activated by the ACT command, and selects a corresponding word line (for example, the word line 11a) in the memory cell array 11. The plurality of memory cells connected to the selected word line are connected to the respective bit lines (the bit line 11b in the case of the memory cell 111m), and the data of each memory cell is read to the bit line. In this embodiment, the row decoder 13 is supplied with the output voltage VPP from the constant voltage generation circuit 10 as a power supply voltage, and boosts the potential of the selected word line. As a result, a level equal to the H level of the bit line can be written into the memory cell.

The sense amplifier 15 is activated by the ACT command, amplifies the voltage read to the bit line by the internal read signal or the internal write signal, and selects the amplified data when the semiconductor device is in a read operation. And output to the data input / output circuit 19 via the I / O line. The sense amplifier 15 writes data input from the data input / output circuit 19 via the column switch and the I / O line to the memory cell when the semiconductor device is in a write operation.
The column decoder 14 is activated by the WRT command (or READ command) following the ACT command, decodes the column address fetched by the address buffer 12, and corresponding column (bit line) in the memory cell region 111. Select.

  The data input / output circuit 19 outputs data read from the memory cell array 11 via the I / O line to the outside via the data input / output terminals DQ0 to DQ15 in the read operation of the semiconductor device. The data input / output circuit 19 latches data input from the outside via the data input / output terminals DQ0 to DQ15 in the write operation, and supplies the latched data to the sense amplifier 15 via the I / O line. The data input / output circuit 19 is configured to determine whether to mask (validate) 16-bit data DQ0 to DQ15, for example, based on a control signal DQM supplied from the outside.

The constant voltage generation circuit 10 is a circuit that is a characteristic part of the present invention. This will be described later, and here, an operation performed by the semiconductor device 100 when a command related to the present invention is supplied from the outside will be briefly described.
First, when the external memory control signals CS and RAS are at the L level and the external memory control signals CAS and WE are at the H level at the rising edge of the clock signal CLK from the outside, the ACT command is input to the command decoder 16. At this time, the internal active signal among the internal command signals of the command decoder 16 changes from the L level to the H level. In response to the change of the internal active signal to the H level, an active operation is performed inside the semiconductor device 100. That is, the row decoder 13 and the address buffer 12 are activated by receiving an activation / deactivation control signal indicating activation. Simultaneously with the input of the ACT command, the externally input address signal is latched in the address buffer 12. The activated row decoder 13 decodes the latched address signal, selects a word line of the memory cell array 11, and boosts the level of the selected word line. In response to the input of the ACT command, the sense amplifier 15 and the data input / output circuit 19 are also activated by the activation / deactivation control signal indicating activation. The control circuit 18 adjusts the timing of an active / inactive control signal indicating activation internally and outputs the signal to the sense amplifier 15. The sense amplifier 15 to which the timing adjusted signal is input amplifies the voltage of the bit line.

  Next, in the write operation, when the external memory control signals CS, CAS, and WE are at the L level and the external memory control signal RAS is at the H level when the clock signal CLK rises, the command decoder 16 receives the WRT command. Entered. At this time, the internal write signal changes from the L level to the H level in the internal command signal of the command decoder 16. A write operation is performed inside the semiconductor device 100 in response to the change of the internal write signal to the H level. That is, the address buffer 12 already activated by the ACT command latches an externally input address signal that is input together with the WRT command, and the column decoder 14 activated by the WRT command receives the latched address signal. Based on the above, the bit line of the memory cell array 11 is selected. The control circuit 18 controls the timing of the write control signal and outputs it to the data input / output circuit 19. The data input / output circuit 19 to which the write control signal is input drives the bit line of the selected memory cell array 11 together with the sense amplifier 15 via the I / O line and the column switch, Write to memory cell. In particular, when H level data is written in the memory cell, the word line is boosted by the constant voltage generation circuit 10 and the row decoder 13 so that the same level as the H level of the bit line can be written.

  In the read operation, the READ command is input to the command decoder 16 when the external memory control signals CS and CAS are at the L level and the external memory control signals RAS and WE are at the H level when the clock signal CLK rises. Is done. At this time, the internal read signal changes from the L level to the H level in the internal command signal of the command decoder 16. Corresponding to the change of the internal read signal to the H level, a read operation is performed inside the semiconductor device 100. That is, the address buffer 12 already activated by the ACT command latches the externally input address signal that is input together with the READ command, and the column decoder 14 activated by the READ command receives the latched address signal. Based on the above, the bit line of the memory cell array 11 is selected. The control circuit 18 controls the timing of the read control signal and outputs it. The data input / output circuit 19 to which the read control signal is input receives the voltage of the bit line of the memory cell array 11 amplified by the sense amplifier 15 via the column switch and the I / O line, and transfers the data of the memory cell to the outside. Read to.

  When shifting to the standby state following the read operation or the write operation, when the external memory control signals CS, RAS, and WE are at the L level and the external memory control signal CAS is at the H level when the clock signal CLK rises, A PRE command is input to the command decoder 16. At this time, the internal precharge signal changes from the L level to the H level in the internal command signal of the command decoder 16. A precharge operation is performed inside the semiconductor device 100 in response to the change of the internal precharge signal to the H level. That is, the row decoder 13 is deactivated by receiving an activation / deactivation control signal indicating deactivation, the word line of the memory cell array 11 is deselected, and the bit line of the memory cell array 11 is preset to a predetermined voltage. The semiconductor device 100 is charged and enters a standby state (IDLE). In response to the input of the PRE command, an activation / deactivation control signal indicating deactivation is also input to the column decoder 14, the sense amplifier 15, and the data input / output circuit 19 to deactivate them. Also, when the power down entry command is supplied to the command decoder 16 and the internal circuit shifts to the standby state (standby state), each internal circuit including the row decoder 13 is deactivated as described above.

  In order to shift to the test operation mode, the MRS command is input to the command decoder 16 when the external memory control signals CS, RAS, WE, and CAS are all at the L level when the clock signal CLK rises. The mode register 17 generates a code (MRS code) indicating that the semiconductor device 100 shifts to the test operation mode when the MRS command is input and the logic of the input address is a predetermined logic. This MRS code is latched in the mode register 17 and used for effective control of the test circuit.

In the present embodiment, the row decoder 13 is described as an example of an internal circuit to which the output voltage VPP of the constant voltage generation circuit 10 is supplied. However, the present invention is not limited to the row decoder 13 and other circuits using a boosted voltage. It may be.
When a reset command is supplied to the command decoder 16 when the semiconductor device 100 is powered on, the control circuit 18 outputs a control signal RESETT to the constant voltage generation circuit 10. As a result, a pumping operation is performed in the constant voltage generation circuit 10, and the output voltage VPP is supplied to the row decoder 13.
Thereafter, the input of the ACT command causes the control circuit 18 to output a charge pump enable signal CPE to the voltage detection circuit 30 in the constant voltage generation circuit 10.
The row decoder 13 drives the word line, but the output voltage VPP drops due to a load (memory cell) connected to the word line. The voltage detection circuit 30 determines that the divided voltage Vd obtained by dividing the output voltage VPP is lower than the reference voltage VR, changes the detection signal VPPT to the active level (H level), and Output.
The clock signal control circuit 40 changes the oscillator drive signal OSCACTB for oscillating the oscillator 51 in the clock signal generation circuit 50 to an active level (L level). The clock signal generation circuit outputs the clock signal VOSC to the booster circuit 20.

The booster circuit 20 performs a pumping operation at the internal node, and supplies a charge corresponding to the drop of the output voltage VPP to the row decoder 13.
At this time, each node in the booster circuit 20 is charged to the precharge potential by the control signal RESETT input to the clock signal control circuit 40 prior to the charge pump enable signal CPE. Thereby, the pumping capacity of the booster circuit 20 is ensured to the maximum capacity, and a large drop in the output voltage is suppressed. In other words, the row decoder 13 does not wait for the time required for the pumping operation for charging the internal node of the booster circuit 20 to the precharge potential from the ACT command input to the predetermined constant voltage from the ACT command input. Thus, the word line boosting operation can be executed.
In this embodiment, the reset command input is described as an example. However, the present invention is not limited to this configuration. For example, when the semiconductor device 100 has a dedicated terminal for inputting the control signal RESETT, this dedicated terminal is used. Alternatively, the clock signal control circuit 40 in the constant voltage generation circuit 10 may receive the control signal RESETT.
Alternatively, when the semiconductor device 100 includes a power-on reset circuit that generates a power-on reset signal of an active level when the power is turned on, a configuration for generating the control signal RESETT from the power-on reset signal, or the power-on reset signal itself May be a control signal RESETT.

Further, when the semiconductor device 100 shifts to the power down mode, when a power down entry command is supplied to the command decoder 16, the internal precharge signal is output to the control circuit 18. The internal circuit of the included semiconductor device 100 is shifted to the standby state. When a power down exit command is supplied to the command decoder 16 as a command to exit from this standby state, the control circuit 18 outputs a control signal RESETT to the constant voltage generation circuit 10. In the constant voltage generation circuit 10, each node in the booster circuit 20 performs a pumping operation to the precharge potential by the input of the control signal RESETT, and the pumping capacity of the booster circuit 20 is sufficiently secured.
Thereafter, the input of the ACT command causes the control circuit 18 to output a charge pump enable signal CPE to the voltage detection circuit 30 in the constant voltage generation circuit 10. The row decoder 13 drives the word line, but the output voltage VPP drops due to a load (memory cell) connected to the word line. The voltage detection circuit 30 determines that the divided voltage Vd obtained by dividing the output voltage VPP is lower than the reference voltage VR, changes the detection signal VPPT to the active level (H level), and Output.
The clock signal control circuit 40 changes the oscillator drive signal OSCACTB for oscillating the oscillator 51 in the clock signal generation circuit 50 to an active level (L level). The clock signal generation circuit outputs the clock signal VOSC to the booster circuit 20.

The booster circuit 20 performs a pumping operation at the internal node, and supplies a charge corresponding to the drop of the output voltage VPP to the row decoder 13.
At this time, each node in the booster circuit 20 is charged to the precharge potential by the control signal RESETT input to the clock signal control circuit 40 prior to the charge pump enable signal CPE. Thereby, the pumping capacity of the booster circuit 20 is ensured to the maximum capacity, and a large drop in the output voltage is suppressed. That is, the row decoder 13 does not wait for the lapse of time required for the pumping operation for charging the internal node of the booster circuit 20 to the precharge potential from the input of the ACT command, as in the case of power-on. The word line boosting operation can be executed at a predetermined constant voltage from the input.

  As described above, when the clock signal VOSC (clock signals φ1, φ2) is input, the semiconductor device of the present invention performs a pumping operation at a plurality of internal nodes (connection point N23 to connection point N25), and inputs to the input terminal. A booster circuit 20 is provided for sequentially transferring supplied charges to an output terminal via a plurality of nodes and generating an output voltage from the output terminal. In the semiconductor device of the present invention, the first control signal (charge pump enable signal CPE) is at the active level (H level), and the output voltage VPP is a preset voltage (reference voltage VREF × (R1 + R2) / R2) is not reached, an active level (H level) detection signal VPUT is output, the first control signal (CPE) is at the active level (H level), and the output voltage VPP is set to a preset voltage. The voltage detection circuit 30 is provided that outputs a detection signal VPUT at an inactive level (L level) when it has reached. The semiconductor device of the present invention outputs the clock signal VOSC to the booster circuit 20 when the detection signal VOPT is at the active level (H level), and outputs the clock signal VOSC when the detection signal VOPT is at the inactive level (L level). Is provided with a clock signal control circuit 40 (or 40a) for stopping output to the booster circuit 20. In this semiconductor device, the clock signal control circuit 40 (or 40a) is configured such that the first control signal (charge pump enable signal CPE) is supplied to the voltage detection circuit 30 even when the detection signal VPUT is at an inactive level (L level). The clock signal VOSC is output to the booster circuit 20 in accordance with the level of the second control signal (control signal RESETT) input prior to the input.

According to the present invention, the clock signal control circuit 40 receives the second control signal (control signal RESETT) that is input before the first control signal (charge pump enable signal CPE) becomes the active level (H level). The clock signal VOSC is output to the booster circuit 20 in accordance with the level of). For this reason, even when the detected voltage detected by the voltage detection circuit 30 is lower than the reference voltage VREF by inputting the second control signal to the clock signal control circuit when the power is turned on, the clock signal control circuit 40 Can supply the clock signal VOSC to each charge pump. The booster circuit 20 can generate a constant voltage by performing a pumping operation at the internal node, and supply the constant voltage to the internal circuit. Therefore, since the internal circuit does not malfunction, it is not necessary to stop the operation of the internal circuit, and the operation start time of the internal circuit (for example, the row decoder 13) can be advanced compared to the conventional case.
Further, even when the power down mode period of the semiconductor device 100 becomes long, the potential of the internal node of the booster circuit 20 is obtained by exiting from the power down mode and giving the second control signal before the first control signal. Can be returned to the precharge potential, and the drop (drop) of the output voltage VPP of the booster circuit 20 can be suppressed. Therefore, since the internal circuit does not malfunction, it is not necessary to stop the operation of the internal circuit, and the operation start time of the internal circuit can be advanced as compared with the conventional case.

The technical idea of the present application can be applied to a semiconductor device having a constant voltage generation circuit. Further, the connection method and circuit format of each block disclosed in the drawings, and other circuits for generating control signals are not limited to the circuit format disclosed in the embodiments.
Further, the technical idea of the semiconductor device of the present invention can be applied to various semiconductor devices. In the embodiment of the present invention, the example mainly in the memory (Memory) has been disclosed. However, the present invention is not limited to this, and semiconductor devices other than the memory, such as a CPU (Central Processing Unit), an MCU (Micro Control Unit), The present invention can be applied to general semiconductor devices such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and an ASSP (Application Specific Standard Product). Further, these semiconductor devices may include redundant memory cells and regular memory cells (normal memory cells).
Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), and POP (package on package). The present invention can be applied to a semiconductor device having any of these product forms and package forms.
The transistor may be a field effect transistor (FET), and may be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor) in addition to MOS (Metal Oxide Semiconductor). it can. It can be applied to various FETs such as transistors. Furthermore, some bipolar transistors may be included in the device.
Further, the PMOS transistor (P-type channel MOS transistor) is a second conductivity type transistor, and the NMOS transistor (N-type channel MOS transistor) is a typical example of the first conductivity type transistor.
Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that can be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor device 10, 10a, 10b ... Constant voltage generation circuit, 11 ... Memory cell array, 111 ... Memory cell area, 111m ... Memory cell, 11a ... Word line, 11b ... Bit line, 12 ... Address buffer, 13 ... Row Decoder, 14 ... column decoder, 15 ... sense amplifier, 16 ... command decoder, 17 ... mode register, 18 ... control circuit, 19 ... data input / output circuit, 16a ... clock generation circuit, 20 ... booster circuit, 20a, 20b, 20c ... Charge pump, 30 ... Voltage detection circuit, 40, 40a, 40b ... Clock signal control circuit, 50 ... Clock signal generation circuit, 60 ... Drive signal generation circuit, 60a, 53, 55, 56, 32, 62, 73 ... Inverter Circuit, 33, 57 ... AND circuit, 52, 71, 72, 61 ... NOR circuit, 58 ... NAND times 74, 82 ... delay circuit 31, 83 ... comparator, 81 ... PMOS transistor, 21, 23, 24, 25, 84 ... NMOS transistor, 23a, 24a, 25a ... switching element, C23, C24, C25 ... capacitor, R1 , R2... Resistor, N23, N24, N25, N26, A, B... Connection point, RESETT, CS, RAS, CAS, WE, DQM... Control signal, CPE. Drive signal, VREF, VR ... reference voltage, Vd ... divided voltage, VPP ... output voltage

Claims (5)

When a clock signal is input, a pumping operation is performed at a plurality of internal nodes, charges supplied to the input terminal are sequentially transferred to the output terminal via the plurality of nodes, and an output voltage is generated from the output terminal. A booster circuit to
When the first control signal is at an active level and the output voltage does not reach a preset voltage, an active level detection signal is output, the first control signal is at an active level, and the output A voltage detection circuit that outputs the detection signal at an inactive level when the voltage reaches a preset voltage;
A clock signal control circuit that outputs the clock signal to the booster circuit when the detection signal is at an active level, and stops outputting the clock signal to the booster circuit when the detection signal is at an inactive level;
With
The clock signal control circuit responds to a level of a second control signal that is input before the first control signal is input to the voltage detection circuit even when the detection signal is at an inactive level. And outputting the clock signal to the booster circuit.   The semiconductor device according to claim 1, wherein the second control signal is input when power is supplied to the semiconductor device.   The second control signal is a power dyne in which the semiconductor device is in a power down mode in which an internal circuit connected to the booster circuit is changed from an operating state to a standby state, and in which the internal circuit is changed from the standby state to the operating state. The semiconductor device according to claim 1, wherein the semiconductor device is input when the mode is shifted to the exit mode. The clock signal control circuit includes:
An oscillator that generates the clock signal at a predetermined period when an oscillator drive signal of an active level is input;
A drive signal generating circuit for generating the oscillator drive signal;
A first delay circuit in which a delay time until the output voltage of the booster circuit reaches the preset voltage is set, and when the second control signal is input, the delay time A delay signal generation circuit for generating a first delay signal that is at an active level in a period;
Including
4. The semiconductor device according to claim 1, wherein the drive signal generation circuit generates the oscillator drive signal based on the first delay signal and the detection signal. 5. . A second delay circuit for generating a second delay signal obtained by delaying the delay signal;
When the second delay signal is at an active level, the output voltage is compared with the preset voltage. When the output voltage is higher than the preset voltage, the output of the booster circuit A charge / discharge circuit that charges or discharges to a power source different from the power source to which the input terminal is connected;
The semiconductor device according to claim 4, further comprising:

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