JP2013038704A - Timing detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing detection device capable of timing detection with high accuracy.SOLUTION: A timing detection device in a receiver for receiving a signal obtained by interposing a signal obtained by mapping data and pilots on subcarriers in a multiplexed manner at equal intervals and adding a guard interval, between signals obtained by mapping data on subcarriers and adding a guard interval, includes: a DFT section 121 for converting the reception signal in a time domain into the reception signal in a frequency domain; a replica F generation section 122 for generating a replica obtained by mapping pilots on the subcarriers; a replica F multiplication section 123 for multiplying the reception signal in a frequency domain by complex conjugate of the replica for each corresponding subcarrier; an IDFT section 124 for the reception signal in a frequency domain after the multiplication of the replica into a signal in a time domain; and a peak detection section 125 for converting the signal in a time domain into power, detecting a maximum peak of the power value and outputting the detection timing.

Description

  The present invention relates to a timing detection device that detects timing from a received signal.

  In recent years, in a broadband wireless transmission system such as a wireless LAN or LTE (Long Term Evolution), a block transmission scheme such as an OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme or a single carrier block transmission scheme is used. In the block transmission scheme, a transmission sequence is mapped to subcarriers in the frequency domain, and converted into a time domain signal by inverse FFT (Fast Fourier Transform) to be a transmission signal. Furthermore, by adding a part of the rear end of the inverse FFT signal as a guard interval in front of the signal, resistance against interchannel interference due to multipath fading is given. In the block transmission scheme, when demodulating, when the position of the added guard interval is accurately estimated and the guard interval is not removed, tolerance against inter-channel interference is impaired, and reception performance deteriorates.

  In order to accurately estimate the position of the guard interval, in the conventional block transmission method, the correlation calculation between the reception signal and the signal obtained by delaying the reception signal is performed, and the timing is detected from the correlation calculation value. The delay amount is the difference between the guard interval source signal and the guard interval when the guard interval is generated, and the correlation value of the guard interval length is calculated. When the correlation value of the guard interval part is actually calculated from the received signal, the correlation value becomes high, and the timing of the guard interval can be detected. Such a technique is disclosed in Patent Document 1 below.

Patent No. 3041171

  However, according to the conventional technique, when the delay spread of the multipath is large, the previous signal is multiplexed in the guard interval portion. Therefore, there is a problem that the correlation is lowered and the timing detection performance is deteriorated.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a timing detection apparatus capable of performing timing detection with high accuracy.

  In order to solve the above-described problems and achieve the object, the present invention provides data and pilot in the frequency domain between signals in which data is mapped to subcarriers in the frequency domain and a guard interval is added in the time domain. A timing detection apparatus in a receiver for receiving a transmission signal into which a signal to which a guard interval is added after being multiplexed and mapped to subcarriers at equal intervals and converted to a time domain is provided, and the received signal in the time domain is converted to a frequency domain DFT means for converting the received signal into a received signal, replica generating means for generating a replica in which the same pilot as the pilot is mapped to a subcarrier, and the complex conjugate of the received signal in the frequency domain and the replica for each corresponding subcarrier Replica multiplier means for multiplying and frequency domain received signal after replica multiplication IDFT means for converting the signal into a signal, and a peak detection means for converting the time domain signal output from the IDFT means to power, detecting the maximum peak of the power value within a predetermined range, and outputting the timing when detected It is characterized by providing.

  According to the present invention, there is an effect that timing detection can be performed with high accuracy.

FIG. 1 is a diagram illustrating a frame configuration of a transmission signal according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of the transmitter according to the first embodiment. FIG. 3 is a diagram illustrating a mapping method to subcarriers. FIG. 4 is a diagram illustrating a configuration example of the receiver according to the first embodiment. FIG. 5 is a diagram illustrating a configuration example of the symbol timing detection unit according to the first embodiment. FIG. 6 is a diagram illustrating a configuration example of the replica F generation unit. FIG. 7 is a diagram illustrating the relationship between the transmission signal and the correlation calculation length. FIG. 8 is a diagram illustrating a configuration example of the symbol timing detection unit of the second embodiment. FIG. 9 is a diagram illustrating the relationship between the pilot symbol and replica timing of the received signal and the cross-correlation power. FIG. 10 is a flowchart showing the main processing of the detection timing correction unit. FIG. 11 is a flowchart showing processing in an asynchronous state. FIG. 12 is a flowchart showing the processing in the synchronization state. FIG. 13 is a diagram illustrating a configuration example of the symbol timing detection unit according to the third embodiment. FIG. 14 is a diagram illustrating a configuration example of the replica T generation unit. FIG. 15 is a diagram illustrating a frame configuration of a transmission signal according to the fourth embodiment. FIG. 16 is a diagram illustrating a configuration example of a transmitter according to the fourth embodiment. FIG. 17 is a diagram illustrating a configuration example of a receiver according to the fourth embodiment. FIG. 18 is a diagram illustrating a configuration example of the frame timing detection unit. FIG. 19 is a diagram illustrating a cycle and a range in which cross-correlation calculation is performed.

  Embodiments of a timing detection device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a frame configuration of a transmission signal applied to the present embodiment. The transmission signal forms a frame with a plurality of symbols (SYM). In addition, data is transmitted in each symbol, but in some symbols, a pilot used for transmission path estimation is multiplexed with data and transmitted. In FIG. 1, one frame is multiplexed with data for 16 symbols and pilots are multiplexed with data for every 4 symbols. However, this is an example, and the present invention is not limited to the configuration shown in FIG.

  FIG. 2 is a diagram illustrating a configuration example of the transmitter according to the present embodiment that generates the transmission signal illustrated in FIG. 1. The transmitter includes a DFT (Discrete Fourier Transform) unit 1, a pilot generation unit 2, a DFT unit 3, a subcarrier mapping unit 4, an IDFT (Inverse Discrete Fourier Transform) unit 5, and a GI (Guard Interval) addition unit. 6, a D / A (Digital to Analogue) conversion unit 7, a transmission radio unit 8, and a control unit 9.

  Note that the data sequence input to the DFT unit 1 is a complex data sequence subjected to information modulation such as QPSK (Quadrature Phase Shift Keying) or 16QAM (Quadrature Amplitude Modulation). Normally, error correction coding or the like is also performed before information modulation, but is omitted because it is not directly related to the operation in the present embodiment.

  The DFT unit 1 converts an input time domain data series into a frequency domain series by discrete Fourier transform (DFT). The sequence length of data differs between when a symbol for transmitting only data is generated and when a symbol multiplexed with a pilot is generated. When 1/2 is used as a pilot in a symbol for multiplexing data and pilot, and the sequence length when only data is transmitted is Ndata, the sequence length in a symbol multiplexed with pilot is Ndata / 2. The sequence length is changed under the control of the control unit 9.

  The pilot generation unit 2 generates a complex pilot sequence. As the pilot sequence, a sequence having a good autocorrelation characteristic in the time domain is used. For example, when N is a sequence length, k is a sequence number, and q is an arbitrary integer, a Zadoff-Chu sequence that is a type of CAZAC (Constant Amplitude Zero Auto-Correlation) sequence generated by the following equation is used. Can do. In addition, as shown in the following formula, the formula used when N is an even number and an odd number is different.

  The DFT unit 3 converts the complex pilot sequence generated by the pilot generation unit 2 into a frequency domain sequence by discrete Fourier transform.

  The subcarrier mapping unit 4 maps the frequency domain data sequence and the frequency domain pilot sequence to subcarriers. FIG. 3 is a diagram illustrating a mapping method to subcarriers. Here, the number of subcarriers is Ndft which is the number of IDFT points of the IDFT unit 5. When the symbol to be generated is a data-only symbol (FIG. 3A), data Data (n) of sequence length Ndata; n = 0 to Ndata-1 is continuously mapped to a certain subcarrier. On the other hand, when the symbol to be generated is a symbol that multiplexes data and pilot (FIG. 3B), data Data (n) of sequence length Ndata / 2; n = 0 to Ndata / 2-1, and sequence length Ndata / 2 Pilot Pilot (n); n = 0 to Ndata / 2-1 are mapped alternately. The controller 9 controls whether only data is mapped or whether data and pilot are mapped.

  The IDFT unit 5 converts the frequency domain sequence mapped to the subcarriers into a time domain sequence by inverse discrete Fourier transform (IDFT).

  The GI adding unit 6 adds the rear end of the time domain sequence output from the IDFT unit 5 as a guard interval to the beginning of the time domain sequence.

  The D / A conversion unit 7 converts the baseband digital signal output from the GI addition unit 6 into a baseband analog signal.

  The transmission radio unit 8 amplifies the baseband analog signal after frequency conversion and converts it into a signal to be transmitted wirelessly.

  Based on the symbol number of the symbol to be generated, the control unit 9 determines whether the generated symbol is only data or data and pilot are multiplexed, and the DFT unit 1 and the subcarrier mapping unit 4 determine whether only the data or the data And a control signal for instructing whether to multiplex the pilot.

  Next, a receiver that receives a signal (transmission signal) transmitted from the transmitter described above will be described. FIG. 4 is a diagram illustrating a configuration example of a receiver according to the present embodiment. The receiver includes a reception radio unit 101, an analog / digital (A / D) conversion unit 102, a symbol timing detection unit 103, a GI removal unit 104, and a DFT unit 105.

  The reception radio unit 101 receives a signal received by the antenna, converts the frequency, and outputs it as a reception analog baseband signal.

  A / D conversion section 102 converts the received analog baseband signal into a received digital baseband signal, and outputs the received digital baseband signal to symbol timing detection section 103 and GI removal section 104.

  The symbol timing detection unit 103 is a timing detection device, which receives the received digital baseband signal from the A / D conversion unit 102, and outputs a detection timing at which the GI removal unit 104 removes the GI of the received digital baseband signal.

  The symbol timing detection unit 103 will be described with reference to FIG. FIG. 5 is a diagram illustrating a configuration example of the symbol timing detection unit 103 in the present embodiment. The symbol timing detection unit 103 includes a DFT unit 121, a replica F generation unit 122, a replica F multiplication unit 123, an IDFT unit 124, and a peak detection unit 125.

  The DFT unit 121 converts the received digital baseband signal in the time domain into a frequency domain signal.

  The replica F generation unit 122 generates a replica F for multiplying a signal obtained by converting the received digital baseband signal in the time domain into the frequency domain.

  The replica F generation unit 122 will be described with reference to FIG. FIG. 6 is a diagram illustrating a configuration example of the replica F generation unit 122. Replica F generation section 122 includes pilot generation section 141, DFT section 142, and subcarrier mapping 143.

  The pilot generation unit 141 performs the same processing as the pilot generation unit 2 of the transmitter, and generates the same pilot sequence as the complex pilot sequence generated by the transmitter.

  The DFT unit 142 performs the same processing as the DFT unit 3 of the transmitter, and converts a time-domain pilot sequence into a frequency-domain sequence.

  Subcarrier mapping section 143 maps pilot sequences to subcarriers in the same manner as when data and pilot are multiplexed in subcarrier mapping section 4 of the transmitter. At this time, 0 is mapped to the subcarrier to which the data is mapped, and is output as a replica F.

  Note that the replica F generation unit 122 may be configured to store and read the replica F generated as described above in a memory or the like.

  Returning to the description of the symbol timing detection unit 103 in FIG. Replica F multiplication section 123 multiplies the frequency domain received signal output from DFT section 121 by the complex conjugate of replica F.

  The IDFT unit 124 converts the frequency domain signal, which is the complex output output from the replica F multiplier 123, into a time domain signal.

  The peak detection unit 125 converts the complex output of the IDFT unit 124 into power, detects the maximum value (peak) of the power value, and outputs the timing at which the maximum value is detected as the detection timing.

  The correlation calculation length, which is the range in which the peak detection unit 125 detects the peak timing, will be described with reference to FIG. FIG. 7 is a diagram showing the relationship between the transmission signal shown in FIG. 1 and the correlation calculation length when the signal is received. The correlation calculation length is a length in which one pilot is included in the range. That is, the pilot multiplex interval becomes the correlation calculation length. In FIG. 7, since the pilot is multiplexed with data every 4 symbols in the transmission signal, the correlation calculation length is also a period of 4 symbols. Thus, since the pilot is always included at the same timing within the range of the correlation calculation length, the peak detection unit 125 detects the peak (the maximum value of the correlation power in FIG. 7) at the head of the symbol where the pilot is multiplexed. Can do. The peak detection may be performed using a power average value obtained by averaging a plurality of power values of the correlation calculation length.

  Since the replica F has 0 as a subcarrier to which data is mapped, the influence of the data portion of the received signal can be eliminated by multiplication, and a sequence having good autocorrelation characteristics is used for the pilot. The correlation power in the time domain is detected as a very sharp peak at the head of the symbol where the pilot is multiplexed. Therefore, timing can be detected with high accuracy.

  Returning to the description of the receiver of FIG. GI removal section 104 removes the GI of the received digital baseband signal based on the detection timing input from symbol timing detection section 103, and outputs the time domain signal after the GI removal to DFT section 105.

  The DFT unit 105 converts the time domain signal output from the GI removal unit 104 into a frequency domain signal. The operations after the DFT unit 105 are carried out, such as transmission path estimation, frequency domain equalization, and error correction, but are not described here because they are general operations.

  In this way, data and pilots are multiplexed in the frequency domain and mapped to subcarriers at equal intervals between signals in which data is mapped to subcarriers in the frequency domain and converted to the time domain and then guard intervals are added. In a receiver that receives a transmission signal into which a signal with a guard interval after conversion is inserted, the GI removal unit 104 can remove the GI based on the timing detected by the symbol timing detection unit 103 with high accuracy. Therefore, it is possible to improve reception performance and prevent deterioration.

  As described above, in the present embodiment, the receiver timing detection apparatus multiplies the reception signal obtained by converting the time domain reception signal into the frequency domain by the complex conjugate of the replica of the subcarrier mapped only to the pilot. Then, after converting to a signal in the time domain, the maximum value of the power value is detected after power generation, and the timing at which the maximum value is detected is output as the detection timing. As a result, since the pilot is detected as a very sharp peak at the head of the multiplexed symbol, the symbol head timing can be detected with high accuracy, and the GI can be removed based on this timing, improving the reception performance. can do.

Embodiment 2. FIG.
In the present embodiment, the receiver includes a symbol timing detection unit different from that in the first embodiment. A different part from Embodiment 1 is demonstrated.

  The configuration of the receiver of this embodiment is the same as that of FIG. 4, but includes a symbol timing detection unit 103 a instead of the symbol timing detection unit 103. FIG. 8 is a diagram illustrating a configuration example of the symbol timing detection unit 103a in the present embodiment. The symbol timing detection unit 103a includes a DFT unit 121, a replica F generation unit 122, a replica F multiplication unit 123, an IDFT unit 124, a peak detection unit 125, and a detection timing correction unit 126. A detection timing correction unit 126 is added to the symbol timing detection unit 103 (see FIG. 5).

  Here, before describing the detection timing correction unit 126, characteristics of the transmission signal will be described. As described in the explanation of the operation of the transmitter shown in FIG. 2, when generating symbols in which pilots and data are multiplexed, every other pilot sequence in the frequency domain is mapped to subcarriers. When this is converted into a signal in the time domain, the same signal is repeated twice. FIG. 9 shows the cross-correlation power between such a signal and a replica. FIG. 9 is a diagram illustrating the relationship between the pilot symbol and replica timing of the received signal and the cross-correlation power. As shown in FIG. 9, when the timing of the pilot symbol of the received signal coincides with the timing of the pilot replica, the maximum peak of the cross-correlation power is detected, and the peak is detected at timings separated by Ndft / 2 before and after that. The Ndft is the number of DFT points. Depending on propagation path fluctuation, the peak before and after this may be the maximum peak, and an incorrect detection timing may be output. For this reason, the detection timing correction unit 126 corrects such erroneous timing detection.

  Although not shown in the figure, when the interval for mapping the pilot sequence is increased from every second to every second, every third, the time domain signal repeats the same signal three times and four times. The number of detected peaks will increase. Hereinafter, as an example, a method of erroneous timing detection when it is repeated twice will be described. However, it is also applicable to a case where it is repeated three times and four times with the same concept.

  Subsequently, the operation of the detection timing correction unit 126 will be described with reference to FIGS. FIG. 10 is a flowchart showing main processing of the detection timing correction unit 126. When activated, the detection timing correction unit 126 first initializes the counter CNTd and the counter CNTnd to 0 (step S101). Next, the state is set to an asynchronous state by setting the initial state (step S102). Here, the synchronized state is a state in which the transmitter that has transmitted the transmission signal is synchronized with the receiver that has received the transmission signal, and the asynchronous state is the synchronization between the transmitter and the receiver. It is assumed that there is no removal. The detection timing correction unit 126 waits for the detection timing from the peak detection unit 125 and receives the detection timing Td (t) (step S103), and determines the state (step S104). If the state is an asynchronous state (step S104: No), the asynchronous state is processed (step S105). On the other hand, when the state is a synchronous state (step S104: Yes), a synchronous state process is performed (step S106). Then, after completion of the asynchronous process (step S105) or the synchronous process (step S106), the next detection timing is waited (step S103).

  Next, the asynchronous process in step S105 of FIG. 10 will be described in detail with reference to FIG. FIG. 11 is a flowchart showing processing in an asynchronous state. First, the detection timing correction unit 126 outputs the latest detection timing Td (t) received this time as it is (step S201). Then, it is determined whether or not the current detection timing Td (t) is within the range of ± ΔTd in the range of the correlation calculation length with respect to the previous detection timing Td (t−1) (step S202). Here, ΔTd is a range in which a multipath exists, and is about the guard interval length.

  When within the range of ± ΔTd (step S202: Yes), the detection timing correction unit 126 increments the counter CNTd by 1 (step S203). On the other hand, if not within the range of ± ΔTd (step S202: No), the detection timing correction unit 126 sets the counter CNTd to 0 (step S204) and ends the asynchronous processing.

  The detection timing correction unit 126 increments the counter CNTd by 1 (step S203), and then compares the counter CNTd with the threshold value THd (step S205). The threshold value THd is a value for determining transition to the synchronous state. When the counter CNTd is less than the threshold value THd (step S205: Yes), the asynchronous process is terminated. On the other hand, when the counter CNTd is greater than or equal to the threshold THd (step S205: No), the detection timing correction unit 126 changes the state to the synchronous state (step S206), and ends the asynchronous state process.

  As a result, the detection timing correction unit 126 does not shift to the synchronization state unless the detection timing Td (t) falls within the range of ± ΔTd for the threshold THd times continuously, and thus prevents the transition to the synchronization state when a timing error is detected. be able to.

  Next, the synchronization processing in step S106 in FIG. 10 will be described in detail with reference to FIG. FIG. 12 is a flowchart showing the processing in the synchronization state. First, the detection timing correction unit 126 determines whether the current (latest) detection timing Td (t) is within the range of ± ΔTd in the range of the correlation calculation length with respect to the previous detection timing Td (t−1). Is determined (step S301). If it is within the range of ± ΔTd (step S301: Yes), the counter CNTd and the counter CNTnd are each initialized to 0 (step S302). And detection timing Td (t) is output (step S303) and the process of a synchronous state is complete | finished.

  Returning to step S301, if it is not within the range of ± ΔTd (step S301: No), the detection timing correction unit 126 then sets the current detection timing to the previous detection timing Td (t-1). It is determined whether Td (t) + Ndft / 2 obtained by adding Ndft / 2 as a predetermined difference is within a range of ± ΔTd in the range of correlation calculation length (step S304). Here, Ndft / 2 is a value obtained by multiplying the number of points Ndft at the time of DFT or IDFT by the ratio of pilot to the total number of pilots and data to be mapped to subcarriers (1/2 here). If it is within the range of ± ΔTd (step S304: Yes), the counter CNTd is incremented by 1 and the counter CNTnd is initialized to 0 (step S305). Then, the counter CNTd is compared with the threshold value THd (step S306). When the counter CNTd is less than the threshold THd (step S306: Yes), the timing is corrected to a timing that is + Ndft / 2 away from the original timing Td (t) (step S307). Thereafter, the corrected detection timing Td (t) is output (step S303), and the process of the synchronization state is ended. On the other hand, when the counter CNTd is equal to or greater than the threshold value THd (step S306: No), the detection timing Td (t) is output as it is (step S303), and the process of the synchronization state is ended.

  As a result, it is possible to correct erroneous detection at a timing separated by + Ndft / 2 from the original timing to the original timing. Further, when the correction occurs THd times as the threshold value continuously, the timing separated by + Ndft / 2 is used as the original timing, so that it is possible to prevent the erroneous detection timing from being taken.

  Returning to step S304, if it is not within the range of ± ΔTd (step S304: No), then the detection timing correction unit 126 starts from the current detection timing with respect to the previous detection timing Td (t−1). It is determined whether or not Td (t) −Ndft / 2 obtained by subtracting Ndft / 2 as a predetermined difference is within a range of ± ΔTd in the range of correlation calculation length (step S308). If it is within the range of ± ΔTd (step S308: Yes), the counter CNTd is decremented by 1, and the counter CNTnd is initialized to 0 (step S309). Then, the counter CNTd is compared with the threshold value -THd (step S310). When the counter CNTd is larger than the threshold value -THd (step S310: Yes), the timing is corrected to a timing that is -Ndft / 2 away from the original timing Td (t) (step S311). Thereafter, the corrected detection timing Td (t) is output (step S303), and the process of the synchronization state is ended. On the other hand, when the counter CNTd is equal to or smaller than the threshold −THd (step S310: No), the detection timing Td (t) is output as it is (step S303), and the process of the synchronization state is ended.

  As a result, it is possible to correct erroneous detection at a timing that is -Ndft / 2 away from the original timing to the original timing. In addition, when the correction occurs THd times as the threshold value continuously, the timing that is -Ndft / 2 apart is set as the original timing, and therefore it is possible to prevent the erroneous detection timing from being taken.

  Returning to step S308, if not within the range of ± ΔTd (step S308: No), the counter CNTd is initialized to 0 and the counter CNTnd is incremented by 1 (step S312). Then, the counter CNTnd is compared with the threshold value THnd (step S313). The threshold value THnd is a value for determining transition to the asynchronous state. When the counter CNTnd is smaller than the threshold value THnd (step S313: Yes), the timing Td (t) detected this time is corrected to Td (t-1) (step S314). Thereafter, the corrected detection timing Td (t) is output (step S303), and the process of the synchronization state is ended. On the other hand, when the counter CNTnd is greater than or equal to the threshold value THnd (step S313: No), the state is changed to an asynchronous state (step S315). Thereafter, the detection timing Td (t) is output (step S303), and the process of the synchronization state is ended.

  Accordingly, when an unexpected detection timing is detected, the detection timing is not used, so that demodulation at an erroneous detection timing can be prevented, and deterioration of demodulation performance can be prevented. If unexpected detection timings occur continuously, it is determined that synchronization has been lost, and the state is changed asynchronously.

  As described above, in the present embodiment, for the detected timing, the result of comparing the timing detected this time or the timing obtained by adding or subtracting Ndft / 2 to the timing detected this time with the timing detected last time. The timing detected this time is corrected or output without correction. As a result, the timing at which erroneous detection is likely to occur due to the signal characteristics can be corrected, and the timing detection performance can be improved as compared with the first embodiment.

Embodiment 3 FIG.
In the present embodiment, the receiver includes a symbol timing detection unit different from those in the first and second embodiments. A different part from Embodiment 1, 2 is demonstrated.

  The configuration of the receiver according to this embodiment is the same as that of FIG. 4, but includes a symbol timing detection unit 103 b instead of the symbol timing detection unit 103. FIG. 13 is a diagram illustrating a configuration example of the symbol timing detection unit 103b in the present embodiment. The symbol timing detection unit 103b includes a replica T generation unit 161, a correlation calculation unit 162, and a peak detection unit 163.

  The replica T generation unit 161 generates a replica T that is a time domain pilot replica.

  The replica T generation unit 161 will be described with reference to FIG. FIG. 14 is a diagram illustrating a configuration example of the replica T generation unit 161. Replica T generation section 161 includes pilot generation section 141, DFT section 142, subcarrier mapping section 143, and IDFT section 144. An IDFT unit 144 is added to the replica F generation unit 122 of the first embodiment.

  The IDFT unit 144 converts the frequency domain sequence subjected to subcarrier mapping into a time domain, and outputs a replica T that is a time domain pilot replica. The replica T generation unit 161 may be configured to store and read the replica F generated as described above in a memory or the like.

  Returning to the description of the symbol timing detection unit 103b in FIG. The correlation calculation unit 162 performs a cross-correlation calculation between the received digital baseband signal input to the timing detection unit 103b and the replica T, and outputs a complex correlation calculation result. The cross-correlation calculation is a calculation generally performed in the receiver. Here, the correlation between the received digital baseband signal and the replica T is obtained, and the vector quantity composed of the I phase and the Q phase is used as a complex correlation calculation result. calculate.

  The peak detector 163 converts the complex correlation calculation result into electric power, and outputs the maximum power timing as the detection timing in the correlation calculation length. The correlation calculation length is the same as that described in FIG. The peak detection may be performed using a power average value obtained by averaging a plurality of power values of the correlation calculation length.

  In the symbol timing detection unit 103b (see FIG. 13) and the symbol timing detection unit 103 (see FIG. 5), signal processing regions differ in time and frequency and have different configurations, but in principle the same processing. Therefore, the symbol timing detection unit 103b can obtain the same effect as the symbol timing detection unit 103, can detect the symbol head timing with high accuracy, and can improve the reception performance.

  As described above, in the present embodiment, the symbol timing detection unit 103b performs peak detection using the received signal in the time domain as it is without converting the received signal into the frequency domain, and using the result of the cross-correlation calculation. I decided to do it. Even in this case, the same effect as in the first embodiment can be obtained.

  Note that the symbol timing detection unit 103b can have the same configuration as the detection timing correction unit 126 described in the second embodiment. In this case, an effect equivalent to that of the second embodiment can be obtained.

Embodiment 4 FIG.
In the present embodiment, there are two types of pilots multiplexed on data. A different part from Embodiments 1-3 is demonstrated.

  FIG. 15 is a diagram illustrating a frame configuration of a transmission signal applied to the present embodiment. The transmission signal forms a frame with a plurality of symbols (SYM). In FIG. 15, 16 symbols form one frame, but this is an example, and the number of symbols in one frame may not be 16. Further, although data is transmitted in each symbol, a pilot is multiplexed with data and transmitted in part. In FIG. 15, the pilot is multiplexed with data every 4 symbols, but may not be every 4 symbols. 1 differs from the transmission signal shown in FIG. 1 in that two types of pilots, pilot 1 as a first pilot and pilot 2 as a second pilot, are multiplexed with data. Pilot 2 is multiplexed on symbol # 0 at the head of the frame, and pilot 1 is multiplexed on the other pilot multiplexed symbols.

  FIG. 16 is a diagram illustrating a configuration example of the transmitter according to the present embodiment that generates the transmission signal illustrated in FIG. 15. The transmitter includes a pilot 1 generation unit 201, a pilot 2 generation unit 202, a pilot selection unit 203, a DFT unit 1, a DFT unit 3, a subcarrier mapping unit 4, an IDFT unit 5, and a GI addition unit 6. And a D / A conversion unit 7, a transmission radio unit 8, and a control unit 204.

  Pilot 1 generator 201 and pilot 2 generator 202 generate a pilot 1 sequence and a pilot 2 sequence, respectively. The pilot 1 sequence and the pilot 2 sequence have good autocorrelation characteristics and low cross correlation. For example, a Zadoff-Chu sequence that is one type of the above-described CAZAC sequence is used that has a different sequence number.

  Pilot selection section 203 selects and outputs either a pilot 1 series or a pilot 2 series in accordance with a control signal from control section 204.

  Based on the symbol number of the symbol to be generated, the control unit 204 determines whether the symbol to be generated is only data, or multiplexes data and pilot, and determines whether only the data for the DFT unit 1 and the subcarrier mapping unit 4 A control signal indicating whether to perform pilot multiplexing is output. Further, when data and pilot are multiplexed, a control signal instructing which one of pilot 1 sequence and pilot 2 sequence is used is output to pilot selection section 203.

  Next, a receiver that receives a signal transmitted from the transmitter described above will be described. FIG. 17 is a diagram illustrating a configuration example of a receiver according to the present embodiment. The receiver includes a reception radio unit 101, an A / D conversion unit 102, a symbol timing detection unit 103, a GI removal unit 104, a DFT unit 105, and a frame timing detection unit 221.

  The operations of reception radio section 101, A / D conversion section 102, symbol timing detection section 103, GI removal section 104, and DFT section 105 are the same as those in Embodiment 1 (see FIG. 4). Note that the pilot replica generated by the symbol timing detection unit 103 is a replica of pilot 1 and outputs the symbol timing to the frame timing detection unit 221.

  FIG. 18 is a diagram illustrating a configuration example of the frame timing detection unit 221. The frame timing detection unit 221 includes a replica 2T generation unit 261, a correlation calculation unit 262, and a peak detection unit 263.

  The replica 2T generation unit 261 is a pilot sequence generated by the pilot generation unit 141 of the replica T generation unit 161 illustrated in FIG. 14 as a pilot 2, and generates a replica 2T.

  The correlation calculation unit 262 receives the replica 2T, the digital baseband signal output from the A / D conversion unit 102, and the symbol timing from the symbol timing detection unit 103. The correlation calculation unit 262 performs a cross-correlation calculation between the digital baseband signal and the replica 2T, and outputs a complex calculation result.

  FIG. 19 is a diagram illustrating a cycle and a range in which cross-correlation calculation is performed. Correlation power 1 is for pilot 1, and correlation power 2 is for pilot 2. The cross-correlation calculation cycle is performed at a cycle in which a pilot sequence is inserted. FIG. 19 shows a case where a pilot sequence is inserted every 4 symbols, and the cross-correlation calculation cycle is also performed every 4 symbols. Here, with respect to the timing of the symbol on which pilot 2 is multiplexed, the detection processing is performed while limiting the correlation calculation range as compared with the case of detecting the timing of the symbol on which pilot 1 is multiplexed. As shown in FIG. 19, the cross-correlation calculation range for the timing of the symbol on which pilot 2 is multiplexed is about the guard interval length around the symbol timing, taking into account fluctuations in peak timing due to multipath.

  The peak detection unit 263 powers the complex cross-correlation calculation result from the correlation calculation unit 262, detects the maximum peak timing among the cross-correlation calculation results for one frame, and outputs the timing as the frame timing.

  In this way, data generated in the time domain and pilot 1 are multiplexed between signals in which a plurality of pilots are used, data is mapped to subcarriers in the frequency domain, and a guard interval is added after conversion to the time domain. While a signal with a guard interval mapped to an interval and added with a guard interval after time domain insertion is inserted at a predetermined period, a transmission signal generated using pilot 2 instead of pilot 1 is received at a frame period. In the receiver, the frame timing detection unit 221 detects timing for only one pilot 2 multiplexed in one frame. At this time, the frame timing detection unit 221 performs cross-correlation calculation processing in a limited range as compared with the symbol timing detection unit 103.

  As described above, in this embodiment, when two types of pilots are used and a pilot multiplexed at the head of a frame is detected, in the timing detection device, the frame timing detection unit limits the cross-correlation calculation range. The peak detection process was performed. Thereby, the amount of processing when performing peak detection can be reduced. The frame timing detection pilot (pilot 2) uses a sequence with good autocorrelation characteristics, and uses a sequence with low cross-correlation with the symbol timing detection pilot (pilot 1). Can be detected.

  In addition, although the case where the symbol timing detection part 103 was used in the receiver was demonstrated, it is not limited to this, It can apply also to symbol timing detection part 103a, 103b.

  As described above, the timing detection apparatus according to the present invention is useful for a broadband wireless transmission system, and is particularly suitable when a block transmission system is used.

DESCRIPTION OF SYMBOLS 1 DFT part 2 Pilot production | generation part 3 DFT part 4 Subcarrier mapping part 5 IDFT part 6 GI addition part 7 D / A conversion part 8 Transmission radio | wireless part 9 Control part 101 Reception radio | wireless part 102 A / D conversion part 103, 103a, 103b Symbol timing detection unit 104 GI removal unit 105 DFT unit 121 DFT unit 122 Replica F generation unit 123 Replica F multiplication unit 124 IDFT unit 125 Peak detection unit 126 Detection timing correction unit 141 Pilot generation unit 142 DFT unit 143 Subcarrier mapping unit 144 IDFT Unit 161 replica T generation unit 162 correlation calculation unit 163 peak detection unit 201 pilot 1 generation unit 202 pilot 2 generation unit 203 pilot selection unit 204 control unit 221 frame timing detection unit 261 replica 2T Generating unit 262 correlation calculation unit 263 the peak detector

Claims (12)

Data and pilots are multiplexed in the frequency domain and mapped to subcarriers at equal intervals between signals in which data is mapped to subcarriers in the frequency domain and converted to the time domain, and then guarded after conversion to the time domain. A timing detection apparatus in a receiver for receiving a transmission signal into which an interval-added signal is inserted,
DFT means for converting a time domain received signal into a frequency domain received signal;
Replica generating means for generating a replica in which the same pilot as the pilot is mapped to a subcarrier;
Replica multiplication means for multiplying the complex conjugate of the received signal in the frequency domain and the replica for each corresponding subcarrier;
IDFT means for converting a frequency domain received signal after replica multiplication into a time domain signal;
Peak detection means for powering the time domain signal output from the IDFT means, detecting the maximum peak of the power value within a predetermined range, and outputting the timing when detected;
A timing detection apparatus comprising: Data and pilots are multiplexed in the frequency domain and mapped to subcarriers at equal intervals between signals in which data is mapped to subcarriers in the frequency domain and converted to the time domain, and then guarded after conversion to the time domain. A timing detection apparatus in a receiver for receiving a transmission signal into which an interval-added signal is inserted,
Replica generating means for mapping a pilot identical to the pilot to a subcarrier and generating a replica converted into a time domain signal;
Correlation calculation means for performing correlation calculation between the received signal in the time domain and the replica, and outputting a complex correlation calculation result;
Peak detection means for converting the complex correlation calculation result into electric power, detecting the maximum peak of the power value within a predetermined range, and outputting the timing when detected;
A timing detection apparatus comprising: The predetermined range is an interval at which a signal in which data and pilot are multiplexed is inserted into a transmission signal.
The timing detection apparatus according to claim 1, wherein Using multiple pilots, data generated in the time domain and the first pilot are multiplexed at equal intervals between signals in which data is mapped to subcarriers in the frequency domain and converted to the time domain and guard intervals are added. While a signal that is mapped to a subcarrier and converted into a time domain and added with a guard interval is inserted at a predetermined period, a transmission signal generated by using a second pilot instead of the first pilot at a frame period A timing detection device in a receiver for receiving,
DFT means for converting a time domain received signal into a frequency domain received signal;
First replica generation means for generating a first replica in which the same pilot as the first pilot is mapped to a subcarrier;
Replica multiplying means for multiplying the frequency domain received signal and the complex conjugate of the first replica for each corresponding subcarrier;
IDFT means for converting a frequency domain received signal after replica multiplication into a time domain signal;
First peak detection means for converting the time domain signal output from the IDFT means to power, detecting the maximum peak of the power value within a predetermined range, and outputting a first timing when detected;
A second replica generating means for mapping the same pilot as the second pilot to a subcarrier and generating a second replica converted into a time domain signal;
Correlation calculation means for performing a correlation calculation between the received signal in the time domain and the second replica in a predetermined range, and outputting a complex correlation calculation result;
A second peak detecting means for converting the complex correlation calculation result into electric power, detecting a maximum peak of the power value within a predetermined range, and outputting a second timing when detected;
A timing detection apparatus comprising: Using multiple pilots, data generated in the time domain and the first pilot are multiplexed at equal intervals between signals in which data is mapped to subcarriers in the frequency domain and converted to the time domain and guard intervals are added. While a signal that is mapped to a subcarrier and converted into a time domain and added with a guard interval is inserted at a predetermined period, a transmission signal generated by using a second pilot instead of the first pilot at a frame period A timing detection device in a receiver for receiving,
First replica generating means for mapping the same pilot as the first pilot to a subcarrier and generating a first replica converted into a time domain signal;
A first correlation calculation means for performing a correlation calculation between the received signal in the time domain and the first replica, and outputting a first complex correlation calculation result;
First peak detection means for converting the first complex correlation calculation result into electric power, detecting a maximum peak of a power value within a first predetermined range, and outputting a first timing when detected;
A second replica generating means for mapping the same pilot as the second pilot to a subcarrier and generating a second replica converted into a time domain signal;
A second correlation calculation means for performing a correlation calculation between the received signal in the time domain and the second replica in a predetermined range, and outputting a second complex correlation calculation result;
Second peak detection means for converting the second complex correlation calculation result into power, detecting a maximum peak of the power value within a second predetermined range, and outputting a second timing when detected;
A timing detection apparatus comprising: The predetermined range or the second predetermined range when the second peak detecting means detects the maximum peak is a range in which the length of the guard interval is given before and after the first timing,
The timing detection apparatus according to claim 4 or 5, wherein further,
Detection timing correction means for correcting and outputting the timing detected by the peak detection means;
The timing detection apparatus according to claim 1, 2 or 3. further,
Detection timing correction means for correcting and outputting the timing detected by the first peak detection means;
The timing detection device according to claim 4, 5 or 6. The detection timing correction means determines whether to perform correction according to the synchronization state between the transmitter that transmits the transmission signal and the receiver.
The timing detection apparatus according to claim 7 or 8, wherein The detection timing correction means, when in a synchronized state, compares the latest detection timing with the latest detection timing, and corrects the latest detection timing by a predetermined difference when a predetermined difference is detected as a result of the comparison.
The timing detection apparatus according to claim 9. The detection timing correction means compares the previous detection timing with the latest detection timing when in a synchronized state, and if a predetermined difference is detected continuously as a result of comparison, the latest detection timing is not corrected. Output,
The timing detection apparatus according to claim 9 or 10, wherein The predetermined difference is a discrete Fourier transform when converting the time domain signal to the frequency domain signal or an inverse discrete Fourier transform point when converting the frequency domain signal to the time domain signal. A value obtained by multiplying the ratio of the pilot to the total number of pilots and the data mapped to the subcarriers,
The timing detection apparatus according to claim 10 or 11, wherein

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