JP2013037472A - Method and program for setting power supply voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a proper power supply voltage to each chip.SOLUTION: A delay ratio of a gate delay and a wiring delay of a critical path is extracted from layout data 20 of a chip (steps S1, S2). A gate delay and a wiring delay actually measured by a monitor circuit of the chip are synthesized on the basis of the delay ratio to generate a first delay value (a step S3), and a gate delay and a wiring delay obtained by simulation of the monitor circuit are synthesized on the basis of the delay ratio to generate a second delay value (steps S4, S5). A chip power supply voltage applied to the chip is set on the basis of the first and second delay values in consideration of the gate delay, wiring delay, and the delay ratio of the critical path (a step S7).

Description

  The present invention relates to a power supply voltage setting method applied to a chip and a power supply voltage setting program.

  In the manufacture of a chip (semiconductor element), due to process variations, a chip that operates at a speed higher or lower than a target speed may be generated at a power supply voltage that is initially set. For a chip that operates at a speed higher than the target speed, the processing voltage can be optimized and the power consumption can be reduced by lowering the power supply voltage. A chip that operates at a lower speed than the target speed can be used by increasing the power supply voltage to ensure the target speed and optimize the processing timing. Such a power supply voltage setting method is called ASV (Adaptive Supply Voltage Scaling). A technique for performing ASV on a processing core such as a DSP (Digital Signal Processor) core in an integrated circuit such as an ASIC (Application Specific Integrated Circuit) is also known.

Special table 2009-519620

  In the ASV that sets the power supply voltage of a chip according to process variations, for example, a predetermined monitor circuit is used for each chip, and a delay (or frequency) according to process variations is acquired. Then, the acquired delay is converted into a power supply voltage using a conversion table showing the relationship between the delay and the power supply voltage, and the power supply voltage applied to the chip is set. For example, a ring oscillation circuit is used as the monitor circuit, and in this case, the gate delay characteristic is reflected in the delay measured by the monitor circuit and the delay of the conversion table. That is, in such an ASV, the power supply voltage is set based on the gate delay characteristic.

  However, in a chip to which such ASV is applied, when a circuit in which wiring delay is dominant is a critical path, a desired operation is realized for the chip with a power supply voltage set based on the gate delay. You may not be able to.

  According to one aspect of the present invention, the ratio between the gate delay and the wiring delay of the critical path is extracted from the layout data of the chip, and the gate delay and the wiring measured under the first power supply voltage condition for the monitor circuit provided in the chip. A delay is combined based on the ratio to generate a first delay value, and a gate delay and a wiring delay obtained by simulation under the first power supply voltage condition for the monitor circuit are combined based on the ratio to generate a second delay. A power supply voltage setting method is provided for generating a value and setting a chip power supply voltage to be applied to the chip based on the first delay value and the second delay value.

  According to another aspect of the present invention, a power supply voltage setting program for causing a computer to execute processing for realizing such a method is provided.

  According to the disclosed technology, it is possible to set an appropriate power supply voltage in consideration of gate delay and wiring delay in the chip, and it is possible to realize a desired operation for the chip.

It is explanatory drawing of an example of the power supply voltage setting method. It is explanatory drawing of a conversion table. It is explanatory drawing of an example of the power supply voltage setting method which considered the gate delay and the wiring delay. It is a figure which shows the structural example of a power supply voltage setting apparatus. It is a figure which shows an example of a critical path. It is a figure which shows an example of a delay analysis result. It is a figure which shows an example of a conversion table. It is a figure which shows an example of a conversion table. It is a figure which shows an example of a chip power supply voltage setting process flow. It is a figure which shows the structural example of the hardware of a power supply voltage setting apparatus.

First, an embodiment of a method for setting a power supply voltage (chip power supply voltage) applied to a chip will be described.
FIG. 1 is an explanatory diagram of an example of a power supply voltage setting method.

  In the power supply voltage setting method shown in FIG. 1, first, the delay value of the monitor circuit 100 mounted on the chip for measuring delay (delay time or frequency) is measured under a predetermined power supply voltage condition (step S10). ). The monitor circuit 100 is provided with a ring oscillation circuit 101, for example. By operating such a monitor circuit 100 under a predetermined power supply voltage condition, a delay value reflecting the gate delay is actually measured.

  Further, with respect to the monitor circuit 100, a simulation using a computer is executed using the layout data (design data) and the like, and a delay value (simulation value) reflecting the gate delay is measured (step S20). This simulation is executed, for example, by changing the conditions of process variation and power supply voltage (including the power supply voltage condition at the time of actual measurement). Then, based on the simulation result of each condition, a conversion table 110 including the relationship between process variation, power supply voltage, and delay value is created (step S30).

FIG. 2 is an explanatory diagram of the conversion table.
Through the simulation as described above, process variation (−3σ to + 3σ), power supply voltage (1.0 [V] to 2.0 [V]), delay value (A [ps], A conversion table 110 showing the relationship of A ′ [ps], B [ps], B ′ [ps]) is created.

  In FIG. 2, for example, the plus (+) side of the process variation σ indicates the case where the chip (monitor circuit 100) operates at a higher speed than the target speed, and the minus (−) side indicates the chip than the target speed. The case where the (monitor circuit 100) operates at a low speed is shown. In this case, the delay values are A [ps]> B [ps] and A ′ [ps]> B ′ [ps]. Further, regarding the relationship between the delay value and the power supply voltage, the delay value increases as the power supply voltage decreases, and A [ps]> A ′ [ps] and B [ps]> B ′ [ps].

With reference to the conversion table 110 created as described above, the chip power supply voltage is set based on the measured delay value (actual measurement, simulation) (step S40).
For example, by referring to the conversion table 110, first, the corresponding process variation of the delay value actually measured under a predetermined power supply voltage condition is obtained as described above. This process variation is the process variation of the chip on which the monitor circuit 100 is mounted. If the chip process variation is the target process variation, the power supply voltage used in the actual measurement of the monitor circuit 100 is set to the chip power supply voltage applied to the chip. If the chip process variation is different from the target process variation, a power supply voltage is obtained from the conversion table 110 to obtain a delay value (the simulation value) corresponding to the target process variation, and the power supply voltage is the chip power supply voltage. Set to

  When the corresponding process variation of the delay value actually measured by the monitor circuit 100 is larger than the target process variation (the chip operates at a higher speed than the target speed), a voltage lower than the power supply voltage at the time of actual measurement is Set to power supply voltage. When the corresponding process variation of the delay value actually measured by the monitor circuit 100 is smaller than the target process variation (the chip operates at a speed lower than the target speed), a voltage higher than the power supply voltage at the time of actual measurement is set. Set to power supply voltage.

  By applying such an ASV technique, for a chip that is closer to high speed (Fast), the processing power can be optimized and the power consumption can be reduced by lowering the chip power supply voltage. In addition, for a chip that is close to a low speed (Slow), the processing power can be optimized and the target speed can be secured by increasing the chip power supply voltage.

  By the way, in the method shown in FIG. 1, the monitor circuit 100 measures (measures and simulates) a delay value reflecting the gate delay, and sets the chip power supply voltage based on the delay value. However, in recent years, with the miniaturization, high integration, and high density of circuit elements (transistors, wiring, etc.) in the chip, the influence of wiring delay on the chip operating speed and chip power supply voltage is also affected. It's getting bigger. If a circuit whose wiring delay becomes dominant is a critical path of a chip, the chip power supply voltage set based on the gate delay as described above can realize a desired operation for the chip. Things that can't be done can happen.

Therefore, hereinafter, a method for setting the chip power supply voltage considering the wiring delay in addition to the gate delay will be described.
FIG. 3 is an explanatory diagram of an example of a power supply voltage setting method in consideration of gate delay and wiring delay.

  In the power supply voltage setting method shown in FIG. 3, a monitor circuit 10 including a gate delay monitor 11 that measures a gate delay and a wiring delay monitor 12 that measures a wiring delay is used. The monitor circuit 10 is mounted on a chip that sets a chip power supply voltage.

  The gate delay monitor 11 of the monitor circuit 10 is composed of a circuit for measuring a gate delay, for example, a ring oscillation circuit 11a. The wiring delay monitor 12 of the monitor circuit 10 includes a circuit provided with a logic gate and a wiring so that the wiring delay is dominant, for example, a ring oscillation circuit 12a, and a gate delay circuit, for example, a ring oscillation circuit 12b. . The measurement of the wiring delay by the wiring delay monitor 12 is performed by subtracting the output obtained by the ring oscillation circuit 12b from the output obtained by the ring oscillation circuit 12a.

  In setting the chip power supply voltage, first, a critical path is extracted from the chip layout data (design data) 20 (step S1). Here, a critical path existing in the layout data 20 is extracted by executing a delay analysis simulation using the layout data 20 by a computer. Next, the gate delay and the wiring delay in the extracted critical path are extracted based on the delay analysis result of the delay analysis simulation, and the ratio (delay ratio) X: Y of the gate delay and the wiring delay is obtained (step S2).

  For the monitor circuit 10, the gate delay and the wiring delay are measured by the gate delay monitor 11 and the wiring delay monitor 12, respectively, under a predetermined power supply voltage condition. Then, the actually measured gate delay and wiring delay are synthesized based on the delay ratio of the critical path extracted from the layout data 20 (step S3). Combining the actually measured gate delay MG and wiring delay ML based on the delay ratio X: Y of the critical path is performed according to the following equation (1).

(MG × X + ML × Y) / (X + Y) (1)
Further, a simulation using a computer using the layout data is executed for the monitor circuit 10, and the gate delay and the wiring delay are measured (simulated) by the gate delay monitor 11 and the wiring delay monitor 12, respectively (step S4). ). This simulation is executed, for example, by changing the conditions of process variation and power supply voltage (including the power supply voltage condition at the time of actual measurement).

  The gate delay and the wiring delay obtained by the simulation are synthesized based on the delay ratio of the critical path (step S5), and the conversion table 30 including the relationship among the process variation, the power supply voltage, and the delay value after synthesis is created ( Step S6). The synthesis of the gate delay SG and the wiring delay SL obtained by the simulation based on the critical path delay ratio X: Y is performed according to the following equation (2).

(SG × X + SL × Y) / (X + Y) (2)
With reference to the conversion table 30 created as described above, the chip power supply voltage is set based on the measured delay value (actual measurement, simulation) (step S7). The details of setting the chip power supply voltage using the conversion table 30 will be described later.

The chip power supply voltage as shown in FIG. 3 is set using, for example, a power supply voltage setting device 50 as shown in FIG.
FIG. 4 is a diagram illustrating a configuration example of the power supply voltage setting device.

The power supply voltage setting device 50 illustrated in FIG. 4 includes a delay ratio extraction unit 53 a including a delay analysis unit 51 and a delay ratio generation unit 52.
The delay analysis unit 51 extracts a critical path from the chip layout data 20 by a delay analysis simulation, and further extracts a gate delay and a wiring delay in the extracted critical path, respectively. The delay ratio generation unit 52 generates a delay ratio between the gate delay and the wiring delay based on the gate delay and the wiring delay in the critical path extracted by the delay analysis unit 51. The delay ratio generated by the delay ratio generation unit 52 is stored in the delay ratio storage unit 53. Thus, the delay ratio (ratio) of the critical path gate delay and the wiring delay is extracted from the layout data 20 by the delay analysis unit 51 and the delay ratio generation unit 52 of the delay ratio extraction unit 53a.

The power supply voltage setting device 50 further includes a first delay value generation unit 55, a monitor circuit simulation unit 56, a second delay value generation unit 57, and a chip power supply voltage setting unit 59.
The first delay value generation unit 55 generates a delay value by using the information in the actual delay storage unit 54 in which the gate delay MG and the wiring delay ML actually measured for the monitor circuit 10 under a predetermined power supply voltage condition are stored. The first delay value generation unit 55 combines the gate delay MG and the wiring delay ML stored in the measured delay storage unit 54 based on the delay ratio stored in the delay ratio storage unit 53 according to the above equation (1). To do.

  The monitor circuit simulation unit 56 executes a simulation for the monitor circuit 10 and acquires a gate delay SG and a wiring delay SL (simulation value). For this simulation, for example, data of the monitor circuit 10 included in the layout data 20 can be used. The monitor circuit simulation unit 56 changes the process variation and power supply voltage conditions, and executes the simulation of the monitor circuit 10 for each condition.

  The second delay value generation unit 57 uses the gate delay SG and the wiring delay SL acquired by changing the conditions in the monitor circuit simulation unit 56 based on the delay ratio stored in the delay ratio storage unit 53 for each condition. And synthesized according to the above formula (2). The second delay value generation unit 57 creates the conversion table 30 including the relationship among the process variation, the power supply voltage, and the combined delay value based on the combined delay value.

  The chip power supply voltage setting unit 59 is a conversion table created based on the combined delay value generated by the first delay value generating unit 55 and the combined delay value generated by the second delay value generating unit 57. 30 is used to set the chip power supply voltage applied to this chip.

The power supply voltage setting device 50 as described above can be realized using a computer.
For example, according to the power supply voltage setting method shown in FIG. 3 using the power supply voltage setting device 50 as shown in FIG. 4, an appropriate chip is taken into account according to the process variation of the chip in consideration of gate delay and wiring delay. The power supply voltage can be set. Hereinafter, the power supply voltage setting method shown in FIG. 3 will be described in more detail with a specific example.

  First, critical path extraction will be described. In setting the chip power supply voltage, as described above, first, the delay analysis unit 51 of the power supply voltage setting device 50 identifies and extracts a critical path of the chip from the layout data 20 by delay analysis simulation.

FIG. 5 shows an example of the extracted critical path.
A portion surrounded by a dotted line in FIG. 5 is an example of the extracted critical path 21. The critical path 21 shown in FIG. 5 includes cells (Cell_A to G) of circuit elements such as flip-flops and logic gates, and wirings (Net_1 to 7) connecting the cells. The critical path 21 has a configuration in which Cell_A, Net_1, Cell_B, Net_2, Cell_C, Net_3, Cell_D, Net_4, Cell_E, Net_5, Cell_F, Net_6, Cell_G, and Net_7 are sequentially connected.

The delay analysis unit 51 extracts such a critical path 21 by delay analysis simulation, and further extracts a delay analysis result of the extracted critical path 21.
FIG. 6 shows an example of the extracted delay analysis result.

  By the delay analysis simulation, the delays of each of Cell_A to G and Net_1 to 7 in the critical path 21 are analyzed, and each delay [ps] is extracted as shown in the delay analysis result 51a of FIG. Each delay of Cell_A to G is extracted as a gate delay, and each delay of Net_1 to 7 is extracted as a wiring delay.

  After the extraction of the gate delay of each Cell_A to G and the wiring delay of each Net_1 to 7, the delay ratio generation unit 52 of the power supply voltage setting device 50 uses these values to determine the delay ratio (gate delay and gate delay) of the critical path 21. Wiring delay ratio). In the case of the example of FIG. 6, the gate delay and the wiring delay are obtained as shown in the following equations (3) and (4), respectively.

Gate delay = 60 [ps] (Cell_A) +60 [ps] (Cell_B) +50 [ps] (Cell_C) +90 [ps] (Cell_D) +70 [ps] (Cell_E) +40 [ps] (Cell_F) +30 [ps] ( Cell_G) = 400 [ps] (3)
Wiring delay = 20 [ps] (Net_1) +30 [ps] (Net_2) +50 [ps] (Net_3) +20 [ps] (Net_4) +30 [ps] (Net_5) +30 [ps] (Net_6) +20 [ps] ( Net — 7) = 200 [ps] (4)
From these calculation results, the delay ratio of the critical path 21 is obtained as gate delay: wiring delay = 2: 1. The delay ratio obtained by the delay ratio generation unit 52 is stored in the delay ratio storage unit 53 of the power supply voltage setting device 50.

  Thus, while the delay ratio of the critical path 21 is obtained, the gate delay and the wiring delay of the monitor circuit 10 of this chip are measured under a predetermined power supply voltage condition, for example, 2.0 [V]. . The gate delay and the wiring delay are measured using the gate delay monitor 11 and the wiring delay monitor 12, respectively. The actually measured gate delay and wiring delay are stored in the actual delay storage unit 54 of the power supply voltage setting device 50.

  The first delay value generation unit 55 of the power supply voltage setting device 50 uses the measured gate delay and wiring delay stored in the measured delay storage unit 54 and synthesizes them based on the previously obtained delay ratio. To do.

  For example, the gate delay (measured value of the gate delay monitor 11) obtained by actual measurement is 80 [ps], and the wiring delay (actual value of the wiring delay monitor 12) obtained by actual measurement is 20 [ps]. To do. In this case, the combined delay value of these gate delay and wiring delay based on the delay ratio is obtained as shown in the following equation (1a) according to the above equation (1).

(80 [ps] × 2 + 20 [ps] × 1) / (2 + 1) = 60 [ps] (1a)
For the monitor circuit 10 of this chip, simulation values of gate delay and wiring delay are acquired by the monitor circuit simulation unit 56 of the power supply voltage setting device 50.

  The monitor circuit simulation unit 56 first performs a simulation for each of the gate delay monitor 11 and the wiring delay monitor 12 of the monitor circuit 10 at the power supply voltage at the time of the actual measurement, which is 2.0 [V] in this example. Get the simulation value of wiring delay. The simulation conditions in the monitor circuit simulation unit 56 can be set in advance by the measurer before the simulation.

  Next, the second delay value generation unit 57 of the power supply voltage setting device 50 uses the gate delay and the wiring delay acquired by the simulation in the monitor circuit simulation unit 56, and calculates them based on the previously obtained delay ratio. Synthesize.

  For example, the gate delay (simulated value of the gate delay monitor 11) obtained by the simulation is 100 [ps], and the wiring delay (simulated value of the wiring delay monitor 12) obtained by the simulation is 40 [ps]. To do. In that case, the combined delay value of these gate delay and wiring delay based on the delay ratio is obtained as shown in the following equation (2a) according to the above equation (2).

(100 [ps] × 2 + 40 [ps] × 1) / (2 + 1) = 80 [ps] (2a)
In this example, the monitor circuit simulation unit 56 further changes the process variation and power supply voltage conditions, executes the simulation of the monitor circuit 10 under each condition, and obtains simulation values of gate delay and wiring delay for each condition. To do. Then, the second delay value generation unit 57 synthesizes the gate delay and the wiring delay acquired under each condition based on the delay ratio as described above, and creates the conversion table 30.

FIG. 7 shows an example of the conversion table.
In FIG. 7, there are two types of process variation conditions: a standard chip (Typ) and a high-speed chip (2σ Fast), and the power supply voltage condition is 1.0 [V]. The conversion table 30 is illustrated with two types of 2.0 and 2.0 [V]. Here, the power supply voltage 2.0 [V] (Typ) is the chip power supply voltage initially set for this chip. In the conversion table 30 of FIG. 7, the post-synthesis delay value 80 [ps] obtained by the above equation (2a) is stored as a simulation value under the conditions of process variation Typ and power supply voltage 2.0 [V]. ing.

  In addition, the conversion table 30 of FIG. 7 includes a delay value 100 after synthesis based on the delay ratio of the gate delay and the wiring delay obtained by the simulation under the conditions of process variation Typ and power supply voltage 1.0 [V]. [Ps] is stored. Further, the conversion table 30 in FIG. 7 includes a combined delay value 80 based on the delay ratio of the gate delay and the wiring delay obtained by the simulation under the conditions of process variation 2σFast and the power supply voltage of 1.0 [V]. [Ps] is stored. Further, the conversion table 30 in FIG. 7 includes a delay value 60 after synthesis based on the delay ratio of the gate delay and the wiring delay obtained by the simulation under the conditions of process variation 2σFast and the power supply voltage of 2.0 [V]. [Ps] is stored.

  The chip power supply voltage setting unit 59 of the power supply voltage setting device 50 refers to the conversion table 30 created as described above, and determines the delay value (actual measurement value) 60 [ps] obtained by the above equation (1a). ], The chip power supply voltage is set.

  For example, the delay value 60 [ps] after the combination of the gate delay and the wiring delay actually measured under the condition of the power supply voltage 2.0 [V] corresponds to the process variation 2σ Fast condition from the conversion table 30. In order to obtain a delay of a delay value of 80 [ps] (simulation value under the condition of a power supply voltage of 2.0 [V]) corresponding to a process variation of Typ, the power supply voltage is set to 2.0 [V] from the conversion table 30. To 1.0 [V]. The chip power supply voltage setting unit 59 sets the power supply voltage 1.0 [V] thus obtained as the chip power supply voltage applied to the chip.

  In this way, for a chip that has become closer to high speed due to process variations, 1.0 [V] lower than the power supply voltage 2.0 [V] that was initially set is set as the chip power supply voltage. Thereby, it is possible to optimize the processing timing and reduce the power consumption of the chip that has become closer to the high speed. In setting the chip power supply voltage, an appropriate chip power supply voltage can be set by considering the gate delay and the wiring delay and further considering their ratio (delay ratio) in the critical path 21.

  The chip power supply voltage setting unit 59 can set the chip power supply voltage in a simplified manner as follows. For example, the chip power supply voltage setting unit 59 compares the delay values (measured values and simulation values of the monitor circuit 10) obtained by the above formulas (1a) and (2a), and the chip power supply is based on the comparison result. Set the voltage.

  In the case of the above example, the synthesized delay value (actual value) obtained by the equation (1a) is 60 [ps], while the synthesized delay value (simulated value) obtained by the equation (2a) is 80 [ps]. ]. Accordingly, since the actually measured delay value is smaller than the simulation value, it can be determined that the actually formed chip is closer to the high speed. In the case of a chip that is closer to high speed, for example, the power supply voltage is lowered to a preset power supply voltage according to the difference between the simulation value and the actual measurement value of the delay value, and the reduced power supply voltage is set as the chip power supply voltage. . By performing such processing in the chip power supply voltage setting unit 59, processing necessary for creating the conversion table 30 can be omitted.

The chip power supply voltage setting method (ASV) using the power supply voltage setting device 50 has been described above.
Next, an example of the chip power supply voltage setting process performed by the chip power supply voltage setting unit 59 will be described with another specific example.

FIG. 8 is a diagram illustrating an example of a conversion table, and FIG. 9 is a diagram illustrating an example of a chip power supply voltage setting process flow.
In FIG. 8, there are three types of process variation conditions of Typ, 2σFast, and 3σFast, and power supply voltage conditions of 1.0 [V], 1.5 [V], and 2.0 [V] (Typ). The conversion table 30a in the case of a type is illustrated. The power supply voltage 2.0 [V] is the power supply voltage initially set for the chip for which the chip power supply voltage is to be set. As shown in FIG. 8, the conversion table 30a stores delay values (simulation values) for each condition of process variation and power supply voltage.

  Note that the conversion table 30a including the contents as shown in FIG. 8 can be created in the same manner as described above. In other words, the monitor circuit simulation unit 56 performs a simulation on the chip monitor circuit for setting the chip power supply voltage under each condition of predetermined process variation and power supply voltage. Then, the gate delay and the wiring delay obtained by the simulation are synthesized by the second delay value generation unit 57 based on the delay ratio of the critical path of the chip for each condition of the simulation. The delay ratio of the critical path of the chip is generated by a delay analysis simulation in the delay analysis unit 51 using the layout data of the chip and a process in the delay ratio generation unit 52 using the analysis result.

  In the case of the conversion table 30a of FIG. 8, in the process variation Typ, when the power supply voltage is 1.0 [V], the delay value is 120 [ps], when the power supply voltage is 1.5 [V], the delay value is 100 [ps]. When 2.0 [V], the delay value is 80 [ps]. In the process variation 2σFast, the delay value is 100 [ps] when the power supply voltage is 1.0 [V], the delay value is 80 [ps] when the power supply voltage is 1.5 [V], and the delay is when the power supply voltage is 2.0 [V]. The value is 60 [ps]. In the process variation 3σFast, the delay value is 80 [ps] when the power supply voltage is 1.0 [V], the delay value is 60 [ps] when the power supply voltage is 1.5 [V], and the delay is when the power supply voltage is 2.0 [V]. The value is 40 [ps].

  Now, assume that a delay value (actual measurement value) obtained by synthesizing the gate delay and the wiring delay actually measured for the chip monitor circuit for setting the chip power supply voltage based on the delay ratio of the critical path is X [ps]. . Further, when setting the chip power supply voltage, the power supply voltage is lowered until the delay (speed) when the process variation is equivalent to Typ is reached for a chip having a large process variation σ, that is, close to high speed (Fast). Shall be allowed to.

  First, the chip power supply voltage setting unit 59 is obtained using the conversion table 30a of FIG. 8 with the target process variation Typ and the initially set power supply voltage of 2.0 [V] (Typ). A delay value of 80 [ps] is set as a target delay value (step S100).

  Next, the chip power supply voltage setting unit 59 extracts the power supply voltage when the target delay value 80 [ps] set in step S100 is obtained in each of the process variations 2σFast and 3σFast (step S101). In the case of the conversion table 30a of FIG. 8, the power supply voltage at which the delay value 80 [ps] is obtained when the process variation 2σFast is 1.5 [V], and the delay value 80 [ps] is obtained at the process variation 3σFast. The power supply voltage to be applied is 1.0 [V]. The chip power supply voltage setting unit 59 extracts such a corresponding power supply voltage from the conversion table 30a.

  When setting the chip power supply voltage, the chip power supply voltage setting unit 59 determines the delay value X [ps] actually measured under the condition of the power supply voltage 2.0 [V] (Typ) and the power supply in the conversion table 30a. Comparison is made with the delay value obtained by the simulation of the condition of voltage 2.0 [V] (Typ).

  At this time, the chip power supply voltage setting unit 59 first determines that the actually measured delay value X [ps] is equal to or less than the delay value 80 [ps] at the process variation Typ and the delay value 60 [ps] at the process variation 2σFast. Is also larger (step S102). If the chip power supply voltage setting unit 59 determines that the actually measured delay value X [ps] satisfies the condition of 80 [ps] ≧ X [ps]> 60 [ps] in step S <b> 102, the delay value X [ The process variation of the chip from which [ps] is obtained is determined as Typ (step S103). Then, the chip power supply voltage setting unit 59 does not change the power supply voltage (step S104), and ends the chip power supply voltage setting process. That is, in this case, the initial power supply voltage 2.0 [V] (Typ) is set as the chip power supply voltage as it is.

  When the chip power supply voltage setting unit 59 determines that the actually measured delay value X [ps] does not satisfy the condition of 80 [ps] ≧ X [ps]> 60 [ps] in step S102, the following is performed. Perform proper processing.

  That is, the chip power supply voltage setting unit 59 determines whether or not the actually measured delay value X [ps] is equal to or less than the delay value 60 [ps] at the process variation 2σFast and greater than the delay value 40 [ps] at the process variation 3σFast. Is determined (step S105). If the chip power supply voltage setting unit 59 determines that the actually measured delay value X [ps] satisfies the condition of 60 [ps] ≧ X [ps]> 40 [ps] in step S <b> 105, the chip power supply voltage setting unit 59 The process variation of the chip for which [ps] is obtained is determined as 2σFast (step S106). Then, the chip power supply voltage setting unit 59 uses, as the chip power supply voltage, the value of 1.5 [V] extracted as the power supply voltage at which the target delay value 80 [ps] is obtained when the process variation is 2σFast in step S101. Settings are made (step S107), and the process is terminated.

  When the chip power supply voltage setting unit 59 determines that the actually measured delay value X [ps] does not satisfy the condition of 60 [ps] ≧ X [ps]> 40 [ps] in step S105, the following is performed. Perform proper processing.

  That is, the chip power supply voltage setting unit 59 determines whether or not the actually measured delay value X [ps] is smaller than the delay value 40 [ps] in the process variation 3σFast (step S108). The chip power supply voltage setting unit 59 determines that the actually measured delay value X [ps] does not satisfy the condition of 40 [ps]> X [ps] in step S108 (X [ps] = 40 [ps]). In step S109, the process variation of the chip from which the delay value X [ps] is obtained is determined to be 3σFast. Then, the chip power supply voltage setting unit 59 uses, as the chip power supply voltage, the value of 1.0 [V] extracted as the power supply voltage at which the target delay value 80 [ps] is obtained when the process variation is 3σFast in step S101. Set (step S110), the process is terminated.

  When the actually measured delay value X [ps] determines that the condition of 40 [ps]> X [ps] in step S108 is satisfied, the chip power supply voltage setting unit 59 determines that the chip is defective (step S111), the process is terminated.

By performing the processing as shown in FIG. 9, the chip power supply voltage in consideration of the gate delay and the wiring delay of the chip can be appropriately set according to the process variation of the chip.
The chip power supply voltage setting method (ASV) has been described above. In the above description, the power supply voltage setting of the chip that is close to the target speed or high speed (Fast) is described as an example, but the same applies to the chip that is close to the low speed (Slow). It is possible to set an appropriate power supply voltage for the chip.

The power supply voltage setting device 50 used for the power supply voltage setting as described above can be realized using a computer.
FIG. 10 is a diagram illustrating a hardware configuration example of the power supply voltage setting device.

  The entire power supply voltage setting device 50 using a computer is controlled by a CPU (Central Processing Unit) 201. A RAM (Random Access Memory) 202 and a plurality of peripheral devices are connected to the CPU 201 via a bus 208.

  The RAM 202 is used as a main storage device of the power supply voltage setting device 50. The RAM 202 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 201. The RAM 202 stores various data necessary for processing by the CPU 201.

  Peripheral devices connected to the bus 208 include a hard disk drive (HDD) 203, a graphic processing device 204, an input interface 205, an optical drive device 206, and a communication interface 207.

  The HDD 203 magnetically writes data to and reads data from a built-in disk. The HDD 203 is used as a secondary storage device of the power supply voltage setting device 50. The HDD 203 stores an OS program, application programs, and various data. A semiconductor storage device such as a flash memory can also be used as the secondary storage device.

  A monitor 221 is connected to the graphic processing device 204. The graphic processing device 204 displays an image on the screen of the monitor 221 in accordance with a command from the CPU 201. Examples of the monitor 221 include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 222 and a mouse 223 are connected to the input interface 205. The input interface 205 transmits a signal transmitted from the keyboard 222 or the mouse 223 to the CPU 201. The mouse 223 is an example of a pointing device, and other pointing devices can be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 206 reads data recorded on the optical disk 224 using laser light or the like. The optical disk 224 is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 224 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 207 is connected to the network 210. The communication interface 207 transmits / receives data to / from other computers or communication devices via the network 210.

With the hardware configuration as described above, the processing function of the power supply voltage setting device 50 can be realized.
The processing function of the power supply voltage setting device 50 can be realized by a computer. In that case, a power supply voltage setting program describing the processing contents of the functions that the power supply voltage setting device 50 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Magnetic storage devices include HDDs, flexible disks (FD), magnetic tapes, and the like. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

Further, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP, an ASIC, or a PLD (Programmable Logic Device).
Regarding the embodiment described above, the following additional notes are further disclosed.

(Supplementary note 1)
Extract ratio of critical path gate delay and wiring delay from chip layout data,
A gate delay and a wiring delay actually measured under the first power supply voltage condition for the monitor circuit provided in the chip are combined based on the ratio to generate a first delay value,
A second delay value is generated by synthesizing a gate delay and a wiring delay obtained by simulation under the first power supply voltage condition for the monitor circuit based on the ratio.
Setting a chip power supply voltage to be applied to the chip based on the first delay value and the second delay value;
A power supply voltage setting method.

(Supplementary note 2) The power supply voltage setting method according to supplementary note 1, wherein the chip power supply voltage is set based on a comparison result between the first delay value and the second delay value.
(Supplementary note 3)
Create a table including a relationship between a plurality of conditions of process variation and power supply voltage, and a third delay value in each of the conditions,
Referencing the table, comparing the first delay value and the third delay value, to extract the process variation within the condition to which the first delay value falls,
Setting the chip power supply voltage based on the extracted process variation and the second delay value;
The power supply voltage setting method according to supplementary note 1, wherein:

(Appendix 4) When setting the chip power supply voltage,
With reference to the table, with the extracted process variation, extract the power supply voltage within the condition for obtaining the second delay value,
Setting the extracted power supply voltage to the chip power supply voltage;
The power supply voltage setting method according to supplementary note 3, wherein:

(Appendix 5) When creating the table,
The third delay value is generated by synthesizing the gate delay and the wiring delay obtained by the simulation under the respective conditions of the monitor circuit based on the ratio for each of the conditions,
The power supply voltage setting method according to appendix 3 or 4, characterized in that:

(Appendix 6) The monitor circuit is
A gate delay monitor for measuring a gate delay used to generate the first delay value and the second delay value;
A wiring delay monitor for measuring a wiring delay used to generate the first delay value and the second delay value;
Including
The wiring delay monitor is
A logic gate and a wiring are provided so that the wiring delay becomes dominant, and includes a first circuit that outputs the gate delay and the wiring delay, and a second circuit that outputs only the gate delay,
A wiring delay used to generate the first delay value and the second delay value is measured by subtracting the output of the second circuit from the output of the first circuit;
The power supply voltage setting method according to any one of appendices 1 to 5, wherein:

(Appendix 7)
Extract ratio of critical path gate delay and wiring delay from chip layout data,
A gate delay and a wiring delay actually measured under the first power supply voltage condition for the monitor circuit provided in the chip are combined based on the ratio to generate a first delay value,
A second delay value is generated by synthesizing a gate delay and a wiring delay obtained by simulation under the first power supply voltage condition for the monitor circuit based on the ratio.
Setting a chip power supply voltage to be applied to the chip based on the first delay value and the second delay value;
A power supply voltage setting program for executing a process.

(Supplementary note 8) The power supply voltage setting program according to supplementary note 7, wherein the chip power supply voltage is set based on a comparison result between the first delay value and the second delay value.
(Supplementary note 9)
Create a table including a relationship between a plurality of conditions of process variation and power supply voltage, and a third delay value in each of the conditions,
Referencing the table, comparing the first delay value and the third delay value, to extract the process variation within the condition to which the first delay value falls,
Setting the chip power supply voltage based on the extracted process variation and the second delay value;
The power supply voltage setting program according to appendix 7, wherein the program is executed.

(Appendix 10) When setting the chip power supply voltage,
With reference to the table, with the extracted process variation, extract the power supply voltage within the condition for obtaining the second delay value,
Setting the extracted power supply voltage to the chip power supply voltage;
The power supply voltage setting program according to appendix 9, wherein

(Appendix 11) When creating the table,
The third delay value is generated by synthesizing the gate delay and the wiring delay obtained by the simulation under the respective conditions of the monitor circuit based on the ratio for each of the conditions,
The power supply voltage setting program according to appendix 9 or 10, characterized by the above.

(Additional remark 12) The extraction part which extracts the ratio of the gate delay and wiring delay of a critical path from the layout data of a chip,
A first generation unit configured to generate a first delay value by synthesizing a gate delay and a wiring delay actually measured under a first power supply voltage condition for the monitor circuit provided in the chip based on the ratio;
A second generation unit that generates a second delay value by synthesizing a gate delay and a wiring delay obtained by simulation under the first power supply voltage condition for the monitor circuit based on the ratio;
A setting unit configured to set a chip power supply voltage applied to the chip based on the first delay value and the second delay value;
A power supply voltage setting device comprising:

DESCRIPTION OF SYMBOLS 10,100 Monitor circuit 11 Gate delay monitor 11a, 12a, 12b, 101 Ring oscillation circuit 12 Wiring delay monitor 20 Layout data 21 Critical path 30, 30a, 110 Conversion table 50 Power supply voltage setting apparatus 51 Delay analysis part 51a Delay analysis result 52 Delay ratio generation unit 53 Delay ratio storage unit 53a Delay ratio extraction unit 54 Actual delay storage unit 55 First delay value generation unit 56 Monitor circuit simulation unit 57 Second delay value generation unit 59 Chip power supply voltage setting unit 201 CPU
202 RAM
203 HDD
204 Graphic Processing Device 205 Input Interface 206 Optical Drive Device 207 Communication Interface 208 Bus 210 Network 221 Monitor 222 Keyboard 223 Mouse 224 Optical Disk

Claims (5)

Computer
Extract ratio of critical path gate delay and wiring delay from chip layout data,
A gate delay and a wiring delay actually measured under the first power supply voltage condition for the monitor circuit provided in the chip are combined based on the ratio to generate a first delay value,
A second delay value is generated by synthesizing a gate delay and a wiring delay obtained by simulation under the first power supply voltage condition for the monitor circuit based on the ratio.
Setting a chip power supply voltage to be applied to the chip based on the first delay value and the second delay value;
A power supply voltage setting method.   2. The power supply voltage setting method according to claim 1, wherein the chip power supply voltage is set based on a comparison result between the first delay value and the second delay value. The computer is
Create a table including a relationship between a plurality of conditions of process variation and power supply voltage, and a third delay value in each of the conditions,
Referencing the table, comparing the first delay value and the third delay value, to extract the process variation within the condition to which the first delay value falls,
Setting the chip power supply voltage based on the extracted process variation and the second delay value;
The power supply voltage setting method according to claim 1. The monitor circuit is
A gate delay monitor for measuring a gate delay used to generate the first delay value and the second delay value;
A wiring delay monitor for measuring a wiring delay used to generate the first delay value and the second delay value;
Including
The wiring delay monitor is
A logic gate and a wiring are provided so that the wiring delay becomes dominant, and includes a first circuit that outputs the gate delay and the wiring delay, and a second circuit that outputs only the gate delay,
A wiring delay used to generate the first delay value and the second delay value is measured by subtracting the output of the second circuit from the output of the first circuit;
The power supply voltage setting method according to any one of claims 1 to 3. On the computer,
Extract ratio of critical path gate delay and wiring delay from chip layout data,
A gate delay and a wiring delay actually measured under the first power supply voltage condition for the monitor circuit provided in the chip are combined based on the ratio to generate a first delay value,
A second delay value is generated by synthesizing a gate delay and a wiring delay obtained by simulation under the first power supply voltage condition for the monitor circuit based on the ratio.
Setting a chip power supply voltage to be applied to the chip based on the first delay value and the second delay value;
A power supply voltage setting program for executing a process.

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