JP2013026896A - Solid state imaging device, method for controlling the same, and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging device constituted by connecting a plurality of chips, capable of acquiring an image of a global exposure system even when a connecting part is shared by a plurality of pixels, a method for controlling the same, and an imaging device.SOLUTION: A solid state imaging device includes first and second circuit boards in which circuit elements constituting pixels are arranged are electrically connected by contacting parts. The solid state imaging device has a plurality of pixels, each being classified to one of one or more groups. A plurality of the pixels shares one of the contacting parts. The pixels each include: a photoelectric conversion element disposed in the first circuit board; a first transfer portion for transferring a signal generated in the photoelectric conversion element to a first storage portion; a second transfer portion for transferring the signal stored in the first storage portion to a second storage portion shared by a plurality of the pixels included in the same group; and an output portion disposed on the second circuit board, for outputting the signal stored in the second storage portion from the pixel.

Description

  The present invention relates to a solid-state imaging device, a control method for a solid-state imaging device, and an imaging device.

In recent years, CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging devices (hereinafter referred to as “MOS-type solid-state imaging devices”) have attracted attention and have been put to practical use as solid-state imaging devices.
Unlike a CCD (Charge Coupled Device) type solid-state imaging device, this MOS-type solid-state imaging device can be driven by a single power source. In addition, while a CCD type solid-state imaging device requires a dedicated manufacturing process, a MOS type solid-state imaging device can be manufactured using the same manufacturing process as other LSIs, so that the SOC (System On Chip). The solid-state imaging device can be made multifunctional.
In addition, since the MOS solid-state imaging device amplifies signal charges in each pixel by providing an amplification circuit in each pixel, the MOS-type solid-state imaging device has a configuration that is not easily affected by noise from a signal transmission path. Further, the signal charge of each pixel can be selected and taken out (selection method), and in principle, the signal accumulation time and readout order can be freely controlled for each pixel.

  Conventionally, a line exposure method and a global exposure method are known as exposure methods for a general MOS solid-state image pickup device (hereinafter also referred to as “solid-state image pickup device”). In the line exposure method, a large number of pixels arranged two-dimensionally in the solid-state imaging device are exposed at different timings for each row. In this method, a video signal of a subject is obtained by sequentially reading out signal charges generated by photoelectric conversion elements in pixels in the row after performing exposure of a certain row. In the case of the line exposure method, it is possible to continuously perform exposure and readout in units of rows. For this reason, the video signal of the subject can be obtained in a state where the influence of noise generated in the storage unit that stores the signal charge generated by the photoelectric conversion element is minimized. However, when a subject moving with the line exposure method is photographed, the subject cannot be imaged correctly because the exposure timing differs for each row. That is, in the line exposure method, there is a problem that an image in which the subject is distorted is obtained depending on the moving direction of the subject.

  On the other hand, the global exposure method is a method in which all pixels arranged two-dimensionally in the solid-state imaging device are exposed at the same timing. In the case of the global exposure method, since all the pixels are exposed at the same timing, there is no problem that a distorted image is obtained even when a moving subject is photographed. However, in the global exposure method, after all the pixels are exposed, the signal charges generated by the photoelectric conversion elements in the pixels are sequentially read out, so it takes time to start reading the signal charges after the exposure is completed. In the required pixel, it is difficult to suppress the influence of noise generated in the storage unit. For this reason, a global exposure type solid-state imaging device often provides a noisy video signal as compared to a line exposure type solid-state imaging device.

  In the global exposure type solid-state imaging device, by adding a circuit for suppressing the influence of noise generated in the storage unit as described above to the solid-state imaging device, even in the solid-state imaging device adopting the global exposure method, the influence of noise is reduced. A video signal that is minimized can be obtained. However, by adding a circuit that suppresses the influence of such noise to the solid-state imaging device, there is a problem that the entire area of the solid-state imaging device increases and the solid-state imaging device itself increases in size.

  As a technique for solving such a problem, for example, as in Patent Document 1, a pixel circuit unit of a MOS type solid-state imaging device is manufactured as a pixel circuit chip, while a signal processing unit is manufactured as a signal processing chip, A method of stacking these separately manufactured chips is disclosed. In the technique disclosed in Patent Document 1, a separately manufactured pixel circuit chip and a signal processing chip are connected via bumps.

JP 2006-49361 A

  Usually, in a semiconductor integrated circuit having a structure in which substrates are bonded together, bumps or the like are used as connection portions for transmitting and receiving electrical signals, as employed in Patent Document 1. However, in the solid-state imaging device, pixel miniaturization is progressing. For this reason, if the pitch of the pixels having one photoelectric conversion element becomes narrower than the pitch at which bumps can be formed, it becomes impossible to produce one bump for each of these pixels. End up.

  In order to solve this problem, the technique disclosed in Patent Document 1 allows bumps to be formed in pixels having a narrow pixel pitch by sharing one bump among a plurality of pixels. However, when a bump is shared by a plurality of pixels, it is necessary to sequentially read out signal charges generated by the photoelectric conversion elements in the pixel sharing the bump. For this reason, there arises a problem that the superiority of the global exposure method that the exposure period of all the pixels is the same period is lost. In particular, as the number of photoelectric conversion elements (pixels) sharing one bump increases, the time difference from the end of exposure to the reading of signal charges between the photoelectric conversion elements sharing the bump increases. Therefore, even in the case of a global exposure type solid-state imaging device, there is a problem that an unnatural image can be obtained if a subject moving at high speed is photographed in a configuration in which bumps are shared by a plurality of pixels.

  The present invention has been made on the basis of the above-mentioned problem recognition, and in a solid-state imaging device configured by connecting a plurality of chips, a plurality of connection units that transmit and receive electrical signals between the connected chips are provided. It is an object of the present invention to provide a solid-state imaging device, a control method for the solid-state imaging device, and an imaging device that can acquire a global exposure method image even when the pixels are shared.

  In order to solve the above problems, in a solid-state imaging device according to an aspect of the present invention, a first substrate on which circuit elements constituting a pixel are arranged and a second substrate are electrically connected by a connection portion. The solid-state imaging device includes a plurality of the pixels, and each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion. The pixel includes a photoelectric conversion element disposed on the first substrate, a first transfer unit that transfers a signal generated by the photoelectric conversion element to a first storage unit, and the first transfer unit. A second transfer unit configured to transfer a signal stored in the storage unit to a second storage unit shared by a plurality of the pixels included in the same group; and the second transfer unit. The signal accumulated in the accumulation unit is output from the pixel. Characterized in that it comprises a force unit.

  The solid-state imaging device control method according to an aspect of the present invention includes a solid-state imaging in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit. A method of controlling an apparatus, wherein the solid-state imaging device includes a plurality of pixels, and each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion. And a first transfer step of transferring a signal generated by the photoelectric conversion element of the pixel arranged on the first substrate to the first storage unit, and the signal stored in the first storage unit From the second transfer step of transferring a signal to a second storage unit shared by a plurality of the pixels included in the same group, and from the output unit of the pixels arranged on the second substrate, the second Outputs the signal accumulated in the storage unit Characterized by comprising an output step of, a.

  Further, an imaging device according to an aspect of the present invention is an imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels are A photoelectric conversion element disposed on a first substrate; a first transfer unit that transfers a signal generated by the photoelectric conversion element to a first storage unit; and a signal stored in the first storage unit, A second transfer unit that transfers to a second storage unit shared by a plurality of the pixels included in the same group, and a signal that is arranged on the second substrate and stored in the second storage unit, An output unit for outputting from the pixel. .

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion. The solid-state imaging device includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels Includes a photoelectric conversion element disposed on the first substrate, a first transfer unit that simultaneously transfers a signal generated by the photoelectric conversion element to a first storage unit in all the pixels, and the first transfer unit. A second transfer unit that sequentially transfers a signal stored in one storage unit to a second storage unit shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; And disposed on the second substrate, Accumulated signal to the storage portion of the, characterized in that it comprises an output unit for outputting from the pixel.

  The solid-state imaging device control method according to an aspect of the present invention includes a solid-state imaging in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit. A method of controlling an apparatus, wherein the solid-state imaging device includes a plurality of pixels, and each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion. A first transfer step in which signals generated by photoelectric conversion elements of the pixels arranged on the first substrate are simultaneously transferred to the first accumulation unit in all the pixels; A second transfer step of sequentially transferring a signal stored in the storage unit to a second storage unit shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; Arranged on the second substrate. From the output of the pixels which are characterized by containing an output step of outputting the stored signal to the second accumulation unit.

  Further, an imaging device according to an aspect of the present invention is an imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels are A photoelectric conversion element disposed on a first substrate; a first transfer unit that simultaneously transfers a signal generated by the photoelectric conversion element to a first storage unit in all the pixels; and the first storage unit. A second transfer unit that sequentially transfers a signal stored in the unit to a second storage unit shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; Arranged on the second substrate, in the second storage section A product signal, characterized in that it comprises an output unit for outputting from the pixel.

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion. The solid-state imaging device includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels Receives the photoelectric conversion element disposed on the first substrate and a signal generated by the photoelectric conversion element at one of the source and the drain, outputs the other from the other of the source and the drain, and transfers them to the first storage capacitor The first transfer transistor and a signal stored in the first storage capacitor are received by one of the source and the drain and output from the other of the source and the drain, and a plurality of front transistors included in the same group A second transfer transistor for transferring to a second storage capacitor shared by the pixel, and a capacitor arranged on the second substrate for outputting a signal stored in the second storage capacitor from the pixel And an output circuit including a transistor.

  The solid-state imaging device control method according to an aspect of the present invention includes a solid-state imaging in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit. A method of controlling an apparatus, wherein the solid-state imaging device includes a plurality of pixels, and each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion. The first transfer transistor that receives the signal generated by the photoelectric conversion element of the pixel disposed on the first substrate at one of the source and the drain and outputs the signal from the other of the source and the drain is supplied to the first transfer transistor. A first transfer step for transferring a signal generated by the photoelectric conversion element to the first storage capacitor, and a signal stored in the first storage capacitor is received by one of the source and the drain. A second transfer transistor that outputs from the other one of the drains and drains to transfer a signal stored in the first storage capacitor to a second storage capacitor shared by a plurality of the pixels included in the same group. And an output step of outputting a signal stored in the second storage capacitor from an output circuit of the pixel arranged on the second substrate.

  Further, an imaging device according to an aspect of the present invention is an imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels are A photoelectric conversion element disposed on a first substrate; a signal generated by the photoelectric conversion element received by one of a source and a drain; output from the other of the source and drain; and transferred to a first storage capacitor A transfer transistor and a signal stored in the first storage capacitor are received by one of the source and drain, output from the other of the source and drain, and shared by the plurality of pixels included in the same group A second transfer transistor that transfers to the second storage capacitor, and a capacitor or transistor that is disposed on the second substrate and that outputs the signal stored in the second storage capacitor from the pixel. And an output circuit.

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion. The solid-state imaging device includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels Is a photoelectric conversion element disposed on the first substrate, and a signal generated by the photoelectric conversion element is received by one of the source and the drain and output from the other of the source and the drain, The first transfer transistor for transferring to the first storage capacitor and the signal stored in the first storage capacitor are received by one of the source and drain, and output from the other of the source and drain, and the same A second transfer transistor for sequentially transferring the second storage capacitor shared by the plurality of pixels included in the loop within the plurality of pixels included in the group, and the second transfer transistor, And an output circuit including a capacitor and a transistor for outputting a signal stored in the second storage capacitor from the pixel.

  The solid-state imaging device control method according to an aspect of the present invention includes a solid-state imaging in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit. A method of controlling an apparatus, wherein the solid-state imaging device includes a plurality of pixels, and each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion. The first transfer transistor that receives the signal generated by the photoelectric conversion element of the pixel disposed on the first substrate at one of the source and the drain and outputs the signal from the other of the source and the drain is supplied to the first transfer transistor. A first transfer step of simultaneously transferring a signal generated in the photoelectric conversion element to the first storage capacitor in all the pixels; and a signal stored in the first storage capacitor as a source and a drain A second storage capacitor shared by a plurality of the pixels included in the same group receives a signal stored in the first storage capacitor in a second transfer transistor that is received by one and output from the other of the source and the drain And a signal stored in the second storage capacitor from a second transfer step of sequentially transferring the pixel in the group and the output circuit of the pixel arranged on the second substrate. And an output step for outputting.

  Further, an imaging device according to an aspect of the present invention is an imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion, and the pixels are A photoelectric conversion element disposed on the first substrate and a signal generated by the photoelectric conversion element are received by one of the source and the drain and output from the other of the source and the drain. A first transfer transistor that transfers to the storage capacitor, and a signal stored in the first storage capacitor is received by one of the source and drain and output from the other of the source and drain to be included in the same group. A second transfer transistor that sequentially transfers the second storage capacitor shared by the plurality of pixels within the plurality of pixels included in the group, and the second storage transistor, And an output circuit including a capacitor and a transistor for outputting a signal stored in the storage capacitor from the pixel.

1 is a block diagram showing a schematic configuration of a digital camera according to an embodiment of the present invention. 1 is an overview diagram illustrating a schematic configuration of an image sensor according to an embodiment. It is a circuit diagram showing a schematic configuration of a pixel chip in the image sensor of the present embodiment. It is the circuit diagram which showed schematic structure of the pixel signal processing chip in the image sensor of this embodiment. It is a circuit diagram showing a schematic configuration of a unit pixel in a pixel chip provided in the image sensor of the present embodiment. It is the circuit diagram which showed schematic structure of the unit pixel memory in the pixel signal processing chip with which the image sensor of this embodiment was equipped. It is the sequence diagram which showed the sequence which drives the image sensor of this embodiment. 4 is a timing chart showing the timing of each drive of the image sensor of the present embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description includes specific details for illustrative purposes. However, those skilled in the art will understand that even if various modifications are made to the detailed contents described below, the scope of the present invention is not exceeded. Accordingly, the exemplary embodiments of the invention described below are set forth without loss of generality or limitation to the claimed invention. .

  FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera (for example, a single-lens reflex digital camera) according to the present embodiment. Each component shown here can be realized in terms of hardware by elements such as a CPU and a memory of a computer, and in terms of software, it can be realized by a computer program. These are shown as functional blocks realized by these linkages. Therefore, those skilled in the art will understand that these functional blocks can be realized in various forms by a combination of hardware and software.

  A digital camera 1 shown in FIG. 1 includes a lens unit 2, an image sensor 3, a light emitting device 4, a memory 5, a recording device 6, a display device 7, an image signal processing circuit 8, a lens control device 9, and an image sensor control device 10. , A light emission control device 11 and a camera control device 12. The digital camera 1 shown in FIG. 1 is a digital camera that does not have a mechanical shutter for shielding the image sensor 3 and performs global exposure that exposes all pixels simultaneously.

The lens unit 2 is driven and controlled by the lens control device 9 such as zoom, focus, and diaphragm, and forms a subject image on the image sensor 3.
The image sensor 3 is a MOS solid-state imaging device that is driven and controlled by the image sensor control device 10 and converts subject light incident on the image sensor 3 through the lens unit 2 into an image signal. In the following description, an image sensor refers to a MOS type solid-state imaging device. A detailed description of the image sensor 3 will be described later.
The light-emitting device 4 is a device such as a strobe or a flash that is driven and controlled by the light-emission control device 11 and adjusts the light reflected from the subject by applying the light emitted from the light-emitting device 4 to the subject.

The image signal processing circuit 8 performs processing such as signal amplification, conversion to image data, various corrections, and image data compression on the image signal output from the image sensor 3. The image signal processing circuit 8 uses the memory 5 as temporary storage means for image data in each process.
The recording device 6 is a detachable recording medium such as a semiconductor memory, and records or reads image data.
The display device 7 is a display device such as a liquid crystal that displays an image based on the image data imaged on the image sensor 3 and processed by the image signal processing circuit 8 or the image data read from the recording device 6.

  The camera control device 12 is a control device that performs overall control of the digital camera 1. In addition, the camera control device 12 controls the image sensor control device 10 and the light emission control device 11 to cooperatively control the image sensor 3 and the light emission device 4.

  Next, the image sensor 3 of this embodiment will be described. FIG. 2 is an overview diagram showing a schematic configuration of the image sensor 3 according to the present embodiment. In FIG. 2, the image sensor 3 includes a pixel chip 31, a pixel signal processing chip 32, a chip connection unit 33, and an external wiring connection unit 34.

The pixel chip 31 is a chip in which pixels including a photoelectric conversion unit, which will be described later, are two-dimensionally arranged and converts incident subject light into an electrical signal. The pixel chip 31 is driven and controlled by a signal transmitted from the pixel signal processing chip 32. Then, the pixel chip 31 transmits the converted electric signal to the pixel signal processing chip 32.
The pixel signal processing chip 32 is a chip that performs temporary storage of the electrical signal transmitted from the pixel chip 31 and processing such as simple calculation on the electrical signal. The pixel signal processing chip 32 transmits a signal for driving and controlling the pixel chip 31 to the pixel chip 31.

  The chip connection unit 33 is a connection unit for electrically connecting the pixel chip 31 and the pixel signal processing chip 32. For the chip connection portion 33, for example, bumps produced by vapor deposition or plating are used. Note that the space existing between the pixel chip 31 and the pixel signal processing chip 32 may be filled with an insulating member such as an adhesive. The pixel chip 31 and the pixel signal processing chip 32 transmit and receive signals via the chip connection unit 33.

  The external wiring connection part 34 is a connection part for electrically connecting the image sensor 3 and another block. The input / output signals of the image sensor 3 are transmitted / received to / from other components (blocks) in the digital camera 1 via the external wiring connection unit 34. For example, a configuration in which a package (not shown) for protecting the image sensor 3 and the external wiring connection portion 34 are connected by a wire and input / output signals of the image sensor 3 are transmitted / received outside the package is conceivable.

  In the image sensor 3 of the present embodiment, global exposure for simultaneously exposing all the pixels in the pixel chip 31 is performed, and an electrical signal obtained by converting incident subject light is transmitted to the pixel signal processing chip 32. The pixel signal processing chip 32 temporarily stores the electrical signal transmitted from the pixel chip 31 and sequentially outputs the electrical signal from the external wiring connection unit 34 to the outside of the image sensor 3.

  Next, the pixel chip 31 of this embodiment will be described. FIG. 3 is a circuit diagram showing a schematic configuration of the pixel chip 31 in the image sensor 3 of the present embodiment. In FIG. 3, a pixel chip 31 includes a pixel chip vertical scanning circuit 311, a pixel array unit 312, a unit pixel 313, a pixel signal line 314, a pixel chip vertical scanning circuit signal line 315, a first pixel reset line 316, and a first pixel transfer. The line 317 includes a first pixel selection line 318, a second pixel reset line 319, a second pixel transfer line 3110, a second pixel selection line 3111, and an FD reset line 3112. In the pixel chip 31 illustrated in FIG. 3, an example of a pixel array unit 312 in which a plurality of unit pixels 313 are two-dimensionally arranged in 10 rows and 10 columns is illustrated. With the configuration of the pixel chip 31, an operation is performed at a readout timing described later.

  In the pixel chip 31 shown in FIG. 3, the numbers and symbols in “(): parentheses” shown after each symbol are a row number and a column number corresponding to the unit pixel 313 arranged in the pixel chip 31. Represents. The first number in “(): brackets” indicates the row number, and the last number indicates the column number. For example, the unit pixel 313 in the second row and the third column is represented as a unit pixel 313 (2, 3). In addition, when only one of the row number or column number, that is, the same row number or column number is represented, the same row number or column number is represented by a number, and the non-identical row number or column number is designated as “ *: Represented by an asterisk. For example, the first pixel reset line 316 in the third row is represented as a first pixel reset line 316 (3, *). Further, when both the row number and the column number are not specified, “(): parenthesis” after each code is not written.

  The pixel chip vertical scanning circuit 311 controls each unit pixel 313 in the pixel array unit 312 and outputs a pixel signal of each unit pixel 313 to the pixel signal line 314. The pixel chip vertical scanning circuit 311 includes control signal lines (first pixel reset line 316, first pixel transfer line 317, first pixel selection line 318, second pixel reset line 319, second pixel transfer line 3110, second pixel. A control signal for controlling the unit pixel 313 is output to the selection line 3111 and the FD reset line 3112) for each row of the unit pixels 313 arranged in the pixel array unit 312.

Each unit pixel 313 in the pixel array unit 312 outputs a reset signal when reset and an electric signal corresponding to the amount of received light of the subject light to the pixel signal line 314 as a pixel signal.
The pixel signal line 314 and the pixel chip vertical scanning circuit signal line 315 are connected to the pixel signal processing chip 32 via the chip connection unit 33. The pixel chip 31 and the pixel signal processing chip 32 include various signals necessary for driving and controlling the pixel chip 31 and each unit pixel in the pixel chip 31 through the pixel signal line 314 and the pixel chip vertical scanning circuit signal line 315. The pixel signal output from 313 is transmitted and received.

  Next, the pixel signal processing chip 32 of this embodiment will be described. FIG. 4 is a circuit diagram showing a schematic configuration of the pixel signal processing chip 32 in the image sensor 3 of the present embodiment. In FIG. 4, a pixel signal processing chip 32 includes a pixel signal processing chip vertical scanning circuit 321, a pixel memory array unit 322, a unit pixel memory 323, a pixel memory signal line 324, a pixel signal processing chip vertical signal line 325, and a pixel signal processing chip. Column processing circuit 326, pixel signal processing chip horizontal scanning circuit 327, pixel signal processing chip horizontal scanning circuit signal line 328, image sensor control circuit 329, image sensor control circuit signal line 3210, first pixel memory reset line 3211, first pixel A memory transfer line 3212, a first pixel memory selection line 3213, a second pixel memory reset line 3214, a second pixel memory transfer line 3215, and a second pixel memory selection line 3216 are configured. In the pixel signal processing chip 32 illustrated in FIG. 4, an example of a pixel memory array unit 322 in which a plurality of unit pixel memories 323 are two-dimensionally arranged in 10 rows and 10 columns is illustrated. With the configuration of the pixel signal processing chip 32, an operation at a readout timing described later is performed.

  In the pixel signal processing chip 32 shown in FIG. 4, numbers and symbols in “(): parentheses” shown after each symbol correspond to the unit pixel memory 323 arranged in the pixel signal processing chip 32. The row number and the column number are represented, and the way of representing them is the same as that of the pixel chip 31 shown in FIG.

  The pixel signal processing chip vertical scanning circuit 321 controls each unit pixel memory 323 in the pixel memory array unit 322 and outputs a pixel memory signal of each unit pixel memory 323 to the pixel signal processing chip vertical signal line 325. The pixel signal processing chip vertical scanning circuit 321 includes control signal lines (first pixel memory reset line 3211, first pixel memory transfer line 3212, first pixel memory selection line 3213, second pixel memory reset line 3214, and second pixel memory. A control signal for controlling the unit pixel memory 323 is output to the transfer line 3215 and the second pixel memory selection line 3216) for each row of the unit pixel memory 323 arranged in the pixel memory array unit 322.

  Each unit pixel memory 323 in the pixel memory array unit 322 is transmitted from each unit pixel 313 in the pixel array unit 312 provided in the pixel chip 31 to the pixel memory signal line 324 through the chip connection unit 33. A pixel signal is input. Each unit pixel memory 323 outputs an electrical signal corresponding to the input pixel signal to the pixel signal processing chip vertical signal line 325 as a pixel memory signal.

  The pixel signal processing chip column processing circuit 326 performs processing on the pixel memory signal transmitted from the unit pixel memory 323. In the pixel signal processing by the pixel signal processing chip column processing circuit 326, signal subtraction (difference processing) is performed based on the clamp pulse ΦCL and the sample hold pulse ΦSH input from the image sensor control circuit 329. Further, processing by the pixel signal processing chip column processing circuit 326 includes processing such as signal amplification and comparison. The pixel signal processing chip column processing circuit 326 includes a current source load connected to the pixel signal processing chip vertical signal line 325.

The pixel signal processing chip horizontal scanning circuit 327 sequentially reads out the processed signals output from the pixel signal processing chip column processing circuit 326 based on the horizontal scanning pulse ΦH input from the image sensor control circuit 329.
The image sensor control circuit 329 controls the pixel signal processing chip vertical scanning circuit 321, the pixel signal processing chip column processing circuit 326, the pixel signal processing chip horizontal scanning circuit 327, and the pixel chip vertical scanning circuit 311 in the pixel chip 31.

  The pixel memory signal line 324 and the image sensor control circuit signal line 3210 are connected to the pixel chip 31 via the chip connection unit 33. The pixel chip 31 and the pixel signal processing chip 32 include various signals necessary for driving and controlling the pixel chip 31 and each unit pixel in the pixel chip 31 through the pixel memory signal line 324 and the image sensor control circuit signal line 3210. The pixel signal output from 313 is transmitted and received.

  The image sensor 3 is controlled by the image sensor control circuit 329, the pixel signal processing chip vertical scanning circuit 321, the pixel signal processing chip column processing circuit 326, the pixel signal processing chip horizontal scanning circuit 327, and the pixel chip vertical scanning circuit 311. An image signal of incident subject light is output.

  Next, the unit pixel 313 of this embodiment will be described. FIG. 5 is a circuit diagram showing a schematic configuration of the unit pixel 313 in the pixel chip 31 provided in the image sensor 3 of the present embodiment. The unit pixel 313 is a circuit that converts incident light into an electrical signal and outputs it to the pixel signal line 314. The unit pixel 313 includes a first photodiode PD1, a first pixel transfer transistor PM1, a first pixel reset transistor PM2, a first pixel selection transistor PM3, a first pixel charge storage unit PC1, a second photodiode PD2, and a second photodiode PD, respectively. The pixel transfer transistor PM6, the second pixel reset transistor PM7, the second pixel selection transistor PM8, the second pixel charge accumulation unit PC2, the unit pixel amplification transistor PM5, the unit pixel charge accumulation unit FD, and the unit pixel reset transistor PM4.

  The unit pixel charge storage unit FD is a capacitor associated with a node connected to the gate terminal of the unit pixel amplification transistor PM5, and is indicated by a capacitor symbol in the schematic configuration of the unit pixel 313 shown in FIG.

The first photodiode PD1 and the second photodiode PD2 are photoelectric conversion units that photoelectrically convert incident light to generate signal charges.
The first pixel charge accumulation unit PC1, the second pixel charge accumulation unit PC2, and the unit pixel charge accumulation unit FD are capacitors that accumulate signal charges.

The first pixel reset transistor PM2 resets the first photodiode PD1 to the power supply potential VDDP based on the first pixel reset pulse ΦPR1 input from the pixel chip vertical scanning circuit 311.
The second pixel reset transistor PM7 resets the second photodiode PD2 to the power supply potential VDDP based on the second pixel reset pulse ΦPR2 input from the pixel chip vertical scanning circuit 311.

The first pixel transfer transistor PM1 transfers the signal charge generated by the first photodiode PD1 to the first pixel charge storage unit PC1 based on the first pixel transfer pulse ΦPT1 input from the pixel chip vertical scanning circuit 311. . The signal charge transferred by the first pixel transfer transistor PM1 is stored in the first pixel charge storage unit PC1.
The second pixel transfer transistor PM6 transfers the signal charge generated by the second photodiode PD2 to the second pixel charge storage unit PC2 based on the second pixel transfer pulse ΦPT2 input from the pixel chip vertical scanning circuit 311. . The signal charge transferred by the second pixel transfer transistor PM6 is stored in the second pixel charge storage portion PC2.

The first pixel selection transistor PM3 converts the signal charge accumulated in the first pixel charge accumulation unit PC1 based on the first pixel selection pulse ΦPS1 input from the pixel chip vertical scanning circuit 311 to the gate of the unit pixel amplification transistor PM5. The data is transferred to the unit pixel charge storage portion FD connected to the terminal. The signal charge transferred by the first pixel selection transistor PM3 is accumulated in the unit pixel charge accumulation unit FD.
The second pixel selection transistor PM8 converts the signal charge accumulated in the second pixel charge accumulation unit PC2 based on the second pixel selection pulse ΦPS2 input from the pixel chip vertical scanning circuit 311 to the gate of the unit pixel amplification transistor PM5. The data is transferred to the unit pixel charge storage portion FD connected to the terminal. The signal charge transferred by the second pixel selection transistor PM8 is accumulated in the unit pixel charge accumulation unit FD.

  The unit pixel reset transistor PM4 resets the unit pixel charge storage unit FD to the power supply potential VDDP based on the FD reset pulse ΦFR input from the pixel chip vertical scanning circuit 311.

  The unit pixel amplification transistor PM5 outputs a voltage corresponding to the signal charge accumulated in the unit pixel charge accumulation unit FD. The unit pixel amplification transistor PM5 uses the voltage corresponding to the signal charge transferred to the unit pixel charge storage unit FD by the first pixel selection transistor PM3 as the output of the unit pixel 313 by the signal charge generated by the first photodiode PD1. Output to the pixel signal line 314. The unit pixel amplification transistor PM5 outputs a voltage corresponding to the signal charge transferred to the unit pixel charge storage unit FD by the second pixel selection transistor PM8, and outputs the unit pixel 313 by the signal charge generated by the second photodiode PD2. Is output to the pixel signal line 314.

  The pixel signal line 314 is connected to the chip connection unit 33. With such a configuration, the unit pixel 313 has a configuration in which one photoelectric conversion unit (the first photodiode PD1 and the second photodiode PD2) shares one chip connection unit 33.

  Next, the unit pixel memory 323 of this embodiment will be described. FIG. 6 is a circuit diagram showing a schematic configuration of the unit pixel memory 323 in the pixel signal processing chip 32 provided in the image sensor 3 of the present embodiment. The unit pixel memory 323 is a circuit that holds a signal input from the pixel memory signal line 324 and outputs the signal to the pixel signal processing chip vertical signal line 325. The unit pixel memory 323 includes a unit pixel memory coupling capacitor CC, a first pixel memory charge accumulation unit MC1, a first pixel memory transfer transistor MM1, a first pixel memory reset transistor MM2, a first pixel memory amplification transistor MM3, and a first pixel memory charge transistor MC1. Pixel memory selection transistor MM4, second pixel memory charge storage unit MC2, second pixel memory transfer transistor MM5, second pixel memory reset transistor MM6, second pixel memory amplification transistor MM7, second pixel memory selection transistor MM8, unit pixel memory It consists of a current load CS.

The unit pixel memory coupling capacitor CC is a coupling capacitor in which one is connected to the chip connection unit 33 and the other is connected to the source terminals of the first pixel memory transfer transistor MM1 and the second pixel memory transfer transistor MM5.
The first pixel memory charge storage unit MC1 and the second pixel memory charge storage unit MC2 are capacitive loads that store signal charges. The first pixel memory charge storage unit MC1 stores signal charges corresponding to the first photodiode PD1 in the unit pixel 313, and the second pixel memory charge storage unit MC2 stores in the second photodiode PD2 in the unit pixel 313. Stores the corresponding signal charge.

The first pixel memory transfer transistor MM1 converts the signal charge generated in one of the unit pixel memory coupling capacitors CC based on the first pixel memory transfer pulse ΦMT1 input from the pixel signal processing chip vertical scanning circuit 321 to the first pixel. The data is transferred to the first pixel memory charge storage unit MC1 connected to the gate terminal of the memory amplification transistor MM3. The signal charge transferred by the first pixel memory transfer transistor MM1 is stored in the first pixel memory charge storage unit MC1.
The second pixel memory transfer transistor MM5 converts the signal charge generated in one of the unit pixel memory coupling capacitors CC based on the second pixel memory transfer pulse ΦMT2 input from the pixel signal processing chip vertical scanning circuit 321 to the second pixel. The data is transferred to the second pixel memory charge storage portion MC2 connected to the gate terminal of the memory amplification transistor MM7. The signal charge transferred by the second pixel memory transfer transistor MM5 is stored in the second pixel memory charge storage unit MC2.

The first pixel memory amplification transistor MM3 outputs a voltage corresponding to the signal charge accumulated in the first pixel memory charge accumulation unit MC1.
The second pixel memory amplification transistor MM7 outputs a voltage corresponding to the signal charge accumulated in the second pixel memory charge accumulation unit MC2.

The first pixel memory reset transistor MM2 resets the first pixel memory charge accumulation unit MC1 to the power supply potential VDDM based on the first pixel memory reset pulse ΦMR1 input from the pixel signal processing chip vertical scanning circuit 321.
The second pixel memory reset transistor MM6 resets the second pixel memory charge accumulation unit MC2 to the power supply potential VDDM based on the second pixel memory reset pulse ΦMR2 input from the pixel signal processing chip vertical scanning circuit 321.

The first pixel memory selection transistor MM4 outputs the voltage output from the first pixel memory amplification transistor MM3 based on the first pixel memory selection pulse ΦMS1 input from the pixel signal processing chip vertical scanning circuit 321 to the unit pixel memory 323. The output is output to the pixel signal processing chip vertical signal line 325.
The second pixel memory selection transistor MM8 outputs the voltage output from the second pixel memory amplification transistor MM7 based on the second pixel memory selection pulse ΦMS2 input from the pixel signal processing chip vertical scanning circuit 321 to the unit pixel memory 323. The output is output to the pixel signal processing chip vertical signal line 325.

  One of the unit pixel memory current loads CS is connected to the pixel memory signal line 324, and the other is connected to the ground of the pixel signal processing chip 32. The unit pixel memory current load CS drives the signal line connected to the chip connection unit 33 with a constant current. The unit pixel memory current load CS may be configured such that one is connected to the pixel signal line 314 of the pixel chip 31 and the other is connected to the ground of the pixel chip 31.

  The pixel memory signal line 324 is connected to the chip connection unit 33. With such a configuration, the unit pixel memory 323 is configured to share one chip connection unit 33 with two pixel memories (the first pixel memory charge storage unit MC1 and the second pixel memory charge storage unit MC2). Yes.

  In the image sensor 3 of the present embodiment, global exposure is performed in which all the unit pixels 313 in the pixel chip 31 are exposed simultaneously, and a signal generated according to subject light incident on the first photodiode PD1 and the second photodiode PD2. A pixel signal based on the charge is output to the pixel signal processing chip 32 via the chip connection unit 33. The pixel signal processing chip 32 temporarily stores the corresponding pixel signals of the first photodiode PD1 and the second photodiode PD2 input from the pixel chip 31, performs processing such as differential processing, and sequentially Output.

  2 to 4, the image sensor 3 includes each unit pixel 313 in the pixel array unit 312 and each unit pixel memory 323 in the pixel memory array unit 322. Are connected via the chip connecting portion 33. 5 and FIG. 6, in the unit pixel 313, two photodiodes share one chip connection unit 33, and the unit pixel memory 323 includes two pixel memories in one chip connection unit 33. Is configured to share. That is, the image sensor 3 is configured to include one chip connection unit 33 for every two pixels. However, the configuration of the image sensor 3 is not limited to the configuration of the image sensor 3 illustrated in FIGS. 2 to 6, and one chip connection portion 33 is shared by two or more photodiodes or pixel memories. It can also be configured.

  Next, a driving sequence of the image sensor 3 of the present embodiment will be described. FIG. 7 is a sequence diagram showing a sequence for driving the image sensor 3 of the present embodiment. Note that the sequence diagram shown in FIG. 7 shows a sequence when the unit pixels 313 and the unit pixel memories 323 for 10 rows are processed in succession. In the image sensor 3 of the present embodiment, as shown in FIGS. 2 to 6, one unit pixel 313 includes two photodiodes, and one unit pixel memory 323 includes two pixel memories. For this reason, the sequence diagram shown in FIG. 7 is a sequence in the case of processing 20 rows of the image sensor 3 continuously.

  In actual operation, the number of rows of photodiodes and pixel memories to be processed continuously, the number of rows of photodiodes and pixel memories, depending on parameters of the image sensor 3, such as the number of pixels and a thinning rate in thinning readout. The number of thinning out changes. As a result, when the unit pixel 313 and the unit pixel memory 323 continuously arranged in the column direction are not processed continuously, one of the two photodiodes in the unit pixel 313, and the unit Only one of the pixel memories in the pixel memory 323 may be processed.

  In FIG. 7, the horizontal axis indicates time, and the vertical axis indicates the row of the image sensor 3. A sequence 201 indicates a global reset operation of the pixel chip 31, and a sequence 202 indicates a global transfer operation of the pixel chip 31. A sequence 203 indicates a rolling read operation of the pixel chip 31, and a sequence 204 indicates a rolling read operation of the pixel signal processing chip 32.

  In the driving sequence of the image sensor 3, first, the global reset operation of the pixel chip 31 shown in the sequence 201 is performed at time t1. In the global reset operation of the sequence 201, the first photodiode PD1 and the second photodiode PD2 in all the unit pixels 313 included in the pixel chip 31, the first pixel charge accumulation unit PC1, the second pixel charge accumulation unit PC2, And the unit pixel charge storage portion FD are simultaneously reset.

  Subsequently, when a predetermined exposure time has elapsed, the global transfer operation of the pixel chip 31 shown in the sequence 202 is performed at time t2. In the global transfer operation of the sequence 202, the signal charge generated by the first photodiode PD1 in all the unit pixels 313 is transferred to the first pixel charge storage unit PC1 and the signal charge generated by the second photodiode PD2 is transferred to the second pixel charge storage unit PC1. Transfer to the pixel charge storage unit PC2 at the same time.

  A period from time t1 to time t2 shown in FIG. 7 is an exposure period in the global exposure of the image sensor 3. Further, the global exposure method has an advantage that a distorted image is not obtained by the global reset operation of the sequence 201 and the global transfer operation of the sequence 202.

  Subsequently, from time t2 to time t4, the rolling readout operation of the pixel chip 31 shown in the sequence 203 is performed. In the image sensor 3 of the present embodiment, as shown in FIG. 5, the unit pixel 313 includes two photodiodes. Therefore, in the rolling readout operation of the sequence 203, first, the signal charge generated by the first photodiode PD1 transferred to the first pixel charge storage unit PC1 by the global transfer operation of the sequence 202 during the period from the time t2 to the time t3. , Transfer to the unit pixel charge storage portion FD. As a result, an output based on the signal charge generated by the first photodiode PD1 is output from the unit pixel 313 to the pixel signal line 314 and input to the pixel memory signal line 324 of the unit pixel memory 323 via the chip connection unit 33. The Then, the output of the signal charge generated by the first photodiode PD1 input to the pixel memory signal line 324 is stored in the first pixel memory charge storage portion MC1.

  In the period from time t3 to time t4, the signal charge generated by the second photodiode PD2 transferred to the second pixel charge storage unit PC2 by the global transfer operation of the sequence 202 is transferred to the unit pixel charge storage unit FD. . As a result, an output based on the signal charge generated by the second photodiode PD2 is output from the unit pixel 313 to the pixel signal line 314 and input to the pixel memory signal line 324 of the unit pixel memory 323 via the chip connection unit 33. The Then, the output of the signal charge generated by the second photodiode PD2 input to the pixel memory signal line 324 is stored in the second pixel memory charge storage portion MC2.

  In this manner, in the rolling readout operation, the output due to the signal charge generated by the photodiode provided in the unit pixel 313 is sequentially transmitted to the unit pixel memory 323 via the chip connection unit 33. Then, the signal transmitted from the unit pixel 313 is sequentially held in the corresponding pixel memory provided in the unit pixel memory 323.

  Subsequently, from time t4 to time t5, the rolling readout operation of the pixel signal processing chip 32 shown in the sequence 204 is performed. In the rolling read operation of sequence 204, the first photodiode PD1 and the second photodiode PD2 stored in the first pixel memory charge storage portion MC1 and the second pixel memory charge storage portion MC2 by the rolling read operation of sequence 203 are Outputs due to the generated signal charges are sequentially read out.

  Next, the drive timing of the image sensor 3 of this embodiment will be described. FIG. 8 is a timing chart showing the timing of each drive of the image sensor 3 of the present embodiment. Note that the timing chart shown in FIG. 8 shows the timing when the unit pixel 313 and the unit pixel memory 323 for one row are processed. In the image sensor 3 of the present embodiment, as shown in FIGS. 2 to 6, one unit pixel 313 includes two photodiodes, and one unit pixel memory 323 includes two pixel memories. For this reason, the timing chart shown in FIG. 8 is a timing at which two rows of the image sensor 3 are processed continuously.

  In actual operation, the number of rows of photodiodes and pixel memories to be processed continuously, the number of rows of photodiodes and pixel memories, depending on parameters of the image sensor 3, such as the number of pixels and a thinning rate in thinning readout. The number of thinning out changes. As a result, when the unit pixel 313 and the unit pixel memory 323 continuously arranged in the column direction are not processed continuously, one of the two photodiodes in the unit pixel 313, and the unit Only one of the pixel memories in the pixel memory 323 may be processed.

  The control pulses (first pixel reset pulse ΦPR1, first pixel transfer pulse ΦPT1, first pixel selection pulse ΦPS1, second pixel reset) output from the pixel chip vertical scanning circuit 311 and the pixel signal processing chip vertical scanning circuit 321 are also described. Pulse ΦPR2, 2 pixel transfer pulse ΦPT2, second pixel selection pulse ΦPS2, FD reset pulse ΦFR, first pixel memory transfer pulse ΦMT1, first pixel memory reset pulse ΦMR1, first pixel memory selection pulse ΦMS1, second pixel memory transfer The timing of the pulse ΦMT2, the second pixel memory reset pulse ΦMR2, and the second pixel memory selection pulse ΦMS2) can be changed according to the driving method.

  Further, in the timing chart shown in FIG. 8, only control pulses for one unit pixel 313 and unit pixel memory 323 are shown for easy explanation. In the configuration of the image sensor 3 of the present embodiment shown in FIGS. 2 to 6, each of the unit pixels 313 in the pixel array unit 312 and each of the unit pixel memories 323 in the pixel memory array unit 322 are respectively They are connected via the respective chip connection portions 33. Therefore, for example, when the digital camera 1 performs global exposure in which all pixels are exposed simultaneously, a control pulse from time t1 to time t7 described later is output to all the pixel array units 312 and the pixel memory array units 322. Therefore, all are controlled at the same time. Therefore, in the following description, regarding the operations common to all the rows, “(): parentheses” after each symbol is not written, and only “(): The parentheses are indicated.

In the timing chart shown in FIG. 8, the PC1 potential V _PC1 indicates the potential of the first pixel charge storage portion PC1, and the PC2 potential V _PC2 indicates the potential of the second pixel charge storage portion PC2. The FD potential V _FD indicates the potential of the unit pixel charge accumulation unit FD. The MC1 potential V _MC1 indicates the potential of the first pixel memory charge storage portion MC1, and the MC2 potential V _MC2 indicates the potential of the second pixel memory charge storage portion MC2.

The power supply potential VDDP and the power supply potential VDDM indicate the power supply potentials of the pixel chip 31 and the pixel signal processing chip 32, respectively. The PC1 signal potential V _PC1SIG indicates a subject-dependent signal potential in the first pixel charge storage unit PC1 obtained by a signal transferred from the first photodiode PD1. The PC2 signal potential V _PC2SIG indicates a subject-dependent signal potential in the second pixel charge storage portion PC2 obtained by a signal transferred from the second photodiode PD2. The first FD signal potential V _FDSIG1 indicates the potential of the signal depending on the subject in the unit pixel charge storage unit FD obtained by the signal transferred from the first pixel charge storage unit PC1. The second FD signal potential V _FDSIG2 indicates the potential of the signal depending on the subject in the unit pixel charge storage unit FD obtained by the signal transferred from the second pixel charge storage unit PC2. The MC1 signal potential V _MC1SIG indicates a subject-dependent signal potential in the first pixel memory charge storage portion MC1 obtained by a signal transferred from the first pixel charge storage portion PC1. The MC2 signal potential V _MC2SIG indicates a subject-dependent signal potential in the second pixel memory charge storage unit MC2 obtained by a signal transferred from the second pixel charge storage unit PC2.

First, at time t1, a global reset operation is performed to reset all the unit pixels 313 in the pixel array unit 312. More specifically, at time t1, the pixel chip vertical scanning circuit 311 sets the first pixel reset pulse ΦPR1, the first pixel transfer pulse ΦPT1, and the first pixel selection pulse ΦPS1 to the “High” level. The first pixel reset transistor PM2, the first pixel transfer transistor PM1, and the first pixel selection transistor PM3 of the pixel 313 are turned on. Thus, the first photodiode PD1 and the first pixel charge accumulation unit PC1 is reset, PC1 potential _{V PC1} becomes the potential of the power supply potential VDDP.

At time t1, the pixel chip vertical scanning circuit 311 sets the second pixel reset pulse ΦPR2, the second pixel transfer pulse ΦPT2, and the second pixel selection pulse ΦPS2 to the “High” level, so that the unit pixel 313 The two-pixel reset transistor PM7, the second pixel transfer transistor PM6, and the second pixel selection transistor PM8 are turned on. Thus, the second photodiode PD2 and the second pixel charge accumulation unit PC2 is reset, PC2 potential _{V PC2} becomes the potential of the power supply potential VDDP.

Further, at time t1, the pixel chip vertical scanning circuit 311 sets the unit pixel reset transistor PM4 of the unit pixel 313 to the ON state by setting the FD reset pulse ΦFR to the “High” level. As a result, the unit pixel charge storage portion FD is reset, and the FD potential V _FD becomes the potential of the power supply potential VDDP.

  Thereafter, the pixel chip vertical scanning circuit 311 includes a first pixel reset pulse ΦPR1, a first pixel transfer pulse ΦPT1, a first pixel selection pulse ΦPS1, a second pixel reset pulse ΦPR2, a second pixel transfer pulse ΦPT2, and a second pixel selection pulse. By resetting ΦPS2 and the FD reset pulse ΦFR to the “Low” level, the reset of the unit pixel 313 is released. Thereby, all the unit pixels 313 in the pixel array unit 312 start global exposure simultaneously.

Subsequently, after the exposure period in the global exposure has elapsed, a global transfer operation is performed at time t2, and the signal charges generated by the photodiodes of all the unit pixels 313 in the pixel array unit 312 are transferred to the corresponding pixel charge storage units. Forward. More specifically, at time t2, the pixel chip vertical scanning circuit 311 sets the first pixel transfer pulse ΦPT1 and the second pixel transfer pulse ΦPT2 to the “High” level, whereby the first pixel transfer transistor of the unit pixel 313 is set. PM1 and the second pixel transfer transistor PM6 are turned on. As a result, the signal charges generated by the first photodiode PD1 and the second photodiode PD2 in the unit pixel 313 during the period from the time t1 to the time t2 are converted into the first pixel charge accumulation unit PC1 and the second pixel charge accumulation unit PC2, respectively. Forwarded to This global transfer operation, PC1 potential _{V PC1} is first photodiode PD1 is based on the signal charges generated, the potential of the PC1 signal potential _{V PC1SIG.} Further, the PC2 potential V _PC2 becomes a PC2 signal potential V _PC2SIG potential based on the signal charge generated by the second photodiode PD2.

Subsequently, the rolling readout operation of the pixel chip 31 is performed from time t3, and the signal charges generated by the photodiodes of all the unit pixels 313 in the pixel array unit 312 are sequentially converted into corresponding units in the pixel signal processing chip 32. Transmit to the pixel memory 323. More specifically, first, at time t3, the pixel chip vertical scanning circuit 311 sets the unit pixel reset transistor PM4 of the unit pixel 313 to the ON state by setting the FD reset pulse ΦFR to the “High” level. As a result, the unit pixel charge storage portion FD is reset, and the FD potential V _FD becomes the potential of the power supply potential VDDP.

At time t3, the pixel signal processing chip vertical scanning circuit 321 sets the first pixel memory reset pulse ΦMR1 and the first pixel memory transfer pulse ΦMT1 to the “High” level, so that the first pixel memory of the unit pixel memory 323 is set. The reset transistor MM2 and the first pixel memory transfer transistor MM1 are turned on. As a result, the first pixel memory charge storage portion MC1 is reset, and the MC1 potential _VMC1 becomes the power supply potential VDDM. Further, the first pixel memory charge storage part MC1 and the unit pixel memory coupling capacitor CC are electrically connected.

Subsequently, at time t4, the pixel chip vertical scanning circuit 311 sets the first pixel selection pulse ΦPS1 to the “High” level, thereby turning on the first pixel selection transistor PM3 of the unit pixel 313. Thereby, the signal charge accumulated in the first pixel charge accumulation unit PC1 is transferred to the unit pixel charge accumulation unit FD for transfer, and the FD potential V _FD is set to the potential of the PC1 potential V _PC1 (PC1 signal potential V _PC1SIG ). The corresponding first FD signal potential V _FDSIG1 is obtained. Then, a voltage corresponding to the first FD signal potential V _FDSIG1 is output from the unit pixel amplification transistor PM5 to the pixel signal line 314.

Further, at time t4, the pixel signal processing chip vertical scanning circuit 321 sets the first pixel memory reset pulse ΦMR1 to the “Low” level, thereby turning off the first pixel memory reset transistor MM2. As a result, the first pixel memory charge storage unit MC1 is released from the reset state, and the MC1 potential V _MC1 is a unit corresponding to the first FD signal potential V _FDSIG1 input to the pixel memory signal line 324 via the chip connection unit 33. The MC1 signal potential _VMC1SIG is based on the signal charge generated by the pixel memory coupling capacitor CC.

Subsequently, at time t5, the pixel signal processing chip vertical scanning circuit 321 sets the first pixel memory transfer pulse ΦMT1 to the “Low” level, thereby turning off the first pixel memory transfer transistor MM1. As a result, the first pixel memory charge storage portion MC1 and the unit pixel memory coupling capacitor CC are electrically disconnected, and the MC1 potential V _MC1 is held at the MC1 signal potential V _MC1SIG .

  Thus far, transmission of the signal charge accumulated in the first pixel charge accumulation unit PC1 to the first pixel memory charge accumulation unit MC1 is completed. In the image sensor 3 of the present embodiment, as shown in FIG. 5, the unit pixel 313 includes two photodiodes. Accordingly, in the rolling readout operation of the pixel chip 31, the signal charge accumulated in the first pixel charge accumulation unit PC1 is accumulated in the second pixel charge accumulation unit PC2 following transmission to the first pixel memory charge accumulation unit MC1. The signal charge is transmitted to the second pixel memory charge accumulation unit MC2.

At time t5, the pixel chip vertical scanning circuit 311 sets the unit pixel reset transistor PM4 of the unit pixel 313 to the ON state by setting the FD reset pulse ΦFR to the “High” level. As a result, the unit pixel charge storage portion FD is reset, and the FD potential V _FD becomes the potential of the power supply potential VDDP.

At time t5, the pixel signal processing chip vertical scanning circuit 321 sets the second pixel memory reset pulse ΦMR2 and the second pixel memory transfer pulse ΦMT2 to the “High” level, so that the second pixel memory of the unit pixel memory 323 is set. The reset transistor MM6 and the second pixel memory transfer transistor MM5 are turned on. As a result, the second pixel memory charge storage portion MC2 is reset, and the MC2 potential _VMC2 becomes the power supply potential VDDM. Further, the second pixel memory charge storage part MC2 and the unit pixel memory coupling capacitor CC are electrically connected.

Subsequently, at time t6, the pixel chip vertical scanning circuit 311 sets the second pixel selection pulse ΦPS2 to the “High” level, thereby turning on the second pixel selection transistor PM8 of the unit pixel 313. Thereby, the signal charge accumulated in the second pixel charge accumulation unit PC2 is transferred to the unit pixel charge accumulation unit FD for transfer, and the FD potential V _FD is set to the potential of the PC2 potential V _PC2 (PC2 signal potential V _PC2SIG ). The corresponding second FD signal potential V _FDSIG2 is obtained. Then, a voltage corresponding to the second FD signal potential V _FDSIG2 is output from the unit pixel amplification transistor PM5 to the pixel signal line 314.

At time t6, the pixel signal processing chip vertical scanning circuit 321 sets the second pixel memory reset pulse ΦMR2 to the “Low” level, thereby turning off the second pixel memory reset transistor MM6. As a result, the second pixel memory charge accumulating unit MC2 is released from the reset state, and the MC2 potential V _MC2 is a unit corresponding to the second FD signal potential V _FDSIG2 input to the pixel memory signal line 324 via the chip connection unit 33. The MC2 signal potential _VMC2SIG is based on the signal charge generated by the pixel memory coupling capacitor CC.

Subsequently, at time t7, the pixel signal processing chip vertical scanning circuit 321 sets the second pixel memory transfer pulse ΦMT2 to the “Low” level, thereby turning off the second pixel memory transfer transistor MM5. As a result, the second pixel memory charge storage portion MC2 and the unit pixel memory coupling capacitor CC are electrically disconnected, and the MC2 potential V _MC2 is held at the MC2 signal potential V _MC2SIG .

  Thus far, transmission of the signal charge accumulated in the second pixel charge accumulation unit PC2 to the second pixel memory charge accumulation unit MC2 is completed. When more unit photodiodes are provided in the unit pixel 313, similarly, transmission of signal charges accumulated in other (remaining) pixel charge accumulation units to the pixel memory charge accumulation unit is continued. Do it.

Thereafter, the pixel signal processing chip vertical scanning circuit 321 performs the rolling readout operation of the pixel signal processing chip 32, and sequentially applies the signal charges held in the pixel memories of all the unit pixel memories 323 in the pixel memory array unit 322. And output to the corresponding pixel signal processing chip column processing circuit 326 in the pixel signal processing chip 32. More specifically, first, at time t7, the pixel signal processing chip vertical scanning circuit 321 sets the first pixel memory selection pulse ΦMS1 to the “High” level, so that the first pixel memory selection transistor of the unit pixel memory 323 is set. Turn on MM4. As a result, a voltage corresponding to the MC1 signal potential _VMC1SIG stored in the first pixel memory charge storage unit MC1 is output to the pixel signal processing chip vertical signal line 325.

In the period from time t7 to time t8, the image sensor control circuit 329 repeatedly inputs the “high” level and the “low” level of the horizontal scanning pulse ΦH to the pixel signal processing chip horizontal scanning circuit 327. As a result, the signal corresponding to the MC1 signal potential V _MC1SIG processed by the pixel signal processing chip column processing circuit 326 is used as the image signal of the first row output from the image sensor 3, and the pixel signal processing chip horizontal scanning circuit signal line 328 is obtained. Read sequentially.

Subsequently, at time t8, the pixel signal processing chip vertical scanning circuit 321 sets the second pixel memory selection pulse ΦMS2 to the “High” level, thereby turning on the second pixel memory selection transistor MM8 of the unit pixel memory 323. To do. As a result, a voltage corresponding to the MC2 signal potential _VMC2SIG stored in the second pixel memory charge storage unit MC2 is output to the pixel signal processing chip vertical signal line 325.

In addition, after time t8, the image sensor control circuit 329 repeatedly inputs the “high” level and the “low” level of the horizontal scanning pulse ΦH to the pixel signal processing chip horizontal scanning circuit 327. As a result, the signal corresponding to the MC2 signal potential _VMC2SIG processed by the pixel signal processing chip column processing circuit 326 is used as the second row image signal output from the image sensor 3, and the pixel signal processing chip horizontal scanning circuit signal line 328 is obtained. Read sequentially.

  Thereafter, by controlling in the same manner as from time t7 to time t8, a signal output from all the unit pixel memories 323 and processed by the pixel signal processing chip column processing circuit 326 is used as an image signal for the third and subsequent rows. Processing chip horizontal scanning circuit signal line 328 is sequentially read. In this way, the image sensor 3 can output an image signal obtained by processing the pixel signal corresponding to the incident subject light.

  As described above, in the image sensor 3 of the present embodiment, the first pixel charge storage portion PC1 corresponding to the first photodiode PD1 and the second photodiode PD2 provided in the unit pixel 313 in the pixel chip 31, respectively. And a second pixel charge storage portion PC2. Then, the signal charges generated by the first photodiode PD1 and the second photodiode PD2 by the global exposure are respectively transferred to the corresponding first pixel charge storage portion PC1 and second pixel charge storage portion PC2 by the global transfer operation. Accumulate temporarily. As a result, even when the first photodiode PD1 and the second photodiode PD2 share one chip connection portion 33, it is possible to drive the global exposure method.

  As described above, according to the embodiment for carrying out the present invention, a plurality of charge storage units corresponding to each of a plurality of photodiodes provided in a unit pixel in a pixel chip are provided. As a result, in a solid-state imaging device configured by connecting a pixel chip and a pixel signal processing chip, a connection unit that transmits and receives electrical signals between the connected chips is shared by pixels including a plurality of photodiodes. Even in this case, it is possible to acquire a complete global exposure system image.

  In the present embodiment, the solid-state imaging device according to an aspect of the present invention corresponds to, for example, the image sensor 3, and the imaging device corresponds to, for example, the digital camera 1. In the present embodiment, the first substrate according to an aspect of the present invention corresponds to, for example, the pixel chip 31, the second substrate corresponds to, for example, the pixel signal processing chip 32, and the connection portion is For example, it corresponds to the chip connecting portion 33. Further, in the present embodiment, the pixel according to an aspect of the present invention corresponds to, for example, the pixel array unit 312 and the pixel memory array unit 322, and the pixels included in the same group include, for example, the unit pixel 313. Corresponds to the unit pixel memory 323.

  In the present embodiment, the photoelectric conversion element according to an aspect of the present invention corresponds to, for example, the first photodiode PD1 or the second photodiode PD2. In the present embodiment, the first accumulation unit according to an aspect of the present invention corresponds to, for example, the first pixel charge accumulation unit PC1 or the second pixel charge accumulation unit PC2, and the first transfer unit is For example, it corresponds to the first pixel transfer transistor PM1 or the second pixel transfer transistor PM6. In the present embodiment, the second accumulation unit according to an aspect of the present invention corresponds to, for example, the unit pixel charge accumulation unit FD, and the second transfer unit includes, for example, the first pixel selection transistor PM3 or This corresponds to the second pixel selection transistor PM8. An output unit according to an aspect of the present invention corresponds to, for example, the unit pixel memory 323 in the present embodiment.

  In the present embodiment, the third storage unit according to an aspect of the present invention corresponds to, for example, the first pixel memory charge storage unit MC1 or the second pixel memory charge storage unit MC2. The first reset unit according to an aspect of the present invention corresponds to, for example, the first pixel reset transistor PM2 or the second pixel reset transistor PM7 in the present embodiment, and the second reset unit includes, for example, This corresponds to the unit pixel reset transistor PM4. In addition, the amplifying unit according to an aspect of the present invention corresponds to, for example, the unit pixel amplifying transistor PM5 in the present embodiment.

  In the present embodiment, the noise reduction unit according to an aspect of the present invention corresponds to, for example, the unit pixel memory coupling capacitor CC and the first pixel memory transfer transistor MM1 or the second pixel memory transfer transistor MM5. In the present embodiment, the clamp unit according to an aspect of the present invention corresponds to, for example, the unit pixel memory coupling capacitor CC, and the sample hold unit includes, for example, the first pixel memory transfer transistor MM1 or the second pixel memory. This corresponds to the transfer transistor MM5.

  In the present embodiment, the first storage capacitor according to an aspect of the present invention corresponds to, for example, the first pixel charge storage unit PC1 or the second pixel charge storage unit PC2, and the first transfer transistor is For example, it corresponds to the first pixel transfer transistor PM1 or the second pixel transfer transistor PM6. In the present embodiment, the second storage capacitor according to an aspect of the present invention corresponds to, for example, the unit pixel charge storage unit FD, and the second transfer transistor is, for example, the first pixel selection transistor PM3 or This corresponds to the second pixel selection transistor PM8. Further, an output circuit according to an aspect of the present invention corresponds to, for example, the unit pixel memory 323 in the present embodiment.

  In the present embodiment, the third storage capacitor according to an aspect of the present invention corresponds to, for example, the first pixel memory charge storage unit MC1 or the second pixel memory charge storage unit MC2. In the present embodiment, the first reset transistor according to an aspect of the present invention corresponds to, for example, the first pixel reset transistor PM2 or the second pixel reset transistor PM7, and the second reset transistor is, for example, This corresponds to the unit pixel reset transistor PM4. The amplification transistor according to an aspect of the present invention corresponds to, for example, the unit pixel amplification transistor PM5 in the present embodiment.

  In the present embodiment, the noise reduction circuit according to an aspect of the present invention corresponds to, for example, the unit pixel memory coupling capacitor CC and the first pixel memory transfer transistor MM1 or the second pixel memory transfer transistor MM5. In the present embodiment, the clamp capacitor according to an aspect of the present invention corresponds to, for example, the unit pixel memory coupling capacitor CC, and the sample hold transistor is, for example, the first pixel memory transfer transistor MM1 or the second pixel memory. This corresponds to the transfer transistor MM5.

  In addition, the specific configuration of the circuit configuration and the driving method in the present invention is not limited to the mode for carrying out the present invention, and various modifications can be made without departing from the spirit of the present invention. . For example, even when the pixel components and the driving method are changed, for example, the driving method can be changed according to the components and circuit configuration in the image sensor 3 and the unit pixel 313.

  Further, the arrangement of the pixels in the row direction and the column direction is not limited to the mode for carrying out the present invention, and the number of pixels in the row direction and the column direction in which the pixels are arranged without departing from the gist of the present invention. Can be changed. Further, the number of photodiodes sharing the connection portion, that is, the number of pixels is not limited to the mode for carrying out the present invention, and the number of pixels is changed without departing from the gist of the present invention. be able to.

  As described above, the description has been given based on the embodiment for carrying out the present invention. However, any combination of each component, each processing process, and the expression of the present invention converted into a computer program product or the like is also an aspect of the present invention. It is effective as Here, the computer program product includes a recording medium (DVD medium, hard disk medium, memory medium, etc.) on which a program code is recorded, a computer on which the program code is recorded, and an Internet system (for example, a server and the like) on which the program code is recorded. A recording medium, apparatus, device or system in which a program code is recorded, such as a system including a client terminal. In this case, each component and each processing process described above are mounted in each module, and a program code including the mounted module is recorded in a computer program product.

  For example, a computer program product according to an aspect of the present invention provides a process for a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit. A computer program product in which a program code for causing a computer to execute is recorded, the solid-state imaging device includes a plurality of pixels, and each of the pixels is classified into one or more groups, A first transfer module in which a plurality of the pixels share one connection unit and transfer a signal generated by the photoelectric conversion element of the pixel arranged on the first substrate to the first storage unit And a second storage unit that transfers a signal stored in the first storage unit to a second storage unit shared by a plurality of the pixels included in the same group. A computer program product recorded with a program code including a sending module and an output module for outputting a signal accumulated in the second accumulation unit from an output unit of the pixel arranged on the second substrate. is there.

  Further, for example, a program for realizing processing by each component of the digital camera 1 shown in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system. By executing, the above-described various processes related to the digital camera 1 may be performed. Here, the “computer system” may include an OS and hardware such as peripheral devices. Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used. The “computer-readable recording medium” means a flexible disk, a magneto-optical disk, a ROM, a writable nonvolatile memory such as a flash memory, a portable medium such as a CD-ROM, a hard disk built in a computer system, etc. This is a storage device.

  Further, the “computer-readable recording medium” refers to a volatile memory (for example, DRAM (Dynamic) in a computer system serving as a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. Random Access Memory)) that holds a program for a certain period of time is also included. The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting unit. The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels Is stored in the first storage means, a photoelectric conversion element disposed on the first substrate, a first transfer means for transferring a signal generated by the photoelectric conversion element to the first storage means, and A second transfer means for transferring a signal to a second storage means shared by a plurality of the pixels included in the same group; and a signal placed on the second substrate and stored in the second storage means Output signal from the pixel And the step may be a solid-state imaging apparatus comprising: a.

  An imaging apparatus according to an aspect of the present invention is an imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging apparatus includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels are A photoelectric conversion element disposed on a first substrate, a first transfer means for transferring a signal generated by the photoelectric conversion element to a first storage means, and a signal stored in the first storage means, A second transfer means for transferring to a second storage means shared by a plurality of the pixels included in the same group, and a signal stored in the second storage means, arranged on the second substrate, Output means for outputting from the pixels. Rukoto or an imaging apparatus according to claim.

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting unit. The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels Includes a photoelectric conversion element disposed on the first substrate, a first transfer unit that simultaneously transfers a signal generated by the photoelectric conversion element to a first storage unit in all the pixels, and the first transfer unit. Second transfer means for sequentially transferring a signal stored in one storage means to a second storage means shared by the plurality of pixels included in the same group within the plurality of pixels included in the group. And disposed on the second substrate. Is, the accumulated signal to said second storage means, and output means for outputting from the pixel may be a solid-state imaging apparatus comprising: a.

  An imaging apparatus according to an aspect of the present invention is an imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging apparatus includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels are A photoelectric conversion element disposed on a first substrate; a first transfer unit configured to simultaneously transfer a signal generated by the photoelectric conversion element to the first storage unit in all the pixels; and the first storage unit. A second transfer means for sequentially transferring the signal accumulated in the means to the second accumulation means shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; Disposed on a second substrate, Signals accumulated in the second accumulation means, and output means for outputting from the pixel may be an imaging device characterized by comprising a.

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting unit. The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels Receives the photoelectric conversion element disposed on the first substrate and a signal generated by the photoelectric conversion element at one of the source and the drain, outputs the other from the other of the source and the drain, and transfers them to the first storage capacitor A first transfer transistor and a signal stored in the first storage capacitor are received by one of a source and a drain and output from the other of the source and the drain, and are included in the same group. A second transfer transistor for transferring to a second storage capacitor shared by the pixel; and a signal disposed on the second substrate and stored in the second storage capacitor for outputting from the pixel. And a solid-state imaging device including output means having a capacitor and a transistor.

  An imaging apparatus according to an aspect of the present invention is an imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging apparatus includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels are A photoelectric conversion element disposed on a first substrate; a signal generated by the photoelectric conversion element received by one of a source and a drain; output from the other of the source and drain; and transferred to a first storage capacitor A transfer transistor and a signal stored in the first storage capacitor are received by one of a source and a drain and output from the other of the source and the drain, and the plurality of pixels included in the same group A second transfer transistor that transfers to a second storage capacitor, and a capacitor or transistor that is disposed on the second substrate and outputs a signal stored in the second storage capacitor from the pixel And an output unit including the imaging unit.

  A solid-state imaging device according to an aspect of the present invention is a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting unit. The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels Is a photoelectric conversion element disposed on the first substrate, and a signal generated by the photoelectric conversion element is received by one of the source and the drain and output from the other of the source and the drain, A first transfer transistor for transferring to the first storage capacitor; and a signal stored in the first storage capacitor is received by one of the source and drain and output from the other of the source and drain; A second transfer transistor that sequentially transfers the second storage capacitor shared by the plurality of pixels included in one group within the plurality of pixels included in the group; and the second transfer transistor, which is disposed on the second substrate. A solid-state imaging device comprising: a capacitor for outputting a signal stored in the second storage capacitor from the pixel; and an output unit having a transistor.

  An imaging apparatus according to an aspect of the present invention is an imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit, The imaging apparatus includes a plurality of pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection means, and the pixels are A photoelectric conversion element disposed on the first substrate and a signal generated by the photoelectric conversion element are received by one of the source and the drain and output from the other of the source and the drain. A first transfer transistor for transferring to a storage capacitor; and a signal stored in the first storage capacitor is received by one of a source and a drain and output from the other of the source and drain; A second transfer transistor configured to sequentially transfer the second storage capacitor shared by the plurality of pixels included in the plurality of pixels included in the group, and the second substrate; And an output means having a capacitor and a transistor for outputting the signal stored in the storage capacitor from the pixel.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and various alternatives and modifications can be made without departing from the spirit of the present invention. The equivalent can also be changed. Accordingly, the scope of the invention should not be determined with reference to the above description, but should be determined by the claims, including the full scope of equivalents. In addition, any of the features described above may be combined with other features regardless of whether or not they are preferable. Also, in the claims, each component is one or more quantities unless explicitly stated otherwise. In addition, the claims should not be construed as including means-plus-function limitations unless explicitly stated in the claims using words such as “means for”.

  In the solid-state imaging device according to the embodiment of the present invention, two substrates may be connected by a connection unit, or three or more substrates may be connected by a connection unit. In the case of a solid-state imaging device in which three or more substrates are connected at the connection portion, two of them correspond to the first substrate and the second substrate according to the claims.

DESCRIPTION OF SYMBOLS 1 ... Digital camera 2 ... Lens unit part 3 ... Image sensor 4 ... Light-emitting device 5 ... Memory 6 ... Recording device 7 ... Display device 8 ... Image signal processing circuit DESCRIPTION OF SYMBOLS 9 ... Lens control apparatus 10 ... Image sensor control apparatus 11 ... Light emission control apparatus 12 ... Camera control apparatus 31 ... Pixel chip 32 ... Pixel signal processing chip 33 ... Chip connection part 34... External wiring connection portion 311... Pixel chip vertical scanning circuit 312... Pixel array portion 313... Unit pixel 314. First pixel reset line 317 ... first pixel transfer line 318 ... first pixel selection line 319 ... second pixel reset line 3110 ... second pixel transfer line 3111 ... second pixel Selection line 3112 FD reset line 321... Pixel signal processing chip vertical scanning circuit 322... Pixel memory array unit 323... Unit pixel memory 324... Pixel memory signal line 325. ... Pixel signal processing chip column processing circuit 327 ... Pixel signal processing chip horizontal scanning circuit 328 ... Pixel signal processing chip horizontal scanning circuit signal line 329 ... Image sensor control circuit 3210 ... Image sensor control circuit Signal line 3211 ... 1st pixel memory reset line 3212 ... 1st pixel memory transfer line 3213 ... 1st pixel memory selection line 3214 ... 2nd pixel memory reset line 3215 ... 2nd pixel memory Transfer line 3216 ... second pixel memory selection line PD1 ... first photodiode PD2 ... second photodiode C1... First pixel charge storage section PC2... Second pixel charge storage section FD... Unit pixel charge storage section PM1... First pixel transfer transistor PM2. First pixel selection transistor PM4 ... Unit pixel reset transistor PM5 ... Unit pixel amplification transistor PM6 ... Second pixel transfer transistor PM7 ... Second pixel reset transistor PM8 ... Second pixel selection transistor MC1 ... 1st pixel memory charge storage part MC2 ... 2nd pixel memory charge storage part MM1 ... 1st pixel memory transfer transistor MM2 ... 1st pixel memory reset transistor MM3 ... 1st pixel memory amplification Transistor MM4... First pixel memory selection transistor MM5. Jistor MM6 ... second pixel memory reset transistor MM7 ... second pixel memory amplification transistor MM8 ... second pixel memory selection transistor CC ... unit pixel memory coupling capacitor CS ... unit pixel memory current load 201 ... Pixel chip global reset operation sequence 202 ... Pixel chip global transfer operation sequence 203 ... Pixel chip rolling readout operation sequence 204 ... Pixel signal processing chip rolling readout operation sequence ΦPT1 ... 1-pixel transfer pulse ΦPT2 ... 2nd pixel transfer pulse ΦPS1 ... 1st pixel selection pulse ΦPS2 ... 2nd pixel selection pulse ΦPR1 ... 1st pixel reset pulse ΦPR2 ... 2nd pixel reset pulse ΦFR ... FD reset pulse ΦMT1 ... First pixel memory transfer pulse ΦMT2 ... Second pixel memory transfer pulse ΦMR1 ... First pixel memory reset pulse ΦMR2 ... Second pixel memory reset pulse ΦMS1 ... First pixel memory selection pulse ΦMS2 ... Second pixel memory selection pulse ΦCL ... Clamp pulse ΦSH ... Sample hold pulse ΦH ... Horizontal scan pulse V _PC1 ... PC1 potential V _PC2 ... PC2 potential V _FD ... FD potential V _MC1 · MC1 potential V _MC2 ... MC2 potential V _PC1SIG ... PC1 signal potential V _PC2SIG ... PC2 signal potential V _FDSIG1 ... first FD signal potential V _FDSIG2 ... second FD signal potential V _MC1SIG ... MC1 signal potential V _MC2SIG ... MC2 signal potential VDDP, VDDM ... power supply potential

Claims (37)

A solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer unit that transfers a signal generated by the photoelectric conversion element to a first storage unit;
A second transfer unit that transfers a signal accumulated in the first accumulation unit to a second accumulation unit shared by a plurality of the pixels included in the same group;
An output unit arranged on the second substrate and outputting a signal accumulated in the second accumulation unit from the pixel;
A solid-state imaging device comprising: The first transfer unit includes:
A signal generated by the photoelectric conversion element is simultaneously transferred to the first accumulation unit in all the pixels;
The solid-state imaging device according to claim 1. The second transfer unit is
Sequentially transferring the signal accumulated in the first accumulation unit to the second accumulation unit within the plurality of pixels included in the same group;
The solid-state imaging device according to claim 2. The pixel is
A third accumulation unit that is disposed on the second substrate and that is obtained via the connection unit and accumulates the signal accumulated in the second accumulation unit;
The output unit is
Outputting the signal accumulated in the third accumulation unit from the pixel;
The solid-state imaging device according to claim 1. The pixel is
A first reset unit for resetting a signal generated by the photoelectric conversion element;
A second reset unit that resets a signal accumulated in the second accumulation unit,
The solid-state imaging device according to claim 1. The pixel is
An amplification unit that outputs an amplified signal obtained by amplifying the signal accumulated in the second accumulation unit as a signal accumulated in the second accumulation unit;
The solid-state imaging device according to claim 1. The pixel is
Prior to transfer of the signal accumulated in the first accumulation unit by the second transfer unit to the second accumulation unit, the signal accumulated in the second accumulation unit by the second reset unit Reset the
The solid-state imaging device according to claim 5. The pixel is
Sharing the second reset unit with the plurality of pixels included in the same group;
The solid-state imaging device according to claim 7. The pixel is
The amplification unit is shared by a plurality of the pixels included in the same group.
The solid-state imaging device according to claim 6. The first substrate and the second substrate are:
Connected via a plurality of the connecting portions,
The pixels sharing the connection part are configured to be classified into the same group.
The solid-state imaging device according to claim 1. The pixel is
A noise reduction unit for reducing noise in the amplified signal output from the amplification unit;
The solid-state imaging device according to claim 9. The noise reduction unit is
A clamping unit for clamping the amplified signal output from the amplification unit;
A sample hold unit that samples and holds a signal corresponding to the amplified signal clamped by the clamp unit; and
The solid-state imaging device according to claim 11, comprising: The connection point on the first substrate side in the connection part and the connection point on the second substrate side in the connection part are:
Arranged at any position on the path from the output terminal of the photoelectric conversion element to the input terminal of the output unit,
The solid-state imaging device according to claim 1. The connecting portion is a bump.
The solid-state imaging device according to claim 1. The connecting portion is
A first electrode formed on the surface of the first substrate; and a second electrode formed on the surface of the second substrate and bonded to the first electrode;
The solid-state imaging device according to claim 1. The second substrate is
Connected to the surface opposite to the surface of the first substrate irradiated with light incident on the photoelectric conversion element;
The solid-state imaging device according to claim 1. A control method for a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
A first transfer step of transferring a signal generated by a photoelectric conversion element of the pixel disposed on the first substrate to a first storage unit;
A second transfer step of transferring a signal accumulated in the first accumulation unit to a second accumulation unit shared by a plurality of the pixels included in the same group;
An output step of outputting a signal accumulated in the second accumulation unit from an output unit of the pixel disposed on the second substrate;
A control method for a solid-state imaging device. An imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and a plurality of the pixels share one connection part,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer unit that transfers a signal generated by the photoelectric conversion element to a first storage unit;
A second transfer unit that transfers a signal accumulated in the first accumulation unit to a second accumulation unit shared by a plurality of the pixels included in the same group;
An output unit arranged on the second substrate and outputting a signal accumulated in the second accumulation unit from the pixel;
An imaging apparatus comprising: A solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer unit that transfers a signal generated by the photoelectric conversion element to a first storage unit simultaneously in all the pixels;
A second storage unit configured to sequentially transfer a signal stored in the first storage unit to a second storage unit shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; A transfer section;
An output unit arranged on the second substrate and outputting a signal accumulated in the second accumulation unit from the pixel;
A solid-state imaging device comprising: The pixel is
A third accumulation unit that is disposed on the second substrate and that is obtained via the connection unit and accumulates the signal accumulated in the second accumulation unit;
The output unit is
Outputting the signal accumulated in the third accumulation unit from the pixel;
The solid-state imaging device according to claim 19. A control method for a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
A first transfer step of transferring a signal generated by a photoelectric conversion element of the pixel disposed on the first substrate to a first accumulation unit simultaneously in all the pixels;
A second storage unit configured to sequentially transfer a signal stored in the first storage unit to a second storage unit shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; A transfer step;
An output step of outputting a signal accumulated in the second accumulation unit from an output unit of the pixel disposed on the second substrate;
A control method for a solid-state imaging device. An imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and a plurality of the pixels share one connection part,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer unit that transfers a signal generated by the photoelectric conversion element to a first storage unit simultaneously in all the pixels;
A second storage unit configured to sequentially transfer a signal stored in the first storage unit to a second storage unit shared by the plurality of pixels included in the same group within the plurality of pixels included in the group; A transfer section;
An output unit arranged on the second substrate and outputting a signal accumulated in the second accumulation unit from the pixel;
An imaging apparatus comprising: A solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer transistor that receives a signal generated by the photoelectric conversion element at one of a source and a drain, outputs the signal from the other of the source and the drain, and transfers the signal to a first storage capacitor;
The signal stored in the first storage capacitor is received by one of the source and drain, output from the other of the source and drain, and transferred to the second storage capacitor shared by the plurality of pixels included in the same group A second transfer transistor that
An output circuit including a capacitor and a transistor disposed on the second substrate and outputting a signal stored in the second storage capacitor from the pixel;
A solid-state imaging device comprising: The pixel is
An analog memory circuit, which is a third storage capacitor that is disposed on the second substrate and that is acquired via the connection unit and stores the signal stored in the second storage capacitor;
The output circuit is
Outputting a signal accumulated in the third accumulation capacitor from the pixel;
The solid-state imaging device according to claim 23. The pixel is
A first reset transistor for resetting a signal generated by the photoelectric conversion element;
A second reset transistor for resetting a signal stored in the second storage capacitor,
The solid-state imaging device according to claim 23. The pixel is
Amplifying the signal stored in the second storage capacitor at the gate, outputting an amplified signal amplified from one of the source and drain, and outputting the amplified signal as a signal stored in the second storage capacitor A transistor further comprising:
The solid-state imaging device according to claim 23. The pixel is
Sharing the second reset transistor among the plurality of pixels included in the same group;
The solid-state imaging device according to claim 25. The pixel is
The amplification transistor is shared by a plurality of the pixels included in the same group.
The solid-state imaging device according to claim 26. The first substrate and the second substrate are:
Connected via a plurality of the connecting portions,
The pixels sharing the connection part are configured to be classified into the same group.
The solid-state imaging device according to claim 23. The pixel is
A noise reduction circuit for reducing noise in the amplified signal output from the amplification transistor;
The solid-state imaging device according to claim 28. The noise reduction circuit is:
A clamp capacitor connected to one of the source and drain of the amplification transistor directly or indirectly and for clamping the output amplified signal;
A sample and hold transistor connected directly or indirectly to the clamp capacitor to sample and hold the clamped amplified signal;
The solid-state imaging device according to claim 30, wherein: A control method for a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
A signal generated by the photoelectric conversion element of the pixel disposed on the first substrate is received by one of the source and the drain, and is output from the other of the source and drain to the first transfer transistor by the photoelectric conversion element of the pixel. A first transfer step of transferring the generated signal to a first storage capacity;
The signal stored in the first storage capacitor is received by one of the source and the drain, and the second transfer transistor that outputs from the other of the source and drain receives the signal stored in the first storage capacitor in the same group. A second transfer step of transferring to a second storage capacitor shared by the plurality of pixels included in
An output step of outputting a signal stored in the second storage capacitor from an output circuit of the pixel disposed on the second substrate;
A control method for a solid-state imaging device. An imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and a plurality of the pixels share one connection part,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer transistor that receives a signal generated by the photoelectric conversion element at one of a source and a drain, outputs the signal from the other of the source and the drain, and transfers the signal to a first storage capacitor;
The signal stored in the first storage capacitor is received by one of the source and drain, output from the other of the source and drain, and transferred to the second storage capacitor shared by the plurality of pixels included in the same group A second transfer transistor that
An output circuit including a capacitor and a transistor disposed on the second substrate and outputting a signal stored in the second storage capacitor from the pixel;
An imaging apparatus comprising: A solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer transistor that receives a signal generated by the photoelectric conversion element at one of a source and a drain, outputs the signal from the other of the source and the drain, and simultaneously transfers the signal to a first storage capacitor in all the pixels;
A signal stored in the first storage capacitor is received by one of the source and the drain, output from the other of the source and the drain, and the second storage capacitor shared by the plurality of pixels included in the same group, A second transfer transistor for sequentially transferring within the plurality of pixels included in the group;
An output circuit including a capacitor and a transistor disposed on the second substrate and outputting a signal stored in the second storage capacitor from the pixel;
A solid-state imaging device comprising: The pixel is
An analog memory circuit, which is a third storage capacitor that is disposed on the second substrate and that is acquired via the connection unit and stores the signal stored in the second storage capacitor;
The output circuit is
Outputting a signal accumulated in the third accumulation capacitor from the pixel;
35. The solid-state imaging device according to claim 34. A control method for a solid-state imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connecting portion,
The solid-state imaging device has a plurality of the pixels, each of the pixels is classified into one or more groups, and the plurality of pixels share one connection portion,
A signal generated by the photoelectric conversion element of the pixel disposed on the first substrate is received by one of the source and the drain, and is output from the other of the source and drain to the first transfer transistor by the photoelectric conversion element of the pixel. A first transfer step of transferring the generated signal to all of the pixels simultaneously to the first storage capacitor;
The signal stored in the first storage capacitor is received by one of the source and the drain, and the second transfer transistor that outputs from the other of the source and drain receives the signal stored in the first storage capacitor in the same group. A second transfer step of sequentially transferring the second storage capacitor shared by the plurality of pixels included in the plurality of pixels included in the group;
An output step of outputting a signal stored in the second storage capacitor from an output circuit of the pixel disposed on the second substrate;
A control method for a solid-state imaging device. An imaging apparatus in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected by a connection unit,
The imaging device has a plurality of pixels, each of the pixels is classified into one or more groups, and a plurality of the pixels share one connection part,
The pixel is
A photoelectric conversion element disposed on the first substrate;
A first transfer transistor that receives a signal generated by the photoelectric conversion element at one of a source and a drain, outputs the signal from the other of the source and the drain, and simultaneously transfers the signal to a first storage capacitor in all the pixels;
A signal stored in the first storage capacitor is received by one of the source and the drain, output from the other of the source and the drain, and the second storage capacitor shared by the plurality of pixels included in the same group, A second transfer transistor for sequentially transferring within the plurality of pixels included in the group;
An output circuit including a capacitor and a transistor disposed on the second substrate and outputting a signal stored in the second storage capacitor from the pixel;
An imaging apparatus comprising:

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