JP2013026565A - Solid-state imaging apparatus, method of manufacturing solid-state imaging apparatus, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve light receiving characteristics in photoelectric conversion parts by thinning an insulating film in a pixel region in a back irradiation type solid-state imaging apparatus having wiring disposed in a peripheral region.SOLUTION: A solid-state imaging apparatus 1-1 includes: a sensor substrate 2 having a pixel region 4 in which photoelectric conversion parts 20 are arrangedly formed thereon; a driving circuit disposed on a surface side opposite a light receiving surface A of the sensor substrate 2; an insulating layer 14 which is disposed on the light receiving surface A in the sensor substrate 2 and has a step structure that a film thickness of the pixel region 4 is thinner than a film thickness of a peripheral region 7; wiring 8 disposed in the peripheral region 7 closer to the light receiving surface A; and on-chip lenses 19 disposed correspondingly to the photoelectric conversion parts 20 on the insulating layer 14.

Description

  The present technology relates to a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an electronic device, and in particular, a solid-state imaging device in which a drive circuit is provided on the surface side opposite to a light-receiving surface of a semiconductor substrate, and the solid-state imaging device The present invention relates to a manufacturing method and an electronic apparatus using the solid-state imaging device.

  For solid-state imaging devices, a so-called back-illuminated structure is proposed in which a drive circuit is formed on the front side of the semiconductor substrate and the back side is the light-receiving surface for the purpose of improving photoelectric conversion efficiency and sensitivity to incident light. Has been. In addition to the semiconductor substrate on which the photoelectric conversion unit is formed, a circuit substrate on which a drive circuit is formed is prepared, and a three-dimensional structure in which the circuit substrate is bonded to the surface opposite to the light receiving surface of the semiconductor substrate is also proposed. Has been.

  The structure on the light receiving surface side in the back-illuminated solid-state imaging device as described above is as follows. A light-shielding film is provided on the light-receiving surface side of the semiconductor substrate on which the photoelectric conversion unit is formed via an insulating film. The light shielding film has a plurality of light receiving openings corresponding to the photoelectric conversion units, and is disposed in a pixel region in which the photoelectric conversion units are arranged. A wiring and an electrode pad are provided on the insulating film covering the light shielding film. These wirings and electrode pads are arranged in a peripheral region outside the pixel region, and are connected to a drive circuit formed on the surface side of the semiconductor substrate. Further, a color filter and an on-chip lens are provided corresponding to each photoelectric conversion portion on the insulating film covering the wiring and the electrode pad on the light receiving surface side (see Patent Document 1 below).

JP 2010-245506 A (see, for example, FIG. 3 and related descriptions)

  However, in the back-illuminated solid-state imaging device having such a configuration, a plurality of insulating films are provided above the light receiving surface, and a color filter and an on-chip lens are arranged through these insulating films. Therefore, the distance from the light receiving surface of the semiconductor substrate to the on-chip lens is large, which becomes a factor of deteriorating the light receiving characteristics in the photoelectric conversion unit.

  Therefore, in the present technology, in a backside illumination type solid-state imaging device in which wiring is provided in a peripheral region outside the pixel region, the light receiving characteristic in the photoelectric conversion unit is improved by thinning the insulating film in the pixel region. An object of the present invention is to provide a back-illuminated solid-state imaging device capable of performing the above. Another object of the present technology is to provide a method for manufacturing a solid-state imaging device having such a configuration and an electronic apparatus using the solid-state imaging device.

  In order to achieve such an object, a solid-state imaging device according to an embodiment of the present technology includes a sensor substrate having a pixel region in which photoelectric conversion units are arrayed, and a surface of the sensor substrate opposite to a light receiving surface for the photoelectric conversion unit. And a provided drive circuit. Furthermore, an insulating layer having a step structure in which the film thickness of the pixel region is thinner than the film thickness of the peripheral region provided outside the pixel region is provided on the light receiving surface of the sensor substrate. In addition, wiring is provided in the peripheral region on the light receiving surface side of the sensor substrate, and on-chip lenses are provided at positions corresponding to the photoelectric conversion portions on the insulating layer.

  The solid-state imaging device having such a configuration is a back-illuminated type in which a light receiving surface is a surface opposite to a front surface on which a driving circuit is formed in a sensor substrate provided with a photoelectric conversion unit. An insulating layer having a step structure with a small thickness in the region is provided. This reduces the distance between the on-chip lens and the light receiving surface by thinning only the insulating layer portion in the pixel area while ensuring the thickness of the insulating layer without affecting the wiring configuration in the peripheral area. Can do.

  The present technology is also a method for manufacturing such a solid-state imaging device, and the following procedure is performed. First, photoelectric conversion units are arrayed in the pixel region set on the sensor substrate. Further, a drive circuit is formed on the surface of the sensor substrate opposite to the light receiving surface for the photoelectric conversion unit. Further, an insulating layer is formed on the light receiving surface of the sensor substrate, and wiring is formed on the light receiving surface side in a peripheral region provided outside the pixel region. After the above, a step structure is formed in the insulating layer by selectively thinning a portion corresponding to the pixel region in the insulating layer with respect to the peripheral region. Thereafter, an on-chip lens is formed at each position corresponding to the photoelectric conversion portion on the insulating layer on which the step structure is formed.

  The present technology is also an electronic device including the above-described solid-state imaging device, and further includes an optical system that guides incident light to the photoelectric conversion unit.

  According to the present technology as described above, in the back-illuminated solid-state imaging device in which wiring is provided in the peripheral region outside the pixel region, the on-chip lens is formed by selectively thinning the insulating layer portion of the pixel region. The distance from the light receiving surface can be reduced. As a result, it is possible to improve the light receiving characteristics in the photoelectric conversion unit.

It is a schematic structure figure showing an example of a solid imaging device to which this art is applied. It is principal part sectional drawing which shows the structure of the solid-state imaging device of 1st Embodiment. FIG. 6 is a cross-sectional process diagram (part 1) illustrating the manufacturing procedure of the solid-state imaging device according to the first embodiment; FIG. 6 is a cross-sectional process diagram (part 2) illustrating the manufacturing procedure of the solid-state imaging device according to the first embodiment; FIG. 6 is a sectional process diagram (part 3) illustrating the manufacturing procedure of the solid-state imaging device according to the first embodiment; FIG. 6 is a cross-sectional process diagram (part 4) illustrating the manufacturing procedure of the solid-state imaging device according to the first embodiment; It is principal part sectional drawing which shows the structure of the solid-state imaging device of 2nd Embodiment. It is sectional process drawing (the 1) which shows the manufacture procedure of the solid-state imaging device of 2nd Embodiment. It is sectional process drawing (the 2) which shows the manufacture procedure of the solid-state imaging device of 2nd Embodiment. It is sectional process drawing (the 3) which shows the manufacture procedure of the solid-state imaging device of 2nd Embodiment. It is principal part sectional drawing which shows the structure of the solid-state imaging device of 3rd Embodiment. It is sectional process drawing (the 1) which shows the manufacture procedure of the solid-state imaging device of 3rd Embodiment. It is sectional process drawing (the 2) which shows the manufacture procedure of the solid-state imaging device of 3rd Embodiment. It is principal part sectional drawing which shows the structure of the solid-state imaging device of 4th Embodiment. It is sectional process drawing (the 1) which shows the manufacture procedure of the solid-state imaging device of 4th Embodiment. It is sectional process drawing (the 2) which shows the manufacture procedure of the solid-state imaging device of 4th Embodiment. It is principal part sectional drawing which shows the structure of the solid-state imaging device of 5th Embodiment. It is a block diagram of the electronic device using the solid-state imaging device obtained by applying this technique.

Hereinafter, embodiments of the present technology will be described in the following order based on the drawings.
1. 1. Schematic configuration example of solid-state imaging device according to embodiment First embodiment (example in which an insulating layer having a step structure is provided)
3. Second Embodiment (Example in which an insulating layer having a step structure in which an insulating pattern is covered with an insulating film is provided)
4). Third Embodiment (Example in which an embedded wiring in which a step structure insulating layer and a sensor substrate are dug is provided)
5. Fourth embodiment (example in which an insulating layer having a step structure and a laminated wiring are provided)
6). Fifth embodiment (example in which a share capacitor is provided for connection of wiring in the sensor substrate)
7). Electronic devices (examples of electronic devices using solid-state imaging devices)
In addition, in each embodiment, the same code | symbol is attached | subjected to a common component, and the overlapping description is abbreviate | omitted.

<< 1. Schematic configuration example of solid-state imaging device of embodiment >>
FIG. 1 shows a schematic configuration of a solid-state imaging device having a three-dimensional structure as an example of a back-illuminated solid-state imaging device to which the present technology is applied. The solid-state imaging device 1 shown in this figure includes a sensor substrate 2 on which photoelectric conversion units are arranged and a circuit substrate 9 that is bonded to the sensor substrate 2 in a stacked state.

  The sensor substrate 2 includes a pixel region 4 in which one surface is a light receiving surface A and a plurality of pixels 3 including a photoelectric conversion unit are two-dimensionally arranged with respect to the light receiving surface A. In the pixel region 4, a plurality of pixel drive lines 5 are wired in the row direction, and a plurality of vertical signal lines 6 are wired in the column direction. One pixel 3 has one pixel drive line 5 and one line. It is arranged in a state of being connected to the vertical signal line 6. Each of these pixels 3 is provided with a photoelectric conversion unit, a charge storage unit, and a pixel circuit composed of a plurality of transistors (so-called MOS transistors) and a capacitor element. A part of the pixel circuit is provided on the surface side opposite to the light receiving surface A. A part of the pixel circuit may be shared by a plurality of pixels.

  The sensor substrate 2 includes a peripheral region 7 outside the pixel region 4. In the peripheral region 7, a wiring 8 including an electrode pad is provided. The wiring 8 is connected to the pixel drive line 5 and the vertical signal line 6 provided on the sensor substrate 2 and the pixel circuit and the drive circuit provided on the circuit board 9 as necessary.

  The circuit board 9 has a vertical drive circuit 10, a column signal processing circuit 11, a horizontal drive circuit 12, and a system control circuit for driving each pixel 3 provided on the sensor board 2 on one side facing the sensor board 2 side. 13 and the like are provided. These drive circuits are connected to the wiring 8 on the sensor substrate 2 side. The pixel circuit provided on the surface side of the sensor substrate 2 is also a part of the drive circuit.

≪2. First Embodiment >>
<Configuration of solid-state imaging device>
(Example of providing an insulating layer with a step structure and embedded wiring)
FIG. 2 is a principal cross-sectional view showing the configuration of the solid-state imaging device 1-1 of the first embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-1 of the first embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device 1-1 according to the first embodiment shown in FIG. 2 is a solid-state imaging device having a three-dimensional structure in which the sensor substrate 2 and the circuit board 9 are bonded together as described above. A wiring layer 2a and a protective film 2b covering the wiring layer 2a are provided on the surface side of the sensor substrate 2, that is, the surface facing the circuit board 9 side. On the other hand, a wiring layer 9a and a protective film 9b covering the wiring layer 9a are provided on the surface side of the circuit board 9, that is, the surface facing the sensor board 2 side. A protective film 9 c is provided on the back side of the circuit board 9. The sensor substrate 2 and the circuit board 9 are bonded together between the protective film 2b and the protective film 9b.

  Further, on the surface of the sensor substrate 2 opposite to the circuit board 9, that is, on the light receiving surface A, an insulating layer 14 having a step structure, a wiring 8, and a light shielding film 16 are provided. The transparent protective film 17, the color filter 18, and the on-chip lens 19 are laminated in this order. The first embodiment is particularly characterized in that the insulating layer 14 has a step structure, and the on-chip lens 19 is disposed below the step structure.

  Next, the configuration of each layer on the sensor substrate 2 side and each layer on the circuit substrate 9 side, the insulating layer 14 having a step structure, the wiring 8, the light shielding film 16, the transparent protective film 17, the color filter 18, and the on-chip lens 19 The configuration will be described in this order.

[Sensor board 2]
The sensor substrate 2 is obtained by thinning a semiconductor substrate made of, for example, single crystal silicon. A plurality of photoelectric conversion units 20 are arrayed along the light receiving surface A in the pixel region 4 of the sensor substrate 2. Each photoelectric conversion unit 20 has a stacked structure of, for example, an n-type diffusion layer and a p-type diffusion layer. The photoelectric conversion unit 20 is provided for each pixel, and a cross section for one pixel is shown in the drawing.

  Further, on the surface side opposite to the light receiving surface A in the sensor substrate 2, a floating diffusion FD composed of an n + -type impurity layer, the source / drain 21 of the transistor Tr, and other impurity layers not shown here, An element isolation 22 and the like are provided.

  Further, in the sensor substrate 2, a through via 23 penetrating the sensor substrate 2 is provided in the peripheral region 7 outside the pixel region 4. The through via 23 is made of a conductive material embedded in a connection hole formed through the sensor substrate 2 via an isolation insulating film 24.

[Wiring layer 2a (sensor substrate 2 side)]
The wiring layer 2a provided on the surface of the sensor substrate 2 is disposed on the interface side with the sensor substrate 2 via a gate insulating film (not shown), the transfer gate TG, the gate electrode 25 of the transistor Tr, and further It has other electrodes which are not shown here. The transfer gate TG and the gate electrode 25 are covered with an interlayer insulating film 26, and a buried wiring 27 using, for example, copper (Cu) is formed in a groove pattern provided in the interlayer insulating film 26. It is provided as a multilayer wiring. These embedded wirings 27 are connected to each other by vias, and a part thereof is connected to the source / drain 21, the transfer gate TG, and further to the gate electrode 25. Further, the through wiring 23 provided in the sensor substrate 2 is also connected to the embedded wiring 27, and a pixel circuit is configured by the transistor Tr and the embedded wiring 27.

  An insulating protective film 2b is provided on the interlayer insulating film 26 on which the embedded wiring 27 as described above is formed, and the sensor substrate 2 is bonded to the circuit board 9 on the surface of the protective film 2b.

[Circuit board 9]
The circuit board 9 is obtained by thinning a semiconductor substrate made of, for example, single crystal silicon. In the circuit board 9, a source / drain 31 of the transistor Tr, an impurity layer not shown here, an element isolation 32, and the like are provided on the surface layer toward the sensor substrate 2.

  Further, the circuit board 9 is provided with a through via 33 penetrating therethrough. The through via 33 is made of a conductive material embedded in a connection hole formed through the circuit board 9 via an isolation insulating film 34.

[Wiring layer 9a (circuit board 9 side)]
The wiring layer 9a provided on the surface of the circuit board 9 is provided on the interface side with the circuit board 9 through a gate insulating film not shown here, and further shown here. The other electrode is omitted. These gate electrodes 35 and other electrodes are covered with an interlayer insulating film 36, and a buried wiring 37 using, for example, copper (Cu) is formed in a multilayer pattern in a groove pattern provided in the interlayer insulating film 36. It is provided as. These embedded wirings 37 are connected to each other by vias and partly connected to the source / drain 31 and the gate electrode 35. Further, the through wiring 33 provided in the circuit board 9 is also connected to the embedded wiring 37, and a drive circuit is configured by the transistor Tr and the embedded wiring 37.

  An insulating protective film 9b is provided on the interlayer insulating film 36 on which the embedded wiring 37 as described above is formed, and the circuit board 9 is bonded to the sensor substrate 2 on the surface of the protective film 9b. Further, in the circuit board 9, a protective film 9c that covers the circuit board 9 is provided on the back surface side opposite to the front surface side on which the wiring layer 9a is provided, and a pad that exposes the through via 33 is provided on the protective film 9c. An opening 33a is provided.

[Insulating layer 14]
The insulating layer 14 is provided on the light receiving surface A of the sensor substrate 2. This insulating layer 14 is characterized in that it has a step structure in which the pixel region 4 is thinner than the peripheral region 7. Such an insulating layer 14 is configured as a laminated film using different insulating materials, for example. Here, as an example, an antireflection film 14-1, an interface state suppression film 14-2, an etching stop film are sequentially formed from the light receiving surface A side. 14-3, a groove formation film 14-4, and a cap film 14-5.

The antireflection film 14-1 is configured using an insulating material having a higher refractive index than silicon oxide, such as hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), or silicon nitride. The interface state suppression film 14-2 is configured using, for example, silicon oxide (SiO ₂ ). The etching stop film 14-3 is made of a material having a low etching selectivity with respect to the material constituting the upper groove forming film 14-4, and is made of, for example, silicon nitride (SiN). The groove forming film 14-4 is configured by using, for example, silicon oxide (SiO ₂ ). The cap film 14-5 is configured using, for example, silicon nitride (SiN).

  In the insulating layer 14 having the five-layer structure as described above, the upper cap film 14-5, the groove forming film 14-4, and the etching stop film 14-3 are removed in the pixel region 4, and the antireflection film 14 is removed. -1 and the interface state suppression film 14-2 are thinned. On the other hand, in the thick film portion of the peripheral region 7, a wiring groove is formed in the second groove forming film 14-4 from the upper layer so as to provide a wiring 8 to be described next.

[Wiring 8]
The wiring 8 is provided as an embedded wiring embedded in the insulating layer 14 in the peripheral region 7 on the light receiving surface A side. The wiring 8 is embedded in a wiring groove formed in the groove forming film 14-4 constituting the insulating layer 14, and an etching stop film 14-3, an interface state suppressing film 14-2, and an antireflection layer thereunder are formed thereunder. The through via 23 provided through the film 14-1 is connected.

  The wiring 8 and the through via 23 are connected to the wiring groove and the connection via the isolation insulating film 24 that continuously covers the wiring groove formed in the groove forming film 14-4 and the inner wall of the connection hole in the lower layer. The hole is integrally formed by embedding copper (Cu). The isolation insulating film 24 is configured by using a material having a copper (Cu) diffusion prevention function such as silicon nitride. The upper portion of the wiring 8 is covered with a cap film 14-5 that constitutes the uppermost layer of the insulating layer 14.

[Light shielding film 16]
In the pixel region 4 on the light receiving surface A side, the light shielding film 16 is provided below the step of the insulating layer 14, that is, above the interface state suppressing film 14-2 constituting the lower layer portion of the laminated structure in the insulating layer 14. Yes. Such a light shielding film 16 includes a plurality of light receiving openings 16 a corresponding to the respective photoelectric conversion units 20.

  Such a light shielding film 16 is made of a conductive material having excellent light shielding properties such as aluminum (Al) or tungsten (W), and is grounded to the sensor substrate 2 at an opening provided in the insulating layer 14. It is provided in the state.

[Transparent protective film 17]
The transparent protective film 17 is provided so as to cover the insulating layer 14 and the light shielding film 16. For example, an acrylic resin is used for the transparent planarizing film 17.

[Color filter 18]
The color filter 18 is provided corresponding to each photoelectric conversion unit 20, and is configured with each color corresponding to each photoelectric conversion unit 20. The arrangement of the color filters 18 for each color is not limited.

[On-chip lens 19]
The on-chip lens 19 is provided corresponding to each photoelectric conversion unit 20, and is configured so that incident light is condensed on each photoelectric conversion unit 20.

<Method for Manufacturing Solid-State Imaging Device>
Next, a manufacturing method of the solid-state imaging device 1-1 having the above-described configuration will be described based on the sectional process diagrams of FIGS.

[FIG. 3A]
First, as shown in FIG. 3A, a plurality of photoelectric conversion portions 20 are arranged and formed in the pixel region 4 of the sensor substrate 2, and an impurity layer and element isolation 22 other than the floating diffusion FD are formed on the sensor substrate 2. Next, the transfer gate TG and the gate electrode 25 are formed on the surface of the sensor substrate 2, and the embedded wiring 27 is formed together with the interlayer insulating film 26 to provide the wiring layer 2a. The upper part of the wiring layer 2a is covered with a protective film. Cover with 2b. On the other hand, an impurity layer other than the source / drain 31 and an element isolation 32 are formed on the circuit board 9. Next, the gate electrode 35 is formed on the surface of the circuit board 9, the embedded wiring 37 is formed together with the interlayer insulating film 36, the wiring layer 9 a is provided, and the via 33 is formed from the wiring layer 9 a to the circuit board 9. Then, the upper part of the wiring layer 9a is covered with a protective film 9b.

  After the above, the sensor substrate 2 and the circuit board 9 are bonded together between the protective film 2b and the protective film 9b. After the bonding is completed, the light receiving surface A side of the sensor substrate 2 is thinned as necessary. The procedure described above is not particularly limited in procedure, and can be performed by applying a normal bonding technique.

[FIG. 3B]
Next, as shown in FIG. 3B, on the light receiving surface A of the sensor substrate 2, an antireflection film 14-1, an interface state suppression film 14-2, an etching stop film 14-3, and a groove forming film 14-4 are formed. The layers are formed in this order. The antireflection film 14-1 is made of, for example, hafnium oxide (HfO ₂ ) and is formed with a film thickness of 10 nm to 300 nm (for example, 60 nm) by an atomic layer deposition method. The interface state suppression film 14-2 is made of, for example, silicon oxide (SiO ₂ ), and is formed with a film thickness of 200 nm by a P-CVD (plasma-chemical vapor deposition) method. The etching stop film 14-3 is made of, for example, silicon nitride (SiN), and is formed with a film thickness of 360 nm by the P-CVD method. The groove forming film 14-4 is made of, for example, silicon oxide (SiO ₂ ) and is formed with a film thickness of 200 nm by the P-CVD method.

  The above four layers are formed as films constituting a part of the insulating layer (14) having the step structure described above.

[FIG. 4A]
Thereafter, as shown in FIG. 4A, in the peripheral region 7 of the sensor substrate 2, a wiring groove 8a is formed in the uppermost groove forming film 14-4. At this time, the groove forming film 14-4 made of silicon oxide (SiO ₂ ) is etched using a resist pattern not shown here as a mask. In this etching, the etching is stopped by an etching stop film 14-3 made of underlying silicon nitride (SiN). After the etching is completed, the resist pattern is removed.

[FIG. 4B]
Next, as shown in FIG. 4B, each connection hole 23a having a depth as required is formed at the bottom of the wiring groove 8a. Each of these connection holes 23a may be formed at each depth reaching the upper portion of the embedded wiring 27 of the wiring layer 2a or the embedded wiring 37 of the wiring layer 9a provided on the surface side of the sensor substrate 2. The embedded wiring 27 and the embedded wiring 37 may not be exposed at the bottom. At this time, a plurality of resist patterns (not shown) are formed for each depth of the connection hole 23a, and the sensor substrate 2 and the interlayer insulating film 26 are etched a plurality of times using these resist patterns as a mask. I do. After the completion of each etching, each resist pattern is removed.

[FIG. 5A]
Next, as shown in FIG. 5A, an isolation insulating film 24 is formed on the groove forming film 14-4 so as to cover the inner walls of the wiring grooves 8a and the connection holes 23a. Here, for example, the isolation insulating film 24 having a two-layer structure is formed. First, a silicon nitride film 24-1 having a thickness of 70 nm is formed by p-CVD, and then silicon oxide having a thickness of 900 nm is formed by p-CVD. A film 24-2 is formed. Note that the isolation insulating film 24 is not limited to a laminated structure, and may be a single layer structure of, for example, a silicon oxide film or a silicon nitride film.

[FIG. 5B]
Thereafter, as shown in FIG. 5B, the isolation insulating film 24 is removed by etching under highly anisotropic etching conditions, so that the top of the trench formation film 14-4, the bottom of the wiring trench 8a, and the bottom of the connection hole 23a are further removed. The isolation insulating film 24 is removed. Subsequently, the interlayer insulating film 26, the protective film 2b, and the protective film 9b at the bottom of the connection hole 23a are removed by etching under highly anisotropic etching conditions, and the connection hole 23a is dug. Thus, the embedded wiring 27 or the embedded wiring 37 is exposed at the bottom of each connection hole 23a.

  In such etching, when the interlayer insulating film 26 is formed of a silicon oxide film, the surface layer of the groove forming film 14-4 made of silicon oxide under the isolation insulating film 24 is also reduced by the etching. . When the protective film 2b and the protective film 9b are formed of a silicon nitride film, the etching stop film 14-3 made of silicon nitride at the bottom of the wiring groove 8a is also reduced by etching. Therefore, in consideration of these film reduction amounts, the film thickness at the time of forming the etching stop film 14-3 made of silicon nitride and the groove forming film 14-4 made of silicon oxide is set.

[FIG. 5C]
Next, as shown in FIG. 5C, the wiring groove 8a and the connection hole 23a are integrally embedded with a conductive material, thereby forming the wiring 8 as an embedded wiring in the wiring groove 8a and further penetrating the sensor substrate 2. A through via 23 is formed in the connection hole 23a. Here, first, a conductive material film [for example, a copper (Cu) film] is formed on the groove forming film 14-4 in a state where the wiring groove 8a and the connection hole 23a are embedded, and then chemical mechanical polishing (CMP). ) The conductive material film on the groove forming film 14-4 is polished and removed by the method. Thus, the conductive material film is left only in the wiring groove 8a and the connection hole 23a, and the wiring 8 and the through via 23 connected thereto are formed in the peripheral region 7 on the light receiving surface A side of the sensor substrate 2.

[FIG. 6A]
Next, as shown in FIG. 6A, a cap film 14-5 having a diffusion preventing effect on copper (Cu) constituting the wiring 8 is formed in a state of covering the wiring 8 and the groove forming film 14-4. Here, as the cap film 14-5, for example, a silicon nitride film is formed to a thickness of 70 nm. Thereby, the antireflection film 14-1, the interface state suppressing film 14-2, the etching stop film 14-3, the groove forming film 14-4, and the cap film 14-5 are formed on the light receiving surface A of the sensor substrate 2. An insulating layer 14 having a five-layer structure laminated in this order is formed. A silicon oxide film may be further formed on the cap film 14-5 made of silicon nitride as the uppermost layer, if necessary.

[FIG. 6B]
Thereafter, as shown in FIG. 6B, the portion corresponding to the pixel region 4 in the insulating layer 14 is selectively thinned with respect to the peripheral region 7, thereby forming a step structure in the insulating layer 14. At this time, using the resist pattern not shown here as a mask, the cap film 14-5 made of silicon nitride (SiN) is etched, and thereafter the groove forming film 14 made of silicon oxide (SiO ₂ ) is changed under different conditions. Etch -4. At this time, the etching is stopped by an etching stop film 14-3 made of lower layer silicon nitride (SiN). Thereafter, the etching stop film 14-3 is etched under different conditions.

  As described above, the insulating layer 14 on the light receiving surface A has a stepped structure in which the film thickness of the pixel region 4 is smaller than the film thickness of the peripheral region 7, and has a cavity structure that is thinned on the pixel region 4. In such a state, only the antireflection film 14-1 and the interface state suppression film 14-2 are left in the pixel region 4. On the other hand, the insulating layer 14 having a five-layer structure is left as it is in the peripheral region 7. The step in the step structure of the insulating layer 14 is about 500 nm.

  Note that the thin film portion in the insulating layer 14 may be set as wide as possible without affecting the wiring 8, whereby the stepped shape of the insulating layer 14 deteriorates application unevenness of the transparent flattening film to be formed later. This prevents the light incident on the photoelectric conversion unit 20 from being affected.

[FIG. 6C]
Next, as illustrated in FIG. 6C, an opening 14 a that exposes the sensor substrate 2 is formed below the step of the insulating layer 14. At this time, the interface state suppressing film 14-2 and the antireflection film 14-1 are etched using a resist pattern not shown here as a mask. The opening 14a is formed at a position avoiding the top of the photoelectric conversion unit 20.

  Next, a light shielding film 16 that is grounded to the sensor substrate 2 through the opening 14 a is formed in a pattern below the step of the insulating layer 14. The light shielding film 16 has a light receiving opening 16 a corresponding to the photoelectric conversion unit 20. Here, first, a light-shielding conductive material film such as aluminum (Al) or tungsten (W) is formed on the insulating layer 14 by sputtering film formation. Thereafter, the conductive material film is subjected to pattern etching using a resist pattern (not shown) as a mask, so that the lower part of the step of the insulating layer 14 is widely covered and the light receiving openings 16a corresponding to the photoelectric conversion portions 20 are provided. Then, the light shielding film 16 grounded to the sensor substrate 2 is formed.

  Such a light shielding film 16 may be removed at the upper part of the step of the insulating layer 14 and widely cover the lower part of the step. Thereby, the level | step difference of the insulating layer 14 is reduced in a wide range.

[Figure 2]
After the above, as shown in FIG. 2 above, a transparent protective film 17 made of a light transmissive material is formed so as to cover the light shielding film 16. The transparent protective film 17 is formed by a coating method such as a spin coating method. Next, the color filters 18 of the respective colors corresponding to the photoelectric conversion unit 20 are formed on the transparent protective film 17, and the on-chip lens 19 corresponding to the photoelectric conversion unit 20 is further formed thereon. Further, the exposed surface of the circuit board 9 is polished to make the circuit board 9 thin, and the via 33 is exposed to form the through via 33. Thereafter, a protective film 9c is formed on the circuit board 9 so as to cover the through via 33, and a pad opening 33a exposing the through via 33 is formed, thereby completing the solid-state imaging device 1-1.

<Effects of First Embodiment>
The solid-state imaging device 1-1 having the configuration described above is a back-illuminated solid-state imaging device in which the wiring 8 is provided in the peripheral region 7 outside the pixel region 4. In such a configuration, on the light receiving surface A, an insulating layer 14 having a step structure with a small thickness in the pixel region 4 with respect to the peripheral region 7 is provided, and an on-chip lens 19 is provided thereon. Thereby, the thickness of the insulating layer 14 is ensured in the peripheral region 7 without affecting the configuration of the wiring 8, while in the pixel region 4, the insulating layer 14 is thinned to form the upper on-chip lens 19 and The distance from the light receiving surface A can be reduced.

  Here, as in the conventional structure, if the light shielding film is covered with an insulating layer and a wiring is provided above the insulating layer, an insulating film is further provided so as to cover the wiring, and an on-chip lens is disposed above this. Be placed. For this reason, an on-chip lens is disposed on the light-receiving surface via at least two layers of insulating films, and the distance from the light-receiving surface to the on-chip lens is large. It was a factor that deteriorated. Moreover, since the pattern shape of the light shielding film is inherited on the surface of the insulating film formed on the light shielding film, when trying to form a wiring groove for forming an embedded wiring in such an insulating film, Accurate patterning cannot be performed. In view of this, it is conceivable to secure the patterning accuracy for forming the wiring trench by forming a planarization insulating film on the light shielding film. However, since the distance from the light receiving surface to the on-chip lens is further increased by the formation of the planarization insulating film, the light receiving characteristics in the photoelectric conversion unit are further deteriorated.

  On the other hand, in the manufacturing method of the first embodiment described above, after forming the insulating layer 14 and the wiring 8 embedded in the insulating layer 14, the insulating layer 14 in the pixel region 4 is thinned and formed into a step structure. This is a procedure for forming the on-chip lens 19 in the pixel region 4. For this reason, the insulating layer portion necessary for forming the wiring 8 is not left as a thick film in the pixel region 4, and the distance between the on-chip lens 19 and the light receiving surface A can be reduced.

  As described above, according to the first embodiment, in the backside illumination type solid-state imaging device 1-1 in which the wiring 8 is provided in the peripheral region 7 outside the pixel region 4, the pattern accuracy of the wiring 8 is secured while being on-chip. By reducing the distance between the lens 19 and the light receiving surface A, it is possible to improve the light receiving characteristics in the photoelectric conversion unit 20. Specifically, the distance between the light receiving surface A and the lower surface of the color filter 18 can be about 600 nm. Thereby, it is possible to improve optical characteristics such as attenuation of incident light to the photoelectric conversion unit 20 and deterioration of color mixture due to light leakage to adjacent pixels in the case of oblique light incidence. The first embodiment can also be applied to a configuration in which the light shielding film 16 is not provided. In this case, the distance between the light receiving surface A and the color filter 18 can be reduced to about 300 nm, and shading and color mixing when the incident angle is increased can be further greatly improved. is there.

  In particular, in the manufacturing method of the first embodiment, as described with reference to FIG. 6B, when the step structure is formed in the insulating layer 14, the conditions are changed after the etching is stopped by the etching stop film 14-3. Thus, the etching stop film 14-3 is etched. Thereby, the antireflection film 14-1 and the interface state suppression film 14-2 can be left on the light receiving surface A of the pixel region 4 with good controllability. As a result, it is possible to obtain stable light receiving characteristics and a dark current prevention effect. It is also possible to keep the light-receiving surface A good without being exposed to etching damage.

<< Second Embodiment >>
<Configuration of solid-state imaging device>
(Example of providing an insulating layer with a step structure in which an insulating pattern is covered with an insulating film)
FIG. 7 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device 1-2 of the second embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-2 of the second embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device 1-2 of the second embodiment shown in FIG. 7 is different from the solid-state imaging device of the first embodiment described with reference to FIG. 2 in the layer structure of the insulating layer 41 having a step structure. Other configurations are the same as those of the first embodiment.

  That is, the insulating layer 41 has a three-layer structure in which, for example, a silicon oxide film 41-1, a silicon nitride film 41-2, and a cap film 41-3 made of silicon nitride are stacked in this order from the light receiving surface A side. A pattern is provided in the peripheral region 7. The insulating layer 41 has an antireflection film 41-4 and an interface state suppression film 41-5 in the pixel region 4 and the peripheral region 7 so as to cover such a three-layer insulating pattern. .

  Such a five-layer insulating layer 41 has a two-layer structure of an antireflection film 41-4 and an interface state suppression film 41-5 in the pixel region 4. On the other hand, in the peripheral region 7, the silicon oxide film 41-1, the silicon nitride film 41-2, the cap film 41-3 made of silicon nitride, the antireflection film 41-4, and the interface state suppression film It is a five-layer structure with 41-5.

  In the insulating layer 41 having the laminated structure as described above, in the thick film portion of the peripheral region 7, the lower silicon oxide film 41-1 and silicon nitride film 41-2 serve as a groove forming film, and a wiring groove in which the wiring 8 is provided is formed. Is formed. The through via 23 provided through the sensor substrate 2 is connected to the wiring 8.

  A light shielding film 16 is provided below the step on the insulating layer 41 above the antireflection film 41-4 and the interface state suppression film 41-5 covering the insulating pattern. The light shielding film 16 is the same as that of the first embodiment, and is provided in a state of being grounded to the sensor substrate 2 in the opening provided in the insulating layer 41.

<Method for Manufacturing Solid-State Imaging Device>
Next, a method for manufacturing the solid-state imaging device 1-2 having the above-described configuration will be described based on the sectional process diagrams of FIGS.

[FIG. 8A]
First, as shown in FIG. 8A, the process until the sensor substrate 2 and the circuit board are bonded together and the light receiving surface A side of the sensor substrate 2 is thinned as necessary is described with reference to FIG. 3A in the first embodiment. Do the same as Thereafter, a silicon oxide film 41-1 and a silicon nitride film 41-2 are formed in this order on the light receiving surface A of the sensor substrate 2.

[FIG. 8B]
Next, as shown in FIG. 8B, in the peripheral region 7 of the sensor substrate 2, a wiring groove 8a is formed in the silicon oxide film 41-1 and the silicon nitride film 41-2. At this time, using the resist pattern not shown here as a mask, the silicon nitride film 41-2 is etched, and the silicon oxide film 41-1 is further etched. In this etching, the surface layer of the lower sensor substrate 2 may be etched. After the etching is completed, the resist pattern is removed.

[FIG. 8C]
Next, as shown in FIG. 8C, each connection hole 23a having a depth as required is formed at the bottom of the wiring groove 8a. Each of these connection holes 23a is the same as in the first embodiment, and is formed at each depth reaching the upper part of the embedded wiring 27 or the embedded wiring 37 provided on the surface side of the sensor substrate 2. Thereafter, a procedure similar to the procedure described with reference to FIGS. 5A to 5C in the first embodiment is performed.

[FIG. 9A]
As described above, as shown in FIG. 9A, the isolation insulating film 24 having a laminated structure is formed on the inner walls of the wiring trench 8a and the connection hole 23a, and the inside is integrally embedded with copper (Cu) and the embedded wiring 27 or embedded The wiring 8 connected to the embedded wiring 37 and the through via 23 are formed.

[FIG. 9B]
Thereafter, as shown in FIG. 9B, a cap film 41-3 having an effect of preventing diffusion of copper (Cu) constituting the wiring 8 is formed so as to cover the wiring 8 and the silicon nitride film 41-2. Here, as the cap film 41-3, for example, a silicon nitride film is formed with a film thickness of 70 nm. Thus, the three layers of the silicon oxide film 41-1, the silicon nitride film 41-2, and the cap film 41-3 are laminated on the light receiving surface A of the sensor substrate 2.

  Next, a portion corresponding to the pixel region 4 in the three-layer laminated film is selectively etched away with respect to the peripheral region 7. As a result, an insulating pattern B is formed on the light receiving surface A corresponding to the peripheral region 7 by patterning the three-layered film. At this time, using the resist pattern not shown here as a mask, the cap film 41-3 and the silicon nitride film 41-2 made of silicon nitride are etched, and the etching conditions are changed to change the silicon oxide film 41-1. Etch. In the etching of the silicon oxide film 41-1, the light receiving surface A of the pixel region 4 is exposed by suppressing the damage to the sensor substrate 2 by performing wet etching.

[FIG. 10A]
Thereafter, as shown in FIG. 10A, an antireflection film 41-4 made of, for example, hafnium oxide (HfO ₂ ) and silicon oxide are formed on the light receiving surface A of the sensor substrate 2 in a state of covering the insulating pattern B of the peripheral region 7. An interface state suppressing film 41-5 made of (SiO ₂ ) is formed in this order. Thereby, on the light receiving surface A, the insulating layer 41 composed of the insulating pattern B, the antireflection film 41-4 covering the insulating pattern B, and the interface state suppressing film 41-5 is formed.

  The insulating layer 41 has a step structure in which the film thickness of the pixel region 4 is smaller than the film thickness of the peripheral region 7, and has a cavity structure that is thinned on the pixel region 4. In such a state, only the antireflection film 41-4 and the interface state suppression film 41-5 are arranged in the pixel region 4. On the other hand, in the peripheral region 7, an insulating layer 41 portion having a five-layer structure including the insulating pattern B, the antireflection film 41-4, and the interface state suppressing film 41-5 is disposed.

  Note that the thin film portion in the insulating layer 41 may be set as wide as possible without affecting the wiring 8, and the stepped shape of the insulating layer 41 deteriorates the application unevenness of the transparent flattening film to be formed later. This prevents the light incident on the photoelectric conversion unit 20 from being affected as in the first embodiment.

[FIG. 10B]
Next, as shown in FIG. 10B, an opening 41a for exposing the sensor substrate 2 is formed below the step of the insulating layer 41, and then the sensor substrate 2 is grounded on the insulating layer 41 in the pixel region 4 via the opening 41a. The light shielding film 16 is patterned. The light shielding film 16 is provided with a light receiving opening 16 a corresponding to each photoelectric conversion unit 20. The above steps are performed in the same procedure as that described with reference to FIG. 6C in the first embodiment. Further, such a light shielding film 16 may be removed in the upper part of the step of the insulating layer 41 and cover the lower part of the step so that the step of the insulating layer 41 can be reduced over a wide range. It is the same as the form.

[Fig. 7]
After the above, as shown in FIG. 7, the transparent protective film 17 made of a light-transmitting material is formed by a coating method such as a spin coating method so as to cover the light shielding film 16. Next, each color filter 18 corresponding to the photoelectric conversion unit 20 is formed on the transparent protective film 17, and each on-chip lens 19 corresponding to the photoelectric conversion unit 20 is formed thereon. Further, the exposed surface of the circuit board 9 is polished to make the circuit board 9 thin, and the via 33 is exposed to form the through via 33. Thereafter, a protective film 9c is formed on the circuit board 9 so as to cover the through via 33, and a pad opening 33a exposing the through via 33 is formed, thereby completing the solid-state imaging device 1-2.

<Effects of Second Embodiment>
The solid-state imaging device 1-2 having the above-described configuration is a back-illuminated type in which the wiring 8 is provided in the peripheral region 7 as in the solid-state imaging device of the first embodiment, and the pixel region 4 is formed on the light receiving surface A. The insulating layer 41 having a thin step structure is provided, and the on-chip lens 19 is provided thereon. Therefore, as in the first embodiment, it is possible to improve the light receiving characteristics in the photoelectric conversion unit 20 by reducing the distance between the on-chip lens 19 and the light receiving surface A while ensuring the pattern accuracy of the wiring 8. It is.

«Third embodiment»
<Configuration of solid-state imaging device>
(Example of providing embedded wiring with a step structure insulating layer and sensor substrate)
FIG. 11 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device 1-3 of the third embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-3 of the third embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device 1-3 of the third embodiment shown in FIG. 11 differs from the solid-state imaging device of the first embodiment described with reference to FIG. 2 in that the layer structure of the insulating layer 43 having a step structure and the wiring The other configuration is the same as that of the first embodiment.

  That is, the insulating layer 43 has a four-layer structure of an antireflection film 43-1, an interface state suppression film 43-2, an etching stop film 43-3, and a cap film 43-4 in order from the light receiving surface A side. The insulating layer 43 having such a four-layer structure is thinned into a two-layer structure of an antireflection film 43-1 and an interface state suppression film 43-2 in the pixel region 4, and thereby the pixel region 4 The step thickness structure is smaller than the thickness of the peripheral region 7.

  In the thick film portion of the peripheral region 7 in the insulating layer 43 having the above-described laminated structure, the etching stop film 43-3, the interface state suppression film 43-2, and the antireflection film 43-, which are lower than the cap film 43-4. 1 and a wiring groove in which the wiring 8 is provided is formed in the surface layer of the sensor substrate 2. That is, a wiring groove dug by etching is also formed in the surface layer of the sensor substrate 2, and the wiring 8 is embedded in the wiring groove. In addition, a through via 23 provided through the sensor substrate 2 is connected to the wiring 8.

<Method for Manufacturing Solid-State Imaging Device>
Next, a manufacturing method of the solid-state imaging device 1-3 having the above-described configuration will be described with reference to cross-sectional process diagrams of FIGS.

[FIG. 12A]
First, as shown in FIG. 12A, the process until the sensor substrate 2 and the circuit board are bonded together and the light receiving surface A side of the sensor substrate 2 is thinned as necessary is described with reference to FIG. 3A in the first embodiment. Do the same as Thereafter, on the light receiving surface A of the sensor substrate 2, for example, an antireflection film 43-1 made of hafnium oxide (HfO ₂ ), an interface state suppression film 43-2 made of silicon oxide (SiO ₂ ), and silicon nitride (SiN) Are formed in this order. The above three layers are formed as films constituting a part of the insulating layer (43) having the step structure described above.

  Thereafter, in the peripheral region 7 of the sensor substrate 2, an antireflection film 43-1, an interface state suppressing film 43-2, an etching stop film 43-3, and a wiring groove 8a ′ are formed in the surface layer of the sensor substrate 2. To do. At this time, etching is performed from the etching stop 43-3 to the surface layer of the sensor substrate 2 using a resist pattern not shown here as a mask. After the etching is completed, the resist pattern is removed.

[FIG. 12B]
Next, as shown in FIG. 12B, each connection hole 23a having a depth as required is formed in the bottom of the wiring groove 8a ′. Each of these connection holes 23a is the same as in the first embodiment, and is formed at each depth reaching the upper part of the embedded wiring 27 or the embedded wiring 37 provided on the surface side of the sensor substrate 2. Thereafter, a procedure similar to the procedure described with reference to FIGS. 5A to 5C in the first embodiment is performed.

[FIG. 12C]
Thus, as shown in FIG. 12C, the isolation insulating film 24 having a laminated structure is formed on the inner walls of the wiring trench 8a ′ and the connection hole 23a, and the interior of these is integrally embedded with copper (Cu) and the embedded wiring 27 or The wiring 8 connected to the embedded wiring 37 and the through via 23 are formed.

[FIG. 13A]
Thereafter, as shown in FIG. 13A, a cap film 43-4 having an effect of preventing diffusion of copper (Cu) constituting the wiring 8 is formed in a state of covering the wiring 8 and the etching stop film 43-3. Here, as a cap film, for example, a silicon nitride film is formed with a thickness of 70 nm. Thus, the four layers in which the antireflection film 43-1, the interface state suppressing film 43-2, the etching stop film 43-3, and the cap film 43-4 are laminated in this order on the light receiving surface A of the sensor substrate 2. An insulating layer 43 having a structure is formed. A silicon oxide film may be further formed on the cap film 43-4 made of the uppermost silicon nitride as necessary.

  After forming the insulating layer 43 and the wiring 8 having a stacked structure as described above, a portion corresponding to the pixel region 4 in the insulating layer 43 is selectively thinned, thereby forming a step structure in the insulating layer 43. At this time, using the resist pattern not shown here as a mask, the cap film 43-4 and the etching stop film 43-3 made of silicon nitride (SiN) are etched.

  As described above, on the light receiving surface A of the sensor substrate 2, the cavity region insulating layer 43 has a stepped structure in which the film thickness of the pixel region 4 is thinner than the film thickness of the peripheral region 7. It will be in the state provided. In such a state, only the antireflection film 43-1 and the interface state suppression film 43-2 are left in the pixel region 4. On the other hand, the insulating layer 43 having a four-layer structure is left as it is in the peripheral region 7.

  Note that the thin film portion in the insulating layer 43 may be set as wide as possible without affecting the wiring 8, whereby the stepped shape of the insulating layer 43 deteriorates application unevenness of the transparent flattening film to be formed later. This prevents the light incident on the photoelectric conversion unit 20 from being affected as in the first embodiment.

[FIG. 13B]
Next, as shown in FIG. 13B, an opening 43a for exposing the sensor substrate 2 is formed below the step of the insulating layer 43, and then the sensor substrate 2 is grounded on the insulating layer 43 in the pixel region 4 through the opening 43a. The light shielding film 16 is patterned. The light shielding film 16 is provided with a light receiving opening 16 a corresponding to each photoelectric conversion unit 20. The above steps are performed in the same procedure as that described with reference to FIG. 6C in the first embodiment. Further, such a light shielding film 16 may be removed in the upper part of the step of the insulating layer 43 and cover the lower part of the step so that the step of the insulating layer 43 can be reduced over a wide range. It is the same as the form.

[Fig. 11]
After the above, as shown in FIG. 11, the transparent protective film 17 made of a light-transmitting material is formed by a coating method such as a spin coating method so as to cover the light shielding film 16. Next, each color filter 18 corresponding to the photoelectric conversion unit 20 is formed on the transparent protective film 17, and each on-chip lens 19 corresponding to the photoelectric conversion unit 20 is formed thereon. Further, the exposed surface of the circuit board 9 is polished to make the circuit board 9 thin, and the via 33 is exposed to form the through via 33. Thereafter, a protective film 9c is formed on the circuit board 9 so as to cover the through via 33, and a pad opening 33a exposing the through via 33 is formed, thereby completing the solid-state imaging device 1-3.

<Effect of the third embodiment>
The solid-state imaging device 1-3 having the above-described configuration is a back-illuminated type in which the wiring 8 is provided in the peripheral region 7 as in the solid-state imaging device of the first embodiment, and the pixel region 4 is formed on the light receiving surface A. The insulating layer 43 having a thin step structure is provided, and the on-chip lens 19 is provided thereon. Therefore, as in the first embodiment, it is possible to improve the light receiving characteristics in the photoelectric conversion unit 20 by reducing the distance between the on-chip lens 19 and the light receiving surface A while ensuring the pattern accuracy of the wiring 8. It is. Further, similarly to the first embodiment, the light receiving surface A can be kept good without being exposed to etching damage.

  In the third embodiment, the configuration in which the wiring groove 8 a ′ for embedding the wiring 8 is provided in the sensor substrate 2 and the lower portion of the insulating layer 43 has been described. However, the wiring groove 8 a ′ may be formed only on the sensor substrate 2 and the wiring 8 completely embedded in the sensor substrate 2 may be used. Even in this case, the insulating layer 43 is ensured to have a film thickness necessary for covering the wiring 8 in the peripheral region 7, and a step structure in which the insulating layer 43 is thinned to a film thickness thinner than this in the pixel region 4. By doing so, the same effect can be obtained.

<< Fourth Embodiment >>
<Configuration of solid-state imaging device>
(Example of providing a stepped structure insulating layer and laminated wiring)
FIG. 14 is a principal cross-sectional view showing the configuration of the solid-state imaging device 1-4 of the fourth embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-4 according to the fourth embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device 1-4 of the fourth embodiment shown in FIG. 14 differs from the solid-state imaging device of the first embodiment described with reference to FIG. 2 in that the layer structure of the insulating layer 45 having a step structure and the wiring The other configurations are the same as those in the first embodiment.

  That is, the insulating layer 45 includes an antireflection film 45-1, an interface state suppressing film 45-2, an etching stop film 45-3, a cap film 45-4, and an interlayer film 45-5 made of silicon oxide in this order from the light receiving surface side. The five-layer structure. Such a five-layered insulating layer 45 is thinned in the pixel region 4 into a two-layer structure of an antireflection film 45-1 and an interface state suppression film 45-2. The step thickness structure is smaller than the thickness of the peripheral region 7.

  In the insulating layer 45 having the laminated structure as described above, in the thick film portion of the peripheral region 7, the through via 23 provided through the sensor substrate 2 extends to the surface of the etching stop film 45-3. .

  The wiring 47 is patterned on the thick film portion of the insulating layer 45 in the peripheral region 7. The wiring 47 is made of an electrically conductive material that can be etched, such as aluminum, and the through via 23 is formed through a connection hole provided in the cap film 45-4 and the interlayer film 45-5 that constitute the upper layer of the insulating layer 45. It is connected to the. Such wiring 47 is covered with an insulating protective film 49.

<Method for Manufacturing Solid-State Imaging Device>
Next, a method for manufacturing the solid-state imaging device 1-4 having the above-described configuration will be described with reference to cross-sectional process diagrams in FIGS.

[FIG. 15A]
First, as shown in FIG. 15A, the process until the sensor substrate 2 and the circuit board are bonded together and the light receiving surface A side of the sensor substrate 2 is thinned as necessary has been described with reference to FIG. 3A in the first embodiment. Do the same. Thereafter, on the light receiving surface A of the sensor substrate 2, for example, an antireflection film 45-1 made of hafnium oxide (HfO ₂ ), an interface state suppression film 45-2 made of silicon oxide (SiO ₂ ), and silicon nitride (SiN) Are formed in this order. The above three layers are formed as films constituting a part of the insulating layer (45) having the step structure described above.

  Thereafter, in the peripheral region 7 of the sensor substrate 2, the etching stop film 45-3, the interface state suppressing film 45-2, the antireflection film 45-1, the sensor substrate 2, and the interlayer insulating film 26 constituting the wiring layer 2a are formed. Each connection hole 23a having a depth as required is formed. Each of these connection holes 23 a is the same as that in the first embodiment, and is formed at each depth reaching the upper portion of the embedded wiring 27 or the embedded wiring 37.

[FIG. 15B]
Next, as shown in FIG. 15B, an isolation insulating film 24 having a laminated structure is formed on the inner wall of the connection hole 23a, and the inside thereof is embedded with copper (Cu), whereby embedded wiring 27 is formed in each connection hole 23a. The through via 23 connected to the embedded wiring 37 is formed. Such an isolation insulating film 24 and the through via 23 can be formed by a procedure similar to the procedure described with reference to FIGS. 5A to 5C in the first embodiment.

[FIG. 15C]
Next, as shown in FIG. 15C, as a cap film 45-4 having an effect of preventing diffusion of copper (Cu) constituting the through via 23 in a state of covering the through via 23 and the etching stop film 45-3, for example, a silicon nitride film Is formed with a film thickness of 70 nm. Further on this, a silicon oxide film is formed as an interlayer film 45-5. Thereby, the antireflection film 45-1, the interface state suppressing film 45-2, the etching stop film 45-3, the cap film 45-4, and the interlayer film 45-5 are formed on the light receiving surface A of the sensor substrate 2. An insulating layer 45 having a five-layer structure that is sequentially stacked is formed.

[FIG. 16A]
Thereafter, as shown in FIG. 16A, in the peripheral region 7, each connection hole 23b reaching the through via 23 is formed in the interlayer film 45-5 and the cap film 45-4. Thereafter, a wiring 47 connected to the through via 23 through the connection hole 23b is formed on the interlayer film 45-5. At this time, first, a conductive material film such as aluminum is formed on the interlayer film 45-5 by the sputtering film forming method, and then the conductive material film is etched using the resist pattern formed thereon as a mask. Thus, the wiring 47 formed by patterning the conductive material film is formed. After the above, a protective film 49 covering the wiring 47 is formed on the interlayer film 45-5 as necessary. The protective film 49 can also be a film constituting the insulating layer 45.

[FIG. 16B]
Next, as shown in FIG. 16B, a portion corresponding to the pixel region 4 in the insulating layer 45 is selectively thinned, thereby forming a step structure in the insulating layer 45. At this time, the protective film 49, the interlayer film 45-5, the cap film 45-4, and the etching stop film 45-3 are etched using a resist pattern not shown here as a mask.

  As described above, the cavity structure insulating layer 45 having a step structure in which the film thickness of the pixel region 4 is thinner than the film thickness of the peripheral region 7 is formed on the light receiving surface A of the sensor substrate. It will be in the provided state. In such a state, only the antireflection film 45-1 and the interface state suppression film 45-2 are left in the pixel region 4. On the other hand, the insulating layer 45 and the protective film 49 having a five-layer structure are left as they are in the peripheral region 7.

  Note that the thin film portion in the insulating layer 45 may be set as wide as possible without affecting the layout of the wiring 47, so that the stepped shape of the insulating layer 45 causes uneven application of the transparent flattening film to be formed later. It is the same as in the first embodiment to prevent the light incident on the photoelectric conversion unit 20 from being affected by the deterioration.

[FIG. 16C]
Next, as shown in FIG. 16C, an opening 45 a that exposes the sensor substrate 2 is formed below the step of the insulating layer 45, and is then grounded to the sensor substrate 2 via the opening 45 a on the insulating layer 45 in the pixel region 4. The light shielding film 16 is patterned. The light shielding film 16 is provided with a light receiving opening 16 a corresponding to each photoelectric conversion unit 20. The above steps are performed in the same procedure as that described with reference to FIG. 6C in the first embodiment. Further, such a light shielding film 16 may be removed in the upper part of the step of the insulating layer 45 and cover the lower part of the step so that the step of the insulating layer 45 can be reduced over a wide range. It is the same as the form.

[FIG. 14]
After the above, as shown in FIG. 14, the transparent protective film 17 made of a light-transmitting material is formed by a coating method such as a spin coating method so as to cover the light shielding film 16. Next, the color filters 18 of the respective colors corresponding to the photoelectric conversion unit 20 are formed on the transparent protective film 17, and the on-chip lens 19 corresponding to the photoelectric conversion unit 20 is further formed thereon. Further, the exposed surface of the circuit board 9 is polished to make the circuit board 9 thin, and the via 33 is exposed to form the through via 33. Thereafter, a protective film 9c is formed on the circuit board 9 so as to cover the through via 33, and a pad opening 33a exposing the through via 33 is formed. Further, if necessary, a pad opening that exposes the wiring 47 (not shown) is formed on the wiring 47 made of aluminum or the like to complete the solid-state imaging device 1-4.

<Effects of Fourth Embodiment>
The solid-state imaging device 1-4 having the above-described configuration is a back-illuminated type in which the wiring 47 is provided in the peripheral region 7 as in the solid-state imaging device of the first embodiment. The insulating layer 45 having a thin step structure is provided, and the on-chip lens 19 is provided thereon. Therefore, while the insulating layer 45 having a film thickness necessary for the configuration of the wiring 47 is left in the peripheral region 7, the distance between the on-chip lens 19 and the light receiving surface A is reduced in the pixel region 4 to receive light in the photoelectric conversion unit 20. It is possible to improve the characteristics. Further, similarly to the first embodiment, the light receiving surface A can be kept good without being exposed to etching damage.

≪6. Fifth embodiment >>
(Example of providing a share capacitor to connect the wiring in the sensor board)
FIG. 17 is a cross-sectional view of the principal part showing the configuration of the solid-state imaging device 1-5 of the fifth embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-5 of the fifth embodiment will be described based on the cross-sectional view of the main part.

  17 differs from the solid-state imaging device according to the first embodiment described with reference to FIG. 2 in the configuration of the through via 51 and the layer structure of the insulating layer 53. Other configurations are the same as those of the first embodiment.

  That is, the through via 51 is a so-called share capacitor that connects, for example, the embedded wiring 27 provided in the wiring layer 2a and the embedded wiring 37 provided in the wiring layer 9a. It is provided as a wiring for connecting to the embedded wiring 37. The through via 51 integrally formed as such wiring is connected to the embedded wiring 27 and the embedded wiring 37 on the bottom surfaces having different heights. Further, the through via 51 protrudes above the light receiving surface A of the sensor substrate 2, and the protruding upper portion is embedded in the insulating layer 53.

  The through via 51 also serving as the wiring is made of a conductive material embedded through the insulating insulating film 24 in the connection hole 51a provided through the sensor substrate 2 from the insulating layer 53 and further provided in the wiring layer 2a. It is configured.

The insulating layer 53 has a step structure in which the film thickness of the pixel region 4 is thinner than the film thickness of the peripheral region 7. For example, the insulating layer 53 is configured as a laminated film using different insulating materials as in the first embodiment. It is the same. As an example, the insulating layer 53 has a four-layer structure of an antireflection film 53-1, an interface state suppression film 53-2, an etching stop film 53-3, and a cap film 53-4 in this order from the light receiving surface side. For example, the antireflection film 53-1 is made of a hafnium oxide (HfO ₂ ) film. The interface state suppression film 53-2 is made of a silicon oxide (SiO ₂ ) film. The etching stop film 53-3 is made of silicon nitride (SiN). Further, the cap film 53-4 is made of silicon nitride (SiN).

  The insulating layer 53 having such a four-layer structure is thinned into a two-layer structure of an antireflection film 53-1 and an interface state suppression film 53-2 in the pixel region 4. Further, in the thick film portion of the peripheral region 7 in the insulating layer 53, the through via 51 is also extended as the above-described wiring into the connection hole 51a provided in the lower layer from the second etching stop film 53-3 from the upper layer. .

  The solid-state imaging device 1-5 having such a configuration is manufactured by forming 1 on both the embedded wiring 27 and the embedded wiring 37 in the formation of the connection hole 23a described with reference to FIG. 15A in the fourth embodiment. Patterning is performed so that two connection holes 51a are arranged. Next, by performing a procedure similar to the procedure described with reference to FIG. 15B, the through via 51 in which copper (Cu) is embedded in the connection hole 51a via the isolation insulating film 24 is embedded in the embedded wiring 27. It is formed as a wiring connected to the wiring 37. Next, by forming the cap film 53-4 and selectively removing the cap film 53-4 and the etching stop film 53-3 in the pixel region 4, the insulating layer 53 has a step structure. After the above, the same procedure as described in other embodiments is performed to form the light shielding film 16, the transparent protective film 17, the color filter 18, and the on-chip lens 19 having the light receiving openings 16a. Further, the circuit board 9 is thinned to expose the vias 33 to form the through vias 33, the protective film 9c is formed on the circuit board 9, and the pad openings 33a exposing the through vias 33 are formed. Complete device 1-5.

<Effect of Fifth Embodiment>
The solid-state imaging device 1-5 having the above-described configuration is a back-illuminated type in which a through via 51 as a wiring is provided in the peripheral region 7 as in the solid-state imaging device of the first embodiment. In the pixel region 4, the insulating layer 53 having a thin step structure is provided, and the on-chip lens 19 is provided on the insulating layer 53. Therefore, while leaving the insulating layer 53 having a film thickness necessary for the configuration of the through via 51 as the wiring in the peripheral region 7, the distance between the on-chip lens 19 and the light receiving surface A is reduced in the pixel region 4, and the photoelectric conversion unit. The light receiving characteristics at 20 can be improved. Further, similarly to the first embodiment, the light receiving surface A can be kept good without being exposed to etching damage.

  In the first to fifth embodiments described above, the configuration in which the present technology is applied to a solid-state imaging device having a three-dimensional structure as an example of a back-illuminated solid-state imaging device has been described. However, the present technology is not limited to a three-dimensional structure, and can be widely applied to back-illuminated solid-state imaging devices. The insulating layer having a step structure is not limited to the stacked structure described in each embodiment, and various stacked structures suitable for forming a wiring and improving light receiving characteristics can be applied.

≪7. Example of electronic equipment using solid-state imaging device >>
The solid-state imaging device according to the present technology described in the above embodiment is applied to an electronic device such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. Can be applied.

  FIG. 18 is a configuration diagram of a camera using a solid-state imaging device as an example of an electronic apparatus according to the present technology. The camera according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 90 includes a solid-state imaging device 91, an optical system 93 that guides incident light to the light receiving sensor unit of the solid-state imaging device 91, a shutter device 94, a drive circuit 95 that drives the solid-state imaging device 91, and the solid-state imaging device 91. And a signal processing circuit 96 for processing the output signal.

  As the solid-state imaging device 91, the solid-state imaging device having the configuration described in the above-described embodiment is applied. The optical system (optical lens) 93 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 91. Thereby, signal charges are accumulated in the solid-state imaging device 91 for a certain period. Such an optical system 93 may be an optical lens system including a plurality of optical lenses. The shutter device 94 controls the light irradiation period and the light shielding period for the solid-state imaging device 91. The drive circuit 95 supplies drive signals to the solid-state imaging device 91 and the shutter device 94, and controls the signal output operation to the signal processing circuit 96 of the solid-state imaging device 91 and the shutter device by the supplied drive signal (timing signal). 94 shutter operation is controlled. That is, the drive circuit 95 performs a signal transfer operation from the solid-state imaging device 91 to the signal processing circuit 96 by supplying a drive signal (timing signal). The signal processing circuit 96 performs various signal processing on the signal transferred from the solid-state imaging device 91. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  According to the electronic device according to the present embodiment described above, in the electronic device having an imaging function by using the solid-state imaging device having good light receiving characteristics of any of the first to fifth embodiments described above. High-definition imaging and downsizing can be achieved.

  In addition, this technique can also take the following structures.

(1)
A sensor substrate having a pixel region in which photoelectric conversion portions are arrayed;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit in the sensor substrate;
An insulating layer provided on the light receiving surface and having a step structure that is thinner than a film thickness of a peripheral region provided on the outside of the pixel region;
Wiring provided in the peripheral region on the light receiving surface side;
A solid-state imaging device comprising: an on-chip lens provided at each position corresponding to the photoelectric conversion unit on the insulating layer.

(2)
The solid-state imaging device according to (1), wherein the wiring is provided as an embedded wiring embedded in the insulating layer.

(3)
The solid-state imaging device according to (1) or (2), wherein the wiring is provided as an embedded wiring embedded on the light receiving surface side of the sensor substrate.

(4)
A light-shielding film having a light-receiving opening corresponding to the photoelectric conversion portion is provided between the insulating layer and the on-chip lens in the pixel region. (Solid according to any one of (1) to (3)) Imaging device.

(5)
The insulating layer is a laminated structure configured using different materials,
The solid-state imaging device according to any one of (1) to (4), wherein a film that forms an upper layer portion of the laminated structure is removed from the insulating layer in the pixel region.

(6)
The insulating layer includes an insulating pattern patterned in the peripheral region, and an insulating film provided on the sensor substrate so as to cover the insulating pattern,
The solid-state imaging device according to any one of (1) to (4), wherein the insulating film is provided in the pixel region.

(7)
The solid-state imaging device according to any one of (1) to (6), wherein a circuit board having the drive circuit is bonded to the front surface side of the sensor board.

(8)
The sensor substrate is provided with a through via that connects the wiring on the light receiving surface side and the driving circuit disposed on the front surface side. (1) to (7) apparatus.

(9)
The solid-state imaging device according to (8), wherein the wiring is formed integrally with the through via.

(10)
The solid-state imaging device according to (4), wherein the light shielding film is grounded to the sensor substrate through an opening formed in a thin film portion of the insulating layer.

(11)
Arraying photoelectric conversion portions in a pixel region set on the sensor substrate;
Forming a driving circuit on the surface side opposite to the light receiving surface for the photoelectric conversion unit in the sensor substrate;
Forming an insulating layer on the light receiving surface of the sensor substrate;
Forming a wiring in a peripheral region provided outside the pixel region on the light receiving surface side;
After forming the insulating layer and the wiring, forming a step structure in the insulating layer by selectively thinning a portion corresponding to the pixel region in the insulating layer with respect to the peripheral region;
The manufacturing method of a solid-state imaging device including forming an on-chip lens in each position corresponding to the photoelectric conversion part on the insulating layer in which the level difference structure was formed.

(12)
When forming the wiring, the wiring is formed as an embedded wiring embedded in the insulating layer. (11) The method for manufacturing a solid-state imaging device according to (11).

(13)
When forming the insulating layer, the insulating layer is formed as a laminated structure composed of different materials,
When the step structure is formed in the insulating layer, the film constituting the upper layer portion of the laminated structure in the insulating layer is selectively removed with respect to the film constituting the lower layer portion (11) or (12) The manufacturing method of the solid-state imaging device of description.

(14)
A sensor substrate having a pixel region in which photoelectric conversion portions are arrayed;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit in the sensor substrate;
An insulating layer provided on the light receiving surface and having a step structure that is thinner than a film thickness of a peripheral region provided on the outside of the pixel region;
Wiring provided in the peripheral region on the light receiving surface side;
An on-chip lens provided at each position corresponding to the photoelectric conversion unit on the insulating layer;
An electronic apparatus comprising an optical system that guides incident light to the photoelectric conversion unit.

  1-1, 1-2, 1-3, 1-4, 1-5 ... solid-state imaging device, 2 ... sensor substrate, 4 ... pixel region, 7 ... peripheral region, 8, 47 ... wiring, 9 ... circuit substrate, DESCRIPTION OF SYMBOLS 10-13 ... Drive circuit, 14, 41, 43, 45, 53 ... Insulating layer, 16 ... Light shielding film, 16a ... Light-receiving opening, 19 ... On-chip lens, 20 ... Photoelectric conversion part, 23, 51 ... Through-via (wiring) ), 90 ... electronic equipment, 93 ... optical system, A ... light receiving surface, B ... insulation pattern

Claims (14)

A sensor substrate having a pixel region in which photoelectric conversion portions are arrayed;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit in the sensor substrate;
An insulating layer provided on the light receiving surface and having a step structure that is thinner than a film thickness of a peripheral region provided on the outside of the pixel region;
Wiring provided in the peripheral region on the light receiving surface side;
A solid-state imaging device comprising on-chip lenses provided at positions corresponding to the photoelectric conversion unit on the insulating layer. The solid-state imaging device according to claim 1, wherein the wiring is provided as an embedded wiring embedded in the insulating layer. The solid-state imaging device according to claim 1, wherein the wiring is provided as an embedded wiring embedded on a light receiving surface side of the sensor substrate. The solid-state imaging device according to claim 1, wherein a light shielding film having a light receiving opening corresponding to the photoelectric conversion unit is provided between the insulating layer and the on-chip lens in the pixel region. The insulating layer is a laminated structure configured using different materials,
The solid-state imaging device according to claim 1, wherein in the pixel region, a film constituting an upper layer portion of the laminated structure is removed from the insulating layer. The insulating layer includes an insulating pattern patterned in the peripheral region, and an insulating film provided on the sensor substrate so as to cover the insulating pattern,
The solid-state imaging device according to claim 1, wherein the insulating film is provided in the pixel region. The solid-state imaging device according to claim 1, wherein a circuit board having the drive circuit is bonded to a front surface side of the sensor substrate. The solid-state imaging device according to claim 1, wherein the sensor substrate is provided with a through via that connects the wiring on the light receiving surface side and the driving circuit disposed on the front surface side. The solid-state imaging device according to claim 8, wherein the wiring is formed integrally with the through via. The solid-state imaging device according to claim 4, wherein the light shielding film is grounded to the sensor substrate through an opening formed in a thin film portion of the insulating layer. Arraying photoelectric conversion portions in a pixel region set on the sensor substrate;
Forming a driving circuit on the surface side opposite to the light receiving surface for the photoelectric conversion unit in the sensor substrate;
Forming an insulating layer on the light receiving surface of the sensor substrate;
Forming a wiring in a peripheral region provided outside the pixel region on the light receiving surface side;
After forming the insulating layer and the wiring, forming a step structure in the insulating layer by selectively thinning a portion corresponding to the pixel region in the insulating layer with respect to the peripheral region;
The manufacturing method of a solid-state imaging device including forming an on-chip lens in each position corresponding to the photoelectric conversion part on the insulating layer in which the level difference structure was formed. The method of manufacturing a solid-state imaging device according to claim 11, wherein when forming the wiring, the wiring is formed as an embedded wiring embedded in the insulating layer. When forming the insulating layer, the insulating layer is formed as a laminated structure composed of different materials,
The solid-state imaging device according to claim 11, wherein when the step structure is formed in the insulating layer, the film constituting the upper layer portion of the laminated structure in the insulating layer is selectively removed with respect to the film constituting the lower layer portion. Manufacturing method. A sensor substrate having a pixel region in which photoelectric conversion portions are arrayed;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit in the sensor substrate;
An insulating layer provided on the light receiving surface and having a step structure that is thinner than a film thickness of a peripheral region provided on the outside of the pixel region;
Wiring provided in the peripheral region on the light receiving surface side;
An on-chip lens provided at each position corresponding to the photoelectric conversion unit on the insulating layer;
An electronic apparatus comprising an optical system that guides incident light to the photoelectric conversion unit.

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