JP2013026431A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax an electric field to a bit line of a target cell caused by influences of potential of a word line adjacent to a word line of the target cell.SOLUTION: A semiconductor device has: an active region formed on a semiconductor substrate 100 and provided for forming a semiconductor element 101; element isolation regions (an STI 102 and an NF 104) formed in the semiconductor substrate 100 and provided for isolating the active region; and cavities 105 provided in the element isolation regions (the STI 102 and the NF 104).

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an element isolation region for isolating an active region for forming an element and a manufacturing method thereof.

  A structure that isolates an active region of a semiconductor device is called an element isolation region, and is generally separated by a shallow trench, and thus has a structure called Shallow Trench Isolation (STI). In many cases, elements are separated.

  In an element isolation structure in a semiconductor device, STI is generally used. In this STI, after a groove for separating elements is formed, an insulating film is embedded in the groove to insulate the element (see, for example, JP 2010-287774 A (Patent Document 1)). In this case, the depth of the groove is set to a depth at which the active region isolated by STI can be electrically isolated.

  In some cases, if the manufacturing circuit pattern has a repetitive structure, the STI trench is thinly covered with an insulating film, and then the same material as that of the gate electrode is embedded to electrically insulate the trench lower region. A method of applying a voltage has also been proposed recently (see, for example, 2008_IEDM_p1-4_6F2 buried wordline DRAM cell for 40 nm and beyond_T. Schloesser etal (Qimonda) (Non-patent Document 1)).

  In the former structure in which the STI is embedded with an insulating film, it is generally embedded in a CVD oxide film. However, even in this structure, for example, when a highly integrated memory device such as a DRAM is miniaturized, data is stored. Depending on the operating voltage conditions of the bit line of the target cell and the word line (Neighbor Word Line (NWL)) of the adjacent cell, the electric lines of force that pass through the STI oxide film (generally, the relative dielectric constant: 3.8-4.2) There is a problem in that it affects the electrostatic potential of the bit line of the target cell and affects the fluctuation of the threshold voltage and the electric field strength of the p / n junction.

  On the other hand, in the latter, an insulating gate (Isolation Gate (IG)) is provided instead of a normal STI in a region for isolating elements described in Non-Patent Document 1, and the lower part of the IG is electrically connected to the lower part. A method of insulating is proposed.

  However, when a bias that electrically insulates the lower part of the IG groove is applied, the influence of the electrostatic potential of the semiconductor layer of the bit line of the adjacent cell affects the transistor characteristics of the bit line. It becomes remarkable with miniaturization.

  For example, when isolating an n-ch transistor in a P-Well, a negative (−) bias is applied to the IG, and the semiconductor layer under the IG is depleted and electrically insulated. Since this IG voltage is directly applied to the semiconductor layer of the bit line of the target cell, there is a problem in that the transistor characteristics vary depending on the IG bias conditions.

JP 2010-287774 A

2008_IEDM_p1-4_6F2 buried wordline DRAM cell for 40nm and beyond _T.Schloesser etal (Qimonda)

  The present invention solves the above-described problems of the prior art, and its object is to alleviate the electric field applied to the bit line of the target cell due to the influence of the potential of the word line adjacent to the word line of the target cell. An object of the present invention is to provide a possible semiconductor device and a manufacturing method thereof.

A semiconductor device according to the present invention includes:
An active region formed on a semiconductor substrate for forming a semiconductor element;
An element isolation region formed in the semiconductor substrate for isolating the active region;
It has a cavity provided in the element isolation region.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
Forming an active region for forming a semiconductor element on a semiconductor substrate;
Forming an element isolation region for isolating the active region in the semiconductor substrate;
A cavity is formed in the element isolation region.

  According to the present invention, the electric field applied to the bit line of the target cell due to the influence of the potential of the word line adjacent to the word line of the target cell can be reduced.

It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the effect by embodiment of this invention.

  Embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
Initially, with reference to FIGS. 1-5, the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention is demonstrated. 1 to 5, (a) is a plan view, (b) is a vertical sectional view of a word line (Word-Line (WL)), and (c) is a vertical direction of a bit line (Bit-Line (BL)). Cross-sectional views are shown respectively.

  As shown in FIG. 1, in order to perform patterning for forming an element isolation region (shallow trench isolation (STI)) 102 for isolating an element (cell array transistor) 101 in a semiconductor substrate 100, a photoresist is used. Application and exposure are performed.

  At this time, the isolation portion between adjacent bit lines (N-BL) 103b in the WL vertical direction simultaneously with the STI 102 of the isolation portion with the adjacent bit line (N-BL) 103b adjacent to the bit line (BL) 103a of the target cell. Both of them (referred to herein as normal field (NF) 104) may be patterned simultaneously or separately in a line pattern.

  Next, dry etching for forming the STI 102 and the NF 104 is performed, and the inner walls of the STI 102 and the NF 104 are covered with a thin inner wall oxide film 105.

  Next, the STI 102 and the NF 104 are filled with a buried insulating film (for example, SiN film) 106 and planarized.

  Next, a cell array transistor 101 having a trench gate structure is formed.

  First, a mask film (not shown) is formed to form a WL (word line) 107 pattern, and then the WL 107 pattern is baked by photolithography to pattern the mask film.

  Next, after removing the resist, a pattern of WL 107 is formed inside the semiconductor layer through a self-alignment process using a patterned mask film.

  Next, after cleaning, a gate insulating film 108 of WL107 is formed. Here, gate oxidation (for example, 6 nm thickness) is performed using a high-temperature rapid thermal process (RTP).

  A polysilicon gate electrode may be formed as it is, but in FIG. 1, a method for forming the buried WL 107 will be described.

  In order to form the embedded WL 107, TiN 109 and W110 are embedded, and an electrode portion of the embedded WL 107 is formed at a desired depth.

  Next, a cap insulating film 111 (for example, a CVD oxide film) is buried in the upper portion and planarized.

  Thereafter, a BL contact 103 and a bit contact interlayer 112 for forming a bit contact (Bit-Contact (BC)) to be described later are deposited.

  Next, as shown in FIG. 2, the bit contact (BC) 113 is opened.

  First, a BC pattern is patterned on the bit contact interlayer film 112 by photolithography using a resist.

  Next, the bit contact (BC) 113 is opened by a dry etching process. At this time, the bit contact (BC) 113 is opened so that the opening end overlaps the WL 107 (field portion) and the surface of the buried insulating film 106 embedded in the surfaces of the STI 102 and the NF 104 is exposed.

  Next, as shown in FIG. 3, a hollow structure (Air Gap) structure is formed in the STI 102 and the NF 104.

  First, after opening the bit contact (BC) 113 as described above, cleaning is performed.

  Thereafter, in order to remove the buried insulating film 106 buried in the STI 102 and the NF 104, the buried insulating film 106 is removed with hot phosphoric acid 114 to form a cavity 115. In this way, an Air-Gap separation structure is formed.

  Next, after forming the Air-Gap isolation structure, as shown in FIG. 4, selective epitaxial growth is performed on the bit contact (BC) 113 to form an epitaxial growth layer 116 and the bottom of the bit contact (BC) 113 is buried. At this time, the opening of the buried insulating film (SIN film) 106 removed by the hot phosphoric acid 114 on the surfaces of the STI 102 and the NF 104 is buried by overgrowth of selective epitaxial growth.

  Next, as shown in FIG. 5, impurities are ion-implanted into the epitaxial growth layer 116 formed in the bit contact (BC) 113, heat treatment is performed, and then metal wiring for forming the bit line (BL) 103 is performed. . Here, a TiN / W film is formed, and wiring patterning of the BL 103 is performed.

  In this manner, a semi-isotopic device having a hollow element isolation structure in the STI 102 and the NF 104 is completed.

  As shown in FIG. 5, this semiconductor device is formed on a semiconductor substrate 100, and an active region for forming a semiconductor element 101 and an element isolation region (in the semiconductor substrate 100 for isolating the active region ( STI 102, NF 104) and a cavity 105 provided in the element isolation region (STI 102, NF 104).

  The element isolation region (STI102, NF104) is formed in a groove shape, and an inner wall oxide film 105 is formed on the inner wall of the element isolation region (STI102, NF104).

  The relative dielectric constant (ideally 1.0) of the cavity portion 105 is lower than the relative dielectric constant (about 3.8 to 4.2) of the inner wall oxide film 105.

  Under such a structure, the semiconductor element is a cell array transistor 101 connected to the word line 107 and the bit line 103 of the target cell (Unit Cell). The cavity 105 relaxes the electric field applied to the bit line (aBL) 103a due to the influence of the potential of the adjacent word line (N-aWL) 107b adjacent to the word line (aWL) 107a. Further, the cavity 105 reduces the junction leakage current of the word line (aWL) 107a.

(Second Embodiment)
Initially, with reference to FIGS. 6-11, the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention is demonstrated. 6 to 11, (a) is a plan view, (b) is a vertical sectional view of a word line (Word-Line (WL)), and (c) is a vertical direction of a bit line (Bit-Line (BL)). Cross-sectional views are shown respectively.

  First, as shown in FIG. 6, in order to perform patterning for forming shallow trench isolation (STI) 201 for element isolation in a semiconductor substrate 200, a photoresist is applied and fog light is applied. At this time, the adjacent bit line (N-BL) 202b in the WL vertical direction simultaneously with the STI 201 of the separation part from the adjacent bit line (N-BL) 202b adjacent to the bit line (aBL) 202a of the target cell (Unit Cell) Both of the separation portions (referred to herein as normal field (NF) 203) may be patterned at the same time, or may be separately formed in a line pattern.

  Next, dry etching for forming the STI 201 and the NF 203 is performed to form the STI trench 204 and the NF trench 205. At this time, the groove shapes of the STI trench 204 and the NF trench 205 are formed in a bowing shape in which the opening is slightly narrowed. In recent miniaturized devices, the separation width of STI 201 and NF 203 has become 100 nm or less. Here, an example of 50 nm is shown.

  Next, as shown in FIG. 7, the inner wall oxidation is performed on the bowed STI trench 204 and the NF trench 205 (element isolation structure portion) shown in FIG. An inner wall oxide film 206 is formed on the inner walls of the 204 and NF trenches 205. The thickness of the inner wall oxide film 206 is, for example, 10 nm. As a result, the element isolation openings of the STI trench 204 and the NF trench 205 are about 45 nm.

  Next, as shown in FIG. 8, an insulating film 207 is deposited on the surface of the inner wall oxide film 206 formed on the inner walls of the STI trench 204 and the NF trench 205. The insulating film 207 is, for example, a CVD oxide film or a plasma oxide film, and the film thickness is about 30 nm. At this time, since the element isolation openings of the STI trench 204 and the NF trench 205 are narrow, the opening is closed first, and the formation of the insulating film 207 is completed with the cavity remaining inside. In this way, the STI 201 and the NF 203 having the cavity 208 are completed. The insulating film 207 may be a CVD-SiN film or a plasma SiN film depending on circumstances.

  Next, after the STI 201 and NF 203 having the cavity 208 are completed, a cell array transistor 209 having a trench gate structure is formed as shown in FIG.

  First, a mask film (not shown) is formed to form a pattern of WL210, and then the pattern of WL210 is baked by photolithography to pattern the mask film.

  After removing the resist, a pattern of WL210 is formed inside the semiconductor layer by a self-alignment process using the patterned mask film.

  After cleaning, a gate insulating film 210 of WL210 is formed. Here, gate oxidation (for example, 6 nm thick) is performed using a high-temperature rapid thermal process (RTP). Although a polysilicon gate electrode may be formed as it is, a method for forming the buried WL 210 will be described with reference to FIG.

  In order to form the embedded WL 210, TiN 211 and W 212 are embedded, and an electrode portion of the embedded WL 210 is formed at a desired depth.

  Next, a cap insulating film 213 (here, a CVD oxide film) is buried in the upper portion and planarized.

  Thereafter, a bit contact interlayer SiN film 214 and a bit contact interlayer oxide film 215 for forming a BL line 103 and a bit contact (Bit-Contact (BC)) described later are deposited.

  Next, as shown in FIG. 10, the bit contact (BC) 216 is opened.

  First, a BC pattern is patterned on the bit contact interlayer oxide film 215 by photolithography using a resist.

  Next, the bit contact (BC) 216 is opened by a dry etching process.

  Thereafter, the bit contact interlayer SiN film 214 is once etched and stopped so that the bit contact (BC) 216 does not protrude from the semiconductor layer, and then a bit contact SW film (SiN film sidewall) 217 is formed, and the bit contact interlayer SiN The film 214 is etched and a bit contact (BC) 216 is opened.

  Next, as shown in FIG. 11, impurities are ion-implanted into the bit contact (BC) 216, heat treatment is performed, and then metal wiring for forming the bit line (BL) 202 is performed. Here, a TiN / W film is formed, and wiring patterning of the bit line (BL) 202 is performed. At this time, polysilicon doped with impurities may be used for connection with the bit contact (BC) 216. As a result, a semiconductor device having a hollow element isolation structure in STI 201 and NF 203 is completed.

  As shown in FIG. 11, this semiconductor device is formed on a semiconductor substrate 200, and an active region for forming a semiconductor element 201 and an element isolation region (in the semiconductor substrate 200, for isolating the active region). STI 201, NF 203) and a cavity 208 provided in the element isolation region (STI 201, NF 203).

  The element isolation region (STI201, NF203) is formed in a bow shape with a narrow opening, and an inner wall oxide film 206 is formed on the inner wall of the element isolation region (STI201, NF203). An insulating film 207 is formed on the surface.

  The relative dielectric constant (ideally 1.0) of the cavity 208 is lower than the relative dielectric constant (about 3.8 to 4.2) of the inner wall oxide film 206.

  Under such a structure, the semiconductor element is a cell array transistor 209 connected to the word line 210 and the bit line 202 of the target cell (Unit Cell). The cavity 208 relieves an electric field applied to the bit line (aBL) 202a due to the influence of the potential of the adjacent word line (N-aWL) 210b adjacent to the word line (aWL) 210a. Further, the cavity 208 reduces the junction leakage current of the word line (aWL) 210a.

  Next, effects of the embodiment of the present invention will be described with reference to FIG. Here, (a) shows the on-current characteristics of the cell array transistor characteristics, and (b) shows the junction leakage current of the cell array transistor characteristics.

  As shown in FIG. 12A, by using the present invention, it is possible to suppress a decrease due to the influence of the adjacent WL of the ON current of the cell array transistor accompanying the miniaturization of the device. Further, the electric field of the target bit line (BL) can be reduced due to the influence of the potential of the adjacent word power (WL).

  Furthermore, as shown in FIG. 12B, junction leakage current can be improved by using the present invention.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on the Example, this invention is not limited to the said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.

100 Semiconductor substrate 101 Cell array transistor 102 STI
103 bit line (BL)
104 NF
105 inner wall oxide film 106 buried insulating film 107 word line (WL)
108 Gate insulating film 109 TiN
110 W
111 Cap insulating film 112 Bit contact interlayer film 113 Bit contact (BC)
114 Hot phosphoric acid 115 Cavity 116 Epitaxial growth layer 200 Semiconductor substrate 201 STI
202 bit line (BL)
203 NF
204 STI trench 205 NF trench 206 Inner wall oxide film 207 Insulating film 208 Cavity 209 Cell array transistor 210 Word line (WL)
211 TiN
212 W
213 Cap insulating film 214 Bit contact interlayer SiN film 215 Bit contact interlayer oxide film 215
216 bit contact (BC)
217 Bit contact SW film

Claims (16)

An active region formed on a semiconductor substrate for forming a semiconductor element;
An element isolation region formed in the semiconductor substrate for isolating the active region;
A semiconductor device having a cavity provided in the element isolation region. The element isolation region is formed in a groove shape,
The semiconductor device according to claim 1, wherein an inner wall oxide film is formed on an inner wall of the element isolation region. The element isolation region is formed in a bow shape with a narrow frontage,
An inner wall oxide film is formed on the inner wall of the element isolation region,
The semiconductor device according to claim 1, wherein an insulating film is formed on a surface of the inner wall oxide film.   4. The semiconductor device according to claim 2, wherein a relative dielectric constant of the hollow portion is lower than a relative dielectric constant of the inner wall oxide film. The semiconductor element is a cell array transistor connected to a word line and a bit line,
5. The semiconductor device according to claim 1, wherein the hollow portion relaxes an electric field applied to the bit line due to an influence of a potential of a word line adjacent to the word line. The semiconductor element is a cell array transistor connected to a word line and a bit line,
5. The semiconductor device according to claim 1, wherein the hollow portion reduces a junction leakage current of the word line. 6. Forming an active region for forming a semiconductor element on a semiconductor substrate;
Forming an element isolation region for isolating the active region in the semiconductor substrate;
A method of manufacturing a semiconductor device, wherein a cavity is formed in the element isolation region. Forming the element isolation region in a groove shape;
8. The method of manufacturing a semiconductor device according to claim 7, wherein an inner wall oxide film is formed on an inner wall of the element isolation region. Forming the element isolation region into a bowing shape with a narrow opening;
Forming an inner wall oxide film on the inner wall of the element isolation region;
8. The method of manufacturing a semiconductor device according to claim 7, wherein an insulating film is formed on a surface of the inner wall oxide film.   10. The opening of the element isolation region is closed by forming the insulating film on the surface of the inner wall oxide film, whereby the cavity is formed in the element isolation region. The manufacturing method of the semiconductor device as described in 2. above.   The method for manufacturing a semiconductor device according to claim 9, wherein the insulating film is a CVD oxide film or a plasma oxide film.   12. The method of manufacturing a semiconductor device according to claim 7, wherein a relative dielectric constant of the hollow portion is lower than a relative dielectric constant of the inner wall oxide film. The semiconductor element is a cell array transistor connected to a word line and a bit line,
13. The cavity according to any one of claims 7 to 12, wherein the cavity is formed in order to reduce an electric field applied to the bit line due to an influence of a potential of a word line adjacent to the word line. Semiconductor device manufacturing method. The semiconductor element is a cell array transistor connected to a word line and a bit line,
13. The method of manufacturing a semiconductor device according to claim 7, wherein the hollow portion is formed in order to reduce a junction leakage current of the word line. After forming the inner wall oxide film on the inner wall of the element isolation region, the element isolation region is buried and buried with a buried insulating film,
Forming a bit contact interlayer for forming the bit line on the surface of the semiconductor substrate;
Opening the bit contact interlayer so that a part of the buried insulating film is exposed from the surface of the element isolation region;
The semiconductor device according to claim 13 or 14, wherein the cavity is formed by removing the buried insulating film buried in the element isolation region through the exposed surface of the element isolation region. Device manufacturing method.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the removal of the buried insulating film is performed with hot phosphoric acid.

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