JP2013025827A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of enhancing reliability of data.SOLUTION: A semiconductor memory device comprises: a memory cell array that includes m pages, where m is a natural number; and a controlling circuit for controlling writing operation. The controlling circuit performs the writing operation of a memory cell of an n-th page, where n is a natural number satisfying 1≤n≤m, and, in a case where memory cells of from (n+1)-th to m-th pages hold data that have threshold values different from those of erased states thereof, subsequently outputs a failure signal.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  There is known a NAND flash memory that can erase a plurality of blocks at once. The NAND flash memory is generally programmed through a program loop having a program section and a verification section.

JP 2010-20891 A

  Embodiments provide a semiconductor memory device capable of improving data reliability.

  According to the semiconductor memory device of the present embodiment, a memory cell array including m pages (m is a natural number) and a control circuit for controlling a write operation are provided, and the nth page (a natural number satisfying 1 ≦ n ≦ m). ), When the memory cells of the (n + 1) th to mth pages hold data having a threshold value different from the erased state, the control circuit outputs a failure. .

1 is a block diagram showing a semiconductor memory device according to a first embodiment. The figure which shows the threshold value distribution of the memory cell of 1st Embodiment. The flowchart figure which shows the write-in operation | movement of the control part of 1st Embodiment. The flowchart figure which shows the write-in operation | movement of the control part of 2nd Embodiment. The flowchart figure which shows the write-in operation | movement of the control part of 3rd Embodiment.

(First embodiment)
Next, a first embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[Configuration of Semiconductor Memory Device]
The semiconductor memory device according to the first embodiment will be described with reference to the block diagram of FIG.

1. Overall Configuration As shown in FIG. 1, the semiconductor memory device according to this embodiment includes a memory cell array 1, row data 2, a driver circuit 3, a voltage generation circuit 4, a data input / output circuit 5, a control unit 6, and a source line driver circuit 7. And a sense amplifier 8.

1-1. Configuration example of the memory cell array 1
The memory cell array 1 includes blocks BLK0 to BLKs including a plurality of nonvolatile memory cells MT (s is a natural number). Each of the blocks BLK0 to BLKs includes a plurality of NAND strings 11 in which nonvolatile memory cells MT are connected in series. Each of the NAND strings 11 includes, for example, 64 memory cells MT and select transistors ST1 and ST2.

  The memory cell MT can hold binary or higher data. The structure of the memory cell MT includes a floating gate (charge conductive layer) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. FG structure including The structure of the memory cell MT may be a MONOS type. The MONOS type includes a charge storage layer (for example, an insulating film) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film (hereinafter, referred to as a dielectric constant higher than the charge storage layer). And a control gate formed on the block layer.

  The control gate of the memory cell MT is electrically connected to the word line WL, the drain is electrically connected to the bit line BL, and the source is electrically connected to the source line SL. Memory cell MT is an n-channel MOS transistor. The number of memory cells MT is not limited to 64, but may be 128, 256, 512, etc., and the number is not limited.

  The adjacent memory cells MT share the source and drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cells MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

  The control gates of the memory cells MT in the same row are commonly connected to any of the word lines WL0 to WL63, and the gate electrodes of the select transistors ST1 and ST2 of the memory cells MT in the same row are connected to the select gate lines SGD1 and SGS1, respectively. Commonly connected. For simplification of description, the word lines WL0 to WL63 may be simply referred to as word lines WL in the following when they are not distinguished. Further, the drains of the select transistors ST1 in the same column in the memory cell array 1 are commonly connected to any one of the bit lines BL1 to BL (n + 1). Hereinafter, the bit lines BL1 to BL (n + 1) are collectively referred to as a bit line BL (n: natural number) unless they are distinguished. The sources of the selection transistors ST2 are commonly connected to the source line SL.

  Data is collectively written in the plurality of memory cells MT connected to the same word line WL, and this unit is called a page. Further, data is erased collectively from the plurality of memory cells MT in units of blocks BLK.

1-2. About threshold distribution of memory cell MT
The threshold distribution of the memory cell MT will be described with reference to FIG. FIG. 2 is a graph in which the horizontal axis represents the threshold distribution (voltage) and the vertical axis represents the number of memory cells MT.

  As shown in the drawing, each memory cell MT can hold, for example, binary (2-levels) data (1-bit data). That is, the memory cell MT can hold two types of data “1” and “0” in ascending order of the threshold voltage Vth.

  The threshold voltage Vth0 of “1” data in the memory cell MT is Vth0 <V01. The threshold voltage Vth1 of “0” data is V01 <Vth1. Thus, the memory cell MT can hold 1-bit data of “0” data and “1” data according to the threshold value. The memory cell MT is set to “1” data (for example, negative voltage) in the erased state, and is set to a positive threshold voltage by writing data and injecting charge into the charge storage layer.

1-3. About row decoder 2
Returning to FIG. 1, the row decoder 2 will be described. The row decoder 2 includes a block decoder 20 and transfer transistors (N channel MOS transistors) 21 to 23. The block decoder 20 decodes a block address given from the control unit 6 during a data write operation, a read operation, and an erase operation, and selects a block BLK based on the result. The block decoder 20 is provided for each block BLK. As shown in FIG. 3, each block decoder 20 has a latch circuit. This latch circuit holds data indicating whether or not the block BLK corresponding to each block decoder 20 is a defective block. A block selection signal is transferred from the block decoder 20 to the transfer transistors 21 to 23. As a result, the transfer transistors 21 to 23 are turned on. Thus, based on the block selection signal supplied from the block decoder 20, the row decoder 2 transfers the voltage supplied from the driver circuit 3 to the select gate lines SGD1 and SGS1 and the word lines WL0 to WL63, respectively.

  In addition, the row decoder 2 decodes the row address given from the control unit 6 and selects a desired word line WL among the plurality of word lines WL in the selected block based on the result.

1-4. About Driver Circuit 3 The driver circuit 3 includes select gate line drivers 31 and 32 provided for the select gate lines SGD1 and SGS1, and a word line driver 33 provided for each word line WL. In the present embodiment, the word line driver 33 and the select gate line drivers 31 and 32 are provided in the blocks BLK0 to BLKs.

  The select gate line driver 31 transfers, for example, a signal sgd to the gate of the select transistor ST1 via the select gate line SGD1 during data writing, reading, erasing, and data verification. The signal sgd is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD (for example, 1.8 [V]) when the signal is at the “H” level.

Similarly to the select gate line driver 31, the select gate line driver 32 passes through the select gate line SGS1 of the selected block BLK, for example, through the select gate line SGS1 at the time of data writing, reading, and data verification. The signal sgs is transferred to the gate of the selection transistor ST2. The signal sgs is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD when the signal is at the “H” level.

1-4. Voltage Generation Circuit 4 The voltage generation circuit 4 generates a voltage required for data programming, reading, and erasing by boosting or stepping down an externally applied voltage. The generated voltage is supplied to the driver circuit 3.

1-5. About the data input / output circuit 5 The data input / output circuit 5 is an address (row address, column address, block address; page including row address and column address) supplied from an external host via an I / O terminal (not shown). And the command are output to the control unit 6. The data input / output circuit 5 outputs write data to the sense amplifier 8 via the data line Dline.

  Further, when outputting the data read from the memory cell array 1 to the host, the data input / output circuit 5 receives the data amplified by the sense amplifier 8 through the data line Dline based on the control of the control unit 6. After that, the data is output to the host via the I / O terminal.

1-6. About Control Unit 6 The control unit 6 controls the operation of the entire NAND flash memory. That is, the operation sequence in the data write operation, read operation, and erase operation is executed based on the address and command given from the host via the data input / output circuit 5. The control unit 6 generates a block selection signal, a column selection signal, and a row selection signal based on the address and the operation sequence.

  The control unit 6 outputs the block selection signal and the row selection signal described above to the row decoder 2. Further, the control unit 6 outputs a column selection signal to a column decoder (not shown). The column selection signal is a signal for selecting the column direction of the sense amplifier 8.

  The control unit 6 is given a control signal supplied from a memory controller connected to the semiconductor memory device. The control unit 6 distinguishes whether the signal supplied from the host to the data input / output circuit 5 via the I / O terminal is an address or data based on the supplied control signal.

1-7. Sense Amplifier 8 The sense amplifier 8 senses and amplifies data read from the memory cell MT to the bit line BL when reading data. Specifically, after precharging the bit line BL to a predetermined voltage, the bit line BL is discharged by the NAND string 11 selected by the row decoder 2, and the discharge state of the bit line BL is sensed. That is, the sense amplifier 8 amplifies the voltage of the bit line BL and senses data stored in the memory cell MT.

  At the time of data writing, write data is transferred to the corresponding bit line BL.

1-8. Column Decoder A column decoder (not shown) decodes a column address given from the control unit 6 and outputs a column selection signal to the sense amplifier 8. Based on this column selection signal, a desired latch circuit in the sense amplifier 8 is selected.

1-9. Address Buffer An address buffer (not shown) has a function of holding an address input to the control unit 6. In the semiconductor memory device of this embodiment, the address is supplied to the address buffer via the control unit 6, but the present invention is not limited to this, and the address may be directly supplied from the data input / output circuit 5. .

[Operation Method of Semiconductor Memory Device]
Next, the write operation of the semiconductor memory device of this embodiment will be described with reference to FIG.
In the present embodiment, after the control unit 6 performs an operation of writing data to, for example, the nth page (n is a natural number), the control unit 6 includes n memory cells having a threshold voltage different from the erased state. It is detected whether it exists in the page after the th.

  When there is a memory cell having a threshold voltage different from the erased state in the nth page and after, the control unit 6 outputs a status fail to, for example, an external host to notify that it is a defective cell that cannot be written. .

  A specific write operation of the present embodiment will be described with reference to FIG. FIG. 3 is a flowchart showing an example in which “0” data is written in the memory cell of the nth page for convenience of explanation.

  First, in step S1, the control unit 6 programs “0” data to the memory cell of the nth page. Specifically, for example, when the memory cell of the nth page is a plurality of memory cells MT connected to the word line WL2, the driver circuit 33 applies the write voltage to the word line WL2 in FIG. Apply VPGM. The driver circuit 33 applies a write pass voltage to the other word lines WL0, WL1, WL3 to WL63 via the row decoder 2. The control unit 6 controls the sense amplifier 8 to supply Vss (when “0” data is written) to the bit line BL.

  Note that VDD is supplied to the bit line BL when writing is prohibited, that is, when “1” data is written.

  In step S1, the control unit 6 holds n + 1 as a detection page number m (m is a natural number), for example, in a RAM (not shown). This detection page number m is a page number for detection used in steps S4 and S5.

  In step S2, the control unit 6 holds “0” data or verifies the memory cell programmed in step S1. Specifically, the control unit 6 determines whether or not the threshold voltage of the memory cell exceeds a desired specified value. Specifically, a predetermined voltage (for example, 0 V) is applied to the word line WL, and it is detected whether or not a current flows through the NAND string 11.

  When the control unit 6 determines that a failure has occurred in the verification in step S2 (step S2, Fail), the maximum number of loops in which the number of programs is held in the semiconductor memory device (for example, the ROMFUSE area of the memory cell array 1) If it does not exceed (No at Step S3), the control unit 6 returns to Step S2 again and executes the program.

  On the other hand, in the case where the control unit 6 determines that the verify is failed in step S2 (step S2, Fail), the maximum number of times the program is held in the semiconductor memory device (for example, the ROMFUSE area of the memory cell array 1). When the number of loops is exceeded (step S3, Yes), the control unit 6 outputs a status fail to the host via the data input / output circuit 5.

  When the control unit 6 determines that the pass is determined by the verification in step S2 (step S2, Pass), the control unit 6 stores “1” data in the memory cell of the mth page corresponding to the detected page number m. Whether or not is verified (step S4). Specifically, the control unit 6 holds “1” data or performs verification on the memory cells MT connected to the word line WLm. Specifically, a predetermined voltage (for example, 0 V) is applied to the word line WL, and it is detected whether or not a current flows through the NAND string 11.

  When the control unit 6 determines that the verification is failed in step S4 (step S4, Fail), the control unit 6 outputs a status fail to the host via the data input / output circuit 5.

  On the other hand, when the control unit 6 determines that the pass is verified in step S4 (step S4, Pass), the control unit 6 determines whether the detected page number m matches the maximum page number in the block (step S4). S5). For example, in FIG. 1, the control unit 6 determines whether m is 64 (m-th word line WL means word line WL63).

  When it is determined that the detected page number m does not match the maximum page number in the block (step S5, No), the control unit 6 increments the detected data number m held in the RAM (step S6), and the step again. Return to S4.

  When the control unit 6 determines that the detected page number m matches the maximum page number in the block (step S5, Yes), the process ends.

[Effect of the first embodiment]
The embodiment can provide a semiconductor memory device capable of improving data reliability.

  For example, the effect of the semiconductor memory device of this embodiment will be described using a semiconductor memory device in which data is written by selecting pages in a block at random.

  In the semiconductor memory device of the comparative example, in order to write data by selecting a page at random, for example, when there is a memory cell in which “0” data has already been written on a page adjacent to the selected page (page to which data is written) There is.

At this time, when data is written to the selected page, erroneous writing may occur or the threshold voltage of the memory cell may vary greatly due to the parasitic capacitance received from the memory cell of the adjacent page. As a result, the reliability of data may be reduced.

  However, in the semiconductor memory device of the present embodiment, after executing the operation of writing data to the nth page, the control unit 6 has memory cells having threshold voltages different from the erased state in the nth and subsequent pages. Detect whether to do. Therefore, it is possible to detect whether there is a memory cell having, for example, “0” data in the nth and subsequent pages.

  When there is a memory cell having “0” data in the nth and subsequent pages, a status fail is output, and by detecting a status path otherwise, a memory having “0” data in the nth and subsequent pages The parasitic capacitance received from the cell can be eliminated.

  Therefore, the semiconductor memory device of this embodiment can provide a semiconductor memory device capable of improving data reliability as compared with the semiconductor memory device of the comparative example.

  If the page numbers are written in the ascending / descending order, steps S4 and S5 perform a status pass.

(Second Embodiment)
Next, the semiconductor memory device of the second embodiment will be described with reference to FIG. The configuration of the semiconductor memory device is the same as that of the first embodiment, and the detailed description is omitted. The semiconductor memory device of the second embodiment is different in write operation compared to the first embodiment.

[Operation Method of Semiconductor Memory Device]
Specifically, in the write operation of the first embodiment, steps S4 and S5 are performed before steps S1 to S3.

  In step S1, the control unit 6 sets n that defines the page to be written and the detection page number m. Here, the control unit 6 sets the detection page number m to n + 1.

  Step S2 and step S3 correspond to step S4 and step S5 of the first embodiment.

  If there is no memory cell that holds “0” data in all the memory cells in the nth and subsequent pages, the process proceeds to step S4, and “0” data is held in all the memory cells in the nth and subsequent pages. If there is a memory cell, the control unit 6 outputs a status fail.

  Steps 4 to S6 correspond to steps S1 to S3 of the first embodiment.

[Effects of Second Embodiment]
The semiconductor memory device of this embodiment has the same effect as that of the first embodiment.

  The semiconductor memory device of this embodiment executes the step of detecting whether or not there is a memory cell holding “0” data in all the memory cells of the nth and subsequent pages before the step of programming.

  That is, when there is a memory cell that holds “0” data in all the memory cells of the nth and subsequent pages, the control unit 6 outputs a status fail without performing a programming process. As a result, in the semiconductor memory device of the second embodiment, the write operation time in the case of status failure can be shortened compared to the first embodiment.

(Third embodiment)
Next, a semiconductor memory device according to a third embodiment will be described with reference to FIG. The configuration of the semiconductor memory device is the same as that of the first embodiment, and the detailed description is omitted. The semiconductor memory device of the third embodiment is different in write operation compared to the first and second embodiments.

[Operation Method of Semiconductor Memory Device]
This embodiment is different only in step S2 and step S3 of the second embodiment. Other processes are the same as those in the second embodiment.

  In step S2 and step S3 of the second embodiment, it is detected whether the memory cell of the mth page has a memory cell holding “0” data. Then, after step S3, m is incremented, and the nth and subsequent pages. It is detected whether there is a memory cell holding “0” data in all the memory cells of the page.

  On the other hand, in this embodiment, in step S2, it is collectively detected whether or not there is a memory cell holding “0” data in all the memory cells of the nth page and subsequent pages.

  Specifically, when the page to be written is the second page (word line WL1 in FIG. 1) corresponding to the nth and subsequent pages, for example, the word line WL2 to the word line WL63. ) Is applied with a desired voltage Vverify. A read pass voltage Vread is applied to the nth word line WL from the first page.

  In this case, when there is even one memory cell having “0” data in the memory cells of the nth and subsequent pages, no current flows through the source line SL. Therefore, the potential of the bit line BL is held. By detecting the potential of the bit line BL, it is possible to collectively detect whether memory cells holding “0” data exist in all the memory cells in the nth and subsequent pages.

[Effect of the third embodiment]
The semiconductor memory device of this embodiment has the same effects as those of the first and second embodiments.

  The semiconductor memory device of this embodiment collectively detects whether there is a memory cell holding “0” data in all the memory cells in the nth and subsequent pages. Therefore, the time for the write operation can be shortened as compared with the second embodiment.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Row decoder 3 ... Driver circuit 4 ... Voltage generation circuit 5 ... Data input / output circuit 6 ... Control part 7 ... Source line driver circuit 8 ... Sense amplifier MT ... Memory cell ST1, ST2 ... Selection transistor

Claims (4)

a memory cell array including m pages (m is a natural number);
A control circuit for controlling the write operation,
In a write operation to the memory cell of the nth page (natural number satisfying 1 ≦ n ≦ m), when the memory cells of the (n + 1) th to mth pages hold data having a threshold different from the erased state, A semiconductor memory device, wherein the control circuit outputs a failure. 2. The control circuit according to claim 1, wherein before the write operation, the control circuit performs an operation of detecting whether or not the memory cells of the (n + 1) th to mth pages hold the data. Semiconductor memory device. When the memory cells of the (n + 1) th to mth pages do not hold the data in the write operation to the memory cells of the nth page,
3. The semiconductor memory device according to claim 1, wherein the control circuit performs the write operation on the memory cell of the nth page. The control circuit selects a plurality of pages from the (n + 1) th to the mth page, and determines whether the memory cells of the (n + 1) th to the mth page hold the data. 4. The semiconductor memory device according to claim 3, wherein the operation of detecting in a lump is performed.

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