JP2013021077A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a groove transistor capable of suppressing variation in threshold voltages.SOLUTION: As shown in FIG. 1, a semiconductor device comprises: a semiconductor substrate 40 including at least one groove portion 250 on a surface; a gate insulating film 20 formed so as to cover a side wall of the groove portion 250; a gate electrode 10 embedded in the groove portion 250; and a source and a drain 150 formed on the surface of the semiconductor substrate 40 so as to face each other via the gate electrode 10. A plurality of bumps 100 are formed on the side wall of the groove portion 250.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent years, miniaturization of transistors in semiconductors and reduction in power consumption have been demanded. However, it has become difficult to achieve both transistor miniaturization and low power consumption. One method for realizing both miniaturization of transistors and low power consumption is a trench transistor (FinFET).

  A trench transistor is obtained by forming a trench in a silicon substrate by etching and embedding a gate electrode in the trench. Patent Documents 1-5 disclose a trench transistor with improved device characteristics. Patent Document 1 describes that the channel width can be increased by increasing the depth of the groove while keeping the element area the same. Patent Document 2 describes that when the channel width is increased without increasing the plane area, the breakdown voltage can be improved together with the mutual conductance. Patent Document 3 describes that the drive capability of a semiconductor device can be improved by forming the source and drain to the vicinity of the bottom of the gate electrode. In Patent Document 4, a photoresist film is applied and patterned in a groove before forming a gate electrode in a part of a source and a drain. Thereafter, it is described that ion implantation can be performed to diffuse deeply from the upper surface to the bottom of the groove. Patent Document 5 describes that a large driving force can be obtained by providing a plurality of protruding epitaxial silicon regions.

Japanese Patent Laid-Open No. 11-103058 JP-A-51-147269 JP 2008-192985 A JP 2009-54999 A JP 2007-5568 A

  In the trench transistor, it is necessary to improve the ON current by increasing the gate width.

According to the present invention, a semiconductor substrate having at least one groove on the surface;
A gate insulating film formed to cover the side wall of the trench,
A gate electrode embedded in the groove,
A source and a drain formed on the surface of the semiconductor substrate and facing each other via the gate electrode;
Including
A semiconductor device in which a plurality of irregularities are formed on the side wall of the groove is provided.

Furthermore, according to the present invention, a groove portion forming step of forming at least one groove portion having a plurality of irregularities on the side wall on the surface of the semiconductor substrate;
Forming a gate insulating film so as to cover the sidewall of the groove,
A gate electrode forming step of burying the gate electrode in the groove,
A source / drain forming step of forming a source and a drain on the surface of the semiconductor substrate so as to face each other through the gate electrode;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, the plurality of irregularities are provided on the side wall of the groove in the groove transistor. Thereby, a trench transistor with an enlarged gate width can be obtained.

  According to the present invention, in the trench transistor, the ON current can be improved by increasing the gate width.

(A) is a BB 'section of the semiconductor device concerning this embodiment, and (b) is a sectional view showing an AA' section perpendicular to a BB 'section. It is a top view of the semiconductor device concerning this embodiment. It is a cross-sectional enlarged view for demonstrating the groove part in the semiconductor device which concerns on this embodiment. In the step of forming a groove in the method for manufacturing a semiconductor device according to the present embodiment, (a) shows formation of an element isolation film, (b) etching, and (c) are diagrams for explaining impurity implantation. It is a cross-sectional photograph for demonstrating the etching method in the manufacturing method of the semiconductor device which concerns on this embodiment. It is a cross-sectional photograph for demonstrating the etching method in the manufacturing method of the semiconductor device which concerns on this embodiment. In the method for manufacturing a semiconductor device according to the present embodiment, (d) illustrates a gate insulating film forming step, and (e) illustrates a gate electrode forming step. In the groove forming step in the semiconductor device manufacturing method according to the present embodiment, (a) is mask formation, (b) element isolation film formation, (c) is etching, and (d) is impurity implantation. It is a figure for demonstrating. In the method of manufacturing a semiconductor device according to the present embodiment, (e) is a diagram for explaining a gate oxide film forming step, and (f) is a diagram for explaining a gate electrode forming step.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
1A is a cross-sectional view taken along the line BB ′ of the semiconductor device according to the present embodiment, and FIG. 1B is a cross-sectional view illustrating the AA ′ cross section perpendicular to the BB ′ cross section.
As shown in FIG. 1, the semiconductor substrate 40 having at least one groove 250 on the surface, the gate insulating film 20 formed so as to cover the sidewall of the groove 250, and embedded in the groove 250. And a source and drain 150 formed on the surface of the semiconductor substrate 40 and facing each other with the gate electrode 10 interposed therebetween, and a plurality of irregularities 100 are formed on the side wall of the groove 250. Yes.

  Examples of the gate insulating film 20 include a silicon oxide film or a high dielectric constant film made of an oxide containing hafnium or aluminum, and examples of the gate electrode 10 include polycrystalline silicon, nickel, cobalt, and titanium silicon. Examples thereof include compounds or nitrides containing titanium or tantalum.

  The semiconductor device according to this embodiment will be described in detail below.

  As shown in FIGS. 1A and 1B, the semiconductor device 300 according to this embodiment includes a semiconductor substrate 40 and a trench transistor formed on one surface side of the semiconductor substrate 40. As the semiconductor substrate 40, a silicon substrate or the like can be used. The trench transistor is located in the element isolation film 30 formed on the semiconductor substrate 40, the element formation region partitioned by the element isolation film 30, and the element formation region.

  The element isolation region on one surface of the semiconductor substrate 40 is provided with a well 110 that is a p-type impurity diffusion region and a source and drain 150 that are n-type impurity diffusion regions. Further, an offset region 130 which is an n-type impurity diffusion region provided therein is formed inside the source and drain 150. The offset region 130 and the source / drain 150 are formed in the well 110. In FIG. 1, only the well 110 and the offset region 130 are indicated by broken lines for easy understanding of the configuration. These are provided between the source and the drain 150 in the gate length direction in the well 110. Further, the region defined by the offset region 130 is a p-type channel region 120.

  In the semiconductor device 300, the channel region 120 is located between the source and drain 150 on one surface of the semiconductor substrate 40. However, the depth of the groove 250 cannot be set deeper than the element isolation. Furthermore, it is preferable that the depth of the groove portion 250 is approximately the same as that of element isolation.

  The gate insulating film 20 is formed on the side wall and the bottom surface of each groove portion 250, and the gate electrode 10 is provided on the gate insulating film 20 so as to be embedded in the groove portion 250. Further, a sidewall 90 is provided on the side wall of the gate electrode 10, and a silicide layer 60 is provided on the gate electrode 10. Further, an interlayer insulating film 50 is provided above the trench transistors. A contact 80 is disposed to be electrically connected to the upper layer through the interlayer insulating film 50.

FIG. 2 is a top view of the semiconductor device according to the present embodiment. FIG. 1 is a cross-sectional view of FIG. 2, FIG. 1 (a) shows a BB ′ cross section, and FIG. 1 (b) shows an AA ′ cross section. In FIG. 2, the gate electrode 10 is not shown, and each region is shown only by a line.
As shown in FIG. 2, the element formation region is disposed inside the element isolation film 30. In this element formation region, the source and drain 150 are provided to face each other with the gate electrode 10 in the gate length direction. Next, the offset region 130 is provided inside the source and drain 150 so as to face each other through the gate electrode 10 in the gate length direction. The gate electrode 10 embedded in the groove 250 having a plurality of irregularities 100 on the side wall is disposed on the inner side of the source / drain region 150 and the offset region 130.

  Next, the plurality of irregularities 100 provided in the semiconductor device 300 will be described in detail.

FIG. 3 is an enlarged cross-sectional view for explaining a groove in the semiconductor device according to the present embodiment.
As shown in FIG. 3, a plurality of irregularities 100 are formed on the side wall of the groove portion 250. The cross-sectional shape of the unevenness 100 may be square or semicircular. However, it is preferable that the depth of each unevenness 100 is substantially equal. Thereby, the perpendicularity of the groove part 250 can be improved. By improving the verticality of the groove 250, the film thickness of the gate insulating film 20 formed on the plurality of irregularities 100 can be controlled substantially uniformly. In addition, when the unevenness | corrugation 100 is square, it is preferable that the angle | corner angle (alpha) which the side which forms the convex part in the unevenness | corrugation 100 forms is the range of 30 degrees or more and less than 180 degrees.

  This is related to the feature of the trench transistor that the ON current increases as the gate width per unit area increases and can contribute to the improvement of characteristics without sacrificing the chip size. Therefore, the gate width can be increased as the depth of each unevenness formed in the groove 250 is increased. However, if the depth is too deep, impurity implantation becomes difficult.

  In the semiconductor device of the present embodiment, for example, the angle α formed by the sides forming the protrusions in the unevenness 100 is 2 °, which is one step deep with respect to one step when the angle α is 60 °. Double the effect can be added to the transistor. Thereby, the gate width can be increased without increasing the depth of the trench 250.

  Further, it is preferable that the impurity concentration on the side wall of the groove 250 is higher than the impurity concentration on the bottom surface. At this time, when the sidewall of the groove 250 is substantially vertical as in the semiconductor device 300 and the film thickness of the gate insulating film 20 is uniform, ions that are impurities are implanted only into the sidewall in the groove 250. Thereby, it is possible to control the variation of the threshold voltage due to the difference in film thickness of the gate insulating film 20.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

4A and 4B are diagrams illustrating a step of forming a trench in the method of manufacturing a semiconductor device according to the present embodiment, in which FIG. 4A illustrates formation of an element isolation film, FIG. 4B illustrates etching, and FIG. 4C illustrates impurity implantation. FIG.
As shown in FIG. 4, at least one groove portion 250 having a plurality of irregularities 100 is formed on the surface of the semiconductor substrate 40. At this time, it is preferable to use the Bosch method for the dry etching related to the formation of the groove portion 250. The Bosch method is an etching method that uses a MEMS application etcher to perform deep digging work by alternately repeating sidewall protection and bottom surface etching. Specifically, it is a method in which etching with an etching gas and a deposition coating step with a fluorocarbon gas are alternately repeated in units of several seconds.

  First, as shown in FIG. 4A, an element isolation film 30 is formed around a region where a trench transistor is to be formed on a semiconductor substrate 40. On this element isolation film 30, a photoresist 200 is formed by opening a portion located on a location to be the trench 250 (groove gate region).

  Next, as shown in FIG. 4B, an anisotropic etch for forming a plurality of irregularities 100 is formed by the Bosch method. As a result, at least one groove 250 is formed. At the same time, a plurality of irregularities 100 are formed on the side wall of the groove 250.

  Next, as shown in FIG. 4C, ions that are impurities are implanted into the sidewalls of the groove 250 with the photoresist 200 left. Ion implantation is performed at an angle of about 15 ° to 40 ° using a high current or medium current ion implanter.

5 and 6 are cross-sectional photographs for explaining an etching method in the method for manufacturing a semiconductor device according to the present embodiment.
As shown in FIGS. 5 and 6, by performing dry etching using the Bosch method, the width 250 does not change to the bottom surface, and a substantially vertical groove portion 250 can be formed.

7A and 7B are diagrams for explaining the gate insulating film forming step and FIG. 7E for explaining the gate electrode forming step in the semiconductor device manufacturing method according to the present embodiment.
As shown in FIG. 7D, after ion implantation is performed on the sidewall of the trench 250, the gate insulating film 20 is formed so as to cover the sidewall of the trench 250. At this time, the thickness of the gate insulating film 20 is controlled to be substantially uniform.

  Next, as illustrated in FIG. 7E, the gate electrode 10 is formed on the gate insulating film 20 so as to be embedded in the groove portion 250. At this time, the gate electrode 10 is formed of polysilicon by a CVD method.

  Next, a source and a drain 150 are formed on the surface of the semiconductor substrate 40 so as to face each other through the gate electrode 10 (not shown).

  The semiconductor device according to this embodiment is formed by the above steps.

  Next, effects of the semiconductor device according to the present embodiment will be described.

A plurality of irregularities 100 were formed on the side wall of the groove portion 250. That is, the gate width can be increased without changing the depth of the groove 250. As a result, the ON current can be increased.
Further, in the groove part 250, the verticality of the side wall of the groove part 250 is maintained. Accordingly, since the thickness of the gate insulating film 20 can be controlled to be uniform, variations in threshold voltage can be suppressed.

  Normally, when the element isolation and the depth of the bottom surface of the groove 250 are the same, when a current flows using the channel region 120 under the groove 250, a leakage current flows. However, in the present application, the impurity concentration on the side wall of the groove portion 250 is provided to be higher than the bottom surface of the groove portion 250. For this reason, the channel region 120 is unlikely to be under the groove 250. Accordingly, it is possible to suppress the leakage current from flowing.

(Second Embodiment)
The semiconductor device 300 according to this embodiment has the same configuration as that of the first embodiment. For this reason, the effect similar to 1st Embodiment can be acquired. However, in this embodiment, in the method of manufacturing a semiconductor device, the photoresist 200 is not used as a dry etching mask, but dry etching is performed using a patterned hard mask, for example, a mask oxide film 210 as a mask. It differs from the first embodiment in that it is.

  Hereinafter, the manufacturing method of the semiconductor device according to the present embodiment will be described in detail.

8A and 8B show a groove forming step in the method of manufacturing a semiconductor device according to the present embodiment, in which FIG. 8A is a mask formation, FIG. 8B is an element isolation film formation, FIG. FIG. 5 is a diagram for explaining impurity implantation; 9A and 9B are diagrams for explaining the gate oxide film forming step and FIG. 9F for explaining the gate electrode forming step in the method of manufacturing a semiconductor device according to the present embodiment.
As shown in FIG. 8A, first, after forming an element isolation film 30 around a region where a trench transistor is to be formed, a mask oxide film 210 is formed by a CVD method.

  Next, as shown in FIG. 8B, by selectively etching a portion of the mask oxide film 210 where the groove portion 250 is to be formed by etching the mask oxide film 210 using the photoresist 200 as a mask. Remove and open.

  Next, as in the first embodiment, an anisotropic etch for forming a plurality of irregularities 100 is formed by the Bosch method (FIG. 8C). Thereby, the groove part 250 which has the some unevenness | corrugation 100 in the side wall is formed. Then, the impurity 200 is implanted into the side wall of the groove 250 with the photoresist 200 left (FIG. 8D).

  Next, as in the first embodiment, after ion implantation is performed on the sidewall of the trench 250, the gate insulating film 20 is formed so as to cover the sidewall of the trench 250 (FIG. 9E). The gate electrode 10 is formed in the shape of the gate insulating film 20 so as to be embedded in the trench 250 (FIG. 9F). Finally, source / drain regions 150 are formed on the surface of the semiconductor substrate 40 so as to face each other with the gate electrode 10 interposed therebetween (not shown).

  By performing the method of manufacturing a semiconductor device according to this embodiment, it is not necessary for the photoresist 200 to serve as a mask for dry etching and a mask for ion implantation. For this reason, the concern about the hardening of the photoresist 200 after ion implantation and the concern about the peelability are eliminated. Further, the mask oxide film 210 has higher processing accuracy than the photoresist 200. For this reason, compared with 1st Embodiment, formation of the groove part 250 becomes easy.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

10 Gate electrode 20 Gate insulating film 30 Element isolation film 40 Semiconductor substrate 50 Interlayer insulating film 60 Silicide layer 80 Contact 90 Side wall 100 Concavity and convexity 110 Well 120 Channel region 130 Offset region 150 Source and drain 160 Impurity 200 Photoresist 210 Mask oxide film 250 Groove 300 Semiconductor Device

Claims (5)

A semiconductor substrate having at least one groove on the surface;
A gate insulating film formed to cover the side wall of the trench,
A gate electrode embedded in the groove;
A source and a drain formed on the surface of the semiconductor substrate and facing each other via the gate electrode;
Including
A semiconductor device in which a plurality of irregularities are formed on a side wall of the groove.   The semiconductor device according to claim 1, wherein a cross-sectional shape of the unevenness formed in the groove is a square shape or a semicircular shape.   3. The semiconductor device according to claim 1, wherein an impurity concentration of the semiconductor substrate in the sidewall of the groove is higher than the impurity concentration of the semiconductor substrate in a bottom surface. A groove portion forming step of forming at least one groove portion having a plurality of irregularities on the side wall on the surface of the semiconductor substrate;
A gate insulating film forming step of forming a gate insulating film so as to cover the side wall of the groove;
Forming a gate electrode in the trench, and forming a gate electrode;
A source / drain formation step of forming source / drain regions on the surface of the semiconductor substrate so as to face each other through the gate electrode;
A method of manufacturing a semiconductor device including: The method of manufacturing a semiconductor device according to claim 4, wherein the groove is formed using a Bosch method.

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