JP2013021076A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device including a variable capacitance element having a large capacitance value, a large amount of change in capacitance value and a high Q value, and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises a variable capacitance element including a lower electrode 13 formed on a semiconductor substrate 11, a capacitance insulation film 14 formed on the lower electrode 13 and an upper electrode 15 formed on the capacitance insulation film 14. The upper electrode 15 includes a low concentration impurity layer 15a located on the capacitance insulation film 14 and a high concentration impurity layer 15b located on the low concentration impurity layer 15a and having an impurity concentration higher than that of the low concentration impurity layer 15a.

Description

  The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a variable capacitance element used in a high-frequency circuit and a manufacturing method thereof.

  The variable capacitance element is used for controlling the oscillation frequency in a voltage controlled oscillation circuit mounted on a high frequency LSI (Large Scale Integration), for example. As an example of the variable capacitance element, there is a MOS (Metal Oxide Semiconductor) type element as described in Patent Document 1.

  FIG. 7 shows a MOS variable capacitance element disclosed in Patent Document 1. The element is formed in the second conductivity type low concentration diffusion region 102 provided on the upper portion of the first conductivity type semiconductor substrate 101. More specifically, a gate electrode 104 is provided on the low concentration diffusion region 102 with a gate insulating film 103 interposed therebetween. A second conductivity type high concentration diffusion region 105 is formed in a portion adjacent to the gate insulating film 103 in the low concentration diffusion region 102. Further, a diffusion region 106 of the first conductivity type that functions as an insulating layer is formed between the high concentration diffusion region 105 and the low concentration diffusion region 102 except for the gate insulating film 103 side.

  In the above structure, the low-concentration diffusion region 102 and the high-concentration diffusion region 105, both of which are of the second conductivity type, act as substrate electrodes, and constitute a MOS capacitor together with the gate electrode 104. When the substrate electrode is connected to the reference potential and a voltage is applied to the gate electrode 104, the depletion layer 107 spreads under the gate insulating film 103. The capacitance value of the capacitor depends on the thickness of the gate insulating film 103 and the thickness of the depletion layer below the gate insulating film 103. Therefore, since the capacitance value can be changed by the voltage applied to the gate electrode 104, the structure in FIG. 7 functions as a variable capacitance element.

JP 2001-267497 A

  There is a desire to increase the capacitance value and the amount of change in the variable capacitance element. Further, there is a demand for a higher Q value indicating the frequency characteristics of the variable capacitance element.

  Here, since the Q value is deteriorated by the parasitic resistance of the element, it is necessary to lower the parasitic resistance in order to realize a high Q value. However, in the variable capacitance element, in order to increase the amount of change in the capacitance value, it is necessary to increase the change in the thickness of the depletion layer. For this purpose, the low concentration diffusion region 102 below the insulating film 103 has to be increased. It is necessary to reduce the impurity concentration. When the impurity concentration is lowered, the parasitic resistance is increased, so that the Q value is deteriorated.

  Further, when the area of the capacitive element (the area of the gate electrode 104) is increased in order to increase the capacitance value, the distance from the central portion of the gate electrode 104 to the high concentration diffusion region 105 is increased. That is, the distance that carriers must move through the low-concentration diffusion region 102 with high resistance becomes longer, and the parasitic resistance during carrier movement increases. Accordingly, the Q value is deteriorated.

  As described above, if the capacitance value and the amount of change are increased, the Q value is deteriorated.

  In view of the above, an object of the present disclosure is to provide a semiconductor device including a variable capacitance element having a large capacitance value and its variation, and a high Q value, and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device of the present disclosure includes a variable capacitance element, and the variable capacitance element includes a lower electrode formed on a semiconductor substrate, a capacitance insulating film formed on the lower electrode, and An upper electrode formed on the capacitor insulating film, and the upper electrode has a low-concentration impurity layer located on the capacitor insulating film and an impurity concentration located on the low-concentration impurity layer and lower than that of the low-concentration impurity layer. And a high concentration impurity layer.

  In such a semiconductor device, when the lower electrode is connected to the reference potential and a voltage is applied to the high concentration impurity layer of the upper electrode, a depletion layer is formed in the low concentration impurity layer of the upper electrode. The lower electrode and at least the high-concentration impurity layer of the upper electrode constitute a capacitive element with the capacitive insulating film and the depletion layer interposed therebetween. Furthermore, since the thickness of the depletion layer changes depending on the applied voltage, it functions as a variable capacitance element.

  Here, it is not necessary to dispose a high-resistance region (low-concentration impurity region) below the capacitor insulating film, and carriers can move mainly in the lower electrode or the high-concentration impurity layer. Therefore, even if the impurity concentration of the low-concentration impurity layer in the upper electrode is decreased in order to increase the amount of change in capacitance, the resistance of the portion where carriers move does not change, so the parasitic resistance of the element does not increase. . Similarly, even if the capacitance area (area of the portion where the upper electrode and the lower electrode face each other) is increased in order to increase the capacitance value, the parasitic resistance of the element does not increase. That is, it is possible to increase the capacitance value and the amount of change while avoiding deterioration of the Q value due to an increase in parasitic resistance.

  The upper electrode is located between the low-concentration impurity layer and the high-concentration impurity layer, and further includes an intermediate-concentration impurity layer having an impurity concentration higher than that of the low-concentration impurity layer and lower than that of the high-concentration impurity layer. You may have.

  Further, the upper electrode may be made of a polysilicon film and further include a silicide layer formed on the upper electrode.

  The upper electrode may have such a structure.

  The lower electrode may be formed on the semiconductor substrate via an insulating film.

  The lower electrode may be made of a polysilicon film, and the impurity concentration of the lower electrode may be higher than the impurity concentration of the low-concentration impurity layer.

  In this way, a depletion layer is formed in the low-concentration impurity layer of the upper electrode, not the lower electrode, by voltage application.

  The lower electrode may be made of a metal film or a metal-containing film.

  Also in this case, it functions as a variable capacitance element.

  The insulating film may be an element isolation insulating film provided on the semiconductor substrate.

  That is, the variable capacitor including the lower electrode, the capacitor insulating film, and the upper electrode may be formed on the element isolation insulating film.

  The lower electrode may be formed of an impurity region provided on the semiconductor substrate, and the impurity concentration of the impurity region may be higher than the impurity concentration of the low-concentration impurity layer.

  Further, the impurity region constituting the lower electrode may be surrounded by an element isolation region provided on the upper portion of the semiconductor substrate.

  The configuration of the lower electrode may be as described above. In this case, when the semiconductor device further includes the MIS transistor, the height of the upper surface of the upper electrode can be matched with the height of the upper surface of the gate electrode of the MIS transistor. This is advantageous when a lithography process or the like is used to manufacture a semiconductor device.

  Further, a MIS transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate may be further provided.

  That is, a semiconductor device including both a variable capacitor and a MIS transistor may be used.

  Further, the capacitor insulating film and the gate insulating film may be made of the same film.

  The upper electrode and the gate electrode may be made of the same film.

  In this way, the component of the variable capacitance element and the component of the MIS transistor can be formed at the same time, and an increase in manufacturing steps can be suppressed.

  Further, the low concentration impurity layer may be depleted by applying a voltage between the lower electrode and the high concentration impurity layer in the upper electrode.

  This functions as a variable capacitance element.

The impurity concentration of the low concentration impurity layer is 1 × 10 ¹⁵ ions / cm ³ or more and 1 × 10 ¹⁸ ions / cm ³ or less, and the impurity concentration of the high concentration impurity layer is 1 × 10 ¹⁹ ions / cm 3. It may be ³ or more and 1 × 10 ²¹ ions / cm ³ or less.

  As an example of each impurity concentration, a value in such a range may be used.

  Next, in order to achieve the above object, in a method of manufacturing a semiconductor device including a variable capacitance element, a step (a) of forming a lower electrode on a semiconductor substrate and a step of forming a capacitive insulating film on the lower electrode (B) and a step (c) of forming an upper electrode on the capacitor insulating film, wherein the step (c) includes a step of providing a low-concentration impurity layer located on the capacitor insulating film, and a step on the low-concentration impurity layer. And a step of forming a high concentration impurity layer having an impurity concentration higher than that of the low concentration impurity layer.

  If it does in this way, the semiconductor device of this indication can be manufactured.

  Note that a step of forming an element isolation insulating film on the upper portion of the semiconductor substrate may be further provided before the step (a), and a lower electrode may be formed on the element isolation insulating film in the step (a).

  Further, before the step (a), a step of forming an element isolation insulating film on the semiconductor substrate is further provided. In the step (a), a portion of the semiconductor substrate surrounded by the element isolation insulating film includes an impurity region. A lower electrode may be formed.

  According to the technique of the present disclosure, in a variable capacitance element, a capacitance value and a change amount thereof can be increased while suppressing an increase in parasitic resistance, and a semiconductor device including a variable capacitance element having a high Q value and a manufacturing method thereof are realized. be able to.

1A to 1C are diagrams schematically illustrating a planar configuration and a cross-sectional configuration of an exemplary semiconductor device according to the first embodiment of the present disclosure. 2A to 2D are views for explaining the manufacturing process of the exemplary semiconductor device according to the first embodiment. 3A to 3C are views for explaining the manufacturing process of the exemplary semiconductor device according to the first embodiment, following FIG. 2D. 4A to 4C are diagrams schematically illustrating a planar configuration and a cross-sectional configuration of an exemplary semiconductor device according to the second embodiment of the present disclosure. FIGS. 5A to 5D are views for explaining the manufacturing process of the exemplary semiconductor device according to the second embodiment. 6A to 6C are diagrams for explaining the manufacturing process of the exemplary semiconductor device according to the second embodiment, following FIG. 6D. FIG. 7 is a diagram schematically showing a cross-sectional configuration of a MOS variable capacitance element of the background art.

(First embodiment)
Hereinafter, a first embodiment of the present disclosure will be described with reference to the drawings. 1A to 1C are diagrams schematically illustrating an exemplary semiconductor device 10 according to the present embodiment. More specifically, FIG. 1A is a plan view showing variable capacitance elements (however, only some components) included in the semiconductor device 10 and corresponds to the Ib-Ib ′ line and the Ic-Ic ′ line. A cross section of the semiconductor device 10 is shown in FIGS. 1B and 1C.

  As shown in FIGS. 1A to 1C, the semiconductor device 10 is formed using a semiconductor substrate 11. An element isolation region 12 made of an insulating film is formed on the semiconductor substrate 11. A lower electrode 13 is formed on the element isolation region 12. An upper electrode 15 is formed on the lower electrode 13 via a capacitive insulating film 14.

As shown in FIG. 1A, the lower electrode 13 and the upper electrode 15 are arranged so that their longitudinal directions are orthogonal to each other. A facing portion 40 between the lower electrode 13 and the upper electrode 15 sandwiching the capacitive insulating film 14 functions as a variable capacitive element. The area of the facing portion 40 is a capacity area and is set according to a desired variable capacity. For example, it is several tens of nm ² to several tens of μm ² .

Here, the lower electrode 13 is made of, for example, DPS (doped poly-silicon) having a thickness of about 20 nm and contains an n-type impurity of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ³ .

  The capacitor insulating film 14 is made of, for example, a silicon oxide film having a thickness of about 2 to 10 nm, and is the same film as the gate insulating film of the MIS transistor formed on the same semiconductor substrate 11 and has the same thickness. In FIG. 1C, the capacitive insulating film 14 is also formed between the element isolation region 12 and the upper electrode 15, but it is not essential to form it in this portion. The capacitor insulating film 14 may be formed so as to cover the upper surface and side surfaces of the lower electrode 13. When the capacitor insulating film 14 is formed by a thermal oxidation method, it is formed only on the upper surface and side surfaces of the lower electrode 13 made of silicon. When deposited using a CVD (Chemical Vapor Deposition) method or the like, it is also formed between the element isolation region 12 and the upper electrode 15.

  The upper electrode 15 is made of, for example, a polysilicon film having a thickness of about 100 nm to 150 nm, and is about the same as the gate electrode of the MIS transistor. The upper electrode 15 is located immediately above the capacitor insulating film 14 and has a low concentration impurity layer 15a where a depletion layer is formed, a high concentration impurity layer 15b located above the low concentration impurity layer 15a, and a low concentration impurity layer 15a. And an intermediate concentration impurity layer 15c located between the high concentration impurity layers 15b.

The low concentration impurity layer 15a has, for example, a thickness of about 50 to 60 nm and contains an n-type impurity of about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ ions / cm ³ . The high concentration impurity layer 15b has, for example, a thickness of about 70 to 80 nm and contains an n-type impurity of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ³ having a higher concentration than the low concentration impurity layer 15a. doing. Intermediate density impurity layer 15c is, for example, the thickness is about: 10 to 20 nm, than the low-concentration impurity layer 15a is lower concentration than the high concentration and is and the high concentration impurity layer 15b 1 × 10 ¹⁸ ~1 × 10 ^It contains n-type impurities of about ¹⁹ ions / cm ³ . However, it is not essential to form the intermediate concentration impurity layer 15c, and the high concentration impurity layer 15b may be formed directly on the low concentration impurity layer 15a.

The lower electrode 13 contains an n-type impurity of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ³ having a higher concentration than the low concentration impurity layer 15 a of the upper electrode 15.

  On the side surface of the upper electrode 15, for example, sidewall spacers 16 a made of an insulating film having a thickness of about several tens of nanometers are formed. A sidewall spacer 16 b is also formed on the side surface of the lower electrode 13. However, the sidewall spacer 16b of the lower electrode 13 is formed at the same time as the sidewall spacer 16a of the upper electrode 15 is formed, and is not essential. Further, as the sidewall spacers 16a and 16b, for example, one of a silicon oxide film and a silicon nitride film or a laminated film thereof is used.

  A silicide layer 17 having a thickness of about 10 nm, for example, is formed in a region outside the sidewall spacer 16a on the upper electrode 15 and the lower electrode 13.

  In addition, contacts (not shown) connected to the silicide layers 17 are formed above the contact formation regions 41 at both ends of the upper electrode 15 and the lower electrode 13 (outside the facing portion 40). However, it is not essential to form two each for the lower electrode 13 and the upper electrode 15, and it is sufficient that at least one is formed.

  In the above description, both the lower electrode 13 and the upper electrode 15 have been described as containing n-type impurities, but instead, both may contain p-type impurities, and one of them may be n-type. The impurity and the other may contain a p-type impurity.

  Further, the structure in which the upper electrode 15 and the lower electrode 13a intersect (so that the longitudinal directions are orthogonal) is not essential. It is sufficient that the upper electrode 15 and the lower electrode 13a have a portion facing each other with the capacitive insulating film 14 interposed therebetween and have a structure that can obtain electrical connection to each.

  The variable capacitance element including the lower electrode 13, the capacitive insulating film 14, and the upper electrode 15 described above is used in a voltage controlled oscillation circuit that operates at, for example, several MHz to several hundred MHz. At this time, for example, by applying a voltage of 1.2 V to the upper electrode 15, a depletion layer having a thickness of several tens of nm is formed in the low concentration impurity layer 15 a of the upper electrode 15. Since the intermediate concentration impurity layer 15c and the high concentration impurity layer 15b on the low concentration impurity layer 15a and the lower electrode 13 below the capacitor insulating film 14 have higher impurity concentrations than the low concentration impurity layer 15a (low The resistance is smaller than that of the concentration impurity layer 15a. Therefore, even if the gate area is increased, the distance that carriers must move through the high resistance region does not increase greatly. Therefore, since an increase in parasitic resistance when carriers move can be suppressed, a high Q value can be realized. As a result, the electrical loss of the circuit can be reduced, and the performance of the circuit such as current consumption and S / N ratio can be improved.

  Note that the thickness of the low-concentration impurity layer 15 a on which the depletion layer is formed needs to be a certain thickness regardless of the thickness of the upper electrode 15. That is, if the low-concentration impurity layer 15a becomes too thin, a sufficiently thick depletion layer is not formed. Therefore, for example, even when the thickness of the upper electrode 15 is different from about 100 nm to 150 nm, the thicknesses of the high concentration impurity layer 15b and the intermediate concentration impurity layer 15c are adjusted, and the thickness of the low concentration impurity layer 15a is adjusted. Is preferably about 50 to 60 nm.

  The lower electrode 13 may be formed of a metal film such as W, Al, TiN, TaN, or TaC or a metal-containing film instead of the polysilicon film.

--Semiconductor device manufacturing method--
Next, a method for manufacturing the semiconductor device 10 will be described with reference to the drawings. Here, a manufacturing method in the case where the semiconductor device 10 includes a MIS transistor in addition to the variable capacitance element shown in FIGS. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views schematically showing the manufacturing process of the semiconductor device 10.

  Description will be made sequentially from the step of FIG. First, an element isolation region 12 made of an insulating film is formed on a predetermined region of the semiconductor substrate 11. For example, an STI (Shallow Trench Isolation) method may be used. In the following, the element isolation region 12 is the variable capacitance element formation region, and the active region 21 of the semiconductor substrate 11 surrounded by the element isolation region 12 is the MIS transistor formation region.

  Next, in the active region 21, p-type well formation, formation of a buried layer for preventing punch-through, ion implantation of conductive impurities for threshold adjustment, etc. are performed as necessary (all are not shown). .

Thereafter, polysilicon containing n-type impurities having a thickness of about 20 nm and a thickness of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ³ on the semiconductor substrate 11 including the element isolation region 12 by, eg, CVD. A film is formed. Further, the polysilicon film is patterned by a lithography process and an etching process to selectively form the lower electrode 13 on the element isolation region 12 where the variable capacitance element is to be formed.

  When the lower electrode 13 made of a metal film (or metal-containing film) is provided, a metal film (or metal-containing film) is formed on the semiconductor substrate 11 including the element isolation region 12 and then etched or the like. Pattern.

  Subsequently, the process of FIG. 2B is performed. First, on the active region 21 and the lower electrode 13, a silicon oxide film having a thickness of about 2 nm to be the capacitor insulating film 14 and the gate insulating film 24 is formed using a thermal oxidation method or the like. Subsequently, a non-doped polysilicon film (a silicon film without intentional introduction of impurities) having a film thickness of, for example, about 150 nm is formed on the silicon oxide film by a CVD method under conditions of, for example, 630 ° C.

Next, the variable capacitance element formation region is masked (not shown), and for example, phosphorus (P), which is an n-type impurity, is implanted into the non-doped polysilicon film in the MIS transistor formation region with an implantation energy of 15 KeV and an implantation dose amount. Ions are implanted under the condition of 5 × 10 ¹⁵ ions / cm ² . Further, for example, RTA (Rapid Thermal Annealing) treatment is performed at 700 ° C. for 40 seconds. As a result, a doped polysilicon film is provided in the MIS transistor formation region, and a non-doped polysilicon film is provided in the variable capacitance element formation region.

  Next, the polysilicon film and the underlying silicon oxide film are patterned by lithography and etching. As a result, a gate electrode 25 made of a doped polysilicon film is formed on the active region 21 via a gate insulating film 24 made of a silicon oxide film. At the same time, an upper electrode 15 made of a non-doped polysilicon film is formed on the lower electrode 13 via a capacitive insulating film 14 made of a silicon oxide film.

Subsequently, the process of FIG. First, the lower electrode 13 and the upper electrode 15 are covered with a resist or the like (not shown). Thereafter, arsenic (As), which is an n-type impurity, is ion-implanted on both sides of the gate electrode 25 in the active region 21 using the gate electrode 25 as a mask to form an n-type extension region 31. The implantation conditions are, for example, an implantation energy of 3 KeV and an implantation dose of 1 × 10 ¹⁵ ions / cm ² . At this time, As is also injected into the gate electrode 25 but is not injected into the lower electrode 13 and the upper electrode 15 covered with resist or the like.

  Subsequently, the process of FIG. 2D is performed. First, an insulating film having a thickness of about 50 nm made of one of a silicon oxide film and a silicon nitride film or a laminated film thereof is formed on the semiconductor substrate 11. Thereafter, the insulating film is anisotropically etched to form side wall spacers 16 a on the side surfaces of the upper electrode 15 and side wall spacers 26 on the side surfaces of the gate electrode 25. At this time, the sidewall spacer 16b is also formed on the side surface of the lower electrode 13, but the formation of the sidewall spacer 16b is not essential.

Subsequently, the process of FIG. Impurity ion implantation is performed in a region outside the sidewall spacer 26 in the active region 21 using the gate electrode 25 and the sidewall spacer 26 as a mask. For example, arsenic (As), which is an n-type impurity, is implanted under the conditions of an implantation energy of 30 KeV and an implantation dose of 1 × 10 ¹⁵ ions / cm ² , and phosphorus (P), which is an n-type impurity, at an implantation energy of 10 KeV. Further, implantation is performed under the condition of an implantation dose amount of 1 × 10 ¹⁴ ions / cm ² . At this time, n-type impurities are also implanted into the gate electrode 25 and the upper electrode 15.

  Thereafter, in order to activate the ion-implanted impurities, for example, an RTA process is performed at 1050 ° C. for 10 seconds or less. As a result, n-type source / drain regions 32 are formed in the active region 21, and a low-concentration impurity layer 15a, an intermediate-concentration impurity layer 15c, and a high-concentration impurity layer 15b are formed in the upper electrode 15.

The impurity concentration peak in the high-concentration impurity layer 15 b by ion implantation is located about 20 to 30 nm from the surface of the upper electrode 15. As a result of thermal diffusion by the RTA treatment, the high concentration impurity layer 15b (impurity concentration of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ³ ) and the upper electrode 15 are formed at a depth of about 70 to 80 nm from the surface of the upper electrode 15. A low-concentration impurity layer 15a (impurity concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ ions / cm ³ ) is formed at a height of about 50 to 60 nm from the bottom surface, and the high-concentration impurity layer 15b and the low-concentration impurity layer 15a An intermediate concentration impurity layer 15c (impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ ions / cm ³ ) is formed therebetween.

Although the three layers are distinguished by the difference in impurity concentration, the impurity concentration changes gently in the upper electrode 15. In order to generate a depletion layer by applying a voltage, the impurity concentration is desirably about 1 × 10 ¹⁸ ions / cm ³ or less. If the change in concentration distribution is steep, the thickness of the intermediate concentration impurity layer 15c is sufficiently small, and it can be considered that the high concentration impurity layer 15b is arranged directly on the low concentration impurity layer 15a. it can.

  Subsequently, as shown in FIG. 3B, a metal film made of nickel (Ni) having a thickness of about 10 nm is formed on the semiconductor substrate 11 by sputtering, for example, and then heat treatment at 300 ° C. to 500 ° C. is performed. Do. Thus, the exposed silicon and metal are reacted to form a silicide layer 27 on the n-type source / drain region 32 and the gate electrode 25, and on the lower electrode 13 and the upper electrode 15. A silicide layer 17 is formed.

  Subsequently, the process of FIG. Here, an interlayer insulating film 18 made of, for example, a silicon oxide film is formed on the semiconductor substrate 11. Next, a contact 19 and a contact 29 made of a conductive film such as tungsten are formed so as to penetrate the interlayer insulating film 18 and reach the silicide layer 17 and the silicide layer 27, respectively.

  Thus, the semiconductor device 10 having the capacitor insulating film 14 and the MIS transistor is manufactured. Here, various components such as the capacitive insulating film 14 and the gate insulating film 24, the upper electrode 15 and the gate electrode 25, the side wall spacer 16a and the side wall spacer 26 can be formed at the same time, thereby reducing the number of processes. be able to.

  The silicide layer 17 and the silicide layer 27 are desirably formed for resistance reduction or the like, but are not essential for the function of the variable capacitance element in the present embodiment.

  In the above, the low concentration impurity layer 15a is always disposed under the intermediate concentration impurity layer 15c. However, the low-concentration impurity layer 15a may be formed between the intermediate-concentration impurity layer 15c and the portion of the capacitor insulating film 14 that covers the lower electrode 13. In the upper electrode 15 in the portion where the lower electrode 13 is not formed, the intermediate concentration impurity layer 15 c (and also the high concentration impurity layer 15 b) may reach the capacitor insulating film 14.

(Second Embodiment)
Hereinafter, a second embodiment of the present disclosure will be described with reference to the drawings. 4A to 4C are diagrams schematically illustrating an exemplary semiconductor device 10a of the present embodiment. More specifically, FIG. 4A shows a plan view showing a variable capacitance element (however, only some components) included in the semiconductor device 10a, and corresponds to the IVb-IVb ′ line and the IVc-IVc ′ line. A cross section of the semiconductor device 10a is shown in FIGS. 4B and 4C.

  In addition, about the component similar to the semiconductor device 10 of 1st Embodiment, the same code | symbol as Fig.1 (a)-(c) is used, and a difference is demonstrated in detail below.

  In the first embodiment, the lower electrode 13 is composed of a polysilicon film formed on the element isolation region 12 (see FIG. 1B and the like). On the other hand, the lower electrode 13a of the semiconductor device 10a of the present embodiment is constituted by an impurity region provided on the upper side of the substrate region 11a in which the semiconductor substrate 11 is surrounded by the element isolation region 12.

The lower electrode 13a has, for example, a depth from the surface of the substrate region 11a of about 20 nm (that is, a thickness of about 20 nm) and an n concentration with an impurity concentration of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ^3. Contains type impurities.

  The capacitor insulating film 14, the upper electrode 15, the side wall spacer 16a, the side wall spacer 26, the silicide layer 17, and the like are the same as those in the semiconductor device 10 of the first embodiment. Since the side surface of the lower electrode 13a does not protrude on the semiconductor substrate 11, the side wall spacer is not formed on the side surface.

  The operation as the variable capacitance element is the same as that described in the first embodiment. That is, when the lower electrode 13 a is connected to the reference potential and a voltage is applied to the upper electrode 15, a depletion layer is formed in the low concentration impurity layer 15 a of the upper electrode 15. Since the thickness of the depletion layer depends on the voltage to be applied and the capacitance of the variable capacitance element depends on the total thickness of the capacitive insulating film 14 and the depletion layer, it functions as a variable capacitance element.

The impurity concentration of the lower electrode 13a (for example, about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ³ ) is the impurity concentration of the low concentration impurity layer 15a (for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ ions / cm ³ ). High enough compared to Therefore, it is not depleted by voltage application, and the resistance is sufficiently low.

  From the above, even if the gate area increases, the distance that carriers must move through the high-resistance region does not increase. Therefore, since an increase in parasitic resistance when carriers move can be suppressed, a high Q value can be realized. As a result, the electrical loss of the circuit can be reduced, and the performance of the circuit such as current consumption and S / N ratio can be improved.

  Further, since the lower electrode 13a is formed in the semiconductor substrate 11, the height of the upper surface of the upper electrode 15 and the height of the upper surface of the gate electrode of the MIS transistor included in the semiconductor device 10a can be matched. This is advantageous in order to prevent dimensional variations accompanying a focus shift in the lithography process.

--Semiconductor device manufacturing method--
Next, a method for manufacturing the semiconductor device 10a will be described with reference to the drawings. Here, a manufacturing method in the case where the semiconductor device 10a includes a MIS transistor in addition to the variable capacitance elements shown in FIGS. 4A to 4C will be described. FIGS. 5A to 5D and FIGS. 6A to 6C are process cross-sectional views schematically showing the manufacturing process of the semiconductor device 10.

  Description will be made in order from the step of FIG. First, an element isolation region 12 made of an insulating film is formed on a predetermined region of the semiconductor substrate 11 by using, for example, the STI method. As a result, an active region 21 composed of a portion of the semiconductor substrate 11 surrounded by the element isolation region 12 is formed in the MIS transistor formation region. At the same time, a substrate region 11a composed of a portion of the semiconductor substrate 11 surrounded by the element isolation region 12 is formed in the variable capacitance element formation region. Here, the substrate region 11a is surrounded by the element isolation region 12 so as to have the shape of the lower electrode 13a of the variable capacitance element.

  Next, in the active region 21 and the substrate region 11a, formation of a p-type well, formation of a buried layer for preventing punch-through, ion implantation of conductive impurities for threshold adjustment, and the like are performed as necessary.

Thereafter, As ion, which is an n-type impurity, is implanted into the substrate region 11a. The implantation conditions are, for example, an implantation energy of 30 KeV and an implantation dose of 1 × 10 ¹⁵ ions / cm ² . By such selective ion implantation, an impurity containing an n-type impurity having a depth from the surface of the substrate region 11a of about 20 nm and an impurity concentration of about 1 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm ^3. A lower electrode 13a is formed as a region.

  Subsequently, the process of FIG. 5B is performed. First, a silicon oxide film having a thickness of about 2 nm is formed on the active region 21 and the lower electrode 13a by using a thermal oxidation method or the like. Next, a non-doped polysilicon film having a film thickness of, for example, about 150 nm is formed on the silicon oxide film by a CVD method under a condition of, for example, 630 ° C.

Next, the variable capacitance element formation region is masked (not shown), and for example, phosphorus (P), which is an n-type impurity, is implanted into the non-doped polysilicon film in the MIS transistor formation region with an implantation energy of 15 KeV and an implantation dose amount. Selective implantation is performed under conditions of 5 × 10 ¹⁵ ions / cm ² . Further, for example, by performing an RTA process at 700 ° C. for 40 seconds, a doped polysilicon film is provided in the MIS transistor formation region and a non-doped polysilicon film is provided in the variable capacitance element formation region.

  Thereafter, the polysilicon film and the silicon oxide film thereunder are patterned using a lithography process and an etching process. As a result, a gate electrode 25 made of a doped polysilicon film is formed on the active region 21 via a gate insulating film 24 made of a silicon oxide film. At the same time, an upper electrode 15 made of a non-doped polysilicon film is formed on the lower electrode 13 via a capacitive insulating film 14 made of a silicon oxide film.

  Here, in the semiconductor device 10 of the first embodiment, the upper surface of the upper electrode 15 is higher than the upper surface of the gate electrode 25 as shown in FIG. That is, since the upper electrode 15 and the gate electrode 25 formed of the same polysilicon film have the same thickness, the height differs depending on the thickness of the lower electrode 13 provided on the element isolation region 12. Has occurred.

  On the other hand, in the semiconductor device 10 a of this embodiment, the upper surface of the upper electrode 15 is the same height as the upper surface of the gate electrode 25. This is because the lower electrode 13a of the semiconductor device 10a is formed in the semiconductor substrate 11 (above the substrate region 11a) and thus does not affect the height of the upper electrode 15.

  If the height of the upper surface of the upper electrode 15 is different from the height of the upper surface of the gate electrode 25, it causes a dimensional variation due to a focus shift when patterning these by a lithography process. In the case of the semiconductor device 10a of this embodiment, such dimensional variations can be prevented.

  Thereafter, the semiconductor device 10a is manufactured as shown in FIGS. 5C and 5D and FIGS. 6A to 6C. These steps may be performed in the same manner as described with reference to FIGS. 2C and 2D and FIGS. 3A to 3C in the first embodiment.

  Also in this embodiment, since the same process can be used to form the constituent elements of the variable capacitor and the MIS transistor, the number of manufacturing processes can be reduced.

  As described above, according to the semiconductor device having the variable capacitance element of the present disclosure and the manufacturing method thereof, a variable capacitance element having a large capacitance value and a large amount of change and a high Q value can be realized. It is also useful for voltage controlled oscillation circuits.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 10a Semiconductor device 11 Semiconductor substrate 11a Substrate region 12 Element isolation region 13 Lower electrode 13a Lower electrode 14 Capacitance insulating film 15 Upper electrode 15a Low concentration impurity layer 15b High concentration impurity layer 15c Intermediate concentration impurity layer 16a Side wall spacer 16b Side wall spacer 16b Wall spacer 17 Silicide layer 18 Interlayer insulating film 19 Contact 21 Active region 24 Gate insulating film 25 Gate electrode 26 Side wall spacer 27 Silicide layer 29 Contact 31 n-type extension region 32 n-type source / drain region 40 Opposing portion 41 Contact formation region

Claims (17)

In a semiconductor device including a variable capacitance element,
The variable capacitance element is
A lower electrode formed on a semiconductor substrate;
A capacitive insulating film formed on the lower electrode;
An upper electrode formed on the capacitor insulating film,
The upper electrode includes a low-concentration impurity layer located on the capacitor insulating film and a high-concentration impurity layer located on the low-concentration impurity layer and having a higher impurity concentration than the low-concentration impurity layer. A semiconductor device. The semiconductor device according to claim 1.
The upper electrode is positioned between the low-concentration impurity layer and the high-concentration impurity layer, and has an impurity concentration higher than that of the low-concentration impurity layer and lower than that of the high-concentration impurity layer. A semiconductor device further comprising a layer. The semiconductor device according to claim 1 or 2,
The upper electrode is made of a polysilicon film,
A semiconductor device, further comprising a silicide layer formed on the upper electrode. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the lower electrode is formed on the semiconductor substrate via an insulating film. The semiconductor device according to claim 4.
The lower electrode is made of a polysilicon film,
The semiconductor device according to claim 1, wherein an impurity concentration of the lower electrode is higher than an impurity concentration of the low-concentration impurity layer. The semiconductor device according to claim 4.
The lower electrode is made of a metal film or a metal-containing film. The semiconductor device according to any one of claims 4 to 6,
The semiconductor device, wherein the insulating film is an element isolation insulating film provided on the semiconductor substrate. The semiconductor device according to any one of claims 1 to 3,
The lower electrode comprises an impurity region provided on the semiconductor substrate,
The semiconductor device, wherein an impurity concentration of the impurity region is higher than an impurity concentration of the low-concentration impurity layer. The semiconductor device according to claim 8.
The semiconductor device, wherein the impurity region constituting the lower electrode is surrounded by an element isolation region provided on the semiconductor substrate. The semiconductor device according to any one of claims 1 to 9,
The semiconductor device further comprises a MIS transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate. Semiconductor device. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein the capacitor insulating film and the gate insulating film are made of the same film. The semiconductor device according to claim 10 or 11,
The semiconductor device, wherein the upper electrode and the gate electrode are made of the same film. The semiconductor device according to any one of claims 1 to 12,
A semiconductor device, wherein a voltage is applied between the lower electrode and the high concentration impurity layer in the upper electrode, whereby the low concentration impurity layer is depleted. The semiconductor device according to any one of claims 1 to 13,
The impurity concentration of the low concentration impurity layer is 1 × 10 ¹⁵ ions / cm ³ or more and 1 × 10 ¹⁸ ions / cm ³ or less,
The semiconductor device according to claim 1, wherein an impurity concentration of the high concentration impurity layer is 1 × 10 ¹⁹ ions / cm ³ or more and 1 × 10 ²¹ ions / cm ³ or less. In a method for manufacturing a semiconductor device including a variable capacitance element,
Forming a lower electrode on the semiconductor substrate (a);
Forming a capacitor insulating film on the lower electrode (b);
And (c) forming an upper electrode on the capacitive insulating film,
The step (c) includes a step of providing a low concentration impurity layer located on the capacitor insulating film, and a step of forming a high concentration impurity layer located on the low concentration impurity layer and having an impurity concentration higher than that of the low concentration impurity layer. Forming the semiconductor device. In the manufacturing method of the semiconductor device of Claim 15,
Before the step (a), further comprising a step of forming an element isolation insulating film on the semiconductor substrate,
In the step (a), the lower electrode is formed on the element isolation insulating film. In the manufacturing method of the semiconductor device of Claim 15,
Before the step (a), further comprising a step of forming an element isolation insulating film on the semiconductor substrate,
In the step (a), the lower electrode made of an impurity region is formed on a portion of the semiconductor substrate surrounded by the element isolation insulating film.

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