JP2013021030A

JP2013021030A - Semiconductor device and manufacturing method of the same

Info

Publication number: JP2013021030A
Application number: JP2011151161A
Authority: JP
Inventors: Nobuyoshi Takahashi; 信義高橋
Original assignee: Panasonic Corp
Current assignee: Panasonic Corp
Priority date: 2011-07-07
Filing date: 2011-07-07
Publication date: 2013-01-31

Abstract

PROBLEM TO BE SOLVED: To enable protection of a low concentration impurity diffusion layer of a high breakdown voltage transistor from contamination to stabilize characteristics of a semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises: forming a gate insulation film 3a and a gate electrode 4a sequentially on a substrate 1; performing impurity injection on the substrate 1 using the gate electrode 4a as a mask to form a low concentration impurity diffusion layer 5a lateral to the gate electrode 4a above the substrate 1; subsequently, forming an impurity diffusion suppression film 7a so as to continuously cover from above the gate electrode 4a through lateral to the gate electrode 4a to a part of above the low concentration impurity diffusion layer 5a; subsequently, performing impurity injection on the substrate 1 using the gate electrode 4a and the impurity diffusion suppression film 7a as a mask to form a high concentration impurity diffusion layer 8a having an impurity concentration higher than that of the low concentration impurity diffusion layer 5a lateral to the gate electrode 4a above the substrate 1; and subsequently, performing a heat treatment on the substrate 1 in a state where the impurity diffusion suppression film 7a remains.

Description

本発明は、半導体装置及びその製造方法に関し、特に、オフセットゲート構造を有するトランジスタを含む半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a transistor having an offset gate structure and a manufacturing method thereof.

高機能デバイスには、高耐圧特性を有する高耐圧トランジスタが多く用いられている。例えば、フラッシュメモリには、メモリセルにおけるデータの書込及び消去に必要な高電圧を供給する回路が必要であるため、高耐圧トランジスタが多く用いられている。近年、半導体装置の微細化に伴い、そのような高耐圧トランジスタの特性のばらつきを小さくすることが要求されている。 Many high voltage transistors having a high breakdown voltage characteristic are used for high function devices. For example, since a flash memory requires a circuit for supplying a high voltage necessary for writing and erasing data in a memory cell, a high voltage transistor is often used. In recent years, with the miniaturization of semiconductor devices, it has been required to reduce variations in characteristics of such high voltage transistors.

高耐圧特性を得るには、トランジスタにオフセットゲート構造を設けることが知られており、そのようなトランジスタの構成が、例えば特許文献１等に提示されている。 In order to obtain high withstand voltage characteristics, it is known to provide an offset gate structure in a transistor, and a configuration of such a transistor is presented in, for example, Patent Document 1 and the like.

以下に、従来の高耐圧トランジスタについて図９を参照しながら説明する。 A conventional high voltage transistor will be described below with reference to FIG.

図９に示すように、従来の高耐圧トランジスタにおいて、基板１００の上にゲート絶縁膜１０１及びゲート電極１０２が順次形成されている。基板１００の上部で且つゲート電極１０２の一側方には第１拡散層１０３が形成されている。また、基板１００の上部で且つゲート電極１０２の第１拡散層１０３が形成された側と反対側には、ゲート電極１０２と離間するように第２拡散層１０４が形成されている。このように、ゲート端と、第２拡散層１０４であるソース・ドレイン（Ｓ／Ｄ）層とが離間しているオフセットゲート構造が形成されていることにより、高耐圧特性を有するトランジスタを得ることができる。 As shown in FIG. 9, in a conventional high voltage transistor, a gate insulating film 101 and a gate electrode 102 are sequentially formed on a substrate 100. A first diffusion layer 103 is formed on the substrate 100 and on one side of the gate electrode 102. A second diffusion layer 104 is formed on the substrate 100 on the opposite side of the gate electrode 102 from the side where the first diffusion layer 103 is formed so as to be separated from the gate electrode 102. As described above, by forming the offset gate structure in which the gate end and the source / drain (S / D) layer as the second diffusion layer 104 are separated from each other, a transistor having high breakdown voltage characteristics can be obtained. Can do.

このような従来の高耐圧トランジスタを形成する方法について特許文献１に詳細な記載はないが、通常、基板の上部に低濃度不純物拡散層（ＬＤＤ層：lightly doped drain）を形成した後に、Ｓ／Ｄ層を形成するための不純物注入及びアッシングが行われる。具体的に想定される従来の高耐圧トランジスタの製造方法は、以下のように行われる。 Although there is no detailed description in Patent Document 1 regarding a method for forming such a conventional high breakdown voltage transistor, normally, after forming a low-concentration impurity diffusion layer (LDD layer: lightly doped drain) on the substrate, S / Impurity implantation and ashing for forming the D layer are performed. Specifically, a conventional method for manufacturing a high voltage transistor is assumed as follows.

まず、基板にウェルを形成した後に、基板の上にゲート絶縁膜及びゲート電極を順次形成し、ゲート電極をパターニングする。次に、基板の上部で且つゲート電極の側方に、不純物注入によりＬＤＤ層を形成する。その後に、ゲート電極の側方のオフセット領域となる部分にレジスト膜を形成し、レジスト膜をマスクとして基板の上部で且つゲート電極の側方に不純物注入を行い、Ｓ／Ｄ層を形成する。続いて、ＬＤＤ層の上にレジスト膜のみが形成された状態でアッシング処理を行う。これにより、オフセットゲート構造を有する従来の高耐圧トランジスタが完成する。 First, after forming a well in the substrate, a gate insulating film and a gate electrode are sequentially formed on the substrate, and the gate electrode is patterned. Next, an LDD layer is formed by impurity implantation on the substrate and on the side of the gate electrode. Thereafter, a resist film is formed in a portion serving as an offset region on the side of the gate electrode, and impurity implantation is performed on the upper portion of the substrate and on the side of the gate electrode using the resist film as a mask to form an S / D layer. Subsequently, ashing is performed with only the resist film formed on the LDD layer. Thereby, a conventional high voltage transistor having an offset gate structure is completed.

特開昭６２−０４５０５６号公報JP 62-045056 A

しかしながら、前記従来の高耐圧トランジスタの製造方法では、不純物注入により高濃度の不純物が基板に注入された後のアッシング処理により、高濃度の不純物が注入された基板から不純物が放出される。その不純物は、レジスト膜が灰化されて露出したＬＤＤ層に再注入されることにより、ＬＤＤ層はコンタミネーションの影響を受けることとなる。このコンタミネーションは、制御することが困難であり、製造ロット毎にばらつきが生じるため、製造ロット毎に高耐圧トランジスタの特性もばらつくという問題が生じる。 However, in the conventional high breakdown voltage transistor manufacturing method, impurities are released from the substrate into which the high-concentration impurities are implanted by ashing after high-concentration impurities are implanted into the substrate by the impurity implantation. The impurities are reinjected into the LDD layer exposed by ashing the resist film, and the LDD layer is affected by contamination. This contamination is difficult to control and varies from production lot to production lot, resulting in a problem that the characteristics of the high voltage transistor vary from production lot to production lot.

具体的に、耐圧、基板リーク電流及び駆動電流の特性がばらつくこととなり、これらの特性のばらつきは、素子の微細化が進行してゲート長及びオフセット長が縮小され、ＬＤＤ層の深さが浅くなるにつれて、半導体装置により大きい影響を与えることとなる。 Specifically, the characteristics of the withstand voltage, the substrate leakage current, and the drive current vary, and the variation in these characteristics is caused by the miniaturization of the device, the gate length and the offset length are reduced, and the depth of the LDD layer is shallow. As a result, the semiconductor device has a greater influence.

そこで、本発明は前記の問題に鑑み、その目的は、高耐圧トランジスタの低濃度不純物拡散層をコンタミネーションから保護し、半導体装置の特性を安定化できるようにすることにある。 In view of the above problems, an object of the present invention is to protect a low-concentration impurity diffusion layer of a high breakdown voltage transistor from contamination and to stabilize characteristics of a semiconductor device.

前記の目的を達成するために、本発明は半導体装置の製造方法を、ゲート電極の上から該ゲート電極の側方を通って低濃度不純物拡散層の上の一部までを連続して覆うように不純物拡散抑制膜を形成する工程を含む構成とする。 In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device so as to continuously cover from the top of a gate electrode to a part of the low concentration impurity diffusion layer through the side of the gate electrode. The method includes a step of forming an impurity diffusion suppression film.

具体的に、本発明に係る第１の半導体装置の製造方法は、基板の上に、ゲート絶縁膜及びゲート電極を順次形成する工程（ａ）と、ゲート電極をマスクとして基板に不純物注入を行うことにより、基板の上部におけるゲート電極の側方に低濃度不純物拡散層を形成する工程（ｂ）と、ゲート電極の上から該ゲート電極の側方を通って低濃度不純物拡散層の上の一部までを連続して覆うように不純物拡散抑制膜を形成する工程（ｃ）と、ゲート電極及び不純物拡散抑制膜をマスクとして基板に不純物注入を行うことにより、基板の上部におけるゲート電極の側方に、低濃度不純物拡散層よりも不純物濃度が高い高濃度不純物拡散層を形成する工程（ｄ）と、工程（ｄ）よりも後に、不純物拡散抑制膜を残存させた状態で基板に対して加熱処理を行う工程（ｅ）とを備えている。 Specifically, in the first method for manufacturing a semiconductor device according to the present invention, a step (a) of sequentially forming a gate insulating film and a gate electrode on a substrate, and impurity implantation into the substrate using the gate electrode as a mask. A step (b) of forming a low-concentration impurity diffusion layer on the side of the gate electrode in the upper portion of the substrate, and a step on the low-concentration impurity diffusion layer through the side of the gate electrode from above the gate electrode. Step (c) of forming an impurity diffusion suppression film so as to continuously cover up to a portion, and by implanting impurities into the substrate using the gate electrode and the impurity diffusion suppression film as a mask, (D) forming a high concentration impurity diffusion layer having a higher impurity concentration than the low concentration impurity diffusion layer, and heating the substrate with the impurity diffusion suppression film remaining after step (d). Processing And a cormorant step (e).

本発明の第１の半導体装置の製造方法によると、ゲート電極の上から該ゲート電極の側方を通って低濃度不純物拡散層の上の一部までを連続して覆うように不純物拡散抑制膜を形成し、不純物拡散抑制膜を残存させた状態で基板に対して加熱処理を行う。このため、低濃度不純物拡散層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるので、半導体装置の特性を安定化することができる。 According to the first method of manufacturing a semiconductor device of the present invention, the impurity diffusion suppression film is formed so as to continuously cover from the top of the gate electrode to a part of the low concentration impurity diffusion layer through the side of the gate electrode. And the substrate is subjected to heat treatment with the impurity diffusion suppression film remaining. This protects the low-concentration impurity diffusion layer from contamination and prevents variations in breakdown voltage, substrate leakage current, and drive current characteristics due to the contamination, so that the characteristics of the semiconductor device can be stabilized.

本発明の第１の半導体装置の製造方法は、工程（ｂ）と（ｃ）との間に、ゲート電極の側面に側壁絶縁膜を形成する工程（ｆ）をさらに備え、工程（ｄ）において、側壁絶縁膜をもマスクとして、基板に不純物注入を行ってもよい。 The manufacturing method of the first semiconductor device of the present invention further includes a step (f) of forming a sidewall insulating film on the side surface of the gate electrode between the steps (b) and (c). The substrate may also be implanted with the sidewall insulating film as a mask.

本発明の第１の半導体装置の製造方法は、工程（ｅ）よりも後に、高濃度不純物拡散層の上部をシリサイド化する工程（ｇ）をさらに備えていてもよい。 The manufacturing method of the first semiconductor device of the present invention may further include a step (g) of silicidizing the upper portion of the high concentration impurity diffusion layer after the step (e).

本発明の第１の半導体装置の製造方法において、工程（ｅ）の加熱処理はアッシング処理であり、アッシング処理を、基板に高周波バイアスを印加することによって行ってもよい。 In the first method for manufacturing a semiconductor device of the present invention, the heat treatment in the step (e) is an ashing treatment, and the ashing treatment may be performed by applying a high frequency bias to the substrate.

本発明の第２の半導体装置の製造方法は、高耐圧である第１のトランジスタ、該第１のトランジスタよりも低耐圧である第２のトランジスタ、及び金属シリサイド層を含まない第３のトランジスタを有する半導体装置の製造方法を対象とし、基板の上における第１のトランジスタ、第２のトランジスタ及び第３のトランジスタを形成する領域のそれぞれに、ゲート絶縁膜及びゲート電極を順次形成する工程（ａ）と、第１のトランジスタ、第２のトランジスタ及び第３のトランジスタを形成する領域のそれぞれにおいて、各ゲート電極をマスクとして基板に不純物を注入することにより、基板の上部における各ゲート電極の側方に低濃度不純物拡散層を形成する工程（ｂ）と、第１のトランジスタ、第２のトランジスタ及び第３のトランジスタを形成する領域のそれぞれにおいて、各ゲート電極の側面に側壁絶縁膜を形成する工程（ｃ）と、第１のトランジスタを形成する領域において、ゲート電極の上から側壁絶縁膜の上を通って低濃度不純物拡散層の上の一部までを連続して覆うように不純物拡散抑制膜を形成すると共に、第３のトランジスタを形成する領域において、基板、ゲート電極及び側壁絶縁膜を覆うように金属シリサイド生成抑制膜を形成する工程（ｄ）と、第１のトランジスタを形成する領域では、ゲート電極、側壁絶縁膜及び不純物拡散抑制膜をマスクとし、第２のトランジスタを形成する領域では、ゲート電極及び側壁絶縁膜をマスクとし、第３のトランジスタを形成する領域では、ゲート電極及び側壁絶縁膜をマスクとし且つ金属シリサイド生成抑制膜を貫通するように、基板にそれぞれ不純物を注入することにより、基板の上部におけるゲート電極の側方に低濃度不純物拡散層よりも不純物濃度が高い高濃度不純物拡散層をそれぞれ形成する工程（ｅ）と、工程（ｅ）よりも後に、第１のトランジスタ、第２のトランジスタ及び第３のトランジスタを形成する領域のそれぞれにおいて、不純物拡散抑制膜及び金属シリサイド生成抑制膜を残存させた状態で基板に対して加熱処理を行う工程（ｆ）と、工程（ｆ）よりも後に、第１のトランジスタを形成する領域において、高濃度不純物拡散層の上部をシリサイド化し、第２のトランジスタを形成する領域において、ゲート電極の上部及び高濃度不純物拡散層の上部をシリサイド化する工程（ｇ）とを備えている。 According to a second method of manufacturing a semiconductor device of the present invention, a first transistor having a high breakdown voltage, a second transistor having a lower breakdown voltage than the first transistor, and a third transistor not including a metal silicide layer are provided. A step of sequentially forming a gate insulating film and a gate electrode in each of regions where a first transistor, a second transistor, and a third transistor are to be formed on a substrate; In each of the regions where the first transistor, the second transistor, and the third transistor are formed, impurities are implanted into the substrate using each gate electrode as a mask, so that the gate electrode is formed laterally on the upper portion of the substrate. A step (b) of forming a low-concentration impurity diffusion layer; a first transistor, a second transistor, and a third transistor; A step (c) of forming a sidewall insulating film on the side surface of each gate electrode in each of the regions for forming the gate electrode; and a region for forming the first transistor in the region for forming the first transistor from the gate electrode through the sidewall insulating film. An impurity diffusion suppression film is formed so as to continuously cover a part of the upper portion of the concentration impurity diffusion layer, and a metal silicide is formed so as to cover the substrate, the gate electrode, and the sidewall insulating film in a region where the third transistor is formed. In the step (d) of forming the generation suppression film and the region where the first transistor is formed, the gate electrode, the sidewall insulating film and the impurity diffusion suppression film are used as a mask, and in the region where the second transistor is formed, the gate electrode and In the region where the sidewall insulating film is used as a mask and the third transistor is formed, the gate electrode and the sidewall insulating film are used as a mask and the metal silicide formation suppressing film is penetrated. (E) forming a high-concentration impurity diffusion layer having an impurity concentration higher than that of the low-concentration impurity diffusion layer on each side of the gate electrode by implanting impurities into the substrate, respectively, After the step (e), the impurity diffusion suppression film and the metal silicide generation suppression film are left on the substrate in the regions where the first transistor, the second transistor, and the third transistor are formed. Step (f) in which heat treatment is performed, and after the step (f), the upper portion of the high concentration impurity diffusion layer is silicided in the region where the first transistor is formed, and the gate is formed in the region where the second transistor is formed. A step (g) of siliciding the upper portion of the electrode and the upper portion of the high-concentration impurity diffusion layer.

本発明の第２の半導体装置の製造方法によると、第１のトランジスタを形成する領域において、ゲート電極の上から側壁絶縁膜の上を通って低濃度不純物拡散層の上の一部までを連続して覆うように不純物拡散抑制膜を形成し、不純物拡散抑制膜を残存させた状態で基板に対して加熱処理を行う。このため、低濃度不純物拡散層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるので、半導体装置の特性を安定化することができる。 According to the second method for fabricating a semiconductor device of the present invention, in the region where the first transistor is formed, the region from the top of the gate electrode to the portion of the low-concentration impurity diffusion layer passes through the sidewall insulating film. Then, an impurity diffusion suppression film is formed so as to cover the substrate, and the substrate is subjected to heat treatment with the impurity diffusion suppression film remaining. This protects the low-concentration impurity diffusion layer from contamination and prevents variations in breakdown voltage, substrate leakage current, and drive current characteristics due to the contamination, so that the characteristics of the semiconductor device can be stabilized.

本発明の第２の半導体装置の製造方法は、工程（ａ）において、第１のトランジスタを形成する領域のゲート絶縁膜を、第２のトランジスタを形成する領域のゲート絶縁膜の膜厚よりも厚く形成してもよい。 According to the second method for manufacturing a semiconductor device of the present invention, in the step (a), the gate insulating film in the region where the first transistor is formed is made larger than the thickness of the gate insulating film in the region where the second transistor is formed. You may form thickly.

本発明の第２の半導体装置の製造方法は、第３のトランジスタを形成する領域の高濃度不純物拡散層を、その下面が第２のトランジスタを形成する領域の高濃度不純物拡散層の下面よりも上に位置するように形成してもよい。 According to the second method of manufacturing a semiconductor device of the present invention, the lower surface of the high concentration impurity diffusion layer in the region where the third transistor is formed is lower than the lower surface of the high concentration impurity diffusion layer in the region where the second transistor is formed. You may form so that it may be located on.

本発明の第２の半導体装置の製造方法において、工程（ｆ）の加熱処理はアッシング処理であり、アッシング処理を、基板に高周波バイアスを印加することによって行ってもよい。 In the second method for manufacturing a semiconductor device of the present invention, the heat treatment in the step (f) is an ashing treatment, and the ashing treatment may be performed by applying a high frequency bias to the substrate.

本発明の第１の半導体装置は、基板の上に順次形成されたゲート絶縁膜及びゲート電極と、基板の上部におけるゲート電極の側方に形成された低濃度不純物拡散層と、ゲート電極の上から該ゲート電極の側方を通って低濃度不純物拡散層の上の一部までを連続して覆うように形成された不純物拡散抑制膜と、基板の上部におけるゲート電極の側方に、基板面に平行な方向にゲート電極と離間するように形成され、低濃度不純物拡散層よりも不純物濃度が高い高濃度不純物拡散層とを備え、不純物拡散抑制膜は、高濃度不純物拡散層を構成する不純物を含む。 A first semiconductor device according to the present invention includes a gate insulating film and a gate electrode that are sequentially formed on a substrate, a low-concentration impurity diffusion layer that is formed on a side of the gate electrode on the substrate, and a gate electrode. An impurity diffusion suppression film formed so as to continuously cover a part of the low-concentration impurity diffusion layer through a side of the gate electrode from the side of the gate electrode, and a substrate surface on the side of the gate electrode on the upper side of the substrate And a high-concentration impurity diffusion layer having a higher impurity concentration than the low-concentration impurity diffusion layer, and the impurity diffusion suppression film is an impurity constituting the high-concentration impurity diffusion layer. including.

本発明の第１の半導体装置によると、ゲート電極の上から該ゲート電極の側方を通って低濃度不純物拡散層の上の一部までを連続して覆うように形成された不純物拡散抑制膜を備えている。このため、不純物拡散抑制膜の下の低濃度不純物拡散層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるので、半導体装置の特性を安定化することができる。 According to the first semiconductor device of the present invention, the impurity diffusion suppression film formed so as to continuously cover from the top of the gate electrode to a part of the low concentration impurity diffusion layer through the side of the gate electrode. It has. For this reason, the low-concentration impurity diffusion layer under the impurity diffusion suppression film is protected from contamination, and variations in characteristics of breakdown voltage, substrate leakage current, and drive current due to the contamination can be prevented, so that the characteristics of the semiconductor device can be stabilized. Can be

本発明の第１の半導体装置は、ゲート電極の側面に形成された側壁絶縁膜をさらに備え、高濃度不純物拡散層は、基板面に平行な方向に側壁絶縁膜と離間していてもよい。 The first semiconductor device of the present invention may further include a sidewall insulating film formed on the side surface of the gate electrode, and the high concentration impurity diffusion layer may be separated from the sidewall insulating film in a direction parallel to the substrate surface.

本発明の第１の半導体装置は、高濃度不純物拡散層の上部に形成された金属シリサイド層をさらに備えていてもよい。 The first semiconductor device of the present invention may further include a metal silicide layer formed on the high concentration impurity diffusion layer.

本発明の第２の半導体装置は、高耐圧である第１のトランジスタ、該第１のトランジスタよりも低耐圧である第２のトランジスタ、及び金属シリサイド層を含まない第３のトランジスタを有する半導体装置を対象とし、第１のトランジスタは、基板の上に順次形成された第１のゲート絶縁膜及び第１のゲート電極と、基板の上部における第１のゲート電極の側方に形成された第１の低濃度不純物拡散層と、第１のゲート電極の側面に形成された第１の側壁絶縁膜と、第１のゲート電極の上から第１の側壁絶縁膜の上を通って第１の低濃度不純物拡散層の上の一部までを連続して覆うように形成された不純物拡散抑制膜と、基板の上部における前記第１のゲート電極の側方に、基板面に平行な方向に第１の側壁絶縁膜と離間するように形成され、第１の低濃度不純物拡散層よりも不純物濃度が高い第１の高濃度不純物拡散層と、第１の高濃度不純物拡散層の上部に形成された第１の金属シリサイド層とを備え、第２のトランジスタは、基板の上に順次形成された第２のゲート絶縁膜及び第２のゲート電極と、基板の上部における第２のゲート電極の側方に形成された第２の低濃度不純物拡散層と、第２のゲート電極の側面に形成された第２の側壁絶縁膜と、基板の上部における第２の側壁絶縁膜の側方に形成され、第２の低濃度不純物拡散領域よりも不純物濃度が高い第２の高濃度不純物拡散領域と、第２のゲート電極の上部及び第２の高濃度不純物拡散領域の上部に形成された第２の金属シリサイド層とを備え、第３のトランジスタは、基板の上に順次形成された第３のゲート絶縁膜及び第３のゲート電極と、基板の上部における第３のゲート電極の側方に形成された第３の低濃度不純物拡散層と、第３のゲート電極の側面に形成された第３の側壁絶縁膜と、基板、ゲート電極及び第３の側壁絶縁膜を覆うように形成された金属シリサイド生成抑制膜と、基板の上部における第３の側壁絶縁膜の側方に形成され、第３の低濃度不純物拡散層よりも不純物濃度が高い第３の高濃度不純物拡散層とを備え、不純物拡散抑制膜と金属シリサイド生成抑制膜とは同一の材料からなり、不純物拡散抑制膜は、第１の高濃度不純物拡散層を構成する不純物を含む。 A second semiconductor device of the present invention includes a first transistor having a high breakdown voltage, a second transistor having a lower breakdown voltage than the first transistor, and a third transistor not including a metal silicide layer. The first transistor includes a first gate insulating film and a first gate electrode sequentially formed on the substrate, and a first transistor formed on the side of the first gate electrode on the substrate. The first low-concentration impurity diffusion layer, the first sidewall insulating film formed on the side surface of the first gate electrode, and the first low-concentration impurity diffusion layer through the first sidewall insulating film from above the first gate electrode. An impurity diffusion suppression film formed so as to continuously cover a part above the concentration impurity diffusion layer, and a first side in a direction parallel to the substrate surface on the side of the first gate electrode in the upper part of the substrate. Formed so as to be separated from the side wall insulating film. A first high-concentration impurity diffusion layer having an impurity concentration higher than that of the first low-concentration impurity diffusion layer; a first metal silicide layer formed on the first high-concentration impurity diffusion layer; The transistor includes a second gate insulating film and a second gate electrode sequentially formed on the substrate, and a second low-concentration impurity diffusion layer formed on the side of the second gate electrode on the substrate. And a second side wall insulating film formed on the side surface of the second gate electrode, and a side wall of the second side wall insulating film on the upper portion of the substrate, and having an impurity concentration higher than that of the second low concentration impurity diffusion region. A second high-concentration impurity diffusion region having a high thickness, and a second metal silicide layer formed above the second gate electrode and the second high-concentration impurity diffusion region, and the third transistor includes: Third gate insulation sequentially formed on the substrate And a third gate electrode, a third low-concentration impurity diffusion layer formed on the side of the third gate electrode in the upper portion of the substrate, and a third sidewall insulation formed on the side surface of the third gate electrode A film, a metal silicide formation suppressing film formed so as to cover the substrate, the gate electrode, and the third sidewall insulating film; and a third low concentration formed on a side of the third sidewall insulating film on the upper portion of the substrate. A third high-concentration impurity diffusion layer having an impurity concentration higher than that of the impurity diffusion layer, the impurity diffusion suppression film and the metal silicide formation suppression film are made of the same material, and the impurity diffusion suppression film is a first high-concentration film. Impurities that constitute the impurity diffusion layer are included.

本発明の第２の半導体装置によると、第１のゲート電極の上から第１の側壁絶縁膜の上を通って第１の低濃度不純物拡散層の上の一部までを連続して覆うように形成された不純物拡散抑制膜を備えている。この、不純物拡散抑制膜の下の低濃度不純物拡散層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるので、半導体装置の特性を安定化することができる。 According to the second semiconductor device of the present invention, the region from the top of the first gate electrode to the top of the first low-concentration impurity diffusion layer is continuously covered through the first sidewall insulating film. An impurity diffusion suppression film formed on the substrate is provided. This low-concentration impurity diffusion layer under the impurity diffusion suppression film is protected from contamination, so that variations in breakdown voltage, substrate leakage current, and drive current characteristics due to the contamination can be prevented, thereby stabilizing the characteristics of the semiconductor device. can do.

本発明の第２の半導体装置において、第１のゲート絶縁膜の膜厚は、第２のゲート絶縁膜の膜厚よりも厚くてもよい。 In the second semiconductor device of the present invention, the thickness of the first gate insulating film may be larger than the thickness of the second gate insulating film.

本発明の第２の半導体装置において、第３の高濃度不純物拡散層の下面は、第２の高濃度不純物拡散層の下面よりも上に位置してもよい。 In the second semiconductor device of the present invention, the lower surface of the third high concentration impurity diffusion layer may be located above the lower surface of the second high concentration impurity diffusion layer.

本発明の第２の半導体装置において、不純物拡散抑制膜が含む不純物は、ヒ素、リン及びホウ素のうちの少なくとも１つであってもよい。 In the second semiconductor device of the present invention, the impurity contained in the impurity diffusion suppression film may be at least one of arsenic, phosphorus, and boron.

本発明に係る半導体装置及びその製造方法によると、高耐圧トランジスタの低濃度不純物拡散層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるため、半導体装置の特性を安定化することができる。 According to the semiconductor device and the manufacturing method thereof according to the present invention, the low-concentration impurity diffusion layer of the high breakdown voltage transistor is protected from contamination, and variations in breakdown voltage, substrate leakage current, and drive current characteristics due to the contamination can be prevented. The characteristics of the semiconductor device can be stabilized.

（ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタをそれぞれ示し、（ａ）は高耐圧トランジスタを示す断面図であり、（ｂ）は低耐圧トランジスタを示す断面図であり、（ｃ）はＥＳＤ保護トランジスタを示す断面図である。(A)-(c) each shows the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows a high voltage transistor, (b) is a cross section which shows a low voltage transistor It is a figure, (c) is sectional drawing which shows an ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. （ａ）〜（ｃ）は本発明の一実施形態に係る半導体装置に含まれるトランジスタの製造方法の一工程をそれぞれ示し、（ａ）は高耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｂ）は低耐圧トランジスタの製造方法の一工程を示す断面図であり、（ｃ）はＥＳＤ保護トランジスタの製造方法の一工程を示す断面図である。(A)-(c) each shows 1 process of the manufacturing method of the transistor contained in the semiconductor device which concerns on one Embodiment of this invention, (a) is sectional drawing which shows 1 process of the manufacturing method of a high voltage | pressure-resistant transistor. FIG. 8B is a cross-sectional view showing one process of the manufacturing method of the low breakdown voltage transistor, and FIG. 7C is a cross-sectional view showing one process of the manufacturing method of the ESD protection transistor. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device.

本発明の一実施形態に係る半導体装置について図１を参照しながら説明する。 A semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

本実施形態の半導体装置は、図１（ａ）に示すオフセットゲート構造を有する第１のトランジスタであるｐＭＯＳ（p-channel MOS）構造を有する高耐圧トランジスタと、図１（ｂ）に示す第２のトランジスタであるｎＭＯＳ（n-channel MOS）構造を有する低耐圧トランジスタと、図１（ｃ）に示す金属シリサイド層を含まない第３のトランジスタであるｎＭＯＳ構造を有する静電気放電（electrostatic discharge：ＥＳＤ）保護トランジスタとを備えている。以下に、各トランジスタについて詳細に説明する。 The semiconductor device of this embodiment includes a high voltage transistor having a pMOS (p-channel MOS) structure, which is a first transistor having an offset gate structure shown in FIG. 1A, and a second transistor shown in FIG. A low breakdown voltage transistor having an nMOS (n-channel MOS) structure, which is a non-transistor transistor, and an electrostatic discharge (ESD) having an nMOS structure, which is a third transistor not including the metal silicide layer shown in FIG. And a protection transistor. Hereinafter, each transistor will be described in detail.

図１（ａ）に示すように、本実施形態に係る半導体装置の高耐圧トランジスタにおいて、例えばｐ型である第１導電型の半導体基板１の上部に、例えばｎ型である第２導電型ウェル２が形成され、半導体基板１の上に、ゲート絶縁膜３ａ及びゲート電極４ａが順次形成されている。ゲート電極４ａの側面には、側壁絶縁膜６ａが形成されている。また、ゲート電極４ａの上の所定の位置から側壁絶縁膜６ａの上を通って半導体基板１の上の一部までを連続して覆うように不純物拡散抑制膜７ａが形成されている。図１（ａ）では、ゲート電極４ａの側方の一方にのみ不純物拡散抑制膜７が形成されているが、その両方に形成されていても構わない。半導体基板１の上部における側壁絶縁膜６ａの下、及び半導体基板１と接する不純物拡散抑制膜７ａの下には、例えばホウ素（Ｂ^＋）等のｐ型不純物を含む低濃度不純物拡散層である第１導電型ＬＤＤ層５ａが形成されている。半導体基板１の上部における第１導電型ＬＤＤ層５ａのゲート電極４ａと反対側の側方には、第１導電型ＬＤＤ層５ａよりも高濃度のＢ^＋等のｐ型不純物を含む高濃度不純物拡散層である第１導電型ソース・ドレイン（Ｓ／Ｄ）層８ａが形成されている。ここで、不純物拡散抑制膜７ａが形成されている側の第１導電型Ｓ／Ｄ層８ａは、ゲート電極４ａ及び側壁絶縁膜６ａから基板面に平行な方向に離間している。このようなオフセットゲート構造が設けられていることにより、高耐圧特性を有するトランジスタが得られる。第１導電型Ｓ／Ｄ層８ａの上部及びゲート電極の上部における不純物拡散抑制膜７ａと接していない領域には、金属シリサイド層９ａが形成されている。 As shown in FIG. 1A, in the high breakdown voltage transistor of the semiconductor device according to the present embodiment, for example, an n-type second conductivity type well is formed on a p-type first conductivity type semiconductor substrate 1. 2 is formed, and a gate insulating film 3 a and a gate electrode 4 a are sequentially formed on the semiconductor substrate 1. A sidewall insulating film 6a is formed on the side surface of the gate electrode 4a. Impurity diffusion suppression film 7a is formed so as to continuously cover from a predetermined position on gate electrode 4a to a part on semiconductor substrate 1 through sidewall insulating film 6a. In FIG. 1A, the impurity diffusion suppression film 7 is formed only on one side of the gate electrode 4a, but it may be formed on both of them. Below the side wall insulating film 6a above the semiconductor substrate 1 and below the impurity diffusion suppression film 7a in contact with the semiconductor substrate 1, a low-concentration impurity diffusion layer containing a p-type impurity such as boron (B ⁺ ), for example. A one conductivity type LDD layer 5a is formed. On the side opposite to the gate electrode 4a of the first conductivity type LDD layer 5a in the upper part of the semiconductor substrate 1, a high concentration impurity containing a p-type impurity such as B ^{+ having a} higher concentration than the first conductivity type LDD layer 5a. A first conductivity type source / drain (S / D) layer 8a which is a diffusion layer is formed. Here, the first conductivity type S / D layer 8a on the side where the impurity diffusion suppression film 7a is formed is separated from the gate electrode 4a and the sidewall insulating film 6a in a direction parallel to the substrate surface. By providing such an offset gate structure, a transistor having high breakdown voltage characteristics can be obtained. A metal silicide layer 9a is formed in a region not in contact with the impurity diffusion suppression film 7a above the first conductivity type S / D layer 8a and above the gate electrode.

図１（ｂ）に示すように、本実施形態に係る半導体装置の低耐圧トランジスタにおいて、第１導電型の半導体基板１の上部に、第１導電型ウェル２ｂが形成され、半導体基板１の上に、ゲート絶縁膜３ｂ及びゲート電極４ｂが順次形成されている。ゲート電極４ｂの側面には、側壁絶縁膜６ｂが形成されている。半導体基板１の上部における側壁絶縁膜６ｂの下には、例えばヒ素（Ａｓ^＋）等のｎ型不純物を含む低濃度不純物拡散層である第２導電型ＬＤＤ層５ｂが形成されている。半導体基板１の上部における第２導電型ＬＤＤ層５ｂのゲート電極４ｂと反対側の側方には、第２導電型ＬＤＤ層５ｂよりも高濃度のＡｓ^＋等のｎ型不純物を含む高濃度不純物拡散層である第２導電型Ｓ／Ｄ層８ｂが形成されている。第２導電型Ｓ／Ｄ層８ｂ及びゲート電極４ｂの上部には金属シリサイド層９ｂが形成されている。 As shown in FIG. 1B, in the low breakdown voltage transistor of the semiconductor device according to the present embodiment, a first conductivity type well 2 b is formed on the top of the first conductivity type semiconductor substrate 1. In addition, a gate insulating film 3b and a gate electrode 4b are sequentially formed. A sidewall insulating film 6b is formed on the side surface of the gate electrode 4b. A second conductivity type LDD layer 5b, which is a low-concentration impurity diffusion layer containing an n-type impurity such as arsenic (As ⁺ ), is formed below the sidewall insulating film 6b on the semiconductor substrate 1. On the side of the upper side of the semiconductor substrate 1 opposite to the gate electrode 4b of the second conductivity type LDD layer 5b, there is a high concentration impurity containing n-type impurities such as As ^{+ and a} higher concentration than the second conductivity type LDD layer 5b. A second conductivity type S / D layer 8b which is a diffusion layer is formed. A metal silicide layer 9b is formed on the second conductivity type S / D layer 8b and the gate electrode 4b.

図１（ｃ）に示すように、本実施形態に係る半導体装置のＥＳＤ保護トランジスタにおいて、第１導電型の半導体基板１の上部に、第１導電型ウェル２ｃが形成され、半導体基板１の上に、ゲート絶縁膜３ｃ及びゲート電極４ｃが順次形成されている。ゲート電極４ｃの側面には、側壁絶縁膜６ｃが形成されている。半導体基板１の上部における側壁絶縁膜６ｃの下には、例えばＡｓ^＋等のｎ型不純物を含む低濃度不純物拡散層である第２導電型ＬＤＤ層５ｃが形成されている。半導体基板１の上部における第２導電型ＬＤＤ層５ｃのゲート電極４ｃと反対側の側方には、第２導電型ＬＤＤ層５ｃよりも高濃度のＡｓ^＋等のｎ型不純物を含む高濃度不純物拡散層である第２導電型Ｓ／Ｄ層８ｃが形成されている。半導体基板１の上には、半導体基板１、ゲート電極４ｃ及び側壁絶縁膜６ｃを覆うように金属シリサイド生成抑制膜７ｃが形成されている。ここで、金属シリサイド生成抑制膜７ｃは、高耐圧トランジスタの不純物拡散抑制膜７ａと同一の材料からなる。また、第２導電型Ｓ／Ｄ層８ｃは、金属シリサイド生成抑制膜７ｃを介した不純物注入により形成されるため、第２導電型Ｓ／Ｄ層８ｃは、低耐圧トランジスタの第２導電型Ｓ／Ｄ層８ｂよりも半導体基板１の浅い領域に形成される。すなわち、第２導電型Ｓ／Ｄ層８ｃの下面は、低耐圧トランジスタの第２導電型Ｓ／Ｄ層８ｂの下面よりも上に位置する。 As shown in FIG. 1C, in the ESD protection transistor of the semiconductor device according to this embodiment, a first conductivity type well 2 c is formed on the first conductivity type semiconductor substrate 1. In addition, a gate insulating film 3c and a gate electrode 4c are sequentially formed. A sidewall insulating film 6c is formed on the side surface of the gate electrode 4c. A second conductivity type LDD layer 5c, which is a low-concentration impurity diffusion layer containing an n-type impurity such as As ⁺ , is formed below the sidewall insulating film 6c on the semiconductor substrate 1. On the side of the upper side of the semiconductor substrate 1 opposite to the gate electrode 4c of the second conductivity type LDD layer 5c, a high concentration impurity containing an n-type impurity such as As ^{+ having a} higher concentration than the second conductivity type LDD layer 5c. A second conductivity type S / D layer 8c, which is a diffusion layer, is formed. On the semiconductor substrate 1, a metal silicide generation suppressing film 7c is formed so as to cover the semiconductor substrate 1, the gate electrode 4c, and the sidewall insulating film 6c. Here, the metal silicide formation suppressing film 7c is made of the same material as the impurity diffusion suppressing film 7a of the high breakdown voltage transistor. In addition, since the second conductivity type S / D layer 8c is formed by impurity implantation through the metal silicide generation suppressing film 7c, the second conductivity type S / D layer 8c is the second conductivity type S of the low breakdown voltage transistor. / D layer 8b is formed in a shallower region of the semiconductor substrate 1 than the layer 8b. That is, the lower surface of the second conductivity type S / D layer 8c is located above the lower surface of the second conductivity type S / D layer 8b of the low breakdown voltage transistor.

本実施形態に係る半導体装置の高耐圧トランジスタにおいて、第１導電型ＬＤＤ層５ａの上に位置する不純物拡散抑制膜７ａは、特にその表面側に、第１導電型Ｓ／Ｄ層８ａ及び第２導電型Ｓ／Ｄ層８ｂから飛散した、例えばＢ^＋及びＡｓ^＋等の不純物を含む。この不純物は、第１導電型Ｓ／Ｄ層８ａ及び第２導電型Ｓ／Ｄ層８ｂが形成された後に行われるアッシング処理により、第１導電型Ｓ／Ｄ層８ａ及び第２導電型Ｓ／Ｄ層８ｂから飛散する。すなわち、不純物拡散抑制膜７ａにより、第１導電型Ｓ／Ｄ層８ａ及び第２導電型Ｓ／Ｄ層８ｂから飛散した不純物による第１導電型ＬＤＤ層７ａのコンタミネーションが防止される。なお、Ｂ^＋及びＡｓ^＋の他に、Ｓ／Ｄ層を形成するための不純物注入にリン（Ｐ^＋）等の不純物を用いた場合、不純物拡散抑制膜７ａは、Ｐ^＋等の不純物を含むこととなる。 In the high breakdown voltage transistor of the semiconductor device according to the present embodiment, the impurity diffusion suppression film 7a located on the first conductivity type LDD layer 5a has a first conductivity type S / D layer 8a and a second conductivity layer on the surface side thereof. For example, impurities such as B ⁺ and As ⁺ scattered from the conductive S / D layer 8b are included. This impurity is caused by ashing performed after the first conductivity type S / D layer 8a and the second conductivity type S / D layer 8b are formed, and thereby the first conductivity type S / D layer 8a and the second conductivity type S / D. It scatters from the D layer 8b. That is, the impurity diffusion suppression film 7a prevents contamination of the first conductivity type LDD layer 7a due to impurities scattered from the first conductivity type S / D layer 8a and the second conductivity type S / D layer 8b. In addition to B ⁺ and As ⁺ , when an impurity such as phosphorus (P ⁺ ) is used for impurity implantation for forming the S / D layer, the impurity diffusion suppression film 7a includes an impurity such as P ^+. It will be.

本発明の一実施形態に係る半導体装置によると、ＬＤＤ層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるため、半導体装置の特性を安定化することができる。 According to the semiconductor device of one embodiment of the present invention, the LDD layer is protected from contamination, and variations in breakdown voltage, substrate leakage current, and drive current due to the contamination can be prevented, so that the characteristics of the semiconductor device can be stabilized. Can be

次に、本発明の一実施形態に係る半導体装置の製造方法について図２〜図８を参照しながら説明する。図２〜図８において、（ａ）はｐＭＯＳ構造を有する高耐圧トランジスタを形成する領域を示し、（ｂ）はｎＭＯＳ構造を有する低耐圧トランジスタを形成する領域を示し、（ｃ）はｎＭＯＳ構造を有するＥＳＤ保護トランジスタを形成する領域を示している。以下の説明において、各領域をそれぞれ（ａ）領域、（ｂ）領域及び（ｃ）領域として説明する。 Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2 to 8, (a) shows a region where a high breakdown voltage transistor having a pMOS structure is formed, (b) shows a region where a low breakdown voltage transistor having an nMOS structure is formed, and (c) shows an nMOS structure. A region for forming an ESD protection transistor is shown. In the following description, each region will be described as a region (a), a region (b), and a region (c).

まず、図２に示すように、例えばｐ型である第１導電型の半導体基板１の上部に、（ａ）領域では、例えばｎ型である第２導電型ウェル２ａを形成し、（ｂ）領域及び（ｃ）領域では、第１導電型ウェル２ｂ、２ｃをそれぞれ形成する。続いて、半導体基板１の上に、（ａ）領域では、膜厚が２０ｎｍ程度のゲート絶縁膜３ａを形成し、（ｂ）領域及び（ｃ）領域では、膜厚が３．５ｎｍ程度のゲート絶縁膜３ｂ、３ｃをそれぞれ形成し、それらの上に共通して膜厚が２００ｎｍ程度のゲート電極材料４を形成する。 First, as shown in FIG. 2, for example, an n-type second conductivity type well 2a is formed in the upper part of the first conductivity type semiconductor substrate 1 which is p-type, for example, in the region (a), and (b) In the region and (c) region, first conductivity type wells 2b and 2c are formed, respectively. Subsequently, a gate insulating film 3a having a thickness of about 20 nm is formed on the semiconductor substrate 1 in the region (a), and a gate having a thickness of about 3.5 nm in the regions (b) and (c). Insulating films 3b and 3c are respectively formed, and a gate electrode material 4 having a thickness of about 200 nm is formed in common on them.

次に、図３に示すように、（ａ）〜（ｃ）領域において、ゲート電極材料４をパターニングし、ゲート電極４ａ、４ｂ及び４ｃをそれぞれ形成する。ここで、（ａ）領域のゲート電極４ａのゲート長方向の寸法は、例えば７００ｎｍ程度であり、（ｂ）領域及び（ｃ）領域のゲート電極４ｂ、４ｃのゲート長方向の寸法は、例えば１８０ｎｍ程度である。 Next, as shown in FIG. 3, in the regions (a) to (c), the gate electrode material 4 is patterned to form gate electrodes 4a, 4b and 4c, respectively. Here, the dimension in the gate length direction of the gate electrode 4a in the (a) region is, for example, about 700 nm, and the dimension in the gate length direction of the gate electrodes 4b, 4c in the (b) region and (c) region is, for example, 180 nm. Degree.

次に、図４に示すように、半導体基板１の上部におけるゲート電極４ａ、４ｂ及び４ｃのそれぞれの側方に、（ａ）領域では、例えばホウ素（Ｂ^＋）イオンを注入することにより、低濃度不純物拡散層である第１導電型ＬＤＤ層５ａを形成し、（ｂ）領域及び（ｃ）領域では、例えばヒ素（Ａｓ^＋）イオンを注入することにより、低濃度不純物拡散層である第２導電型ＬＤＤ層５ｂ、５ｃをそれぞれ形成する。ここで、（ａ）領域におけるＢ^＋の注入量は、例えば１×１０^１３／ｃｍ^２オーダであり、（ｂ）領域及び（ｃ）領域におけるＡｓ^＋の注入量は、例えば１×１０^１４／ｃｍ^２オーダである。 Next, as shown in FIG. 4, for example, boron (B ⁺ ) ions are implanted into the sides of the gate electrodes 4 a, 4 b, and 4 c on the upper side of the semiconductor substrate 1 in the (a) region, thereby reducing A first conductivity type LDD layer 5a which is a concentration impurity diffusion layer is formed, and in the regions (b) and (c), for example, arsenic (As ⁺ ) ions are implanted, thereby forming a second concentration diffusion layer. Conductive LDD layers 5b and 5c are formed. Here, the implantation amount of B ^{+ in} the region (a) is, for example, on the order of 1 × 10 ¹³ / cm ² , and the implantation amount of As ^{+ in} the region (b) and the region (c) is, for example, 1 × 10 ¹⁴ / cm ^2. cm ² order.

次に、図５に示すように、（ａ）〜（ｃ）の各領域において、エッチバック法等を用いてゲート電極４ａ、４ｂ及び４ｃのそれぞれの側面に膜厚が１００ｎｍ程度の側壁絶縁膜６ａ、６ｂ及び６ｃを形成する。 Next, as shown in FIG. 5, in each of the regions (a) to (c), sidewall insulating films having a film thickness of about 100 nm are formed on the respective side surfaces of the gate electrodes 4a, 4b, and 4c by using an etch back method or the like. 6a, 6b and 6c are formed.

次に、図６に示すように、（ａ）領域において、ゲート電極４ａの所定の位置から側壁絶縁膜６ａの上を通って第１導電型ＬＤＤ層５ａの上の一部までを連続して覆うように、膜厚が３０ｎｍ程度の不純物拡散抑制膜７ａを形成する。これと共に、（ｃ）領域において、半導体基板１、ゲート電極４ｃ及び側壁絶縁膜６ｃを覆うように、膜厚が３０ｎｍ程度の金属シリサイド生成抑制膜７ｃを形成する。ここで、不純物拡散抑制膜７ａと金属シリサイド生成抑制膜７ｃとは、同一の材料を用いて形成されてもよい。なお、不純物拡散抑制膜７ａ及び金属シリサイド生成抑制膜７ｃは、ウェハの全面に堆積した後に、ウエットエッチング法等により選択的に除去して形成する。前記の領域の他に、後に金属シリサイド層を形成しない領域があれば、その領域の上にも金属シリサイド生成抑制膜７ｃを形成しても構わない。また、本実施形態において、（ａ）領域ではゲート電極４ａの側方の一方の第１導電型ＬＤＤ層５ａの上にのみ不純物拡散抑制膜７ａを形成したが、その両側の第１導電型ＬＤＤ層５ａの上に不純物拡散抑制膜７ａを形成しても構わない。 Next, as shown in FIG. 6, in the region (a), from the predetermined position of the gate electrode 4a through the sidewall insulating film 6a to a part on the first conductivity type LDD layer 5a continuously. An impurity diffusion suppression film 7a having a thickness of about 30 nm is formed so as to cover it. Along with this, in the region (c), a metal silicide generation suppressing film 7c having a thickness of about 30 nm is formed so as to cover the semiconductor substrate 1, the gate electrode 4c, and the sidewall insulating film 6c. Here, the impurity diffusion suppression film 7a and the metal silicide generation suppression film 7c may be formed using the same material. The impurity diffusion suppression film 7a and the metal silicide generation suppression film 7c are formed by being selectively removed by a wet etching method or the like after being deposited on the entire surface of the wafer. In addition to the above region, if there is a region where the metal silicide layer is not formed later, the metal silicide generation suppressing film 7c may be formed on the region. In the present embodiment, in the region (a), the impurity diffusion suppression film 7a is formed only on one of the first conductivity type LDD layers 5a on the side of the gate electrode 4a. An impurity diffusion suppression film 7a may be formed on the layer 5a.

次に、図７に示すように、半導体基板１の上部におけるゲート電極４ａ、４ｂ及び４ｃのそれぞれの側方に、（ａ）領域では、高濃度不純物拡散層である第１導電型Ｓ／Ｄ層８ａを形成し、（ｂ）領域及び（ｃ）領域では、それぞれ高濃度不純物拡散層である第２導電型Ｓ／Ｄ層８ｂ、８ｃを形成する。 Next, as shown in FIG. 7, on the sides of the gate electrodes 4a, 4b and 4c in the upper part of the semiconductor substrate 1, in the (a) region, the first conductivity type S / D which is a high concentration impurity diffusion layer. A layer 8a is formed, and second conductivity type S / D layers 8b and 8c, which are high-concentration impurity diffusion layers, are formed in the regions (b) and (c), respectively.

具体的に、（ａ）領域において、半導体基板１の上部におけるゲート電極４ａの側方に、ゲート電極４ａ、側壁絶縁膜６ａ、不純物拡散抑制膜７ａ及びその上に予め形成したレジスト膜をマスクとして不純物注入を行うことにより、側壁絶縁膜６ａの端部からゲート電極４ａと反対側に向かって、例えば約６００ｎｍのオフセット領域を設けて、第１導電型Ｓ／Ｄ層８ａを形成する。その不純物注入は、例えばＢ^＋を用い、加速電圧３ｋｅＶで注入量を１×１０^１５／ｃｍ^２オーダとして行われる。（ｂ）領域では、半導体基板１の上部におけるゲート電極４ｂの側方に、ゲート電極４ｂ及び側壁絶縁膜６ｂをマスクとして不純物注入を行うことにより、第２導電型Ｓ／Ｄ層８ｂを形成する。その不純物注入は、例えばＡｓ^＋を用い、加速電圧５０ｋｅＶで注入量を１×１０^１５／ｃｍ^２オーダとして行われる。（ｃ）領域では、半導体基板１の上部におけるゲート電極４ｃの側方に、ゲート電極４ｃ及び側壁絶縁膜６ｃをマスクとして不純物注入を行うことにより、第２導電型Ｓ／Ｄ層８ｃを形成する。その不純物注入は、例えばＡｓ^＋を用い、加速電圧５０ｋｅＶで注入量を１×１０^１５／ｃｍ^２オーダとして行われる。なお、第２導電型Ｓ／Ｄ層８ｂ、８ｃの形成は、同一の不純物注入工程により行われ得る。また、（ｃ）領域の第２導電型Ｓ／Ｄ層８ｃの形成のための不純物注入は、金属シリサイド生成抑制膜７ｃを介して行われるため、必然的に（ｃ）領域の第２導電型Ｓ／Ｄ層８ｃは、（ｂ）領域の第２導電型Ｓ／Ｄ層８ｂよりも半導体基板１の浅い位置に形成される。すなわち、（ｃ）領域の第２導電型Ｓ／Ｄ層８ｃの下面は、（ｂ）領域の第２導電型Ｓ／Ｄ層８ｂの下面よりも上に位置し、例えば約３０ｎｍ以上、上に位置する。 Specifically, in the region (a), a gate electrode 4a, a sidewall insulating film 6a, an impurity diffusion suppression film 7a, and a resist film previously formed thereon are used as a mask on the side of the gate electrode 4a in the upper part of the semiconductor substrate 1. By performing impurity implantation, an offset region of, for example, about 600 nm is provided from the end of the sidewall insulating film 6a toward the side opposite to the gate electrode 4a to form the first conductivity type S / D layer 8a. The impurity implantation is performed, for example, using B ⁺ and an acceleration voltage of 3 keV and an implantation amount of the order of 1 × 10 ¹⁵ / cm ² . In the region (b), the second conductivity type S / D layer 8b is formed by performing impurity implantation on the side of the gate electrode 4b above the semiconductor substrate 1 using the gate electrode 4b and the sidewall insulating film 6b as a mask. . The impurity implantation is performed using, for example, As ⁺ and an accelerating voltage of 50 keV and an implantation amount of the order of 1 × 10 ¹⁵ / cm ² . In the region (c), the second conductivity type S / D layer 8c is formed by implanting impurities on the side of the gate electrode 4c on the upper side of the semiconductor substrate 1 using the gate electrode 4c and the sidewall insulating film 6c as a mask. . The impurity implantation is performed using, for example, As ⁺ and an accelerating voltage of 50 keV and an implantation amount of the order of 1 × 10 ¹⁵ / cm ² . The second conductivity type S / D layers 8b and 8c can be formed by the same impurity implantation process. Further, since the impurity implantation for forming the second conductivity type S / D layer 8c in the (c) region is performed through the metal silicide generation suppressing film 7c, the second conductivity type in the (c) region is inevitably required. The S / D layer 8c is formed at a shallower position on the semiconductor substrate 1 than the second conductivity type S / D layer 8b in the region (b). That is, the lower surface of the second conductivity type S / D layer 8c in the (c) region is located above the lower surface of the second conductivity type S / D layer 8b in the (b) region, for example, about 30 nm or more above To position.

各Ｓ／Ｄ層を形成した後に、基板に対して加熱処理を行う。この加熱処理はアッシング処理であり、半導体基板１の上のレジスト膜を除去する。このようなアッシング処理は、例えば高周波（radio frequency：ＲＦ）バイアスを半導体基板１に印加することによって行うことができる。アッシングの際に、第１導電型Ｓ／Ｄ層８ａ及び第２導電型Ｓ／Ｄ層８ｂから不純物が放出し、（ａ）領域の第１導電型ＬＤＤ層５ａが露出していると、第１導電型ＬＤＤ層５ａに再注入される。（ａ）領域の第１導電型ＬＤＤ層５ａの不純物濃度は比較的小さいため、第１導電型ＬＤＤ層５ａに不純物が再注入されると、コンタミネーションにより、高耐圧トランジスタの耐圧、基板リーク電流及び駆動電流の特性にばらつきが生じる。しかしながら、本実施形態においては、高耐圧トランジスタとなる（ａ）領域の第１導電型ＬＤＤ層５ａの上には不純物拡散抑制膜７ａが形成されているため、不純物が第１導電型ＬＤＤ層５ａに再注入されることはなく、高耐圧トランジスタの耐圧、基板リーク電流及び駆動電流の特性が安定する。 After each S / D layer is formed, heat treatment is performed on the substrate. This heat treatment is an ashing treatment, and the resist film on the semiconductor substrate 1 is removed. Such an ashing process can be performed, for example, by applying a radio frequency (RF) bias to the semiconductor substrate 1. When ashing, impurities are released from the first conductivity type S / D layer 8a and the second conductivity type S / D layer 8b, and the first conductivity type LDD layer 5a in the region (a) is exposed. It is reinjected into the one conductivity type LDD layer 5a. (A) Since the impurity concentration of the first conductivity type LDD layer 5a in the region is relatively small, when impurities are reinjected into the first conductivity type LDD layer 5a, the breakdown voltage of the high voltage transistor and the substrate leakage current are caused by contamination. In addition, the drive current characteristics vary. However, in the present embodiment, since the impurity diffusion suppression film 7a is formed on the first conductivity type LDD layer 5a in the (a) region to be a high breakdown voltage transistor, the impurity is the first conductivity type LDD layer 5a. In other words, the breakdown voltage, substrate leakage current, and drive current characteristics of the high breakdown voltage transistor are stabilized.

次に、図８に示すように、（ａ）領域では、不純物拡散抑制膜７ａが形成されずに露出している第１導電型Ｓ／Ｄ層８ａの上部及びゲート電極４ａの上部に、金属シリサイド層９ａを形成し、（ｂ）領域では、第２導電型Ｓ／Ｄ層８ｂの上部、及びゲート電極４ｂの上部に、金属シリサイド層９ｂを形成する。 Next, as shown in FIG. 8, in the region (a), a metal is formed on the upper part of the first conductivity type S / D layer 8a and the upper part of the gate electrode 4a exposed without forming the impurity diffusion suppression film 7a. A silicide layer 9a is formed, and in the region (b), a metal silicide layer 9b is formed above the second conductivity type S / D layer 8b and above the gate electrode 4b.

以降の工程は周知であり、配線、層間絶縁膜及び保護絶縁膜等を形成して半導体装置を完成する。 Subsequent processes are well known, and a semiconductor device is completed by forming wirings, interlayer insulating films, protective insulating films, and the like.

本発明の一実施形態に係る半導体装置の製造方法によると、ＬＤＤ層がコンタミネーションから保護されて、該コンタミネーションによる耐圧、基板リーク電流及び駆動電流の特性のばらつきを防止できるため、半導体装置の特性を安定化することができる。また、上記の不純物拡散抑制膜は金属シリサイド生成抑制膜と共通の工程により形成されるため、不純物拡散抑制膜を形成するための新たな工程は発生せず、製造工程数の増加を防ぐことができる。 According to the method for manufacturing a semiconductor device according to an embodiment of the present invention, the LDD layer is protected from contamination, and variations in breakdown voltage, substrate leakage current, and drive current characteristics due to the contamination can be prevented. The characteristics can be stabilized. In addition, since the impurity diffusion suppression film is formed by a process common to the metal silicide generation suppression film, a new process for forming the impurity diffusion suppression film does not occur, thereby preventing an increase in the number of manufacturing processes. it can.

なお、本実施形態において、ｐＭＯＳ構造を有する高耐圧トランジスタ、ｎＭＯＳ構造を有する低耐圧トランジスタ及びｎＭＯＳ構造を有するＥＳＤ保護トランジスタが混在する半導体装置について説明したが、これらのトランジスタの導電型は前記の例示した導電型に限定されるものではなく、それらを逆の導電型にしても構わない。また、本発明に係る半導体装置は、少なくとも高耐圧トランジスタを含む半導体装置であればよい。さらに、金属シリサイド層を含まない非シリサイド系トランジスタとしてＥＳＤ保護トランジスタを例示して説明したが、これに限定されるものではなく、他の機能を有する非シリサイド系トランジスタを含んでも構わない。 In the present embodiment, a semiconductor device in which a high breakdown voltage transistor having a pMOS structure, a low breakdown voltage transistor having an nMOS structure, and an ESD protection transistor having an nMOS structure are mixed is described. However, the conductive type is not limited to the above, and the conductive type may be reversed. The semiconductor device according to the present invention may be any semiconductor device including at least a high voltage transistor. Furthermore, although the ESD protection transistor has been described as an example of a non-silicide transistor that does not include a metal silicide layer, the present invention is not limited to this, and a non-silicide transistor having other functions may be included.

本発明の半導体装置及びその製造方法は、半導体装置の特性を安定化でき、特に、オフセットゲート構造を有するトランジスタを含む半導体装置及びその製造方法等に有用である。 The semiconductor device and the manufacturing method thereof of the present invention can stabilize the characteristics of the semiconductor device, and are particularly useful for a semiconductor device including a transistor having an offset gate structure, a manufacturing method thereof, and the like.

１半導体基板
２ａ（第１のトランジスタの）第２導電型ウェル
２ｂ（第２のトランジスタの）第１導電型ウェル
２ｃ（第３のトランジスタの）第１導電型ウェル
３ａ（第１のトランジスタの）ゲート絶縁膜
３ｂ（第２のトランジスタの）ゲート絶縁膜
３ｃ（第３のトランジスタの）ゲート絶縁膜
４ゲート電極材料
４ａ（第１のトランジスタの）ゲート電極
４ｂ（第２のトランジスタの）ゲート電極
４ｃ（第３のトランジスタの）ゲート電極
５ａ（第１のトランジスタの）第１導電型低濃度拡散（ＬＤＤ）層
５ｂ（第２のトランジスタの）第２導電型低濃度拡散（ＬＤＤ）層
５ｃ（第３のトランジスタの）第２導電型低濃度拡散（ＬＤＤ）層
６ａ（第１のトランジスタの）側壁絶縁膜
６ｂ（第２のトランジスタの）側壁絶縁膜
６ｃ（第３のトランジスタの）側壁絶縁膜
７ａ不純物拡散抑制膜
７ｃ金属シリサイド生成抑制膜
８ａ（第１のトランジスタの）第１導電型ソース・ドレイン（Ｓ／Ｄ）層
８ｂ（第２のトランジスタの）第２導電型ソース・ドレイン（Ｓ／Ｄ）層
８ｃ（第３のトランジスタの）第２導電型ソース・ドレイン（Ｓ／Ｄ）層
９ａ（第１のトランジスタの）金属シリサイド層
９ｂ（第２のトランジスタの）金属シリサイド層
９ｃ（第３のトランジスタの）金属シリサイド層 1 Semiconductor substrate 2a Second conductivity type well 2b (for the first transistor) First conductivity type well 2c (for the second transistor) First conductivity type well 3a (for the third transistor) Gate insulating film 3b Gate insulating film 3c (for the second transistor) Gate insulating film 4 (for the third transistor) Gate electrode material 4a Gate electrode 4b (for the first transistor) Gate electrode 4c (for the second transistor) Gate electrode 5a (for the third transistor) First conductivity type low concentration diffusion (LDD) layer 5b (for the first transistor) Second conductivity type low concentration diffusion (LDD) layer 5c (for the second transistor) Second conductivity type low concentration diffusion (LDD) layer 6a (of the first transistor) Side wall insulating film 6b (of the first transistor) Side wall insulating film 6c (of the second transistor) Side wall insulating film 7a (for third transistor) Impurity diffusion suppressing film 7c Metal silicide generation suppressing film 8a First conductivity type source / drain (S / D) layer 8b (for the first transistor) 2 conductivity type source / drain (S / D) layer 8c (second transistor) second conductivity type source / drain (S / D) layer 9a (first transistor) metal silicide layer 9b (second transistor) Metal silicide layer 9c (for third transistor) metal silicide layer

Claims

A step (a) of sequentially forming a gate insulating film and a gate electrode on the substrate;
Forming a low-concentration impurity diffusion layer on the side of the gate electrode in the upper portion of the substrate by implanting impurities into the substrate using the gate electrode as a mask; and
A step (c) of forming an impurity diffusion suppression film so as to continuously cover a part of the low-concentration impurity diffusion layer through the side of the gate electrode from above the gate electrode;
By implanting impurities into the substrate using the gate electrode and the impurity diffusion suppression film as a mask, high concentration impurity diffusion having an impurity concentration higher than that of the low concentration impurity diffusion layer is formed on the side of the gate electrode on the upper portion of the substrate. Forming a layer (d);
And a step (e) of performing a heat treatment on the substrate in a state where the impurity diffusion suppression film is left after the step (d).

A step (f) of forming a sidewall insulating film on a side surface of the gate electrode between the steps (b) and (c);
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), impurities are implanted into the substrate using the sidewall insulating film as a mask.

3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step (g) of siliciding an upper portion of the high-concentration impurity diffusion layer after the step (e). 4.

In the step (e), the heat treatment is an ashing treatment,
The method of manufacturing a semiconductor device according to claim 1, wherein the ashing process is performed by applying a high frequency bias to the substrate.

A method of manufacturing a semiconductor device having a first transistor having a high breakdown voltage, a second transistor having a lower breakdown voltage than the first transistor, and a third transistor not including a metal silicide layer,
A step (a) of sequentially forming a gate insulating film and a gate electrode in each of the regions for forming the first transistor, the second transistor, and the third transistor on the substrate;
In each of the regions where the first transistor, the second transistor, and the third transistor are formed, by implanting impurities into the substrate using the gate electrodes as masks, the gate electrodes in the upper portion of the substrate are formed. Forming a low-concentration impurity diffusion layer laterally (b);
Forming a sidewall insulating film on a side surface of each gate electrode in each of the regions for forming the first transistor, the second transistor, and the third transistor;
In the region where the first transistor is to be formed, an impurity diffusion suppression film is formed so as to continuously cover a part of the low-concentration impurity diffusion layer from above the gate electrode to above the sidewall insulating film. Forming a metal silicide formation suppressing film so as to cover the substrate, the gate electrode, and the sidewall insulating film in a region where the third transistor is to be formed;
In the region for forming the first transistor, the gate electrode, the sidewall insulating film and the impurity diffusion suppression film are used as a mask. In the region for forming the second transistor, the gate electrode and the sidewall insulating film are used as a mask. In the region where the third transistor is to be formed, the gate electrode and the sidewall insulating film are used as a mask, and impurities are implanted into the substrate so as to penetrate the metal silicide formation suppression film, whereby the upper portion of the substrate is Forming a high-concentration impurity diffusion layer having an impurity concentration higher than that of the low-concentration impurity diffusion layer on the side of the gate electrode, respectively (e);
After the step (e), the impurity diffusion suppression film and the metal silicide generation suppression film are left in the regions where the first transistor, the second transistor, and the third transistor are formed. A step (f) of performing a heat treatment on the substrate;
After the step (f), the upper portion of the high-concentration impurity diffusion layer is silicided in the region where the first transistor is to be formed, and the upper portion of the gate electrode and the upper portion of the region where the second transistor is to be formed. And a step (g) of siliciding the upper part of the concentration impurity diffusion layer.

In the step (a), the gate insulating film in the region for forming the first transistor is formed thicker than the film thickness of the gate insulating film in the region for forming the second transistor. A method for manufacturing a semiconductor device according to claim 5.

In the step (e), the high-concentration impurity diffusion layer in the region for forming the third transistor has a lower surface above the lower surface of the high-concentration impurity diffusion layer in the region for forming the second transistor. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is formed so as to be positioned.

In the step (f), the heat treatment is an ashing treatment,
The method of manufacturing a semiconductor device according to claim 5, wherein the ashing process is performed by applying a high frequency bias to the substrate.

A gate insulating film and a gate electrode sequentially formed on the substrate;
A low-concentration impurity diffusion layer formed on the side of the gate electrode at the top of the substrate;
An impurity diffusion suppression film formed so as to continuously cover a part of the low-concentration impurity diffusion layer through the side of the gate electrode from above the gate electrode;
A high-concentration impurity diffusion layer formed on the side of the gate electrode on the upper side of the substrate so as to be separated from the gate electrode in a direction parallel to the substrate surface and having a higher impurity concentration than the low-concentration impurity diffusion layer; Prepared,
The semiconductor device, wherein the impurity diffusion suppression film includes an impurity constituting the high-concentration impurity diffusion layer.

A sidewall insulating film formed on a side surface of the gate electrode;
The semiconductor device according to claim 9, wherein the high-concentration impurity diffusion layer is separated from the sidewall insulating film in a direction parallel to the substrate surface.

11. The semiconductor device according to claim 9, further comprising a metal silicide layer formed on the upper portion of the high concentration impurity diffusion layer.

A semiconductor device having a first transistor having a high breakdown voltage, a second transistor having a lower breakdown voltage than the first transistor, and a third transistor not including a metal silicide layer,
The first transistor includes:
A first gate insulating film and a first gate electrode sequentially formed on the substrate;
A first low-concentration impurity diffusion layer formed on the side of the first gate electrode on the substrate;
A first sidewall insulating film formed on a side surface of the first gate electrode;
An impurity diffusion suppression film formed so as to continuously cover a part of the first low-concentration impurity diffusion layer from above the first gate electrode through the first sidewall insulating film. When,
Formed on the side of the first gate electrode in the upper part of the substrate so as to be separated from the first sidewall insulating film in a direction parallel to the substrate surface, and more impurity than the first low-concentration impurity diffusion layer A first high-concentration impurity diffusion layer having a high concentration;
A first metal silicide layer formed on the first high-concentration impurity diffusion layer,
The second transistor is
A second gate insulating film and a second gate electrode sequentially formed on the substrate;
A second low-concentration impurity diffusion layer formed on the side of the second gate electrode at the top of the substrate;
A second sidewall insulating film formed on a side surface of the second gate electrode;
A second high-concentration impurity diffusion region formed on a side of the second sidewall insulating film on the substrate and having an impurity concentration higher than that of the second low-concentration impurity diffusion region;
A second metal silicide layer formed on the second gate electrode and on the second high-concentration impurity diffusion region,
The third transistor is:
A third gate insulating film and a third gate electrode sequentially formed on the substrate;
A third low-concentration impurity diffusion layer formed on the side of the third gate electrode at the top of the substrate;
A third sidewall insulating film formed on a side surface of the third gate electrode;
A metal silicide formation suppressing film formed to cover the substrate, the gate electrode, and the third sidewall insulating film;
A third high-concentration impurity diffusion layer formed on a side of the third sidewall insulating film on the substrate and having an impurity concentration higher than that of the third low-concentration impurity diffusion layer;
The impurity diffusion suppression film and the metal silicide generation suppression film are made of the same material,
The semiconductor device, wherein the impurity diffusion suppression film includes impurities constituting the first high-concentration impurity diffusion layer.

The semiconductor device according to claim 12, wherein a film thickness of the first gate insulating film is thicker than a film thickness of the second gate insulating film.

14. The semiconductor device according to claim 12, wherein a lower surface of the third high-concentration impurity diffusion layer is located above a lower surface of the second high-concentration impurity diffusion layer.

The semiconductor device according to claim 9, wherein the impurity contained in the impurity diffusion suppression film is at least one of arsenic, phosphorus, and boron.